From 4a1eafc312974f3aa2a7b59e31e5fcd366f54232 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Thu, 5 Nov 2009 12:02:10 +0000 Subject: [PATCH] - added global clock generator Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@608 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/sim/tb_mips_sys.fdo | 5 ++- projects/mips_sys/src/mips_sys.vhd | 51 +++++++++------------- projects/mips_sys/src/mips_sys_sim.vhd | 58 +++++++++----------------- 3 files changed, 41 insertions(+), 73 deletions(-) diff --git a/projects/mips_sys/sim/tb_mips_sys.fdo b/projects/mips_sys/sim/tb_mips_sys.fdo index 6d5417c..27e770e 100644 --- a/projects/mips_sys/sim/tb_mips_sys.fdo +++ b/projects/mips_sys/sim/tb_mips_sys.fdo @@ -41,7 +41,6 @@ vcom -explicit -93 "../../../lib/misc/rom_wb.vhd" # VGA vcom -explicit -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd" vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_types.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd" vcom -explicit -93 "../../../lib/VGA_ctrl/src/char_gen.vhd" vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd" vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd" @@ -74,7 +73,6 @@ vcom -explicit -93 "../../../lib/SSRAM/src/CY7C1354B.vhd" vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd" # SDRAM -vcom -explicit -93 "../../../lib/misc/clockgen_virtex4.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd" @@ -89,6 +87,9 @@ vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd" vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd" vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd" +# Clock Generator +vcom -explicit -93 "../src/clockgen_virtex4.vhd" + # Top and TB vcom -explicit -93 "../src/mips_sys_sim.vhd" vcom -explicit -93 "../src/tb_mips_sys.vhd" diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd index 9458d4f..22bf247 100644 --- a/projects/mips_sys/src/mips_sys.vhd +++ b/projects/mips_sys/src/mips_sys.vhd @@ -319,14 +319,13 @@ ARCHITECTURE behavior OF mips_sys IS signal sdram_clk270 : std_logic; signal sdram_clk270var : std_logic; signal vga_clk : std_logic; - signal vga_clk_lock : std_logic; + signal dcm_lock : std_logic; signal rst_in : std_logic; signal int_timer : std_logic; signal int_uart0 : std_logic; signal int_uart1 : std_logic; signal uart1_tx : std_logic; signal uart1_rx : std_logic; - signal sdram_clk_lock : std_logic; signal usb_addr : unsigned(31 downto 0); signal ac97_rstn : std_logic; signal mem_mapped_io : std_logic; @@ -471,8 +470,7 @@ BEGIN sys_flash_a <= '0' & flash_addr(24 downto 2) & '0'; flash_page_mode_en <= not mem_mapped_io; - CLK_O <= sys_clk_in; - RST_O <= not (sdram_clk_lock and vga_clk_lock); + RST_O <= not dcm_lock; SDAT_I_sdram <= MDAT_O & MDAT_O; SEL_I_sdram <= "0000" & SEL_O; @@ -811,22 +809,25 @@ inst_uart_wb_1 : uart_wb inst_clockgen : entity work.clockgen GENERIC MAP ( - clk_in_freq_hz => 100E6, - clk0_out_phaseshift => 0, - clk1_out_phaseshift => 0 + clk_in_freq_hz => 100E6, + vga_clk_out_freq_hz => tsvga.f_pxl_clk, + sdr_clk0_out_phaseshift => 0, + sdr_clk1_out_phaseshift => 0 ) PORT MAP ( -- Clocks and Reset - rst => rst_in, -- external async reset, low active - clk_in => CLK_O, -- system clock (e.g. 100MHz), from board - clk_fb_in => sys_sdr_clk_fb, -- feedback clock - clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0° - clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270° - clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - locked_out => sdram_clk_lock, -- DCM locked status - error_out => open + rst => rst_in, -- external async reset, low active + clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board + sys_clk_out => CLK_O, + vga_clk_out => vga_clk, + sdr_clk0_fb_in => sys_sdr_clk_fb, -- feedback clock + sdr_clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0° + sdr_clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270° + sdr_clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° + sdr_clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° + locked_out => dcm_lock, -- DCM locked status + error_out => open ); inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb @@ -872,25 +873,11 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb ); -inst_clkgen: entity work.clkgen - GENERIC MAP - ( - clk_in_freq_hz => sys_freq, - clk_out_freq_hz => tsvga.f_pxl_clk - ) - PORT MAP - ( - rst => rst_in, - clk_in => CLK_O, - clk_out => vga_clk, - locked => vga_clk_lock - ); - inst_vga_frontend : vga_frontend64 GENERIC MAP ( fifo_depth => 2048, - fifo_almost_full_thresh => 1860, + fifo_almost_full_thresh => 2048-128, fifo_almost_empty_thresh => 256, tsvga => tsvga ) @@ -926,7 +913,7 @@ inst_vga_frontend : vga_frontend64 -- VGA signals vga_clk_in => vga_clk, - vga_clk_ce => vga_clk_lock, + vga_clk_ce => dcm_lock, vga_red => sys_vga_red, vga_green => sys_vga_green, vga_blue => sys_vga_blue, diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd index 841d318..a0a69e7 100644 --- a/projects/mips_sys/src/mips_sys_sim.vhd +++ b/projects/mips_sys/src/mips_sys_sim.vhd @@ -357,13 +357,11 @@ ARCHITECTURE behavior OF mips_sys IS signal nmi : std_logic; signal eb : std_logic; - signal sdram_clk_lock : std_logic; signal sdram_clk0 : std_logic; signal sdram_clk270 : std_logic; signal sdram_clk270var : std_logic; signal vga_clk : std_logic; - signal vga_clk_prebuf : std_logic; - signal vga_clk_lock : std_logic; + signal dcm_lock : std_logic; signal rst_in : std_logic; signal int_timer : std_logic; signal int_uart0 : std_logic; @@ -528,8 +526,7 @@ BEGIN SEL_I_sdram <= "0000" & SEL_O; sys_flash_ac97_rstn <= ac97_rstn and flash_rstn; - CLK_O <= sys_clk_in; - RST_O <= not (sdram_clk_lock and vga_clk_lock); + RST_O <= not dcm_lock; sys_flash_ssram_out: process(CLK_O) @@ -959,24 +956,28 @@ inst_ssram_port_wb : entity work.ssram_port_wb inst_clockgen : entity work.clockgen GENERIC MAP ( - clk_in_freq_hz => 100E6, - clk0_out_phaseshift => 0, - clk1_out_phaseshift => 0 + clk_in_freq_hz => 100E6, + vga_clk_out_freq_hz => tsvga.f_pxl_clk, + sdr_clk0_out_phaseshift => 0, + sdr_clk1_out_phaseshift => 0 ) PORT MAP ( -- Clocks and Reset - rst => rst_in, -- external async reset, low active - clk_in => CLK_O, -- system clock (e.g. 100MHz), from board - clk_fb_in => sys_sdr_clk_fb, -- feedback clock - clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0° - clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270° - clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - locked_out => sdram_clk_lock, -- DCM locked status - error_out => open + rst => rst_in, -- external async reset, low active + clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board + sys_clk_out => CLK_O, + vga_clk_out => vga_clk, + sdr_clk0_fb_in => sys_sdr_clk_fb, -- feedback clock + sdr_clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0° + sdr_clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270° + sdr_clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° + sdr_clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° + locked_out => dcm_lock, -- DCM locked status + error_out => open ); + inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb GENERIC MAP ( @@ -1020,27 +1021,6 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb ); -inst_clkgen: entity work.clkgen - GENERIC MAP - ( - clk_in_freq_hz => sys_freq, - clk_out_freq_hz => tsvga.f_pxl_clk - ) - PORT MAP - ( - rst => rst_in, - clk_in => CLK_O, - clk_out => vga_clk_prebuf, - locked => vga_clk_lock - ); - - BUFG_out_clk : BUFG - port map - ( - O => vga_clk, -- Clock buffer output - I => vga_clk_prebuf -- Clock buffer input - ); - inst_vga_frontend : vga_frontend64 GENERIC MAP ( @@ -1081,7 +1061,7 @@ inst_vga_frontend : vga_frontend64 -- VGA signals vga_clk_in => vga_clk, - vga_clk_ce => vga_clk_lock, + vga_clk_ce => dcm_lock, vga_red => sys_vga_red, vga_green => sys_vga_green, vga_blue => sys_vga_blue,