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Added data mask support

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git-svn-id: http://moon:8086/svn/vhdl/trunk@22 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-02 13:26:38 +00:00
parent a2c574150f
commit 496be499fb
6 changed files with 30 additions and 6 deletions
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lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd
+5 -1
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@@ -65,6 +65,8 @@ architecture struct of tb_sdr_ctrl is
signal u_busy : std_logic; signal u_busy : std_logic;
signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal u_data_vld : std_logic; signal u_data_vld : std_logic;
signal u_req_wr : std_logic; signal u_req_wr : std_logic;
@@ -121,7 +123,9 @@ begin
u_cmd_we => u_cmd_we, u_cmd_we => u_cmd_we,
u_data_wr => u_data_w, u_data_wr => u_data_w,
u_data_rd => u_data_r, u_data_rd => u_data_r,
u_dm => u_dm, u_dm_wr_in => u_dm,
u_dm_rd_in => u_dm_rd_in,
u_dm_rd_out => u_dm_rd_out,
-- SDRAM signals -- SDRAM signals
sd_clk_p => part_clk_p, sd_clk_p => part_clk_p,
lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd
+5 -1
View File
@@ -65,6 +65,8 @@ architecture struct of tb_sdr_ctrl_fifo is
signal u_busy : std_logic; signal u_busy : std_logic;
signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal u_data_vld : std_logic; signal u_data_vld : std_logic;
signal u_req_wr : std_logic; signal u_req_wr : std_logic;
@@ -205,7 +207,9 @@ begin
u_cmd_we => u_cmd_we, u_cmd_we => u_cmd_we,
u_data_wr => u_data_w, u_data_wr => u_data_w,
u_data_rd => u_data_r, u_data_rd => u_data_r,
u_dm => u_dm, u_dm_wr_in => u_dm,
u_dm_rd_in => u_dm_rd_in,
u_dm_rd_out => u_dm_rd_out,
-- SDRAM signals -- SDRAM signals
sd_clk_p => part_clk_p, sd_clk_p => part_clk_p,
lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd
+5 -1
View File
@@ -67,6 +67,8 @@ architecture struct of tb_sdr_ctrl is
signal u_busy : std_logic; signal u_busy : std_logic;
signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal u_data_vld : std_logic; signal u_data_vld : std_logic;
signal u_req_wr : std_logic; signal u_req_wr : std_logic;
@@ -124,7 +126,9 @@ begin
u_cmd_we => u_cmd_we, u_cmd_we => u_cmd_we,
u_data_wr => u_data_w, u_data_wr => u_data_w,
u_data_rd => u_data_r, u_data_rd => u_data_r,
u_dm => u_dm, u_dm_wr_in => u_dm,
u_dm_rd_in => u_dm_rd_in,
u_dm_rd_out => u_dm_rd_out,
-- SDRAM signals -- SDRAM signals
sd_clk_p => part_clk_p, sd_clk_p => part_clk_p,
lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd
+5 -1
View File
@@ -67,6 +67,8 @@ architecture struct of tb_sdr_ctrl is
signal u_busy : std_logic; signal u_busy : std_logic;
signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal u_data_vld : std_logic; signal u_data_vld : std_logic;
signal u_req_wr : std_logic; signal u_req_wr : std_logic;
@@ -124,7 +126,9 @@ begin
u_cmd_we => u_cmd_we, u_cmd_we => u_cmd_we,
u_data_wr => u_data_w, u_data_wr => u_data_w,
u_data_rd => u_data_r, u_data_rd => u_data_r,
u_dm => u_dm, u_dm_wr_in => u_dm,
u_dm_rd_in => u_dm_rd_in,
u_dm_rd_out => u_dm_rd_out,
-- SDRAM signals -- SDRAM signals
sd_clk_p => part_clk_p, sd_clk_p => part_clk_p,
lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd
+5 -1
View File
@@ -65,6 +65,8 @@ architecture struct of tb_sdr_ctrl is
signal u_busy : std_logic; signal u_busy : std_logic;
signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal u_data_vld : std_logic; signal u_data_vld : std_logic;
signal u_req_wr : std_logic; signal u_req_wr : std_logic;
@@ -121,7 +123,9 @@ begin
u_cmd_we => u_cmd_we, u_cmd_we => u_cmd_we,
u_data_wr => u_data_w, u_data_wr => u_data_w,
u_data_rd => u_data_r, u_data_rd => u_data_r,
u_dm => u_dm, u_dm_wr_in => u_dm,
u_dm_rd_in => u_dm_rd_in,
u_dm_rd_out => u_dm_rd_out,
-- SDRAM signals -- SDRAM signals
sd_clk_p => part_clk_p, sd_clk_p => part_clk_p,
lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd
+5 -1
View File
@@ -65,6 +65,8 @@ architecture struct of tb_sdr_ctrl is
signal u_busy : std_logic; signal u_busy : std_logic;
signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal u_data_vld : std_logic; signal u_data_vld : std_logic;
signal u_req_wr : std_logic; signal u_req_wr : std_logic;
@@ -122,7 +124,9 @@ begin
u_cmd_we => u_cmd_we, u_cmd_we => u_cmd_we,
u_data_wr => u_data_w, u_data_wr => u_data_w,
u_data_rd => u_data_r, u_data_rd => u_data_r,
u_dm => u_dm, u_dm_wr_in => u_dm,
u_dm_rd_in => u_dm_rd_in,
u_dm_rd_out => u_dm_rd_out,
-- SDRAM signals -- SDRAM signals
sd_clk_p => part_clk_p, sd_clk_p => part_clk_p,