From 496be499fbdf960e1363c9661620b9b814aa6fe0 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Thu, 2 Oct 2008 13:26:38 +0000 Subject: [PATCH] Added data mask support git-svn-id: http://moon:8086/svn/vhdl/trunk@22 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd | 6 +++++- lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd | 6 +++++- lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd | 6 +++++- lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd | 6 +++++- lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd | 6 +++++- lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd | 6 +++++- 6 files changed, 30 insertions(+), 6 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd index cc18253..034215c 100644 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd +++ b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd @@ -65,6 +65,8 @@ architecture struct of tb_sdr_ctrl is signal u_busy : std_logic; signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; + signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; + signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_vld : std_logic; signal u_req_wr : std_logic; @@ -121,7 +123,9 @@ begin u_cmd_we => u_cmd_we, u_data_wr => u_data_w, u_data_rd => u_data_r, - u_dm => u_dm, + u_dm_wr_in => u_dm, + u_dm_rd_in => u_dm_rd_in, + u_dm_rd_out => u_dm_rd_out, -- SDRAM signals sd_clk_p => part_clk_p, diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd index 6a2a9da..51910b0 100644 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd +++ b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd @@ -65,6 +65,8 @@ architecture struct of tb_sdr_ctrl_fifo is signal u_busy : std_logic; signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; + signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; + signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_vld : std_logic; signal u_req_wr : std_logic; @@ -205,7 +207,9 @@ begin u_cmd_we => u_cmd_we, u_data_wr => u_data_w, u_data_rd => u_data_r, - u_dm => u_dm, + u_dm_wr_in => u_dm, + u_dm_rd_in => u_dm_rd_in, + u_dm_rd_out => u_dm_rd_out, -- SDRAM signals sd_clk_p => part_clk_p, diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd index 3ab72bd..961b58e 100644 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd +++ b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd @@ -67,6 +67,8 @@ architecture struct of tb_sdr_ctrl is signal u_busy : std_logic; signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; + signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; + signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_vld : std_logic; signal u_req_wr : std_logic; @@ -124,7 +126,9 @@ begin u_cmd_we => u_cmd_we, u_data_wr => u_data_w, u_data_rd => u_data_r, - u_dm => u_dm, + u_dm_wr_in => u_dm, + u_dm_rd_in => u_dm_rd_in, + u_dm_rd_out => u_dm_rd_out, -- SDRAM signals sd_clk_p => part_clk_p, diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd index 312d2a8..286fb33 100644 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd +++ b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd @@ -67,6 +67,8 @@ architecture struct of tb_sdr_ctrl is signal u_busy : std_logic; signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; + signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; + signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_vld : std_logic; signal u_req_wr : std_logic; @@ -124,7 +126,9 @@ begin u_cmd_we => u_cmd_we, u_data_wr => u_data_w, u_data_rd => u_data_r, - u_dm => u_dm, + u_dm_wr_in => u_dm, + u_dm_rd_in => u_dm_rd_in, + u_dm_rd_out => u_dm_rd_out, -- SDRAM signals sd_clk_p => part_clk_p, diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd index e20e4af..5f96aa3 100644 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd +++ b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd @@ -65,6 +65,8 @@ architecture struct of tb_sdr_ctrl is signal u_busy : std_logic; signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; + signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; + signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_vld : std_logic; signal u_req_wr : std_logic; @@ -121,7 +123,9 @@ begin u_cmd_we => u_cmd_we, u_data_wr => u_data_w, u_data_rd => u_data_r, - u_dm => u_dm, + u_dm_wr_in => u_dm, + u_dm_rd_in => u_dm_rd_in, + u_dm_rd_out => u_dm_rd_out, -- SDRAM signals sd_clk_p => part_clk_p, diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd index 26c8b9b..c60d600 100644 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd +++ b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd @@ -65,6 +65,8 @@ architecture struct of tb_sdr_ctrl is signal u_busy : std_logic; signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; + signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; + signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); signal u_data_vld : std_logic; signal u_req_wr : std_logic; @@ -122,7 +124,9 @@ begin u_cmd_we => u_cmd_we, u_data_wr => u_data_w, u_data_rd => u_data_r, - u_dm => u_dm, + u_dm_wr_in => u_dm, + u_dm_rd_in => u_dm_rd_in, + u_dm_rd_out => u_dm_rd_out, -- SDRAM signals sd_clk_p => part_clk_p,