- removed latch pc_branch_take with latching signal 'branch_ce'
git-svn-id: http://moon:8086/svn/vhdl/trunk@1620 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -150,7 +150,7 @@ architecture Behavioral of pipeline is
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signal sdu : sdu_t;
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signal reg_a : word_t;
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signal reg_b : word_t;
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signal branch_ce : STD_LOGIC;
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signal branch_taken : STD_LOGIC;
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signal alu_result : word_t;
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signal mul_result : word_t;
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signal mul_busy : STD_LOGIC;
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@@ -168,6 +168,18 @@ architecture Behavioral of pipeline is
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signal pipe_rst : STD_LOGIC;
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signal pc : pc_t;
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signal pc_branch : word_t;
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signal pc_curr : word_t;
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signal pc_last : word_t;
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signal pc_nxt : word_t;
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signal pc_branch_take : STD_LOGIC;
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signal ID_ctrl_branch : STD_LOGIC;
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signal EX_ctrl_branch : STD_LOGIC;
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signal MEM_ctrl_branch : STD_LOGIC;
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signal sdu_ID_stall : STD_LOGIC;
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signal sdu_ID_nop : STD_LOGIC;
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signal c0_ctrl_in_exc_pending : STD_LOGIC;
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signal c0_ctrl_in_exc_inject : STD_LOGIC;
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--------------------------------------------------------------------------
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begin
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@@ -189,7 +201,19 @@ begin
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sdu.dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en;
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---------------------------------------------------------------------------
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imem_en <= ce and not (sdu.mul_dep or sdu.dmem_dep or c0_ctrl_in.exc_commit);
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pc_branch <= pc.pc_branch;
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pc_curr <= pc.curr;
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pc_last <= pc.last;
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pc_nxt <= pc.nxt;
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pc_branch_take <= pc.branch_take;
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ID_ctrl_branch <= ID_stage.ctrl.branch;
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EX_ctrl_branch <= EX_stage.ctrl.branch;
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MEM_ctrl_branch <= MEM_stage.ctrl.branch;
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sdu_ID_stall <= sdu.ID_stall;
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sdu_ID_nop <= sdu.ID_nop;
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c0_ctrl_in_exc_pending <= c0_ctrl_in.exc_pending;
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c0_ctrl_in_exc_inject <= c0_ctrl_in.exc_inject;
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--------------------------------------------------------------------------
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-- Coprocessor assignments
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--------------------------------------------------------------------------
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@@ -263,42 +287,41 @@ proc_stage_pc_next:
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end if;
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end process;
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proc_stage_branch_ce:
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process(clk)
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proc_stage_branch:
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process(EX_stage, bcu_flags)
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begin
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if rising_edge(clk) then
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if pipe_rst = '1' then
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branch_ce <= '1';
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else
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branch_ce <= c0_ctrl_in.exc_pending;
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if sdu.ID_stall = '0' and c0_ctrl_in.exc_inject = '0' then
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branch_ce <= '1';
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end if;
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end if;
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pc.branch_take <= '0';
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if EX_stage.ctrl.branch = '1' then
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case EX_stage.ctrl.bc_src is
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when bc_eq_ne =>
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pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.eq;
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when bc_lez_gtz =>
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pc.branch_take <= EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz);
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when bc_ltz_gez =>
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pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.ltz;
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when others => null;
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end case;
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end if;
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end process;
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proc_stage_branch:
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process(EX_stage, bcu_flags, branch_ce)
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proc_stage_branch_taken:
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process(clk)
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begin
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if branch_ce = '1' then
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pc.branch_take <= '0';
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if EX_stage.ctrl.branch = '1' then
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case EX_stage.ctrl.bc_src is
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when bc_eq_ne =>
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pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.eq;
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when bc_lez_gtz =>
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pc.branch_take <= EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz);
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when bc_ltz_gez =>
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pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.ltz;
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when others => null;
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end case;
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end if;
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if rising_edge(clk) then
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if branch_taken = '0' then
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if sdu.ID_stall = '1' or c0_ctrl_in.exc_inject = '1' then
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if pc.branch_take = '1' then
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branch_taken <= '1';
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end if;
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end if;
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elsif sdu.ID_stall = '0' then
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branch_taken <= '0';
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end if;
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end if;
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end process;
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@@ -306,16 +329,16 @@ proc_stage_pc_branch:
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process(clk)
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begin
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if rising_edge(clk) then
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if sdu.ID_stall = '0' then
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if sdu.ID_stall = '0' and ID_stage.ctrl.branch = '1' then
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pc.pc_branch <= pc.curr + ID_stage.bimm18;
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end if;
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end if;
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end process;
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proc_stage_pc:
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process(pc)
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process(pc, branch_taken)
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begin
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if pc.branch_take = '1' then
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if pc.branch_take = '1' or branch_taken = '1' then
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pc.curr <= pc.pc_branch;
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else
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pc.curr <= pc.nxt;
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