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- removed latch pc_branch_take with latching signal 'branch_ce'

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1620 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-04-02 13:28:11 +00:00
parent 8e7477b83b
commit 484940f8de
1 changed files with 59 additions and 36 deletions
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lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+59 -36
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@@ -150,7 +150,7 @@ architecture Behavioral of pipeline is
signal sdu : sdu_t; signal sdu : sdu_t;
signal reg_a : word_t; signal reg_a : word_t;
signal reg_b : word_t; signal reg_b : word_t;
signal branch_ce : STD_LOGIC; signal branch_taken : STD_LOGIC;
signal alu_result : word_t; signal alu_result : word_t;
signal mul_result : word_t; signal mul_result : word_t;
signal mul_busy : STD_LOGIC; signal mul_busy : STD_LOGIC;
@@ -168,6 +168,18 @@ architecture Behavioral of pipeline is
signal pipe_rst : STD_LOGIC; signal pipe_rst : STD_LOGIC;
signal pc : pc_t; signal pc : pc_t;
signal pc_branch : word_t;
signal pc_curr : word_t;
signal pc_last : word_t;
signal pc_nxt : word_t;
signal pc_branch_take : STD_LOGIC;
signal ID_ctrl_branch : STD_LOGIC;
signal EX_ctrl_branch : STD_LOGIC;
signal MEM_ctrl_branch : STD_LOGIC;
signal sdu_ID_stall : STD_LOGIC;
signal sdu_ID_nop : STD_LOGIC;
signal c0_ctrl_in_exc_pending : STD_LOGIC;
signal c0_ctrl_in_exc_inject : STD_LOGIC;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
begin begin
@@ -189,7 +201,19 @@ begin
sdu.dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en; sdu.dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
imem_en <= ce and not (sdu.mul_dep or sdu.dmem_dep or c0_ctrl_in.exc_commit); imem_en <= ce and not (sdu.mul_dep or sdu.dmem_dep or c0_ctrl_in.exc_commit);
pc_branch <= pc.pc_branch;
pc_curr <= pc.curr;
pc_last <= pc.last;
pc_nxt <= pc.nxt;
pc_branch_take <= pc.branch_take;
ID_ctrl_branch <= ID_stage.ctrl.branch;
EX_ctrl_branch <= EX_stage.ctrl.branch;
MEM_ctrl_branch <= MEM_stage.ctrl.branch;
sdu_ID_stall <= sdu.ID_stall;
sdu_ID_nop <= sdu.ID_nop;
c0_ctrl_in_exc_pending <= c0_ctrl_in.exc_pending;
c0_ctrl_in_exc_inject <= c0_ctrl_in.exc_inject;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
-- Coprocessor assignments -- Coprocessor assignments
-------------------------------------------------------------------------- --------------------------------------------------------------------------
@@ -263,42 +287,41 @@ proc_stage_pc_next:
end if; end if;
end process; end process;
proc_stage_branch_ce: proc_stage_branch:
process(clk) process(EX_stage, bcu_flags)
begin begin
if rising_edge(clk) then pc.branch_take <= '0';
if pipe_rst = '1' then if EX_stage.ctrl.branch = '1' then
branch_ce <= '1';
else case EX_stage.ctrl.bc_src is
branch_ce <= c0_ctrl_in.exc_pending;
if sdu.ID_stall = '0' and c0_ctrl_in.exc_inject = '0' then when bc_eq_ne =>
branch_ce <= '1'; pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.eq;
end if;
end if; when bc_lez_gtz =>
pc.branch_take <= EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz);
when bc_ltz_gez =>
pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.ltz;
when others => null;
end case;
end if; end if;
end process; end process;
proc_stage_branch: proc_stage_branch_taken:
process(EX_stage, bcu_flags, branch_ce) process(clk)
begin begin
if branch_ce = '1' then if rising_edge(clk) then
pc.branch_take <= '0'; if branch_taken = '0' then
if EX_stage.ctrl.branch = '1' then if sdu.ID_stall = '1' or c0_ctrl_in.exc_inject = '1' then
if pc.branch_take = '1' then
case EX_stage.ctrl.bc_src is branch_taken <= '1';
end if;
when bc_eq_ne => end if;
pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.eq; elsif sdu.ID_stall = '0' then
branch_taken <= '0';
when bc_lez_gtz => end if;
pc.branch_take <= EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz);
when bc_ltz_gez =>
pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.ltz;
when others => null;
end case;
end if;
end if; end if;
end process; end process;
@@ -306,16 +329,16 @@ proc_stage_pc_branch:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if sdu.ID_stall = '0' then if sdu.ID_stall = '0' and ID_stage.ctrl.branch = '1' then
pc.pc_branch <= pc.curr + ID_stage.bimm18; pc.pc_branch <= pc.curr + ID_stage.bimm18;
end if; end if;
end if; end if;
end process; end process;
proc_stage_pc: proc_stage_pc:
process(pc) process(pc, branch_taken)
begin begin
if pc.branch_take = '1' then if pc.branch_take = '1' or branch_taken = '1' then
pc.curr <= pc.pc_branch; pc.curr <= pc.pc_branch;
else else
pc.curr <= pc.nxt; pc.curr <= pc.nxt;