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git-svn-id: http://moon:8086/svn/vhdl/trunk@1525 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2021-03-24 16:57:19 +00:00
parent c4cf1e850b
commit 47ec6a20ee
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lib/JBUS/src/async_port/async_port_wb.vhd
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-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010/02/09 09:56:37 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.async_types.all;
------------------------------------------------------------------
entity async_port_wb is
Generic
(
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
page_mode_en : in STD_LOGIC;
async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic;
async_wr : out std_logic;
async_rd : out std_logic;
async_be : out unsigned(byte_sel_width-1 downto 0);
async_rst : out std_logic
);
end async_port_wb;
architecture Behavioral of async_port_wb is
type async_t is record
cs : std_logic;
wr : std_logic;
rd : std_logic;
rst : std_logic;
drive_d : std_logic;
end record;
type async_state_t is (start, reset, idle, leadin, pulse, leadout, release);
signal s, sn : async_state_t;
signal as : async_t;
signal ack : std_logic;
signal cc_rst : std_logic;
signal cycle_cnt : natural range 0 to 31;
signal cycle_reload : natural range 0 to 31;
signal rdy : std_logic;
signal rdyo : std_logic;
signal en : std_logic;
signal is_idle : std_logic;
signal DAT_I_r : unsigned(data_width-1 downto 0);
signal SEL_I_r : unsigned(byte_sel_width-1 downto 0);
signal WE_I_r : std_logic;
signal ADDR_I_r : unsigned(addr_width-1 downto 0);
signal page_mode_en_r : std_logic;
signal do_page_read : std_logic;
------------------------------------------------------------------
begin
ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk) > 0 report "Read pulse length must be greater than zero!" severity failure;
ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk) > 0 report "Write pulse length must be greater than zero!" severity failure;
ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) > 1)) report "Read page pulse length must be greater than one!" severity failure;
SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I;
do_page_read <= '1' when (async_timespec.can_page_rd and (WE_I = '0') and (WE_I_r = '0') and (ADDR_I(addr_width-1 downto async_timespec.nbits_page_rd) = ADDR_I_r(addr_width-1 downto async_timespec.nbits_page_rd))) else '0';
proc_cycle_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if cc_rst = '1' then
cycle_cnt <= cycle_reload;
elsif cycle_cnt /= 0 then
cycle_cnt <= cycle_cnt - 1;
end if;
end if;
end process;
------------------------------------------------------------------
proc_state_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
s <= start;
else
s <= sn;
end if;
end if;
end process;
proc_state:
process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read)
begin
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
cc_rst <= '0';
as.rst <= '0';
as.cs <= '0';
as.wr <= '0';
as.rd <= '0';
as.drive_d <= '0';
ack <= '0';
rdy <= '0';
is_idle <= '0';
sn <= s;
case s is
when start =>
cc_rst <= '1';
sn <= reset;
when reset =>
as.rst <= '1';
if cycle_cnt = 0 then
sn <= idle;
end if;
when idle =>
rdy <= '1';
is_idle <= '1';
if en = '1' then
as.cs <= '1';
cc_rst <= '1';
if to_cycles(async_timespec.T_leadin, f_sysclk) = 0 then
sn <= pulse;
if WE_I = '1' then
cycle_reload <= 0;
sn <= leadin; -- always lead-in for writes
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
as.rd <= '1';
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk) - 1;
sn <= leadin;
end if;
end if;
when leadin =>
as.cs <= '1';
as.rd <= not WE_I_r;
as.drive_d <= WE_I_r;
as.wr <= WE_I_r;
if cycle_cnt = 0 then
cc_rst <= '1';
sn <= pulse;
if WE_I_r = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk) - 1;
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
end if;
end if;
when pulse =>
as.cs <= '1';
as.rd <= not WE_I_r;
as.drive_d <= WE_I_r;
as.wr <= WE_I_r;
if cycle_cnt = 0 then
as.wr <= '0';
cc_rst <= '1';
ack <= not WE_I_r;
rdy <= do_page_read;
if en = '1' and do_page_read = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) - 1;
sn <= pulse;
elsif to_cycles(async_timespec.T_leadout, f_sysclk) = 0 then
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
sn <= release;
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk) - 1;
sn <= leadout;
end if;
end if;
when leadout =>
as.cs <= '1';
as.drive_d <= WE_I_r;
if cycle_cnt = 0 then
cc_rst <= '1';
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
sn <= release;
end if;
end if;
when release =>
if cycle_cnt = 0 then
sn <= idle;
end if;
when others =>
sn <= idle;
end case;
end process;
------------------------------------------------------------------
output_ctrl:
process(CLK_I)
begin
if rising_edge(CLK_I) then
async_cs <= (not async_timespec.pol_cs) xor as.cs;
async_wr <= (not async_timespec.pol_we) xor as.wr;
async_rd <= (not async_timespec.pol_oe) xor as.rd;
async_rst <= (not async_timespec.pol_rst) xor as.rst;
end if;
end process;
------------------------------------------------------------------
din_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if as.rd = '1' then
DAT_O(data_width-1 downto 0) <= async_d;
end if;
end if;
end process;
------------------------------------------------------------------
output_addr:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
async_a <= (others => '0');
SEL_I_r <= (others => '0');
elsif en = '1' and rdy = '1' then
async_a <= ADDR_I(addr_width-1 downto 0);
async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I(byte_sel_width-1 downto 0));
SEL_I_r <= SEL_I(byte_sel_width-1 downto 0);
if is_idle = '1' then
ADDR_I_r <= ADDR_I(addr_width-1 downto 0);
end if;
end if;
end if;
end process;
------------------------------------------------------------------
data_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
page_mode_en_r <= page_mode_en;
if en = '1' and rdy = '1' then
DAT_I_r <= DAT_I(data_width-1 downto 0);
WE_I_r <= WE_I;
end if;
end if;
end process;
------------------------------------------------------------------
output_SRDY:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
rdyo <= '1';
elsif en = '1' then
rdyo <= rdy and not rdyo;
end if;
end if;
end process;
------------------------------------------------------------------
output_ACK:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= ack;
end if;
end if;
end process;
------------------------------------------------------------------
output_data:
process(CLK_I)
begin
if rising_edge(CLK_I) then
async_d <= (others => 'Z');
if as.drive_d = '1' then
async_d <= DAT_I_r;
end if;
end if;
end process;
------------------------------------------------------------------
end Behavioral;
lib/JBUS/src/async_port/async_types.vhd
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-------------------------------------------------------------------------
-- Project: MIPS System controller
-- This file:
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.MATH_REAL.ALL;
package async_types is
type async_timespec_t is record
T_leadin : real;
T_pulse_rd : real;
T_pulse_wr : real;
T_leadout : real;
T_release : real;
T_pulse_rst : real;
T_pulse_page_rd : real;
can_page_rd : boolean;
nbits_page_rd : natural;
pol_cs : std_logic;
pol_oe : std_logic;
pol_we : std_logic;
pol_be : std_logic;
pol_rst : std_logic;
end record;
function to_cycles(T_ns : real; f_Mhz : real) return natural;
end async_types;
package body async_types is
function to_cycles(T_ns : real; f_Mhz : real) return natural is
begin
return natural(ceil(1.0E-3*T_ns*f_Mhz));
end to_cycles;
end async_types;
lib/JBUS/src/flash_port/flash_port_wb.vhd
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-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/misc/flash_port_wb.vhd,v 1.2 2010/03/13 11:06:43 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.async_types.all;
------------------------------------------------------------------
entity flash_port_wb is
Generic
(
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
async_timespec : async_timespec_t
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
port_bsyi : in std_logic;
port_bsyo : out std_logic;
port_a : out unsigned(addr_width-1 downto 0);
port_di : in unsigned(data_width-1 downto 0);
port_do : out unsigned(data_width-1 downto 0);
port_d_drv : out STD_LOGIC;
port_wr : out STD_LOGIC;
port_rd : out STD_LOGIC;
flash_cs : out std_logic;
flash_rst : out std_logic
);
end flash_port_wb;
architecture Behavioral of flash_port_wb is
type async_t is record
cs : std_logic;
wr : std_logic;
rd : std_logic;
rst : std_logic;
drive_d : std_logic;
end record;
type async_state_t is (start, reset, idle, go, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
signal s, sn : async_state_t;
signal as : async_t;
signal ack : std_logic;
signal cc_rst : std_logic;
signal cycle_cnt : natural range 0 to 31;
signal cycle_reload : natural range 0 to 31;
signal rdy : std_logic;
signal rdyo : std_logic;
signal en : std_logic;
signal we_reg : std_logic;
signal data_reg : unsigned(data_width-1 downto 0);
signal addr_reg : unsigned(addr_width-1 downto 0);
------------------------------------------------------------------
begin
SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I;
port_a <= addr_reg;
port_do <= data_reg;
port_d_drv <= as.drive_d;
port_wr <= (not async_timespec.pol_we) xor as.wr;
port_rd <= (not async_timespec.pol_oe) xor as.rd;
proc_cycle_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if cc_rst = '1' then
cycle_cnt <= cycle_reload;
elsif cycle_cnt /= 0 then
cycle_cnt <= cycle_cnt - 1;
end if;
end if;
end process;
------------------------------------------------------------------
proc_state_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
s <= start;
else
s <= sn;
end if;
end if;
end process;
proc_state:
process(s, cycle_cnt, en, we_reg, port_bsyi)
begin
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
cc_rst <= '0';
as.rst <= '0';
as.cs <= '0';
as.wr <= '0';
as.rd <= '0';
as.drive_d <= '0';
ack <= '0';
rdy <= '0';
port_bsyo <= '1';
sn <= s;
case s is
when start =>
cc_rst <= '1';
sn <= reset;
when reset =>
as.rst <= '1';
if cycle_cnt = 0 then
sn <= idle;
end if;
when idle =>
port_bsyo <= '0';
rdy <= '1';
if en = '1' then
sn <= go;
end if;
when go =>
port_bsyo <= '0';
if port_bsyi = '0' then
as.cs <= '1';
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk)-1;
if we_reg = '0' then
sn <= leadin_rd;
else
sn <= leadin_wr;
end if;
end if;
when leadin_rd =>
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk)-1;
as.rd <= '1';
sn <= read;
end if;
when leadin_wr =>
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk)-1;
as.wr <= '1';
as.drive_d <= '1';
sn <= write;
end if;
when read =>
as.cs <= '1';
as.rd <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
-- as.rd <= '0';
sn <= leadout_rd;
ack <= '1';
end if;
when write =>
as.drive_d <= '1';
as.cs <= '1';
as.wr <= '1';
if cycle_cnt = 0 then
as.wr <= '0';
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
sn <= leadout_wr;
-- ack <= '1';
end if;
when leadout_rd =>
as.cs <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
sn <= release;
as.cs <= '0';
end if;
when leadout_wr =>
as.cs <= '1';
as.drive_d <= '1';
if cycle_cnt = 0 then
cc_rst <= '1';
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
sn <= release;
as.cs <= '0';
end if;
when release =>
if cycle_cnt = 0 then
sn <= idle;
end if;
when others =>
sn <= idle;
end case;
end process;
------------------------------------------------------------------
output_ctrl:
process(CLK_I)
begin
if rising_edge(CLK_I) then
flash_cs <= (not async_timespec.pol_cs) xor as.cs;
flash_rst <= (not async_timespec.pol_rst) xor as.rst;
end if;
end process;
------------------------------------------------------------------
din_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if as.rd = '1' then
DAT_O(data_width-1 downto 0) <= port_di;
end if;
end if;
end process;
------------------------------------------------------------------
data_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if en = '1' and rdy = '1' then
we_reg <= WE_I;
data_reg <= DAT_I(data_width-1 downto 0);
end if;
end if;
end process;
------------------------------------------------------------------
addr_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if en = '1' and rdy = '1' then
addr_reg <= ADDR_I(addr_width-1 downto 0);
end if;
end if;
end process;
------------------------------------------------------------------
output_SRDY:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
rdyo <= '1';
elsif en = '1' then
rdyo <= rdy and not rdyo;
end if;
end if;
end process;
------------------------------------------------------------------
output_ACK:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= ack;
end if;
end if;
end process;
------------------------------------------------------------------
end Behavioral;
lib/JBUS/src/gpio/gpio_wb.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY gpio_wb IS
Generic
(
f_sysclk : real := 100.0
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
INT_TIM_O : out STD_LOGIC;
sys_gpi_0 : in unsigned(31 downto 0);
sys_gpo_0 : out unsigned(31 downto 0)
);
END gpio_wb;
ARCHITECTURE behavior OF gpio_wb IS
constant num_timers : natural := 2;
constant ncycles_usec : natural := natural(f_sysclk);
signal gpio_0_dout_reg : unsigned(31 downto 0);
signal gpio_0_dir_reg : unsigned(31 downto 0);
signal gpio_0_din_reg : unsigned(31 downto 0);
-- Signals to form an timer generating an interrupt every microsecond
subtype tick_usec_t is natural range 0 to ncycles_usec-1;
signal tick_usec : tick_usec_t := 0;
signal cnt_usec : unsigned(31 downto 0);
signal cnt_sec : unsigned(31 downto 0);
signal cnt_usec_preset : unsigned(31 downto 0);
signal cnt_sec_preset : unsigned(31 downto 0);
signal cnt_usec_en : std_logic;
signal cnt_usec_we : std_logic;
signal cnt_sec_en : std_logic;
signal cnt_sec_we : std_logic;
type timer_array_t is array (0 to num_timers-1) of unsigned(31 downto 0);
signal timer_cnt : timer_array_t;
signal timer_cmp : timer_array_t;
signal timer_en : unsigned(0 to num_timers-1);
signal timer_inten : unsigned(0 to num_timers-1);
signal timer_irq : unsigned(0 to num_timers-1);
signal timer_ovl : unsigned(0 to num_timers-1);
signal timer_irq_ack : unsigned(0 to num_timers-1);
signal timer_cnt_we : unsigned(0 to num_timers-1);
signal timer_cmp_we : unsigned(0 to num_timers-1);
signal reg_data_wr : unsigned(31 downto 0);
begin
SRDY_O <= CYC_I;
tim_irq:
process(timer_irq)
variable irq : std_logic;
begin
irq := '0';
for i in 0 to num_timers-1 loop
irq := irq or timer_irq(i);
end loop;
INT_TIM_O <= irq;
end process;
------------------------------------------------------------------
gpio_0_out:
process(gpio_0_dir_reg, gpio_0_dout_reg)
begin
for i in 0 to 31 loop
sys_gpo_0(i) <= 'Z';
if gpio_0_dir_reg(i) = '1' then
sys_gpo_0(i) <= gpio_0_dout_reg(i);
end if;
end loop;
end process;
------------------------------------------------------------------
gpio_0_in:
process(CLK_I)
begin
if rising_edge(CLK_I) then
for i in 0 to 31 loop
if gpio_0_dir_reg(i) = '1' then
gpio_0_din_reg(i) <= gpio_0_dout_reg(i);
else
gpio_0_din_reg(i) <= sys_gpi_0(i);
end if;
end loop;
end if;
end process;
------------------------------------------------------------------
registers_write:
process(CLK_I)
begin
if rising_edge(CLK_I) then
cnt_usec_we <= '0';
cnt_sec_we <= '0';
timer_cnt_we <= (others => '0');
timer_cmp_we <= (others => '0');
timer_irq_ack <= (others => '0');
if RST_I = '1' then
gpio_0_dout_reg <= (others => '0');
gpio_0_dir_reg <= (others => '0');
timer_en <= (others => '0');
timer_inten <= (others => '0');
elsif (STB_I and CYC_I and WE_I) = '1' then
reg_data_wr <= DAT_I;
case ADDR_I(6 downto 2) is
when "00000" =>
gpio_0_dout_reg <= DAT_I;
when "00001" =>
gpio_0_dir_reg <= DAT_I;
when "00010" =>
cnt_usec_we <= '1';
when "00011" =>
cnt_sec_we <= '1';
when "00110" => -- timer control
for i in 0 to num_timers-1 loop
timer_en(i) <= DAT_I(2*i+0);
timer_inten(i) <= DAT_I(2*i+1);
end loop;
when "00111" => -- timer status
for i in 0 to num_timers-1 loop
timer_irq_ack(i) <= DAT_I(2*i); -- IRQ acknowledge
end loop;
when "01000" => -- timer count 0
timer_cnt_we(0) <= '1';
when "01001" => -- timer count 1
timer_cnt_we(1) <= '1';
when "01100" => -- timer compare 0
timer_cmp_we(0) <= '1';
when "01101" => -- timer compare 1
timer_cmp_we(1) <= '1';
when others => null;
end case;
end if;
end if;
end process;
registers_read:
process(CLK_I)
begin
if rising_edge(CLK_I) then
ACK_O <= '0';
if (STB_I and CYC_I) = '1' then
ACK_O <= not WE_I;
DAT_O <= (others => '0');
case ADDR_I(6 downto 2) is
when "00000" =>
DAT_O <= gpio_0_din_reg;
when "00001" =>
DAT_O <= gpio_0_dir_reg;
when "00010" =>
DAT_O <= cnt_usec;
when "00011" =>
DAT_O <= cnt_sec;
when "00110" => -- timer control
for i in 0 to num_timers-1 loop
DAT_O(2*i+0) <= timer_en(i);
DAT_O(2*i+1) <= timer_inten(i);
end loop;
when "00111" => -- timer status
for i in 0 to num_timers-1 loop
DAT_O(2*i+0) <= timer_irq(i);
DAT_O(2*i+1) <= timer_ovl(i);
end loop;
when "01000" => -- timer count 0
DAT_O <= timer_cnt(0);
when "01001" => -- timer count 1
DAT_O <= timer_cnt(1);
when "01100" => -- timer compare 0
DAT_O <= timer_cmp(0);
when "01101" => -- timer compare 1
DAT_O <= timer_cmp(1);
when others => null;
end case;
end if;
end if;
end process;
cnt_usec_tick:
process(CLK_I)
begin
if rising_edge(CLK_I) then
cnt_usec_en <= '0';
if tick_usec >= tick_usec_t'high then
tick_usec <= 0;
cnt_usec_en <= '1';
else
tick_usec <= tick_usec + 1;
end if;
end if;
end process;
-- H/W Clock
cnt_usec_clock:
process(CLK_I)
begin
if rising_edge(CLK_I) then
cnt_sec_en <= '0';
if cnt_usec_we = '1' then
cnt_usec <= reg_data_wr;
elsif cnt_usec_en = '1' then
if to_01(cnt_usec) >= to_unsigned(1E6 - 1, 32) then
cnt_usec <= (others => '0');
cnt_sec_en <= '1';
else
cnt_usec <= cnt_usec + 1;
end if;
end if;
end if;
end process;
cnt_sec_clock:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if cnt_sec_we = '1' then
cnt_sec <= reg_data_wr;
elsif cnt_sec_en = '1' then
cnt_sec <= cnt_sec + 1;
end if;
end if;
end process;
-- Interrupt timer
proc_int_timer:
process(CLK_I)
begin
if rising_edge(CLK_I) then
for i in 0 to num_timers-1 loop
if RST_I = '1' then
timer_ovl(i) <= '0';
timer_irq(i) <= '0';
elsif timer_irq_ack(i) = '1' then
timer_ovl(i) <= '0';
timer_irq(i) <= '0';
elsif timer_cnt_we(i) = '1' then
timer_cnt(i) <= reg_data_wr;
elsif timer_en(i) = '1' then
if to_01(timer_cnt(i)) >= timer_cmp(i) then
timer_cnt(i) <= (others => '0');
if timer_inten(i) = '1' then
if timer_irq(i) = '1' then
timer_ovl(i) <= '1';
end if;
timer_irq(i) <= '1';
end if;
else
timer_cnt(i) <= timer_cnt(i) + 1;
end if;
end if;
end loop;
end if;
end process;
proc_int_timer_reload:
process(CLK_I)
begin
if rising_edge(CLK_I) then
for i in 0 to num_timers-1 loop
if timer_cmp_we(i) = '1' then
timer_cmp(i) <= reg_data_wr;
end if;
end loop;
end if;
end process;
------------------------------------------------------------------
end behavior;
lib/JBUS/src/memory/ram_wb.vhd
+126
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
library work;
use work.utils_pkg.all;
ENTITY ram_wb IS
GENERIC
(
NUM_WORDS : integer := 64
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0)
);
END ram_wb;
ARCHITECTURE behavior OF ram_wb IS
constant addr_width : natural := NextExpBaseTwo(NUM_WORDS);
signal ram_en : std_logic;
signal we : unsigned(3 downto 0);
signal re : std_logic;
begin
SRDY_O <= CYC_I;
ram_en <= CYC_I and STB_I and MRDY_I;
we <= SEL_I and (3 downto 0 => ram_en and WE_I);
re <= ram_en and not WE_I;
data_valid_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= re;
end if;
end if;
end process;
inst_ram_0 : entity work.dpram_1w1r1c_ra
GENERIC MAP
(
addr_width => addr_width,
data_width => 8
)
PORT MAP
(
clk => CLK_I,
we_a => we(0),
re_b => '1',
addr_a => ADDR_I(addr_width+1 downto 2),
addr_b => ADDR_I(addr_width+1 downto 2),
din_a => DAT_I(7 downto 0),
dout_b => DAT_O(7 downto 0)
);
inst_ram_1 : entity work.dpram_1w1r1c_ra
GENERIC MAP
(
addr_width => addr_width,
data_width => 8
)
PORT MAP
(
clk => CLK_I,
we_a => we(1),
re_b => '1',
addr_a => ADDR_I(addr_width+1 downto 2),
addr_b => ADDR_I(addr_width+1 downto 2),
din_a => DAT_I(15 downto 8),
dout_b => DAT_O(15 downto 8)
);
inst_ram_2 : entity work.dpram_1w1r1c_ra
GENERIC MAP
(
addr_width => addr_width,
data_width => 8
)
PORT MAP
(
clk => CLK_I,
we_a => we(2),
re_b => '1',
addr_a => ADDR_I(addr_width+1 downto 2),
addr_b => ADDR_I(addr_width+1 downto 2),
din_a => DAT_I(23 downto 16),
dout_b => DAT_O(23 downto 16)
);
inst_ram_3 : entity work.dpram_1w1r1c_ra
GENERIC MAP
(
addr_width => addr_width,
data_width => 8
)
PORT MAP
(
clk => CLK_I,
we_a => we(3),
re_b => '1',
addr_a => ADDR_I(addr_width+1 downto 2),
addr_b => ADDR_I(addr_width+1 downto 2),
din_a => DAT_I(31 downto 24),
dout_b => DAT_O(31 downto 24)
);
end behavior;
lib/JBUS/src/memory/rom_wb.vhd
+62
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY rom_wb IS
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SRDY_O : out STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0)
);
END rom_wb;
ARCHITECTURE behavior OF rom_wb IS
COMPONENT rom
PORT
(
clk : in STD_LOGIC;
ce : in STD_LOGIC;
addr : in unsigned(31 downto 0);
dout : out unsigned(31 downto 0)
);
END COMPONENT;
signal data_en : std_logic;
begin
data_en <= CYC_I and STB_I and MRDY_I;
SRDY_O <= CYC_I;
data_valid_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= data_en and not WE_I;
end if;
end if;
end process;
inst_rom : rom
PORT MAP
(
clk => CLK_I,
ce => data_en,
addr => ADDR_I,
dout => DAT_O
);
end behavior;
lib/JBUS/src/memory/tb_ram_wb.vhd
+414
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@@ -0,0 +1,414 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for system test using Xilinx ML-402
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
ENTITY tb_ram_wb IS
END tb_ram_wb;
ARCHITECTURE behavior OF tb_ram_wb IS
constant CLK_PERIOD : time := 10 ns;
constant RAM_NUM_WORDS : integer := 256;
signal CLK_O : std_logic := '1';
signal RST_O : std_logic := '1';
signal CYC_O : std_logic := '0';
signal STB_O : std_logic := '0';
signal WE_O : std_logic := '0';
signal SEL_O : unsigned(3 downto 0) := (others => '1');
signal ACK_I : std_logic;
signal MRDY_O : std_logic := '1';
signal SRDY_I : std_logic;
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(31 downto 0);
signal DAT_O : unsigned(31 downto 0) := (others => '-');
signal dout_rst : std_logic := '0';
signal dout_reg : unsigned(31 downto 0);
signal dout_cnt : natural range 0 to 255;
BEGIN
inst_ram_wb : entity work.ram_wb
GENERIC MAP
(
NUM_WORDS => RAM_NUM_WORDS
)
PORT MAP
(
RST_I => RST_O,
CLK_I => CLK_O,
CYC_I => CYC_O,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_I
);
read_register:
process(CLK_O)
begin
if rising_edge(CLK_O) then
if dout_rst = '1' then
dout_cnt <= 0;
elsif ACK_I = '1' and WE_O = '0' then
dout_reg <= DAT_I;
dout_cnt <= dout_cnt + 1;
end if;
end if;
end process;
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
CLK_O <= not CLK_O;
end process;
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
RST_O <= '0';
-- 8 single cycles
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
DAT_O <= X"1234_CAF0";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
DAT_O <= DAT_O + 1;
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
-- 8-word burst cycle
wait for 3*CLK_PERIOD;
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 7;
CYC_O <= '0';
wait for 3*CLK_PERIOD;
wait until rising_edge(CLK_O);
-- 1-word burst cycle
CYC_O <= '1';
STB_O <= '1';
WE_O <= '1';
SEL_O <= "0011";
ADDR_O <= X"0000_0080";
DAT_O <= X"DEADBEEF";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
wait for 3*CLK_PERIOD;
wait until rising_edge(CLK_O);
-- 1-word burst cycle
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0080";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O);
CYC_O <= '0';
-- 8-word burst cycle
wait for 3*CLK_PERIOD;
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
MRDY_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
MRDY_O <= '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 54;
CYC_O <= '0';
wait;
end process;
END;
lib/JBUS/src/memory/tb_rom_wb.vhd
+224
View File
@@ -0,0 +1,224 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for system test using Xilinx ML-402
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
ENTITY tb_rom_wb IS
END tb_rom_wb;
ARCHITECTURE behavior OF tb_rom_wb IS
constant CLK_PERIOD : time := 10 ns;
signal CLK_O : std_logic := '1';
signal RST_O : std_logic := '1';
signal CYC_O : std_logic := '0';
signal STB_O : std_logic := '0';
signal ACK_I : std_logic;
signal MRDY_O : std_logic := '1';
signal SRDY_I : std_logic;
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(31 downto 0);
signal dout_rst : std_logic := '0';
signal dout_reg : unsigned(31 downto 0);
signal dout_cnt : natural range 0 to 255;
BEGIN
inst_rom_wb : entity work.rom_wb
PORT MAP
(
RST_I => RST_O,
CLK_I => CLK_O,
CYC_I => CYC_O,
STB_I => STB_O,
WE_I => '0',
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_O => DAT_I
);
read_register:
process(CLK_O)
begin
if rising_edge(CLK_O) then
if dout_rst = '1' then
dout_cnt <= 0;
elsif ACK_I = '1' then
dout_reg <= DAT_I;
dout_cnt <= dout_cnt + 1;
end if;
end if;
end process;
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
CLK_O <= not CLK_O;
end process;
STIMULUS: process
begin
wait for 3*CLK_PERIOD;
RST_O <= '0';
-- 8-word burst cycle
wait for 3*CLK_PERIOD;
dout_rst <= '1';
wait until rising_edge(CLK_O);
dout_rst <= '0';
CYC_O <= '1';
STB_O <= '1';
ADDR_O <= X"0000_0180";
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
MRDY_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
MRDY_O <= '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= ADDR_O + 4;
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and dout_cnt = 54;
CYC_O <= '0';
wait;
end process;
END;