jens
47ec6a20ee
git-svn-id: http://moon:8086/svn/vhdl/trunk@1525 cc03376c-175c-47c8-b038-4cd826a8556b
225 lines
6.7 KiB
VHDL
225 lines
6.7 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: testbench for system test using Xilinx ML-402
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-- Copyright (C) 2007 J. Ahrensfeld
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-----------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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ENTITY tb_rom_wb IS
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END tb_rom_wb;
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ARCHITECTURE behavior OF tb_rom_wb IS
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constant CLK_PERIOD : time := 10 ns;
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signal CLK_O : std_logic := '1';
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signal RST_O : std_logic := '1';
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signal CYC_O : std_logic := '0';
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signal STB_O : std_logic := '0';
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signal ACK_I : std_logic;
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signal MRDY_O : std_logic := '1';
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signal SRDY_I : std_logic;
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signal ADDR_O : unsigned(31 downto 0) := (others => '-');
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signal DAT_I : unsigned(31 downto 0);
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signal dout_rst : std_logic := '0';
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signal dout_reg : unsigned(31 downto 0);
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signal dout_cnt : natural range 0 to 255;
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BEGIN
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inst_rom_wb : entity work.rom_wb
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PORT MAP
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(
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RST_I => RST_O,
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CLK_I => CLK_O,
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CYC_I => CYC_O,
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STB_I => STB_O,
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WE_I => '0',
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ACK_O => ACK_I,
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SRDY_O => SRDY_I,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_O => DAT_I
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);
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read_register:
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process(CLK_O)
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begin
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if rising_edge(CLK_O) then
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if dout_rst = '1' then
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dout_cnt <= 0;
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elsif ACK_I = '1' then
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dout_reg <= DAT_I;
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dout_cnt <= dout_cnt + 1;
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end if;
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end if;
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end process;
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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CLK_O <= not CLK_O;
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end process;
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STIMULUS: process
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begin
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wait for 3*CLK_PERIOD;
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RST_O <= '0';
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-- 8-word burst cycle
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wait for 3*CLK_PERIOD;
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dout_rst <= '1';
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wait until rising_edge(CLK_O);
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dout_rst <= '0';
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CYC_O <= '1';
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STB_O <= '1';
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ADDR_O <= X"0000_0180";
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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STB_O <= '0';
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MRDY_O <= '0';
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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STB_O <= '1';
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MRDY_O <= '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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ADDR_O <= ADDR_O + 4;
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wait until rising_edge(CLK_O) and SRDY_I = '1';
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STB_O <= '0';
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wait until rising_edge(CLK_O) and dout_cnt = 54;
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CYC_O <= '0';
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wait;
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end process;
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END;
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