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- simplified PHY control signals

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- revert apparent BURST fix

git-svn-id: http://moon:8086/svn/vhdl/trunk@1260 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-30 08:31:08 +00:00
parent b2c5bcb279
commit 4646c2ef34
4 changed files with 72 additions and 79 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+19 -26
View File
@@ -57,7 +57,6 @@ architecture behaviour of sdram_cmd is
signal cycle_finished : std_logic;
signal cycle_cnt : cycle_cnt_t;
signal burst_load_en : std_logic;
signal burst_finished : std_logic;
signal burst_cnt : burst_cnt_t;
@@ -90,10 +89,8 @@ fsm_sdr_state:
phy_ctrl.part.cke <= '1';
phy_ctrl.u_tag <= tag;
cc_load_en <= '0';
burst_load_en <= '0';
cmd_ack <= '0';
phy_ctrl.re <= '0';
phy_ctrl.drive_en <= '0';
phy_ctrl.we <= '0';
phy_ctrl.utag_we <= '0';
phy_ctrl.part.addr <= mode_word(phy_ctrl.part.addr'left downto phy_ctrl.part.addr'right);
@@ -121,7 +118,6 @@ fsm_sdr_state:
if cmd_we = '1' then
cmd_ack <= '1';
cc_load_en <= '1';
burst_load_en <= '1';
phy_ctrl.part.cmd <= COMMAND(cmd);
case cmd is
when SD_PRE =>
@@ -138,7 +134,7 @@ fsm_sdr_state:
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
when SD_WRITE =>
phy_ctrl.utag_we <= '1';
phy_ctrl.drive_en <= '1';
phy_ctrl.we <= '1';
st_sdr_next <= WRITE;
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
when others => null;
@@ -146,37 +142,34 @@ fsm_sdr_state:
end if;
when WRITE =>
phy_ctrl.drive_en <= '1';
phy_ctrl.we <= '1';
phy_ctrl.part.cmd <= COMMAND(SD_NOP);
if cmd_we = '1' and cmd = SD_WRITE then
cc_load_en <= '1';
cmd_ack <= '1';
phy_ctrl.utag_we <= '1';
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
if burst_finished = '1' then
burst_load_en <= '1';
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
if burst_finished = '1' then
if cmd_we = '1' and cmd = SD_WRITE then
cmd_ack <= '1';
cc_load_en <= '1';
phy_ctrl.part.cmd <= COMMAND(cmd);
phy_ctrl.utag_we <= '1';
else
phy_ctrl.we <= '0';
st_sdr_next <= IDLE_WAIT;
end if;
else
phy_ctrl.drive_en <= '0';
st_sdr_next <= IDLE_WAIT;
end if;
when READ =>
phy_ctrl.re <= '1';
phy_ctrl.part.cmd <= COMMAND(SD_NOP);
if cmd_we = '1' and cmd = SD_READ then
cc_load_en <= '1';
cmd_ack <= '1';
phy_ctrl.utag_we <= '1';
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
if burst_finished = '1' then
burst_load_en <= '1';
phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
if burst_finished = '1' then
if cmd_we = '1' and cmd = SD_READ then
cmd_ack <= '1';
cc_load_en <= '1';
phy_ctrl.part.cmd <= COMMAND(cmd);
phy_ctrl.utag_we <= '1';
else
st_sdr_next <= IDLE_WAIT;
end if;
else
st_sdr_next <= IDLE_WAIT;
end if;
when PRECHARGE =>
@@ -248,7 +241,7 @@ burst_counter:
process (clk)
begin
if rising_edge(clk) then
if burst_load_en = '1' then
if cc_load_en = '1' then
burst_finished <= '0';
burst_cnt <= burst_cnt_t'high;
if 2**(LMR_BL_CURR) = DATA_RATE_FACTOR then