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- added two addtional UARTs. UART2 not operable (just loopback) due to synthesize problems - or a bug

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git-svn-id: http://moon:8086/svn/vhdl/trunk@504 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-10-08 21:34:00 +00:00
parent 15d9de633c
commit 45d8f099ca
1 changed files with 63 additions and 24 deletions
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projects/mips_sys/src/mips_sys.vhd
+63 -24
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@@ -57,8 +57,12 @@ PORT
sys_led : out unsigned(8 downto 0); sys_led : out unsigned(8 downto 0);
-- UART -- UART
sys_rx : in std_logic; sys_uart0_rx : in std_logic;
sys_tx : out std_logic; sys_uart0_tx : out std_logic;
sys_uart1_rx : in std_logic;
sys_uart1_tx : out std_logic;
sys_uart2_rx : in std_logic;
sys_uart2_tx : out std_logic;
-- LCD -- LCD
sys_lcd_d : inout unsigned(3 downto 0); sys_lcd_d : inout unsigned(3 downto 0);
@@ -312,7 +316,8 @@ ARCHITECTURE behavior OF mips_sys IS
signal clk270var : std_logic; signal clk270var : std_logic;
signal rst_in : std_logic; signal rst_in : std_logic;
signal int_timer : std_logic; signal int_timer : std_logic;
signal int_uart : std_logic; signal int_uart0 : std_logic;
signal int_uart1 : std_logic;
signal locked : std_logic; signal locked : std_logic;
signal usb_addr : unsigned(31 downto 0); signal usb_addr : unsigned(31 downto 0);
signal flash_addr : unsigned(31 downto 0); signal flash_addr : unsigned(31 downto 0);
@@ -389,10 +394,14 @@ ARCHITECTURE behavior OF mips_sys IS
signal SRDY_O_gpio : std_logic; signal SRDY_O_gpio : std_logic;
signal SDAT_O_gpio : unsigned(31 downto 0); signal SDAT_O_gpio : unsigned(31 downto 0);
signal CYC_I_uart : std_logic; signal CYC_I_uart0 : std_logic;
signal ACK_O_uart : std_logic; signal ACK_O_uart0 : std_logic;
signal SRDY_O_uart : std_logic; signal SRDY_O_uart0 : std_logic;
signal SDAT_O_uart : unsigned(31 downto 0); signal SDAT_O_uart0 : unsigned(31 downto 0);
signal CYC_I_uart1 : std_logic;
signal ACK_O_uart1 : std_logic;
signal SRDY_O_uart1 : std_logic;
signal SDAT_O_uart1 : unsigned(31 downto 0);
signal CYC_I_vga : std_logic; signal CYC_I_vga : std_logic;
signal ACK_O_vga : std_logic; signal ACK_O_vga : std_logic;
@@ -421,7 +430,7 @@ ARCHITECTURE behavior OF mips_sys IS
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED"; -- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED"; -- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97); type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_sdram, mem_vga, mem_ac97);
signal mem_area : mem_area_t; signal mem_area : mem_area_t;
BEGIN BEGIN
@@ -450,6 +459,7 @@ BEGIN
SEL_I_sdram <= "0000" & SEL_O; SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn; sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
sys_uart2_tx <= sys_uart2_rx;
--------------------------------------------------------------- ---------------------------------------------------------------
-- Arbiter -- Arbiter
@@ -494,7 +504,7 @@ int_sample:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
INT <= int_timer & '0' & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & int_uart & sys_btn(4); INT <= int_timer & '0' & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4);
end if; end if;
end process; end process;
@@ -509,7 +519,11 @@ mem_mux:
if ADDR_O(18 downto 16) = "000" then if ADDR_O(18 downto 16) = "000" then
mem_area <= mem_gpio; mem_area <= mem_gpio;
elsif ADDR_O(18 downto 16) = "001" then elsif ADDR_O(18 downto 16) = "001" then
mem_area <= mem_uart; if ADDR_O(9 downto 8) = "00" then
mem_area <= mem_uart0;
elsif ADDR_O(9 downto 8) = "01" then
mem_area <= mem_uart1;
end if;
elsif ADDR_O(18 downto 16) = "010" then elsif ADDR_O(18 downto 16) = "010" then
mem_area <= mem_usb; mem_area <= mem_usb;
elsif ADDR_O(18 downto 16) = "011" then elsif ADDR_O(18 downto 16) = "011" then
@@ -532,7 +546,8 @@ signal_mux:
process(mem_area, CYC_O) process(mem_area, CYC_O)
begin begin
CYC_I_uart <= '0'; CYC_I_uart0 <= '0';
CYC_I_uart1 <= '0';
CYC_I_gpio <= '0'; CYC_I_gpio <= '0';
CYC_I_flash <= '0'; CYC_I_flash <= '0';
CYC_I_usb <= '0'; CYC_I_usb <= '0';
@@ -546,8 +561,11 @@ signal_mux:
when mem_gpio => when mem_gpio =>
CYC_I_gpio <= CYC_O; CYC_I_gpio <= CYC_O;
when mem_uart => when mem_uart0 =>
CYC_I_uart <= CYC_O; CYC_I_uart0 <= CYC_O;
when mem_uart1 =>
CYC_I_uart1 <= CYC_O;
when mem_flash => when mem_flash =>
CYC_I_flash <= CYC_O; CYC_I_flash <= CYC_O;
@@ -574,13 +592,14 @@ signal_mux:
end process; end process;
------------------------------------------------------------------ ------------------------------------------------------------------
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97; SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97; ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
SDAT_O_rom when CYC_I_rom = '1' else SDAT_O_rom when CYC_I_rom = '1' else
SDAT_O_flash when CYC_I_flash = '1' else SDAT_O_flash when CYC_I_flash = '1' else
SDAT_O_usb when CYC_I_usb = '1' else SDAT_O_usb when CYC_I_usb = '1' else
SDAT_O_uart when CYC_I_uart = '1' else SDAT_O_uart0 when CYC_I_uart0 = '1' else
SDAT_O_uart1 when CYC_I_uart1 = '1' else
SDAT_O_vga when CYC_I_vga = '1' else SDAT_O_vga when CYC_I_vga = '1' else
SDAT_O_ac97 when CYC_I_ac97 = '1' else SDAT_O_ac97 when CYC_I_ac97 = '1' else
SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF"; SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
@@ -721,24 +740,44 @@ inst_usb_port : async_port_wb
async_rst => open async_rst => open
); );
inst_uart_wb : uart_wb inst_uart_wb_0 : uart_wb
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
RST_I => rst, RST_I => rst,
CYC_I => CYC_I_uart, CYC_I => CYC_I_uart0,
STB_I => STB_O, STB_I => STB_O,
SEL_I => SEL_O, SEL_I => SEL_O,
WE_I => WE_O, WE_I => WE_O,
ACK_O => ACK_O_uart, ACK_O => ACK_O_uart0,
SRDY_O => SRDY_O_uart, SRDY_O => SRDY_O_uart0,
MRDY_I => MRDY_O, MRDY_I => MRDY_O,
ADDR_I => ADDR_O, ADDR_I => ADDR_O,
DAT_I => MDAT_O, DAT_I => MDAT_O,
DAT_O => SDAT_O_uart, DAT_O => SDAT_O_uart0,
INT_O => int_uart, INT_O => int_uart0,
ser_rx => sys_rx, ser_rx => sys_uart0_rx,
ser_tx => sys_tx ser_tx => sys_uart0_tx
);
inst_uart_wb_1 : uart_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_uart1,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_uart1,
SRDY_O => SRDY_O_uart1,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_uart1,
INT_O => int_uart1,
ser_rx => sys_uart1_rx,
ser_tx => sys_uart1_tx
); );