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- Bugfix: Registers not correctly update during read

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git-svn-id: http://moon:8086/svn/vhdl/trunk@961 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-05-11 14:13:44 +00:00
parent f0093103fa
commit 41978bb08c
1 changed files with 6 additions and 2 deletions
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lib/VGA_ctrl/src/vga_frontend64.vhd
+6 -2
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@@ -126,6 +126,7 @@ architecture Behavioral of vga_frontend64 is
-- Bus master signals -- Bus master signals
constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan; constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
signal reg_read_vld : std_logic;
signal bufchg : std_logic; signal bufchg : std_logic;
signal bufchg_irq_en : std_logic; signal bufchg_irq_en : std_logic;
signal bufchg_flag : std_logic; signal bufchg_flag : std_logic;
@@ -1078,8 +1079,11 @@ registers_read:
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
ACK_O <= '0'; ACK_O <= '0';
if (STB_I and CYC_I) = '1' then reg_read_vld <= '0';
ACK_O <= not WE_I; if CYC_I = '1' and WE_I = '0' then
ACK_O <= reg_read_vld;
reg_read_vld <= STB_I;
SDAT_O <= (others => '0'); SDAT_O <= (others => '0');
case ADDR_I(6 downto 2) is case ADDR_I(6 downto 2) is