diff --git a/lib/VGA_ctrl/src/vga_frontend64.vhd b/lib/VGA_ctrl/src/vga_frontend64.vhd
index b812135..6d63daf 100644
--- a/lib/VGA_ctrl/src/vga_frontend64.vhd
+++ b/lib/VGA_ctrl/src/vga_frontend64.vhd
@@ -126,6 +126,7 @@ architecture Behavioral of vga_frontend64 is
 	-- Bus master signals
 	constant MAX_REQUEST_CNT			: natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
 
+	signal reg_read_vld					: std_logic;
 	signal bufchg						: std_logic;
 	signal bufchg_irq_en				: std_logic;
 	signal bufchg_flag					: std_logic;
@@ -1078,8 +1079,11 @@ registers_read:
 	begin
 		if rising_edge(CLK_I) then
 			ACK_O			<= '0';
-			if (STB_I and CYC_I) = '1' then
-				ACK_O		<= not WE_I;
+			reg_read_vld	<= '0';
+			if CYC_I = '1' and WE_I = '0' then
+				ACK_O			<= reg_read_vld;
+				reg_read_vld	<= STB_I;
+				
 				SDAT_O		<= (others => '0');
 				case ADDR_I(6 downto 2) is