- cleaned up

git-svn-id: http://moon:8086/svn/vhdl/trunk@1171 cc03376c-175c-47c8-b038-4cd826a8556b
2015-05-23 08:44:57 +00:00
parent b1dfffbc2a
commit 3ddbfdff33
2 changed files with 8 additions and 7 deletions
@@ -21,10 +21,11 @@
 --
 --------------------------------------------------------------------------

-library ieee, work;
+library IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;

+library WORK;
 USE WORK.utils_pkg.ALL;

 Library UNISIM;
@@ -41,8 +42,8 @@ entity clockgen is
 		-- Clocks and Reset
 		rst_in				: in std_logic;   -- external async reset, low active
 		clk_in				: in std_logic;   -- system clock (e.g. 100MHz), from board
-		clk_out				: out std_logic;
-		rst_out				: out std_logic
+		rst_out				: out std_logic;
+		clk_out				: out std_logic
 	);
 end;