From 3ddbfdff33ede82d9bb5cc8b7e738277943af584 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 23 May 2015 08:44:57 +0000 Subject: [PATCH] - cleaned up git-svn-id: http://moon:8086/svn/vhdl/trunk@1171 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/src/clockgen.vhd | 7 ++++--- projects/mips_sys/src/mips_sys_sim.vhd | 8 ++++---- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/projects/mips_sys/src/clockgen.vhd b/projects/mips_sys/src/clockgen.vhd index e983333..922d53e 100644 --- a/projects/mips_sys/src/clockgen.vhd +++ b/projects/mips_sys/src/clockgen.vhd @@ -21,10 +21,11 @@ -- -------------------------------------------------------------------------- -library ieee, work; +library IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; +library WORK; USE WORK.utils_pkg.ALL; Library UNISIM; @@ -41,8 +42,8 @@ entity clockgen is -- Clocks and Reset rst_in : in std_logic; -- external async reset, low active clk_in : in std_logic; -- system clock (e.g. 100MHz), from board - clk_out : out std_logic; - rst_out : out std_logic + rst_out : out std_logic; + clk_out : out std_logic ); end; diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd index 0acf86f..77e3452 100644 --- a/projects/mips_sys/src/mips_sys_sim.vhd +++ b/projects/mips_sys/src/mips_sys_sim.vhd @@ -821,8 +821,8 @@ inst_clockgen_cpu : entity work.clockgen -- Clocks and Reset rst_in => rst_in, clk_in => sys_clk_in, - clk_out => CLK_O, - rst_out => RST_O + rst_out => RST_O, + clk_out => CLK_O ); inst_clocken_vga : entity work.clockgen @@ -836,8 +836,8 @@ inst_clocken_vga : entity work.clockgen -- Clocks and Reset rst_in => rst_in, clk_in => sys_clk_in, - clk_out => vga_clk, - rst_out => vga_rst + rst_out => vga_rst, + clk_out => vga_clk ); inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb