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git-svn-id: http://moon:8086/svn/vhdl/trunk@269 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-20 21:19:41 +00:00
parent 523e216793
commit 3db7aa0fb4
1 changed files with 2 additions and 31 deletions
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lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+2 -31
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@@ -615,7 +615,7 @@ proc_stage_DMEM_ADDR:
process(clk_1) process(clk_1)
begin begin
if rising_edge(clk_1) then if rising_edge(clk_1) then
if sdu.EX_stall = '0' then --and ID_stage.ctrl.dmem_en = '1' then if sdu.EX_stall = '0' then
EX_stage.va <= vaddr; EX_stage.va <= vaddr;
if cop_stat.RE = '1' then if cop_stat.RE = '1' then
EX_stage.pa_off <= not vaddr(1 downto 0); EX_stage.pa_off <= not vaddr(1 downto 0);
@@ -677,28 +677,7 @@ proc_stage_bcu_op:
end if; end if;
end process; end process;
alu_op1_mux: EX_stage.alu_op1 <= EX_stage.reg_a;
process(EX_stage)
variable data : word_t;
begin
data := EX_stage.reg_a;
-- case EX_stage.ctrl.alu.op1_src is
--
-- when alu_src_reg =>
-- data := EX_stage.reg_a;
--
-- when alu_src_muldiv =>
-- data := mul_result;
--
-- when others => null;
--
-- end case;
EX_stage.alu_op1 <= data;
end process;
alu_op2_mux: alu_op2_mux:
process(clk_1) process(clk_1)
@@ -810,11 +789,6 @@ proc_stage_MEM_n:
MEM_stage.ctrl <= ctrl_lines_default; MEM_stage.ctrl <= ctrl_lines_default;
MEM_stage.pa_off <= (others => '0'); MEM_stage.pa_off <= (others => '0');
MEM_stage.events_in <= events_clr; MEM_stage.events_in <= events_clr;
-- MEM_stage.epc <= (others => '0');
-- MEM_stage.pcn <= (others => '0');
-- MEM_stage.va <= (others => '0');
-- MEM_stage.reg_wptr <= (others => '0');
-- MEM_stage.ex_result <= (others => '0');
elsif sdu.MEM_stall = '0' then elsif sdu.MEM_stall = '0' then
MEM_stage.events_in <= EX_stage.events; MEM_stage.events_in <= EX_stage.events;
MEM_stage.op <= EX_stage.op; MEM_stage.op <= EX_stage.op;
@@ -894,9 +868,6 @@ proc_stage_WB_p:
if rst = '1' then if rst = '1' then
WB_stage.op <= NOP; WB_stage.op <= NOP;
WB_stage.wreg_we <= '0'; WB_stage.wreg_we <= '0';
-- WB_stage.epc <= (others => '0');
-- WB_stage.reg_wptr <= (others => '0');
-- WB_stage.data <= (others => '0');
elsif sdu.WB_stall = '0' then elsif sdu.WB_stall = '0' then
WB_stage.op <= MEM_stage.op; WB_stage.op <= MEM_stage.op;
WB_stage.wreg_we <= MEM_stage.wreg_we; WB_stage.wreg_we <= MEM_stage.wreg_we;