From 3db7aa0fb49fd9eab0b905a0506962cc0fbb1dfa Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 20 Jan 2009 21:19:41 +0000 Subject: [PATCH] - removed commented lines Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@269 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_pipeline.vhd | 33 ++---------------------- 1 file changed, 2 insertions(+), 31 deletions(-) diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd index 00080b4..a07fffc 100644 --- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd +++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd @@ -615,7 +615,7 @@ proc_stage_DMEM_ADDR: process(clk_1) begin if rising_edge(clk_1) then - if sdu.EX_stall = '0' then --and ID_stage.ctrl.dmem_en = '1' then + if sdu.EX_stall = '0' then EX_stage.va <= vaddr; if cop_stat.RE = '1' then EX_stage.pa_off <= not vaddr(1 downto 0); @@ -677,28 +677,7 @@ proc_stage_bcu_op: end if; end process; -alu_op1_mux: - process(EX_stage) - variable data : word_t; - begin - - data := EX_stage.reg_a; - --- case EX_stage.ctrl.alu.op1_src is --- --- when alu_src_reg => --- data := EX_stage.reg_a; --- --- when alu_src_muldiv => --- data := mul_result; --- --- when others => null; --- --- end case; - - EX_stage.alu_op1 <= data; - - end process; +EX_stage.alu_op1 <= EX_stage.reg_a; alu_op2_mux: process(clk_1) @@ -810,11 +789,6 @@ proc_stage_MEM_n: MEM_stage.ctrl <= ctrl_lines_default; MEM_stage.pa_off <= (others => '0'); MEM_stage.events_in <= events_clr; --- MEM_stage.epc <= (others => '0'); --- MEM_stage.pcn <= (others => '0'); --- MEM_stage.va <= (others => '0'); --- MEM_stage.reg_wptr <= (others => '0'); --- MEM_stage.ex_result <= (others => '0'); elsif sdu.MEM_stall = '0' then MEM_stage.events_in <= EX_stage.events; MEM_stage.op <= EX_stage.op; @@ -894,9 +868,6 @@ proc_stage_WB_p: if rst = '1' then WB_stage.op <= NOP; WB_stage.wreg_we <= '0'; --- WB_stage.epc <= (others => '0'); --- WB_stage.reg_wptr <= (others => '0'); --- WB_stage.data <= (others => '0'); elsif sdu.WB_stall = '0' then WB_stage.op <= MEM_stage.op; WB_stage.wreg_we <= MEM_stage.wreg_we;