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- added PS2 interface 0

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git-svn-id: http://moon:8086/svn/vhdl/trunk@617 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-06 13:14:44 +00:00
parent f9d1fc4945
commit 33f61f3007
5 changed files with 135 additions and 6 deletions
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projects/mips_sys/src/mips_sys_sim.vhd
+55 -1
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@@ -129,6 +129,9 @@ PORT
sys_ac97_sdata_out : out std_logic;
sys_ac97_ssync : out std_logic;
sys_ps2_clk : inout std_logic;
sys_ps2_data : inout std_logic;
sys_error : out unsigned(1 downto 0) -- indicates Errors
);
@@ -386,6 +389,11 @@ ARCHITECTURE behavior OF mips_sys IS
signal flash_d_drv : std_logic;
signal flash_bsy : std_logic;
signal flash_page_mode_en : std_logic;
signal ps2_clk_rx : std_logic;
signal ps2_data_rx : std_logic;
signal ps2_clk_tx : std_logic;
signal ps2_data_tx : std_logic;
-- Arbiter
constant ARB_MAX_MASTER : natural := 2;
@@ -488,6 +496,12 @@ ARCHITECTURE behavior OF mips_sys IS
signal SRDY_O_ac97 : std_logic;
signal SDAT_O_ac97 : unsigned(31 downto 0);
signal INT_O_ps2 : std_logic;
signal CYC_I_ps2 : std_logic;
signal ACK_O_ps2 : std_logic;
signal SRDY_O_ps2 : std_logic;
signal SDAT_O_ps2 : unsigned(31 downto 0);
signal gpo0 : unsigned(31 downto 0);
signal gpo1 : unsigned(31 downto 0);
signal gpi0 : unsigned(31 downto 0);
@@ -956,7 +970,7 @@ inst_ssram_port_wb : entity work.ssram_port_wb
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => 100E6,
clk_in_freq_hz => sys_freq,
vga_clk_out_freq_hz => tsvga.f_pxl_clk,
sdr_clk0_out_phaseshift => 0,
sdr_clk1_out_phaseshift => 0
@@ -1100,5 +1114,45 @@ inst_ac97_wb : entity work.ac97_wb
ac97_ssync => sys_ac97_ssync
);
inst_ps2_wb: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk_hz => sys_freq
)
PORT MAP
(
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_ps2,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_ps2,
SRDY_O => SRDY_O_ps2,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_ps2,
INT_O => INT_O_ps2,
clk_rx => ps2_clk_rx,
data_rx => ps2_data_rx,
clk_tx => ps2_clk_tx,
data_tx => ps2_data_tx
);
inst_ps2_phy: entity work.ps2_phy
PORT MAP
(
rst => RST_O,
clk => CLK_O,
ps2_clk => sys_ps2_clk,
ps2_data => sys_ps2_data,
rx_clk => ps2_clk_rx,
rx_data => ps2_data_rx,
tx_clk => ps2_clk_tx,
tx_data => ps2_data_tx
);
------------------------------------------------------------------
END;