diff --git a/projects/mips_sys/sim/tb_mips_sys.fdo b/projects/mips_sys/sim/tb_mips_sys.fdo index 27e770e..b5575a2 100644 --- a/projects/mips_sys/sim/tb_mips_sys.fdo +++ b/projects/mips_sys/sim/tb_mips_sys.fdo @@ -55,6 +55,12 @@ vcom -explicit -93 "../../../lib/uart/uart_rx.vhd" vcom -explicit -93 "../../../lib/uart/uart_tx.vhd" vcom -explicit -93 "../../../lib/uart/uart_wb.vhd" +# PS2 +vcom -explicit -93 "../../../lib/ps2_port/src/debounce.vhd" +vcom -explicit -93 "../../../lib/ps2_port/src/ps2_core.vhd" +vcom -explicit -93 "../../../lib/ps2_port/src/ps2_phy_virtex.vhd" +vcom -explicit -93 "../../../lib/ps2_port/src/ps2_wb.vhd" + # GPIO vcom -explicit -93 "../../../lib/misc/gpio_wb.vhd" diff --git a/projects/mips_sys/sim/tb_mips_sys.wdo b/projects/mips_sys/sim/tb_mips_sys.wdo index 83991f7..a09eaed 100644 --- a/projects/mips_sys/sim/tb_mips_sys.wdo +++ b/projects/mips_sys/sim/tb_mips_sys.wdo @@ -9,6 +9,8 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in add wave -noupdate -format Literal /tb_mips_sys/dip add wave -noupdate -format Literal /tb_mips_sys/btn add wave -noupdate -format Literal /tb_mips_sys/led +add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_clk +add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_data add wave -noupdate -format Logic /tb_mips_sys/sys_rx add wave -noupdate -format Logic /tb_mips_sys/sys_tx add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d @@ -203,7 +205,7 @@ add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/ add wave -noupdate -divider D-Cache add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {1804093493 ps} 0} {{Cursor 100} {0 ps} 0} +WaveRestoreCursors {{Cursor 2} {1804093493 ps} 0} {{Cursor 100} {853399231 ps} 0} configure wave -namecolwidth 187 configure wave -valuecolwidth 64 configure wave -justifyvalue left diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd index e4cbef9..1a15bf6 100644 --- a/projects/mips_sys/src/mips_sys.vhd +++ b/projects/mips_sys/src/mips_sys.vhd @@ -120,6 +120,9 @@ PORT sys_ac97_sdata_out : out std_logic; sys_ac97_ssync : out std_logic; + sys_ps2_0_clk : inout std_logic; + sys_ps2_0_data : inout std_logic; + sys_error : out unsigned(1 downto 0) -- indicates Errors ); @@ -332,6 +335,10 @@ ARCHITECTURE behavior OF mips_sys IS signal flash_rstn : std_logic; signal flash_page_mode_en : std_logic; signal flash_addr : unsigned(24 downto 0); + signal ps2_0_clk_rx : std_logic; + signal ps2_0_data_rx : std_logic; + signal ps2_0_clk_tx : std_logic; + signal ps2_0_data_tx : std_logic; -- Arbiter constant ARB_MAX_MASTER : natural := 2; @@ -425,6 +432,12 @@ ARCHITECTURE behavior OF mips_sys IS signal SRDY_O_ac97 : std_logic; signal SDAT_O_ac97 : unsigned(31 downto 0); + signal INT_O_ps2_0 : std_logic; + signal CYC_I_ps2_0 : std_logic; + signal ACK_O_ps2_0 : std_logic; + signal SRDY_O_ps2_0 : std_logic; + signal SDAT_O_ps2_0 : unsigned(31 downto 0); + signal gpo0 : unsigned(31 downto 0); signal gpo1 : unsigned(31 downto 0); signal gpi0 : unsigned(31 downto 0); @@ -441,7 +454,7 @@ ARCHITECTURE behavior OF mips_sys IS -- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED"; -- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED"; - type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_sdram, mem_vga, mem_ac97); + type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_ps2_0, mem_ps2_1, mem_sdram, mem_vga, mem_ac97); signal mem_area : mem_area_t; attribute KEEP : string; @@ -526,7 +539,7 @@ int_sample: process(CLK_O) begin if rising_edge(CLK_O) then - INT <= int_timer & '0' & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4); + INT <= int_timer & INT_O_ps2_0 & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4); end if; end process; @@ -547,6 +560,10 @@ mem_mux: mem_area <= mem_uart0; elsif ADDR_O(9 downto 8) = "01" then mem_area <= mem_uart1; + elsif ADDR_O(9 downto 8) = "10" then + mem_area <= mem_ps2_0; + elsif ADDR_O(9 downto 8) = "11" then + mem_area <= mem_ps2_1; end if; elsif ADDR_O(18 downto 16) = "010" then mem_area <= mem_usb; @@ -571,6 +588,7 @@ signal_mux: CYC_I_uart0 <= '0'; CYC_I_uart1 <= '0'; + CYC_I_ps2_0 <= '0'; CYC_I_gpio <= '0'; CYC_I_flash <= '0'; CYC_I_usb <= '0'; @@ -590,6 +608,9 @@ signal_mux: when mem_uart1 => CYC_I_uart1 <= CYC_O; + when mem_ps2_0 => + CYC_I_ps2_0 <= CYC_O; + when mem_flash => CYC_I_flash <= CYC_O; @@ -615,14 +636,15 @@ signal_mux: end process; ------------------------------------------------------------------ - SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97; - ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97; + SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_ps2_0 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97; + ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_ps2_0 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97; MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else SDAT_O_rom when CYC_I_rom = '1' else SDAT_O_flash when CYC_I_flash = '1' else SDAT_O_usb when CYC_I_usb = '1' else SDAT_O_uart0 when CYC_I_uart0 = '1' else SDAT_O_uart1 when CYC_I_uart1 = '1' else + SDAT_O_ps2_0 when CYC_I_ps2_0 = '1' else SDAT_O_vga when CYC_I_vga = '1' else SDAT_O_ac97 when CYC_I_ac97 = '1' else SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF"; @@ -952,5 +974,44 @@ inst_ac97_wb : entity work.ac97_wb ac97_ssync => sys_ac97_ssync ); +inst_ps2_wb_0: entity work.ps2_wb + GENERIC MAP + ( + f_sys_clk_hz => sys_freq + ) + PORT MAP + ( + CLK_I => CLK_O, + RST_I => RST_O, + CYC_I => CYC_I_ps2_0, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_O_ps2_0, + SRDY_O => SRDY_O_ps2_0, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_I => MDAT_O, + DAT_O => SDAT_O_ps2_0, + INT_O => INT_O_ps2_0, + clk_rx => ps2_0_clk_rx, + data_rx => ps2_0_data_rx, + clk_tx => ps2_0_clk_tx, + data_tx => ps2_0_data_tx + ); + +inst_ps2_phy_0: entity work.ps2_phy + PORT MAP + ( + rst => RST_O, + clk => CLK_O, + ps2_clk => sys_ps2_0_clk, + ps2_data => sys_ps2_0_data, + rx_clk => ps2_0_clk_rx, + rx_data => ps2_0_data_rx, + tx_clk => ps2_0_clk_tx, + tx_data => ps2_0_data_tx + ); + ------------------------------------------------------------------ END; diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd index a0a69e7..44749a5 100644 --- a/projects/mips_sys/src/mips_sys_sim.vhd +++ b/projects/mips_sys/src/mips_sys_sim.vhd @@ -129,6 +129,9 @@ PORT sys_ac97_sdata_out : out std_logic; sys_ac97_ssync : out std_logic; + sys_ps2_clk : inout std_logic; + sys_ps2_data : inout std_logic; + sys_error : out unsigned(1 downto 0) -- indicates Errors ); @@ -386,6 +389,11 @@ ARCHITECTURE behavior OF mips_sys IS signal flash_d_drv : std_logic; signal flash_bsy : std_logic; signal flash_page_mode_en : std_logic; + + signal ps2_clk_rx : std_logic; + signal ps2_data_rx : std_logic; + signal ps2_clk_tx : std_logic; + signal ps2_data_tx : std_logic; -- Arbiter constant ARB_MAX_MASTER : natural := 2; @@ -488,6 +496,12 @@ ARCHITECTURE behavior OF mips_sys IS signal SRDY_O_ac97 : std_logic; signal SDAT_O_ac97 : unsigned(31 downto 0); + signal INT_O_ps2 : std_logic; + signal CYC_I_ps2 : std_logic; + signal ACK_O_ps2 : std_logic; + signal SRDY_O_ps2 : std_logic; + signal SDAT_O_ps2 : unsigned(31 downto 0); + signal gpo0 : unsigned(31 downto 0); signal gpo1 : unsigned(31 downto 0); signal gpi0 : unsigned(31 downto 0); @@ -956,7 +970,7 @@ inst_ssram_port_wb : entity work.ssram_port_wb inst_clockgen : entity work.clockgen GENERIC MAP ( - clk_in_freq_hz => 100E6, + clk_in_freq_hz => sys_freq, vga_clk_out_freq_hz => tsvga.f_pxl_clk, sdr_clk0_out_phaseshift => 0, sdr_clk1_out_phaseshift => 0 @@ -1100,5 +1114,45 @@ inst_ac97_wb : entity work.ac97_wb ac97_ssync => sys_ac97_ssync ); +inst_ps2_wb: entity work.ps2_wb + GENERIC MAP + ( + f_sys_clk_hz => sys_freq + ) + PORT MAP + ( + CLK_I => CLK_O, + RST_I => RST_O, + CYC_I => CYC_I_ps2, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_O_ps2, + SRDY_O => SRDY_O_ps2, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_I => MDAT_O, + DAT_O => SDAT_O_ps2, + INT_O => INT_O_ps2, + clk_rx => ps2_clk_rx, + data_rx => ps2_data_rx, + clk_tx => ps2_clk_tx, + data_tx => ps2_data_tx + ); + +inst_ps2_phy: entity work.ps2_phy + PORT MAP + ( + rst => RST_O, + clk => CLK_O, + ps2_clk => sys_ps2_clk, + ps2_data => sys_ps2_data, + rx_clk => ps2_clk_rx, + rx_data => ps2_data_rx, + tx_clk => ps2_clk_tx, + tx_data => ps2_data_tx + ); + + ------------------------------------------------------------------ END; diff --git a/projects/mips_sys/src/tb_mips_sys.vhd b/projects/mips_sys/src/tb_mips_sys.vhd index a50abf3..4907719 100644 --- a/projects/mips_sys/src/tb_mips_sys.vhd +++ b/projects/mips_sys/src/tb_mips_sys.vhd @@ -106,6 +106,9 @@ ARCHITECTURE behavior OF tb_mips_sys IS SIGNAL sys_ac97_ssync : std_logic; SIGNAL sys_ac97_sdata_in : std_logic; + SIGNAL sys_ps2_clk : std_logic := 'Z'; + SIGNAL sys_ps2_data : std_logic := 'Z'; + signal flash_reg : word_t; type flash_data_t is array (natural range 0 to 2**16-1) of word_t; @@ -189,6 +192,9 @@ uut: entity work.mips_sys sys_ac97_ssync => sys_ac97_ssync, sys_ac97_sdata_in => sys_ac97_sdata_in, + sys_ps2_clk => sys_ps2_clk, + sys_ps2_data => sys_ps2_data, + sys_error => sys_error );