Initial import

git-svn-id: http://moon:8086/svn/vhdl/trunk@2 cc03376c-175c-47c8-b038-4cd826a8556b
2008-08-23 07:19:47 +00:00
parent 6badec2df7
commit 335cc4e9d2
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+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: Testbench for JCPU
+--            also writes 'opc.lst' for JASM-assembler
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.mips_types.all;
+use work.mips_instr.all;
+
+ENTITY tb_mips_top IS
+END tb_mips_top;
+
+ARCHITECTURE behavior OF tb_mips_top IS 
+
+	COMPONENT mips_top
+	Port 
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		halt		: in  STD_LOGIC;
+		imem_din	: in  unsigned (WORD_WIDTH-1 downto 0);
+		imem_addr	: out unsigned (WORD_WIDTH-1 downto 0);
+		dmem_we		: out STD_LOGIC;
+		dmem_re		: out STD_LOGIC;
+		dmem_din	: in  unsigned (WORD_WIDTH-1 downto 0);
+		dmem_dout	: out unsigned (WORD_WIDTH-1 downto 0);
+		dmem_addr	: out unsigned (WORD_WIDTH-1 downto 0)
+		
+	);
+	END COMPONENT;
+
+	COMPONENT rom
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		addr		: in  word_t;
+		dout		: out word_t
+	);
+	END COMPONENT;
+
+	COMPONENT ram
+	Generic 
+	(
+		word_addr_width 	: integer
+	);
+	Port 
+	(
+		clk			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		addr		: in  word_t;
+		din			: in  word_t;
+		dout		: out word_t
+	);
+	END COMPONENT;
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal rst 			: std_logic := '1';
+	signal clk 			: std_logic := '1';
+	signal cpu_halt		: std_logic;
+	signal irom_data	: word_t := (others => '-');
+	signal irom_addr	: word_t;
+	signal dmem_din		: word_t := (others => '-');
+	signal dmem_dout 	: word_t;
+	signal dmem_addr 	: word_t;
+	signal dmem_we 		: std_logic;
+	signal dmem_re 		: std_logic;
+	
+BEGIN
+
+uut: mips_top
+	PORT MAP(
+		rst				=> rst,
+		clk				=> clk,
+		halt			=> cpu_halt,
+		imem_din		=> irom_data,
+		imem_addr		=> irom_addr,
+		dmem_we			=> dmem_we,
+		dmem_re			=> dmem_re,
+		dmem_din		=> dmem_din,
+		dmem_dout		=> dmem_dout,
+		dmem_addr		=> dmem_addr
+	);
+
+inst_rom: rom
+	PORT MAP
+	(
+		clk				=> clk,
+		addr			=> irom_addr,
+		dout 			=> irom_data
+	);
+
+inst_ram: ram
+	GENERIC MAP
+	(
+		word_addr_width	=> 6
+	)
+	PORT MAP
+	(
+		clk			=> clk,
+		we			=> dmem_we,
+		addr		=> dmem_addr,
+		din 		=> dmem_dout,
+		dout 		=> dmem_din
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+HLT_GEN: 
+	process(rst, clk)
+	subtype cnt_t is natural range 0 to 2;
+	variable cnt : cnt_t;
+	begin
+		if rst = '1' then
+			cnt := cnt_t'high;
+			cpu_halt <= '0';
+		elsif rising_edge(clk) then
+			cpu_halt <= '0';
+			if cnt /= 0 then
+				cnt := cnt - 1;
+			else
+				cnt := cnt_t'high;
+				cpu_halt <= '1';
+			end if;	
+		end if;
+	end process;
+
+STIMULUS: process
+
+	begin
+
+--		for i in 0 to instr_name_array'length-1 loop
+--			fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i));
+--		end loop;	
+
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(clk);
+		rst <= '0';
+		wait for 2*CLK_PERIOD;
+	
+--		assert false report "Test finished" severity error;
+		wait; 
+	
+	end process;
+	
+END;