diff --git a/lib/CPUs/JCpu/asm/dctest.jsm b/lib/CPUs/JCpu/asm/dctest.jsm
new file mode 100644
index 0000000..38d5947
--- /dev/null
+++ b/lib/CPUs/JCpu/asm/dctest.jsm
@@ -0,0 +1,56 @@
+; -------------------------------------------------	
+;			PROJECT	"dctest"
+; -------------------------------------------------	
+
+include "../../../jasm/cregs.inc.jsm"
+
+; -------------------------------------------------	
+				xmem
+				org		4
+konst:			dc		0x01, 0x12,"A"
+gap1:			db		16
+mesg:			dc		"Hallo", 13,0x0A, 0
+name:			dc		"Jens",0
+msg1:			dc		"Welcome to JASM CPU",0
+msg2:			dc		"Ready",0
+msg3:			dc		"Testing",0
+msg4:			dc		"Passed",0
+msg5:			dc		"Error",0
+crlf:			dc		0x0D, 0x0A
+
+				org		0x00
+shit:			db		4	
+
+				cmem	0
+				org		8
+cram1:			db		16
+cram2:			db		6
+cram3:			db		4
+
+				cmem	1
+cram4:			db		8
+cram5:			db		8
+				org		0x20
+cram6:			db		8
+cram7:			db		4
+
+reg_revision:	equ		0x00			
+reg_testid:		equ		0x01			
+
+; -------------------------------------------------	
+				code
+				org		0x000
+reset:			jmp		start
+
+; -------------------------------------------------	
+				org		0x001
+int_vec:		jmp		isr
+
+; -------------------------------------------------	
+				org		0x010
+			
+start:			jmp		start
+
+; -------------------------------------------------	
+isr:			reti
+
diff --git a/lib/CPUs/JCpu/asm/dctest.tcl b/lib/CPUs/JCpu/asm/dctest.tcl
new file mode 100644
index 0000000..ca88834
--- /dev/null
+++ b/lib/CPUs/JCpu/asm/dctest.tcl
@@ -0,0 +1,212 @@
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: The ROM file for upload to target over JTAG 
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+# ---------------------------------------------------------------------
+# For Chipscope 9.1
+# ---------------------------------------------------------------------
+# Source JTAG/TCL frame work
+cd $env(CHIPSCOPE)\\bin\\nt
+source csejtag.tcl
+
+namespace import ::chipscope::*
+
+# Platform USB Cable
+set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
+# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
+
+# Create session
+set handle [::chipscope::csejtag_session create 0]
+
+# Open JTAG and lock
+set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
+set lock_result [::chipscope::csejtag_target lock $handle 1000]
+
+set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
+
+# Get Device ID
+set devtype "Virtex-4SX"
+set devid 2
+set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
+set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
+
+set CSE_OP $CSEJTAG_SHIFT_READWRITE
+set CSE_ES $CSEJTAG_RUN_TEST_IDLE
+
+# Write Program
+# JASM_ROM_INSERT_HERE
+# Assembled from dctest.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
+# User 1
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
+
+# 0x000: JMP 0x010
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010"
+
+# 0x001: JMP 0x011
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130011"
+
+# 0x002:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000"
+
+# 0x003:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000"
+
+# 0x004:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000"
+
+# 0x005:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
+
+# 0x006:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000"
+
+# 0x007:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
+
+# 0x008:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000"
+
+# 0x009:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
+
+# 0x00A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000"
+
+# 0x00B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
+
+# 0x00C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000"
+
+# 0x00D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
+
+# 0x00E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000"
+
+# 0x00F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
+
+# 0x010: JMP 0x010
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01030010"
+
+# 0x011: RETI
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0113F000"
+
+# Assembled from dctest.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
+# User 2
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
+
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0401"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0512"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0641"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1748"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1861"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "196C"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A6C"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B6F"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C0D"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D0A"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F4A"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2065"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "216E"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2273"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2457"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2565"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "266C"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2763"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "286F"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "296D"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A65"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B20"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C74"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D6F"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E20"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F4A"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3041"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3153"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "324D"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3320"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3443"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3550"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3655"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3852"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3965"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A61"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B64"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C79"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E54"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F65"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4073"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4174"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4269"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "436E"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4467"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4650"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4761"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4873"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4973"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A65"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B64"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D45"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E72"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F72"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "506F"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5172"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "530D"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "540A"
+
+::chipscope::csejtag_target unlock $handle
+::chipscope::csejtag_target close $handle
+::chipscope::csejtag_session destroy $handle
+exit
diff --git a/lib/CPUs/JCpu/asm/itest.jsm b/lib/CPUs/JCpu/asm/itest.jsm
new file mode 100644
index 0000000..9666253
--- /dev/null
+++ b/lib/CPUs/JCpu/asm/itest.jsm
@@ -0,0 +1,858 @@
+; -------------------------------------------------	
+;			PROJECT	"itest"
+; -------------------------------------------------	
+
+include "../../../jasm/cregs.inc.jsm"
+
+; -------------------------------------------------	
+				xmem
+msg:			dc		"Hallo", 0
+xram:			db		256
+
+				cmem	0
+cram:			db		256
+
+reg_revision:	equ		0x00			
+reg_testid:		equ		0x01			
+
+; -------------------------------------------------	
+			code
+			org		0x000
+reset:		jmp		start
+
+; -------------------------------------------------	
+			org		0x001
+int_vec:	jmp		isr
+
+; -------------------------------------------------	
+			org		0x010
+			
+start:		call	init
+			cin		R0, (cpu_revision)
+			xout	(reg_revision), R0
+			
+			; Test 0
+			call	test0
+			
+			; Test 1
+			mov		R0, 1
+			xout	(reg_testid), R0
+			call	test1
+			
+			; Test 2
+			mov		R0, 2
+			xout	(reg_testid), R0
+			call	test2
+
+			; Test 3
+			mov		R0, 3
+			xout	(reg_testid), R0
+			call	test3
+
+			; Test 4
+			mov		R0, 4
+			xout	(reg_testid), R0
+			call	test4
+
+			; Test 5
+			mov		R0, 5
+			xout	(reg_testid), R0
+			call	test5
+
+			; Test 6
+			mov		R0, 6
+			xout	(reg_testid), R0
+			call	test6
+
+			; Test 7
+			mov		R0, 7
+			xout	(reg_testid), R0
+			call	test7
+
+			; Test 8
+			mov		R0, 8
+			xout	(reg_testid), R0
+			call	test8
+
+			; Test 9
+			mov		R0, 9
+			xout	(reg_testid), R0
+			call	test9
+			
+			; Test 10
+			mov		R0, 10
+			xout	(reg_testid), R0
+			call	test10
+
+			; Test 11
+			mov		R0, 11
+			xout	(reg_testid), R0
+			call	test11
+
+			; Test 12
+			mov		R0, 12
+			xout	(reg_testid), R0
+			call	test12
+
+			; End of test
+			mov		R0, 0xFF
+			xout	(reg_testid), R0
+			
+			jmp		ok
+
+; -------------------------------------------------	
+init:		mov		R0, 0
+			mov		R1, 0
+			mov		R2, 0
+			mov		R3, 0
+			mov		R4, 0
+			mov		R5, 0
+			mov		R6, 0
+			mov		R7, 0
+			mov		R8, 0
+			mov		R9, 0
+			mov		R10, 0
+			mov		R11, 0
+			mov		R12, 0
+			mov		R13, 0
+			mov		R14, 0
+			mov		R15, 0
+			ret
+
+; -------------------------------------------------	
+; MOV|R|K
+; MOV|R|R
+test0:		mov		R0, 0x10
+			cmp		R0, 0x10
+			jne		error
+			add		R0, 1
+
+			mov		R1, R0
+			cmp		R1, 0x11
+			jne		error
+			add		R1, 1
+
+			mov		R2, R1
+			cmp		R2, 0x12
+			jne		error
+			add		R2, 1
+
+			mov		R3, R2
+			cmp		R3, 0x13
+			jne		error
+			add		R3, 1
+
+			mov		R4, R3
+			cmp		R4, 0x14
+			jne		error
+			add		R4, 1
+
+			mov		R5, R4
+			cmp		R5, 0x15
+			jne		error
+			add		R5, 1
+
+			mov		R6, R5
+			cmp		R6, 0x16
+			jne		error
+			add		R6, 1
+
+			mov		R7, R6
+			cmp		R7, 0x17
+			jne		error
+			add		R7, 1
+
+			mov		R8, R7
+			cmp		R8, 0x18
+			jne		error
+			add		R8, 1
+
+			mov		R9, R8
+			cmp		R9, 0x19
+			jne		error
+			add		R9, 1
+
+			mov		R10, R9
+			cmp		R10, 0x1A
+			jne		error
+			add		R10, 1
+
+			mov		R11, R10
+			cmp		R11, 0x1B
+			jne		error
+			add		R11, 1
+
+			mov		R12, R11
+			cmp		R12, 0x1C
+			jne		error
+			add		R12, 1
+
+			mov		R13, R12
+			cmp		R13, 0x1D
+			jne		error
+			add		R13, 1
+
+			mov		R14, R13
+			cmp		R14, 0x1E
+			jne		error
+			add		R14, 1
+
+			mov		R15, R14
+			cmp		R15, 0x1F
+			jne		error
+			add		R15, 1
+			
+			ret
+
+; -------------------------------------------------	
+; Instruction test
+; TST|R
+; CMP|R|K
+; JNZ|K
+; JC|K
+; JNE|K
+; JLT|K
+; JGT|K
+; JLE|K
+; JGE|K
+; JMP|K
+test1:		mov		R0, 0			; R0 <= 0
+			tst		R0
+			jnz		error	
+			jc		error	
+			cmp		R0, 0	
+			jne		error	
+			jlt		error	
+			jgt		error
+			jle		t1_ok10
+			jmp		error
+
+t1_ok10:	jeq		t1_ok20
+			jmp		error
+			
+t1_ok20:	jge		t1_ok30
+			jmp		error
+			
+t1_ok30:	cmp		R0, 0x55
+			jeq		error	
+			jlt		t1_ok40
+			jmp		error
+			
+t1_ok40:	jle		t1_ok50
+			jmp		error
+			
+t1_ok50:	jge		error
+			jgt		error
+			
+			mov		R0, 0x55		; R0 <= 0xAA
+			tst		R0
+			jz		error	
+			jc		error	
+			
+			cmp		R0, 0xAA
+			jeq		error	
+			jne		t1_ok60
+			jmp		error
+
+t1_ok60:	jlt		t1_ok70	
+			jmp		error
+
+t1_ok70:	jle		t1_ok80
+			jmp		error
+
+t1_ok80:	jgt		error
+
+			cmp		R0, 0x55
+			jeq		t1_ok90
+			jmp		error
+			
+t1_ok90:	jne		error
+			jlt		error
+			
+			jle		t1_ok100
+			jmp		error
+
+t1_ok100:	jgt		error
+			jge		t1_ok110
+			jmp		error
+			
+t1_ok110:	mov		R0, 0xAA		; R0 <= 0x55
+			tst		R0
+			jz		error	
+			jc		error	
+			
+			cmp		R0, 0x55
+			jeq		error	
+			jne		t1_ok120
+			jmp		error
+
+t1_ok120:	jgt		t1_ok130	
+			jmp		error
+
+t1_ok130:	jge		t1_ok140
+			jmp		error
+
+t1_ok140:	jlt		error
+			jle		error
+
+			ret
+			
+; -------------------------------------------------	
+; ADD|R|K
+; ADDC|R|K
+; ToDo: ADD|R|R
+; ToDo: ADDC|R|R
+; CMP|R|R
+test2:		mov		R0, 0
+			mov		R1, 0
+			mov		R2, R0
+			mov		R3, R1
+
+t2_loop:	add		R0, 0x01
+			addc	R1, 0x00
+			add		R2, 1
+			cmp		R2, 0
+			jne		t2_L1
+			add		R3, 1
+			cmp		R3, 0x02
+t2_L1:		jne		t2_loop
+			cmp		R0, R2
+			jne		error
+			cmp		R1, R3
+			jne		error
+			mov		R0, 0
+
+			ret
+
+; -------------------------------------------------	
+; SUB|R|K
+; SUBC|R|K
+; ToDo: SUB|R|R
+; ToDo: SUBC|R|R
+; CMP|R|R
+test3:		mov		R0, 0x00
+			mov		R1, 0x03
+			mov		R2, R0
+			mov		R3, R1
+
+t3_loop:	sub		R0, 0x01
+			subc	R1, 0x00
+			sub		R2, 1
+			cmp		R2, 0xFF
+			jne		t3_L1
+			sub		R3, 1
+			cmp		R3, 0x00
+t3_L1:		jne		t3_loop
+			cmp		R0, R2
+			jne		error
+			cmp		R1, R3
+			jne		error
+			mov		R0, 0
+
+			ret
+; -------------------------------------------------	
+; SUB|K|R
+; SUB|R|R
+; SUBC|R|R
+; SUBC|K|R
+; CMP|R|R
+test4:		mov		R0, 0x03
+			mov		R1, 0x05
+			sub		0x05, R0
+			sub		R1, 0x03
+			cmp		R0, R1
+			jne		error
+			mov		R0, 0x03
+			mov		R1, 0x05
+			sub		R0, R1
+			subc	0, R0
+			cmp		R0, 0x01
+			jne		error
+			add		R0, 0	
+			subc	R1, R0
+			cmp		R1, 0x04
+			jne		error
+			mov		R0, 0
+
+			ret
+						
+; -------------------------------------------------	
+; MOVC|R|Ri
+; MOVC|R|Ki
+; MOVC|Ri|R
+; MOVC|Ri|K
+; MOVC|Ki|R
+test5:		mov		R0, 1
+			movc	(cram+0x5A), R0
+			dec		R0			
+			movc	(cram+0), R0
+			movc	R1, (cram+0x5A)
+			movc	(R1), 0xA5
+			movc	R0, (R1)
+			movc	R1, (R1)
+			add		R1, 0xFF-0xA5
+			movc	R0, (R1)
+t5_loop1:	movc	(R0), R0
+			movc	R2, (R0)
+			cmp		R2, R0
+			jne		error
+			movc	(R2), R1
+			movc	R2, (R2)
+			cmp		R2, R1
+			jne		error
+			dec		R1
+			inc		R0
+			jnz		t5_loop1
+			
+			ret
+
+; -------------------------------------------------	
+; MOVX|R|Ri
+; MOVX|R|Ki
+; MOVX|Ri|R
+; MOVX|Ri|K
+; MOVX|Ki|R
+test6:		mov		R0, 1
+			movx	(xram+0x5A), R0
+			dec		R0			
+			movx	(xram+0), R0
+			movx	R1, (xram+0x5A)
+			movx	(R1), 0xA5
+			movx	R0, (R1)
+			movx	R1, (R1)
+			add		R1, 0xFF-0xA5
+			movx	R0, (R1)
+t6_loop1:	movx	(R0), R0
+			movx	R2, (R0)
+			cmp		R2, R0
+			jne		error
+			movx	(R2), R1
+			movx	R2, (R2)
+			cmp		R2, R1
+			jne		error
+			dec		R1
+			inc		R0
+			jnz		t6_loop1
+			
+			ret
+
+; -------------------------------------------------	
+; PUSH|R
+; POP|R
+test7:		mov		R0, 0xAA
+			mov		R1, 0
+t7_loop1:	push	R0
+			inc		R0
+			dec		R1
+			jnz		t7_loop1
+t7_loop2:	pop		R0
+			dec		R1
+			jnz		t7_loop2
+			cmp		R0, 0xAA
+			jne		error
+			
+			ret
+
+; -------------------------------------------------	
+; JMP|K
+; CALL|K
+; RET
+test8:		mov		R0, 0x55
+			push	R0
+			mov		R0, 0
+			mov		R1, 0xFF
+			call	t8_rec
+			pop		R0
+			cmp		R0, 0x55
+			jne		error
+
+			; Stack manipulations 1
+			mov		R0, return1'high
+			mov		R1, return1'low
+			cout	(cpu_stack_high), R0
+			push	R1
+
+			mov		R0, init'high
+			mov		R1, init'low
+			cout	(cpu_stack_high), R0
+			push	R1
+			ret
+			
+			; Stack manipulations 2
+return1:	mov		R0, return2'high
+			mov		R1, return2'low
+			cout	(cpu_stack_high), R0
+			push	R1
+
+			mov		R0, init'high
+			mov		R1, init'low
+			cout	(cpu_stack_high), R0
+			push	R1
+return2:	ret
+
+t8_rec:		cmp		R0, R1
+			jeq		ex_t8_rec
+			inc		R0
+			jmp		t8_rstub
+ex_t8_rec:	dec		R0
+			dec		R1
+			ret
+
+t8_rstub:	call	t8_rec
+			jmp		ex_t8_rec
+
+; -------------------------------------------------	
+; SWAP|R
+; SHL|R  
+; SHR|R  
+; ROL|R  
+; ROR|R  
+; ROLC|R 
+; RORC|R 
+test9:		mov		R0, 0xA5	; SWAP test
+			mov		R1, 0x5A
+			swap	R0
+			cmp		R0, 0x5A
+			jne		error
+			swap	R0
+			cmp		R0, 0xA5
+			jne		error
+			mov		R0, 0xD2
+			swap	R0
+			cmp		R0, 0x2D
+			jne		error
+			swap	R1
+			cmp		R0, 0x2D
+			jne		error
+			cmp		R1, 0xA5
+			jne		error
+			
+			mov		R0, 0x2D
+			shl		R0			; SHL test
+			cmp		R0, 0x5A
+			jne		error
+			shl		R0
+			cmp		R0, 0xB4
+			jne		error
+			shl		R0
+			cmp		R0, 0x68
+			jne		error
+			shl		R0
+			cmp		R0, 0xD0
+			jne		error
+			shl		R0
+			cmp		R0, 0xA0
+			jne		error
+			shl		R0
+			cmp		R0, 0x40
+			jne		error
+			shl		R0
+			cmp		R0, 0x80
+			jne		error
+			shl		R0
+			cmp		R0, 0x00
+			jne		error
+
+			mov		R1, 0x84
+			shr		R1			; SHR test
+			cmp		R1, 0x42
+			jne		error
+			shr		R1
+			cmp		R1, 0x21
+			jne		error
+			shr		R1
+			cmp		R1, 0x10
+			jne		error
+			shr		R1
+			cmp		R1, 0x08
+			jne		error
+			shr		R1
+			cmp		R1, 0x04
+			jne		error
+			shr		R1
+			cmp		R1, 0x02
+			jne		error
+			shr		R1
+			cmp		R1, 0x01
+			jne		error
+			shr		R1
+			cmp		R1, 0x00
+			jne		error
+
+			mov		R0, 0xC5	; ROL test
+			rol		R0			
+			cmp		R0, 0x8B
+			jne		error
+			rol		R0			
+			cmp		R0, 0x17
+			jne		error
+			rol		R0			
+			cmp		R0, 0x2E
+			jne		error
+			rol		R0			
+			cmp		R0, 0x5C
+			jne		error
+			rol		R0			
+			cmp		R0, 0xB8
+			jne		error
+			rol		R0			
+			cmp		R0, 0x71
+			jne		error
+			rol		R0			
+			cmp		R0, 0xE2
+			jne		error
+			rol		R0			
+			cmp		R0, 0xC5
+			jne		error
+
+			mov		R1, 0x63	; ROR test
+			ror		R1
+			cmp		R1, 0xB1
+			jne		error
+			ror		R1
+			cmp		R1, 0xD8
+			jne		error
+			ror		R1
+			cmp		R1, 0x6C
+			jne		error
+			ror		R1
+			cmp		R1, 0x36
+			jne		error
+			ror		R1
+			cmp		R1, 0x1B
+			jne		error
+			ror		R1
+			cmp		R1, 0x8D
+			jne		error
+			ror		R1
+			cmp		R1, 0xC6
+			jne		error
+			ror		R1
+			cmp		R1, 0x63
+			jne		error
+
+
+			xor		R0, R0		; ROLC generate
+			mov		R0, 0xC5	
+			rolc	R0		
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+
+			cmp		R0, 0xC5	; ROLC verify
+			jne		error
+			pop		R0
+			cmp		R0, 0x62
+			jne		error
+			pop		R0
+			cmp		R0, 0xB1
+			jne		error
+			pop		R0
+			cmp		R0, 0x58
+			jne		error
+			pop		R0
+			cmp		R0, 0xAC
+			jne		error
+			pop		R0
+			cmp		R0, 0x56
+			jne		error
+			pop		R0
+			cmp		R0, 0x2B
+			jne		error
+			pop		R0
+			cmp		R0, 0x15
+			jne		error
+			pop		R0
+			cmp		R0, 0x8A
+			jne		error
+
+			xor		R1, R1		; RORC generate
+			mov		R1, 0x63
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+
+			cmp		R1, 0x63	; RORC verify
+			jne		error
+			pop		R1
+			cmp		R1, 0xC6
+			jne		error
+			pop		R1
+			cmp		R1, 0x8C
+			jne		error
+			pop		R1
+			cmp		R1, 0x19
+			jne		error
+			pop		R1
+			cmp		R1, 0x33
+			jne		error
+			pop		R1
+			cmp		R1, 0x66
+			jne		error
+			pop		R1
+			cmp		R1, 0xCC
+			jne		error
+			pop		R1
+			cmp		R1, 0x98
+			jne		error
+			pop		R1
+			cmp		R1, 0x31
+			jne		error
+
+			ret
+			
+; -------------------------------------------------
+; AND|R|R
+; AND|R|K
+; OR|R|R 
+; OR|R|K 
+; XOR|R|R
+; XOR|R|K
+test10:		mov		R0, 0xA5	; AND
+			swap	R0
+			push	R0
+			and		R0, 0x0F
+			cmp		R0, 0x0A
+			jne		error
+			pop		R0
+			push	R0
+			and		R0, 0x0F
+			cmp		R0, 0x0A
+			pop		R1
+			jne		error
+			swap	R1
+			mov		R2, 0x0F
+			and		R1, R2
+			cmp		R1, 0x05
+			jne		error
+			
+			mov		R0, 0x05	; OR
+			mov		R2, 0xA0
+			swap	R0
+			or		R2, R0
+			cmp		R2, 0xF0
+			jne		error
+			swap	R0
+			or		R0, 0x50
+			cmp		R0, 0x55
+			jne		error
+			
+			mov		R1, 0x01
+			mov		R0, 0x01
+			xor		R0, 0x01
+			jnz		error
+			xor		R0, R1
+			cmp		R0, 0x01
+			jne		error
+			
+			ret
+			
+; -------------------------------------------------	
+test11:
+			mov		R0, 0x03
+			cout	(cpu_int_ctrl), R0
+			
+			xin		R0, (2)
+			or		R0, 1
+			xout	(2), R0
+			nop
+			nop
+			nop
+			nop
+			nop
+			nop
+			xin		R0, (2)
+			and		R0, 0xFE
+			xout	(2), R0
+			nop
+			nop
+			nop
+			nop
+			
+			cin		R0, (cpu_int_ctrl)
+			or		R0, 0x80
+			cout	(cpu_int_ctrl), R0
+			nop
+			cin		R0, (cpu_int_ctrl)
+			or		R0, 0x80
+			cout	(cpu_int_ctrl), R0
+			nop
+			cin		R0, (cpu_int_ctrl)
+			or		R0, 0x80
+			cout	(cpu_int_ctrl), R0
+			nop
+			cin		R0, (cpu_int_ctrl)
+			or		R0, 0x80
+			cout	(cpu_int_ctrl), R0
+			nop
+			nop
+			nop
+			nop
+			nop
+			nop
+			nop
+			nop
+			nop
+			ret
+
+; -------------------------------------------------	
+; Tests clrc, setc
+test12:		sub		R0, 0
+			jc		error
+			setc
+			jnc		error
+			nop
+			sub		R0, 0
+			jc		error
+			
+			mov		R0, 0
+			clrc
+			jc		error
+			setc
+			jnc		error
+			nop
+			clrc
+			jc		error
+			ret
+
+; -------------------------------------------------	
+isr:		inc		R14
+			reti
+
+; -------------------------------------------------	
+			org		0x3FF
+error:		jmp		error
+
+; -------------------------------------------------	
+			org		0x2FF
+ok:			jmp		ok
+
+; -------------------------------------------------	
+			
\ No newline at end of file
diff --git a/lib/CPUs/JCpu/asm/itest.tcl b/lib/CPUs/JCpu/asm/itest.tcl
new file mode 100644
index 0000000..3724ca6
--- /dev/null
+++ b/lib/CPUs/JCpu/asm/itest.tcl
@@ -0,0 +1,3407 @@
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: The ROM file for upload to target over JTAG 
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+# ---------------------------------------------------------------------
+# For Chipscope 9.1
+# ---------------------------------------------------------------------
+# Source JTAG/TCL frame work
+cd $env(CHIPSCOPE)\\bin\\nt
+source csejtag.tcl
+
+namespace import ::chipscope::*
+
+# Platform USB Cable
+set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
+# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
+
+# Create session
+set handle [::chipscope::csejtag_session create 0]
+
+# Open JTAG and lock
+set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
+set lock_result [::chipscope::csejtag_target lock $handle 1000]
+
+set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
+
+# Get Device ID
+set devtype "Virtex-4SX"
+set devid 2
+set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
+set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
+
+set CSE_OP $CSEJTAG_SHIFT_READWRITE
+set CSE_ES $CSEJTAG_RUN_TEST_IDLE
+
+# Write Program
+# JASM_ROM_INSERT_HERE
+# Assembled from itest.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
+# User 1
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
+
+# 0x000: JMP 0x010
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010"
+
+# 0x001: JMP 0x288
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130288"
+
+# 0x002:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000"
+
+# 0x003:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000"
+
+# 0x004:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000"
+
+# 0x005:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
+
+# 0x006:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000"
+
+# 0x007:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
+
+# 0x008:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000"
+
+# 0x009:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
+
+# 0x00A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000"
+
+# 0x00B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
+
+# 0x00C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000"
+
+# 0x00D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
+
+# 0x00E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000"
+
+# 0x00F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
+
+# 0x010: CALL 0x03B
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103B03B"
+
+# 0x011: CIN R00, (0x00)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01129000"
+
+# 0x012: XOUT (0x00), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01224000"
+
+# 0x013: CALL 0x04C
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0133B04C"
+
+# 0x014: MOV R00, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01403010"
+
+# 0x015: XOUT (0x01), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01524010"
+
+# 0x016: CALL 0x08D
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163B08D"
+
+# 0x017: MOV R00, 0x02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01703020"
+
+# 0x018: XOUT (0x01), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01824010"
+
+# 0x019: CALL 0x0C9
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193B0C9"
+
+# 0x01A: MOV R00, 0x03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A03030"
+
+# 0x01B: XOUT (0x01), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B24010"
+
+# 0x01C: CALL 0x0DB
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01C3B0DB"
+
+# 0x01D: MOV R00, 0x04
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01D03040"
+
+# 0x01E: XOUT (0x01), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01E24010"
+
+# 0x01F: CALL 0x0ED
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01F3B0ED"
+
+# 0x020: MOV R00, 0x05
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02003050"
+
+# 0x021: XOUT (0x01), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02124010"
+
+# 0x022: CALL 0x0FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0223B0FF"
+
+# 0x023: MOV R00, 0x06
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02303060"
+
+# 0x024: XOUT (0x01), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02424010"
+
+# 0x025: CALL 0x115
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0253B115"
+
+# 0x026: MOV R00, 0x07
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02603070"
+
+# 0x027: XOUT (0x01), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02724010"
+
+# 0x028: CALL 0x12B
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0283B12B"
+
+# 0x029: MOV R00, 0x08
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02903080"
+
+# 0x02A: XOUT (0x01), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02A24010"
+
+# 0x02B: CALL 0x137
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02B3B137"
+
+# 0x02C: MOV R00, 0x09
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02C03090"
+
+# 0x02D: XOUT (0x01), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02D24010"
+
+# 0x02E: CALL 0x15A
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02E3B15A"
+
+# 0x02F: MOV R00, 0x0A
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02F030A0"
+
+# 0x030: XOUT (0x01), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03024010"
+
+# 0x031: CALL 0x22A
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0313B22A"
+
+# 0x032: MOV R00, 0x0B
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "032030B0"
+
+# 0x033: XOUT (0x01), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03324010"
+
+# 0x034: CALL 0x24D
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0343B24D"
+
+# 0x035: MOV R00, 0x0C
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "035030C0"
+
+# 0x036: XOUT (0x01), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03624010"
+
+# 0x037: CALL 0x278
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0373B278"
+
+# 0x038: MOV R00, 0xFF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03803FF0"
+
+# 0x039: XOUT (0x01), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03924010"
+
+# 0x03A: JMP 0x2FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03A302FF"
+
+# 0x03B: MOV R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03B03000"
+
+# 0x03C: MOV R01, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03C03001"
+
+# 0x03D: MOV R02, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03D03002"
+
+# 0x03E: MOV R03, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03E03003"
+
+# 0x03F: MOV R04, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03F03004"
+
+# 0x040: MOV R05, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04003005"
+
+# 0x041: MOV R06, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04103006"
+
+# 0x042: MOV R07, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04203007"
+
+# 0x043: MOV R08, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04303008"
+
+# 0x044: MOV R09, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04403009"
+
+# 0x045: MOV R10, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0450300A"
+
+# 0x046: MOV R11, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0460300B"
+
+# 0x047: MOV R12, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0470300C"
+
+# 0x048: MOV R13, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0480300D"
+
+# 0x049: MOV R14, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0490300E"
+
+# 0x04A: MOV R15, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04A0300F"
+
+# 0x04B: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04B3E000"
+
+# 0x04C: MOV R00, 0x10
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04C03100"
+
+# 0x04D: CMP R00, 0x10
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04D0F100"
+
+# 0x04E: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04E3A3FF"
+
+# 0x04F: ADD R00, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04F11010"
+
+# 0x050: MOV R01, R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05002001"
+
+# 0x051: CMP R01, 0x11
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0510F111"
+
+# 0x052: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0523A3FF"
+
+# 0x053: ADD R01, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05311011"
+
+# 0x054: MOV R02, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05402012"
+
+# 0x055: CMP R02, 0x12
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0550F122"
+
+# 0x056: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0563A3FF"
+
+# 0x057: ADD R02, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05711012"
+
+# 0x058: MOV R03, R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05802023"
+
+# 0x059: CMP R03, 0x13
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0590F133"
+
+# 0x05A: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05A3A3FF"
+
+# 0x05B: ADD R03, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05B11013"
+
+# 0x05C: MOV R04, R03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05C02034"
+
+# 0x05D: CMP R04, 0x14
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05D0F144"
+
+# 0x05E: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05E3A3FF"
+
+# 0x05F: ADD R04, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05F11014"
+
+# 0x060: MOV R05, R04
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06002045"
+
+# 0x061: CMP R05, 0x15
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0610F155"
+
+# 0x062: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0623A3FF"
+
+# 0x063: ADD R05, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06311015"
+
+# 0x064: MOV R06, R05
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06402056"
+
+# 0x065: CMP R06, 0x16
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0650F166"
+
+# 0x066: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0663A3FF"
+
+# 0x067: ADD R06, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06711016"
+
+# 0x068: MOV R07, R06
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06802067"
+
+# 0x069: CMP R07, 0x17
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0690F177"
+
+# 0x06A: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06A3A3FF"
+
+# 0x06B: ADD R07, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06B11017"
+
+# 0x06C: MOV R08, R07
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06C02078"
+
+# 0x06D: CMP R08, 0x18
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06D0F188"
+
+# 0x06E: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06E3A3FF"
+
+# 0x06F: ADD R08, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06F11018"
+
+# 0x070: MOV R09, R08
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07002089"
+
+# 0x071: CMP R09, 0x19
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0710F199"
+
+# 0x072: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0723A3FF"
+
+# 0x073: ADD R09, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07311019"
+
+# 0x074: MOV R10, R09
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0740209A"
+
+# 0x075: CMP R10, 0x1A
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0750F1AA"
+
+# 0x076: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0763A3FF"
+
+# 0x077: ADD R10, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0771101A"
+
+# 0x078: MOV R11, R10
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "078020AB"
+
+# 0x079: CMP R11, 0x1B
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0790F1BB"
+
+# 0x07A: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07A3A3FF"
+
+# 0x07B: ADD R11, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07B1101B"
+
+# 0x07C: MOV R12, R11
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07C020BC"
+
+# 0x07D: CMP R12, 0x1C
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07D0F1CC"
+
+# 0x07E: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07E3A3FF"
+
+# 0x07F: ADD R12, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07F1101C"
+
+# 0x080: MOV R13, R12
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "080020CD"
+
+# 0x081: CMP R13, 0x1D
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0810F1DD"
+
+# 0x082: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0823A3FF"
+
+# 0x083: ADD R13, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0831101D"
+
+# 0x084: MOV R14, R13
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "084020DE"
+
+# 0x085: CMP R14, 0x1E
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0850F1EE"
+
+# 0x086: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0863A3FF"
+
+# 0x087: ADD R14, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0871101E"
+
+# 0x088: MOV R15, R14
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "088020EF"
+
+# 0x089: CMP R15, 0x1F
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0890F1FF"
+
+# 0x08A: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08A3A3FF"
+
+# 0x08B: ADD R15, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08B1101F"
+
+# 0x08C: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08C3E000"
+
+# 0x08D: MOV R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08D03000"
+
+# 0x08E: TST R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08E0F000"
+
+# 0x08F: JNZ 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08F323FF"
+
+# 0x090: JC 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "090333FF"
+
+# 0x091: CMP R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0910F000"
+
+# 0x092: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0923A3FF"
+
+# 0x093: JLT 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "093353FF"
+
+# 0x094: JGT 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "094363FF"
+
+# 0x095: JLE 0x097
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09537097"
+
+# 0x096: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "096303FF"
+
+# 0x097: JEQ 0x099
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09739099"
+
+# 0x098: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "098303FF"
+
+# 0x099: JGE 0x09B
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0993809B"
+
+# 0x09A: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09A303FF"
+
+# 0x09B: CMP R00, 0x55
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09B0F550"
+
+# 0x09C: JEQ 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09C393FF"
+
+# 0x09D: JLT 0x09F
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09D3509F"
+
+# 0x09E: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09E303FF"
+
+# 0x09F: JLE 0x0A1
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09F370A1"
+
+# 0x0A0: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A0303FF"
+
+# 0x0A1: JGE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A1383FF"
+
+# 0x0A2: JGT 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A2363FF"
+
+# 0x0A3: MOV R00, 0x55
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A303550"
+
+# 0x0A4: TST R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A40F000"
+
+# 0x0A5: JZ 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A5313FF"
+
+# 0x0A6: JC 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A6333FF"
+
+# 0x0A7: CMP R00, 0xAA
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A70FAA0"
+
+# 0x0A8: JEQ 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A8393FF"
+
+# 0x0A9: JNE 0x0AB
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A93A0AB"
+
+# 0x0AA: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AA303FF"
+
+# 0x0AB: JLT 0x0AD
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AB350AD"
+
+# 0x0AC: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AC303FF"
+
+# 0x0AD: JLE 0x0AF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AD370AF"
+
+# 0x0AE: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AE303FF"
+
+# 0x0AF: JGT 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AF363FF"
+
+# 0x0B0: CMP R00, 0x55
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B00F550"
+
+# 0x0B1: JEQ 0x0B3
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B1390B3"
+
+# 0x0B2: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B2303FF"
+
+# 0x0B3: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B33A3FF"
+
+# 0x0B4: JLT 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B4353FF"
+
+# 0x0B5: JLE 0x0B7
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B5370B7"
+
+# 0x0B6: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B6303FF"
+
+# 0x0B7: JGT 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B7363FF"
+
+# 0x0B8: JGE 0x0BA
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B8380BA"
+
+# 0x0B9: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B9303FF"
+
+# 0x0BA: MOV R00, 0xAA
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BA03AA0"
+
+# 0x0BB: TST R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BB0F000"
+
+# 0x0BC: JZ 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BC313FF"
+
+# 0x0BD: JC 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BD333FF"
+
+# 0x0BE: CMP R00, 0x55
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BE0F550"
+
+# 0x0BF: JEQ 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BF393FF"
+
+# 0x0C0: JNE 0x0C2
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C03A0C2"
+
+# 0x0C1: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C1303FF"
+
+# 0x0C2: JGT 0x0C4
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C2360C4"
+
+# 0x0C3: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C3303FF"
+
+# 0x0C4: JGE 0x0C6
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C4380C6"
+
+# 0x0C5: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C5303FF"
+
+# 0x0C6: JLT 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C6353FF"
+
+# 0x0C7: JLE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C7373FF"
+
+# 0x0C8: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C83E000"
+
+# 0x0C9: MOV R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C903000"
+
+# 0x0CA: MOV R01, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CA03001"
+
+# 0x0CB: MOV R02, R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CB02002"
+
+# 0x0CC: MOV R03, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CC02013"
+
+# 0x0CD: ADD R00, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CD11010"
+
+# 0x0CE: ADDC R01, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CE13001"
+
+# 0x0CF: ADD R02, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CF11012"
+
+# 0x0D0: CMP R02, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D00F002"
+
+# 0x0D1: JNE 0x0D4
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D13A0D4"
+
+# 0x0D2: ADD R03, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D211013"
+
+# 0x0D3: CMP R03, 0x02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D30F023"
+
+# 0x0D4: JNE 0x0CD
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D43A0CD"
+
+# 0x0D5: CMP R00, R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D50E020"
+
+# 0x0D6: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D63A3FF"
+
+# 0x0D7: CMP R01, R03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D70E031"
+
+# 0x0D8: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D83A3FF"
+
+# 0x0D9: MOV R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D903000"
+
+# 0x0DA: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DA3E000"
+
+# 0x0DB: MOV R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DB03000"
+
+# 0x0DC: MOV R01, 0x03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DC03031"
+
+# 0x0DD: MOV R02, R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DD02002"
+
+# 0x0DE: MOV R03, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DE02013"
+
+# 0x0DF: SUB R00, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DF15010"
+
+# 0x0E0: SUBC R01, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E017001"
+
+# 0x0E1: SUB R02, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E115012"
+
+# 0x0E2: CMP R02, 0xFF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E20FFF2"
+
+# 0x0E3: JNE 0x0E6
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E33A0E6"
+
+# 0x0E4: SUB R03, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E415013"
+
+# 0x0E5: CMP R03, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E50F003"
+
+# 0x0E6: JNE 0x0DF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E63A0DF"
+
+# 0x0E7: CMP R00, R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E70E020"
+
+# 0x0E8: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E83A3FF"
+
+# 0x0E9: CMP R01, R03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E90E031"
+
+# 0x0EA: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EA3A3FF"
+
+# 0x0EB: MOV R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EB03000"
+
+# 0x0EC: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EC3E000"
+
+# 0x0ED: MOV R00, 0x03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0ED03030"
+
+# 0x0EE: MOV R01, 0x05
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EE03051"
+
+# 0x0EF: SUB 0x05, R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EF2E050"
+
+# 0x0F0: SUB R01, 0x03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F015031"
+
+# 0x0F1: CMP R00, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F10E010"
+
+# 0x0F2: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F23A3FF"
+
+# 0x0F3: MOV R00, 0x03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F303030"
+
+# 0x0F4: MOV R01, 0x05
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F403051"
+
+# 0x0F5: SUB R00, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F514010"
+
+# 0x0F6: SUBC 0x00, R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F62F000"
+
+# 0x0F7: CMP R00, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F70F010"
+
+# 0x0F8: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F83A3FF"
+
+# 0x0F9: ADD R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F911000"
+
+# 0x0FA: SUBC R01, R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FA16001"
+
+# 0x0FB: CMP R01, 0x04
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FB0F041"
+
+# 0x0FC: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FC3A3FF"
+
+# 0x0FD: MOV R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FD03000"
+
+# 0x0FE: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FE3E000"
+
+# 0x0FF: MOV R00, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FF03010"
+
+# 0x100: MOVC (0x5A), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1000D5A0"
+
+# 0x101: DEC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10115010"
+
+# 0x102: MOVC (0x00), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1020D000"
+
+# 0x103: MOVC R01, (0x5A)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1030A5A1"
+
+# 0x104: MOVC (R01), 0xA5
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1040CA51"
+
+# 0x105: MOVC R00, (R01)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10509010"
+
+# 0x106: MOVC R01, (R01)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10609011"
+
+# 0x107: ADD R01, 0x5A
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "107115A1"
+
+# 0x108: MOVC R00, (R01)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10809010"
+
+# 0x109: MOVC (R00), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1090B000"
+
+# 0x10A: MOVC R02, (R00)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10A09002"
+
+# 0x10B: CMP R02, R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10B0E002"
+
+# 0x10C: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10C3A3FF"
+
+# 0x10D: MOVC (R01), R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10D0B021"
+
+# 0x10E: MOVC R02, (R02)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10E09022"
+
+# 0x10F: CMP R02, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10F0E012"
+
+# 0x110: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1103A3FF"
+
+# 0x111: DEC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11115011"
+
+# 0x112: INC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11211010"
+
+# 0x113: JNZ 0x109
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11332109"
+
+# 0x114: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1143E000"
+
+# 0x115: MOV R00, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11503010"
+
+# 0x116: MOVX (0x60), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11608600"
+
+# 0x117: DEC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11715010"
+
+# 0x118: MOVX (0x06), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11808060"
+
+# 0x119: MOVX R01, (0x60)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11905601"
+
+# 0x11A: MOVX (R01), 0xA5
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11A07A51"
+
+# 0x11B: MOVX R00, (R01)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11B04010"
+
+# 0x11C: MOVX R01, (R01)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11C04011"
+
+# 0x11D: ADD R01, 0x5A
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11D115A1"
+
+# 0x11E: MOVX R00, (R01)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11E04010"
+
+# 0x11F: MOVX (R00), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11F06000"
+
+# 0x120: MOVX R02, (R00)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12004002"
+
+# 0x121: CMP R02, R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1210E002"
+
+# 0x122: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1223A3FF"
+
+# 0x123: MOVX (R01), R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12306021"
+
+# 0x124: MOVX R02, (R02)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12404022"
+
+# 0x125: CMP R02, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1250E012"
+
+# 0x126: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1263A3FF"
+
+# 0x127: DEC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12715011"
+
+# 0x128: INC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12811010"
+
+# 0x129: JNZ 0x11F
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1293211F"
+
+# 0x12A: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12A3E000"
+
+# 0x12B: MOV R00, 0xAA
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12B03AA0"
+
+# 0x12C: MOV R01, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12C03001"
+
+# 0x12D: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12D3C000"
+
+# 0x12E: INC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12E11010"
+
+# 0x12F: DEC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12F15011"
+
+# 0x130: JNZ 0x12D
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1303212D"
+
+# 0x131: POP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1313D000"
+
+# 0x132: DEC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13215011"
+
+# 0x133: JNZ 0x131
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13332131"
+
+# 0x134: CMP R00, 0xAA
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1340FAA0"
+
+# 0x135: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1353A3FF"
+
+# 0x136: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1363E000"
+
+# 0x137: MOV R00, 0x55
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13703550"
+
+# 0x138: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1383C000"
+
+# 0x139: MOV R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13903000"
+
+# 0x13A: MOV R01, 0xFF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13A03FF1"
+
+# 0x13B: CALL 0x151
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13B3B151"
+
+# 0x13C: POP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13C3D000"
+
+# 0x13D: CMP R00, 0x55
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13D0F550"
+
+# 0x13E: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13E3A3FF"
+
+# 0x13F: MOV R00, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13F03010"
+
+# 0x140: MOV R01, 0x48
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14003481"
+
+# 0x141: COUT (0x05), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14126050"
+
+# 0x142: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1423C001"
+
+# 0x143: MOV R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14303000"
+
+# 0x144: MOV R01, 0x3B
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "144033B1"
+
+# 0x145: COUT (0x05), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14526050"
+
+# 0x146: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1463C001"
+
+# 0x147: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1473E000"
+
+# 0x148: MOV R00, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14803010"
+
+# 0x149: MOV R01, 0x50
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14903501"
+
+# 0x14A: COUT (0x05), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14A26050"
+
+# 0x14B: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14B3C001"
+
+# 0x14C: MOV R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14C03000"
+
+# 0x14D: MOV R01, 0x3B
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14D033B1"
+
+# 0x14E: COUT (0x05), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14E26050"
+
+# 0x14F: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14F3C001"
+
+# 0x150: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1503E000"
+
+# 0x151: CMP R00, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1510E010"
+
+# 0x152: JEQ 0x155
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15239155"
+
+# 0x153: INC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15311010"
+
+# 0x154: JMP 0x158
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15430158"
+
+# 0x155: DEC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15515010"
+
+# 0x156: DEC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15615011"
+
+# 0x157: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1573E000"
+
+# 0x158: CALL 0x151
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1583B151"
+
+# 0x159: JMP 0x155
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15930155"
+
+# 0x15A: MOV R00, 0xA5
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15A03A50"
+
+# 0x15B: MOV R01, 0x5A
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15B035A1"
+
+# 0x15C: SWAP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15C2A000"
+
+# 0x15D: CMP R00, 0x5A
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15D0F5A0"
+
+# 0x15E: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15E3A3FF"
+
+# 0x15F: SWAP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15F2A000"
+
+# 0x160: CMP R00, 0xA5
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1600FA50"
+
+# 0x161: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1613A3FF"
+
+# 0x162: MOV R00, 0xD2
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16203D20"
+
+# 0x163: SWAP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1632A000"
+
+# 0x164: CMP R00, 0x2D
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1640F2D0"
+
+# 0x165: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1653A3FF"
+
+# 0x166: SWAP R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1662A001"
+
+# 0x167: CMP R00, 0x2D
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1670F2D0"
+
+# 0x168: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1683A3FF"
+
+# 0x169: CMP R01, 0xA5
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1690FA51"
+
+# 0x16A: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16A3A3FF"
+
+# 0x16B: MOV R00, 0x2D
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16B032D0"
+
+# 0x16C: SHL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16C1E000"
+
+# 0x16D: CMP R00, 0x5A
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16D0F5A0"
+
+# 0x16E: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16E3A3FF"
+
+# 0x16F: SHL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16F1E000"
+
+# 0x170: CMP R00, 0xB4
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1700FB40"
+
+# 0x171: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1713A3FF"
+
+# 0x172: SHL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1721E000"
+
+# 0x173: CMP R00, 0x68
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1730F680"
+
+# 0x174: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1743A3FF"
+
+# 0x175: SHL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1751E000"
+
+# 0x176: CMP R00, 0xD0
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1760FD00"
+
+# 0x177: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1773A3FF"
+
+# 0x178: SHL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1781E000"
+
+# 0x179: CMP R00, 0xA0
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1790FA00"
+
+# 0x17A: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17A3A3FF"
+
+# 0x17B: SHL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17B1E000"
+
+# 0x17C: CMP R00, 0x40
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17C0F400"
+
+# 0x17D: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17D3A3FF"
+
+# 0x17E: SHL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17E1E000"
+
+# 0x17F: CMP R00, 0x80
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17F0F800"
+
+# 0x180: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1803A3FF"
+
+# 0x181: SHL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1811E000"
+
+# 0x182: CMP R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1820F000"
+
+# 0x183: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1833A3FF"
+
+# 0x184: MOV R01, 0x84
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18403841"
+
+# 0x185: SHR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1851F001"
+
+# 0x186: CMP R01, 0x42
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1860F421"
+
+# 0x187: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1873A3FF"
+
+# 0x188: SHR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1881F001"
+
+# 0x189: CMP R01, 0x21
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1890F211"
+
+# 0x18A: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18A3A3FF"
+
+# 0x18B: SHR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18B1F001"
+
+# 0x18C: CMP R01, 0x10
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18C0F101"
+
+# 0x18D: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18D3A3FF"
+
+# 0x18E: SHR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18E1F001"
+
+# 0x18F: CMP R01, 0x08
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18F0F081"
+
+# 0x190: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1903A3FF"
+
+# 0x191: SHR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1911F001"
+
+# 0x192: CMP R01, 0x04
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1920F041"
+
+# 0x193: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1933A3FF"
+
+# 0x194: SHR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1941F001"
+
+# 0x195: CMP R01, 0x02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1950F021"
+
+# 0x196: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1963A3FF"
+
+# 0x197: SHR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1971F001"
+
+# 0x198: CMP R01, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1980F011"
+
+# 0x199: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1993A3FF"
+
+# 0x19A: SHR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19A1F001"
+
+# 0x19B: CMP R01, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19B0F001"
+
+# 0x19C: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19C3A3FF"
+
+# 0x19D: MOV R00, 0xC5
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19D03C50"
+
+# 0x19E: ROL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19E20000"
+
+# 0x19F: CMP R00, 0x8B
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19F0F8B0"
+
+# 0x1A0: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A03A3FF"
+
+# 0x1A1: ROL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A120000"
+
+# 0x1A2: CMP R00, 0x17
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A20F170"
+
+# 0x1A3: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A33A3FF"
+
+# 0x1A4: ROL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A420000"
+
+# 0x1A5: CMP R00, 0x2E
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A50F2E0"
+
+# 0x1A6: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A63A3FF"
+
+# 0x1A7: ROL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A720000"
+
+# 0x1A8: CMP R00, 0x5C
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A80F5C0"
+
+# 0x1A9: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A93A3FF"
+
+# 0x1AA: ROL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AA20000"
+
+# 0x1AB: CMP R00, 0xB8
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AB0FB80"
+
+# 0x1AC: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AC3A3FF"
+
+# 0x1AD: ROL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AD20000"
+
+# 0x1AE: CMP R00, 0x71
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AE0F710"
+
+# 0x1AF: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AF3A3FF"
+
+# 0x1B0: ROL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B020000"
+
+# 0x1B1: CMP R00, 0xE2
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B10FE20"
+
+# 0x1B2: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B23A3FF"
+
+# 0x1B3: ROL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B320000"
+
+# 0x1B4: CMP R00, 0xC5
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B40FC50"
+
+# 0x1B5: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B53A3FF"
+
+# 0x1B6: MOV R01, 0x63
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B603631"
+
+# 0x1B7: ROR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B721001"
+
+# 0x1B8: CMP R01, 0xB1
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B80FB11"
+
+# 0x1B9: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B93A3FF"
+
+# 0x1BA: ROR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BA21001"
+
+# 0x1BB: CMP R01, 0xD8
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BB0FD81"
+
+# 0x1BC: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BC3A3FF"
+
+# 0x1BD: ROR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BD21001"
+
+# 0x1BE: CMP R01, 0x6C
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BE0F6C1"
+
+# 0x1BF: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BF3A3FF"
+
+# 0x1C0: ROR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C021001"
+
+# 0x1C1: CMP R01, 0x36
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C10F361"
+
+# 0x1C2: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C23A3FF"
+
+# 0x1C3: ROR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C321001"
+
+# 0x1C4: CMP R01, 0x1B
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C40F1B1"
+
+# 0x1C5: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C53A3FF"
+
+# 0x1C6: ROR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C621001"
+
+# 0x1C7: CMP R01, 0x8D
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C70F8D1"
+
+# 0x1C8: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C83A3FF"
+
+# 0x1C9: ROR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C921001"
+
+# 0x1CA: CMP R01, 0xC6
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CA0FC61"
+
+# 0x1CB: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CB3A3FF"
+
+# 0x1CC: ROR R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CC21001"
+
+# 0x1CD: CMP R01, 0x63
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CD0F631"
+
+# 0x1CE: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CE3A3FF"
+
+# 0x1CF: XOR R00, R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CF1C000"
+
+# 0x1D0: MOV R00, 0xC5
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D003C50"
+
+# 0x1D1: ROLC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D122000"
+
+# 0x1D2: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D23C000"
+
+# 0x1D3: ROLC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D322000"
+
+# 0x1D4: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D43C000"
+
+# 0x1D5: ROLC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D522000"
+
+# 0x1D6: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D63C000"
+
+# 0x1D7: ROLC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D722000"
+
+# 0x1D8: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D83C000"
+
+# 0x1D9: ROLC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D922000"
+
+# 0x1DA: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DA3C000"
+
+# 0x1DB: ROLC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DB22000"
+
+# 0x1DC: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DC3C000"
+
+# 0x1DD: ROLC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DD22000"
+
+# 0x1DE: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DE3C000"
+
+# 0x1DF: ROLC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DF22000"
+
+# 0x1E0: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E03C000"
+
+# 0x1E1: ROLC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E122000"
+
+# 0x1E2: CMP R00, 0xC5
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E20FC50"
+
+# 0x1E3: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E33A3FF"
+
+# 0x1E4: POP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E43D000"
+
+# 0x1E5: CMP R00, 0x62
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E50F620"
+
+# 0x1E6: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E63A3FF"
+
+# 0x1E7: POP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E73D000"
+
+# 0x1E8: CMP R00, 0xB1
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E80FB10"
+
+# 0x1E9: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E93A3FF"
+
+# 0x1EA: POP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EA3D000"
+
+# 0x1EB: CMP R00, 0x58
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EB0F580"
+
+# 0x1EC: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EC3A3FF"
+
+# 0x1ED: POP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1ED3D000"
+
+# 0x1EE: CMP R00, 0xAC
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EE0FAC0"
+
+# 0x1EF: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EF3A3FF"
+
+# 0x1F0: POP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F03D000"
+
+# 0x1F1: CMP R00, 0x56
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F10F560"
+
+# 0x1F2: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F23A3FF"
+
+# 0x1F3: POP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F33D000"
+
+# 0x1F4: CMP R00, 0x2B
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F40F2B0"
+
+# 0x1F5: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F53A3FF"
+
+# 0x1F6: POP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F63D000"
+
+# 0x1F7: CMP R00, 0x15
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F70F150"
+
+# 0x1F8: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F83A3FF"
+
+# 0x1F9: POP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F93D000"
+
+# 0x1FA: CMP R00, 0x8A
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FA0F8A0"
+
+# 0x1FB: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FB3A3FF"
+
+# 0x1FC: XOR R01, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FC1C011"
+
+# 0x1FD: MOV R01, 0x63
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FD03631"
+
+# 0x1FE: RORC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FE23001"
+
+# 0x1FF: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FF3C001"
+
+# 0x200: RORC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20023001"
+
+# 0x201: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2013C001"
+
+# 0x202: RORC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20223001"
+
+# 0x203: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2033C001"
+
+# 0x204: RORC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20423001"
+
+# 0x205: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2053C001"
+
+# 0x206: RORC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20623001"
+
+# 0x207: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2073C001"
+
+# 0x208: RORC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20823001"
+
+# 0x209: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2093C001"
+
+# 0x20A: RORC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20A23001"
+
+# 0x20B: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20B3C001"
+
+# 0x20C: RORC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20C23001"
+
+# 0x20D: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20D3C001"
+
+# 0x20E: RORC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20E23001"
+
+# 0x20F: CMP R01, 0x63
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20F0F631"
+
+# 0x210: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2103A3FF"
+
+# 0x211: POP R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2113D001"
+
+# 0x212: CMP R01, 0xC6
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2120FC61"
+
+# 0x213: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2133A3FF"
+
+# 0x214: POP R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2143D001"
+
+# 0x215: CMP R01, 0x8C
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2150F8C1"
+
+# 0x216: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2163A3FF"
+
+# 0x217: POP R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2173D001"
+
+# 0x218: CMP R01, 0x19
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2180F191"
+
+# 0x219: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2193A3FF"
+
+# 0x21A: POP R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21A3D001"
+
+# 0x21B: CMP R01, 0x33
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21B0F331"
+
+# 0x21C: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21C3A3FF"
+
+# 0x21D: POP R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21D3D001"
+
+# 0x21E: CMP R01, 0x66
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21E0F661"
+
+# 0x21F: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21F3A3FF"
+
+# 0x220: POP R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2203D001"
+
+# 0x221: CMP R01, 0xCC
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2210FCC1"
+
+# 0x222: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2223A3FF"
+
+# 0x223: POP R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2233D001"
+
+# 0x224: CMP R01, 0x98
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2240F981"
+
+# 0x225: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2253A3FF"
+
+# 0x226: POP R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2263D001"
+
+# 0x227: CMP R01, 0x31
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2270F311"
+
+# 0x228: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2283A3FF"
+
+# 0x229: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2293E000"
+
+# 0x22A: MOV R00, 0xA5
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22A03A50"
+
+# 0x22B: SWAP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22B2A000"
+
+# 0x22C: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22C3C000"
+
+# 0x22D: AND R00, 0x0F
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22D190F0"
+
+# 0x22E: CMP R00, 0x0A
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22E0F0A0"
+
+# 0x22F: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22F3A3FF"
+
+# 0x230: POP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2303D000"
+
+# 0x231: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2313C000"
+
+# 0x232: AND R00, 0x0F
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "232190F0"
+
+# 0x233: CMP R00, 0x0A
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2330F0A0"
+
+# 0x234: POP R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2343D001"
+
+# 0x235: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2353A3FF"
+
+# 0x236: SWAP R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2362A001"
+
+# 0x237: MOV R02, 0x0F
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "237030F2"
+
+# 0x238: AND R01, R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23818021"
+
+# 0x239: CMP R01, 0x05
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2390F051"
+
+# 0x23A: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23A3A3FF"
+
+# 0x23B: MOV R00, 0x05
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23B03050"
+
+# 0x23C: MOV R02, 0xA0
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23C03A02"
+
+# 0x23D: SWAP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23D2A000"
+
+# 0x23E: OR R02, R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23E1A002"
+
+# 0x23F: CMP R02, 0xF0
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23F0FF02"
+
+# 0x240: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2403A3FF"
+
+# 0x241: SWAP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2412A000"
+
+# 0x242: OR R00, 0x50
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2421B500"
+
+# 0x243: CMP R00, 0x55
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2430F550"
+
+# 0x244: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2443A3FF"
+
+# 0x245: MOV R01, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24503011"
+
+# 0x246: MOV R00, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24603010"
+
+# 0x247: XOR R00, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2471D010"
+
+# 0x248: JNZ 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "248323FF"
+
+# 0x249: XOR R00, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2491C010"
+
+# 0x24A: CMP R00, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24A0F010"
+
+# 0x24B: JNE 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24B3A3FF"
+
+# 0x24C: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24C3E000"
+
+# 0x24D: MOV R00, 0x03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24D03030"
+
+# 0x24E: COUT (0x03), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24E26030"
+
+# 0x24F: XIN R00, (0x02)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24F28020"
+
+# 0x250: OR R00, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2501B010"
+
+# 0x251: XOUT (0x02), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25124020"
+
+# 0x252: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25200000"
+
+# 0x253: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25300000"
+
+# 0x254: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25400000"
+
+# 0x255: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25500000"
+
+# 0x256: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25600000"
+
+# 0x257: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25700000"
+
+# 0x258: XIN R00, (0x02)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25828020"
+
+# 0x259: AND R00, 0xFE
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25919FE0"
+
+# 0x25A: XOUT (0x02), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25A24020"
+
+# 0x25B: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25B00000"
+
+# 0x25C: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25C00000"
+
+# 0x25D: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25D00000"
+
+# 0x25E: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25E00000"
+
+# 0x25F: CIN R00, (0x03)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25F29030"
+
+# 0x260: OR R00, 0x80
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2601B800"
+
+# 0x261: COUT (0x03), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26126030"
+
+# 0x262: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26200000"
+
+# 0x263: CIN R00, (0x03)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26329030"
+
+# 0x264: OR R00, 0x80
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2641B800"
+
+# 0x265: COUT (0x03), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26526030"
+
+# 0x266: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26600000"
+
+# 0x267: CIN R00, (0x03)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26729030"
+
+# 0x268: OR R00, 0x80
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2681B800"
+
+# 0x269: COUT (0x03), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26926030"
+
+# 0x26A: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26A00000"
+
+# 0x26B: CIN R00, (0x03)
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26B29030"
+
+# 0x26C: OR R00, 0x80
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26C1B800"
+
+# 0x26D: COUT (0x03), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26D26030"
+
+# 0x26E: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26E00000"
+
+# 0x26F: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26F00000"
+
+# 0x270: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27000000"
+
+# 0x271: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27100000"
+
+# 0x272: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27200000"
+
+# 0x273: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27300000"
+
+# 0x274: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27400000"
+
+# 0x275: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27500000"
+
+# 0x276: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27600000"
+
+# 0x277: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2773E000"
+
+# 0x278: SUB R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27815000"
+
+# 0x279: JC 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "279333FF"
+
+# 0x27A: SETC
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27A2B000"
+
+# 0x27B: JNC 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27B343FF"
+
+# 0x27C: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27C00000"
+
+# 0x27D: SUB R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27D15000"
+
+# 0x27E: JC 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27E333FF"
+
+# 0x27F: MOV R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27F03000"
+
+# 0x280: CLRC
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28015000"
+
+# 0x281: JC 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "281333FF"
+
+# 0x282: SETC
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2822B000"
+
+# 0x283: JNC 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "283343FF"
+
+# 0x284: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28400000"
+
+# 0x285: CLRC
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28515000"
+
+# 0x286: JC 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "286333FF"
+
+# 0x287: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2873E000"
+
+# 0x288: INC R14
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2881101E"
+
+# 0x289: RETI
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2893F000"
+
+# 0x28A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28A00000"
+
+# 0x28B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28B00000"
+
+# 0x28C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28C00000"
+
+# 0x28D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28D00000"
+
+# 0x28E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28E00000"
+
+# 0x28F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28F00000"
+
+# 0x290:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29000000"
+
+# 0x291:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29100000"
+
+# 0x292:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29200000"
+
+# 0x293:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29300000"
+
+# 0x294:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29400000"
+
+# 0x295:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29500000"
+
+# 0x296:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29600000"
+
+# 0x297:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29700000"
+
+# 0x298:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29800000"
+
+# 0x299:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29900000"
+
+# 0x29A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29A00000"
+
+# 0x29B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29B00000"
+
+# 0x29C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29C00000"
+
+# 0x29D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29D00000"
+
+# 0x29E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29E00000"
+
+# 0x29F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29F00000"
+
+# 0x2A0:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A000000"
+
+# 0x2A1:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A100000"
+
+# 0x2A2:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A200000"
+
+# 0x2A3:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A300000"
+
+# 0x2A4:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A400000"
+
+# 0x2A5:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A500000"
+
+# 0x2A6:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A600000"
+
+# 0x2A7:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A700000"
+
+# 0x2A8:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A800000"
+
+# 0x2A9:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A900000"
+
+# 0x2AA:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AA00000"
+
+# 0x2AB:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AB00000"
+
+# 0x2AC:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AC00000"
+
+# 0x2AD:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AD00000"
+
+# 0x2AE:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AE00000"
+
+# 0x2AF:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AF00000"
+
+# 0x2B0:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B000000"
+
+# 0x2B1:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B100000"
+
+# 0x2B2:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B200000"
+
+# 0x2B3:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B300000"
+
+# 0x2B4:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B400000"
+
+# 0x2B5:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B500000"
+
+# 0x2B6:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B600000"
+
+# 0x2B7:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B700000"
+
+# 0x2B8:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B800000"
+
+# 0x2B9:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B900000"
+
+# 0x2BA:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BA00000"
+
+# 0x2BB:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BB00000"
+
+# 0x2BC:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BC00000"
+
+# 0x2BD:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BD00000"
+
+# 0x2BE:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BE00000"
+
+# 0x2BF:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BF00000"
+
+# 0x2C0:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C000000"
+
+# 0x2C1:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C100000"
+
+# 0x2C2:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C200000"
+
+# 0x2C3:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C300000"
+
+# 0x2C4:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C400000"
+
+# 0x2C5:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C500000"
+
+# 0x2C6:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C600000"
+
+# 0x2C7:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C700000"
+
+# 0x2C8:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C800000"
+
+# 0x2C9:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C900000"
+
+# 0x2CA:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CA00000"
+
+# 0x2CB:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CB00000"
+
+# 0x2CC:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CC00000"
+
+# 0x2CD:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CD00000"
+
+# 0x2CE:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CE00000"
+
+# 0x2CF:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CF00000"
+
+# 0x2D0:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D000000"
+
+# 0x2D1:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D100000"
+
+# 0x2D2:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D200000"
+
+# 0x2D3:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D300000"
+
+# 0x2D4:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D400000"
+
+# 0x2D5:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D500000"
+
+# 0x2D6:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D600000"
+
+# 0x2D7:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D700000"
+
+# 0x2D8:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D800000"
+
+# 0x2D9:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D900000"
+
+# 0x2DA:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DA00000"
+
+# 0x2DB:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DB00000"
+
+# 0x2DC:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DC00000"
+
+# 0x2DD:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DD00000"
+
+# 0x2DE:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DE00000"
+
+# 0x2DF:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DF00000"
+
+# 0x2E0:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E000000"
+
+# 0x2E1:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E100000"
+
+# 0x2E2:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E200000"
+
+# 0x2E3:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E300000"
+
+# 0x2E4:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E400000"
+
+# 0x2E5:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E500000"
+
+# 0x2E6:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E600000"
+
+# 0x2E7:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E700000"
+
+# 0x2E8:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E800000"
+
+# 0x2E9:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E900000"
+
+# 0x2EA:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EA00000"
+
+# 0x2EB:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EB00000"
+
+# 0x2EC:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EC00000"
+
+# 0x2ED:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2ED00000"
+
+# 0x2EE:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EE00000"
+
+# 0x2EF:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EF00000"
+
+# 0x2F0:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F000000"
+
+# 0x2F1:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F100000"
+
+# 0x2F2:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F200000"
+
+# 0x2F3:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F300000"
+
+# 0x2F4:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F400000"
+
+# 0x2F5:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F500000"
+
+# 0x2F6:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F600000"
+
+# 0x2F7:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F700000"
+
+# 0x2F8:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F800000"
+
+# 0x2F9:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F900000"
+
+# 0x2FA:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FA00000"
+
+# 0x2FB:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FB00000"
+
+# 0x2FC:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FC00000"
+
+# 0x2FD:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FD00000"
+
+# 0x2FE:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FE00000"
+
+# 0x2FF: JMP 0x2FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FF302FF"
+
+# 0x300:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30000000"
+
+# 0x301:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30100000"
+
+# 0x302:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30200000"
+
+# 0x303:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30300000"
+
+# 0x304:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30400000"
+
+# 0x305:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30500000"
+
+# 0x306:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30600000"
+
+# 0x307:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30700000"
+
+# 0x308:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30800000"
+
+# 0x309:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30900000"
+
+# 0x30A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30A00000"
+
+# 0x30B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30B00000"
+
+# 0x30C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30C00000"
+
+# 0x30D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30D00000"
+
+# 0x30E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30E00000"
+
+# 0x30F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30F00000"
+
+# 0x310:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31000000"
+
+# 0x311:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31100000"
+
+# 0x312:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31200000"
+
+# 0x313:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31300000"
+
+# 0x314:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31400000"
+
+# 0x315:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31500000"
+
+# 0x316:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31600000"
+
+# 0x317:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31700000"
+
+# 0x318:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31800000"
+
+# 0x319:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31900000"
+
+# 0x31A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31A00000"
+
+# 0x31B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31B00000"
+
+# 0x31C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31C00000"
+
+# 0x31D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31D00000"
+
+# 0x31E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31E00000"
+
+# 0x31F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31F00000"
+
+# 0x320:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32000000"
+
+# 0x321:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32100000"
+
+# 0x322:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32200000"
+
+# 0x323:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32300000"
+
+# 0x324:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32400000"
+
+# 0x325:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32500000"
+
+# 0x326:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32600000"
+
+# 0x327:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32700000"
+
+# 0x328:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32800000"
+
+# 0x329:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32900000"
+
+# 0x32A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32A00000"
+
+# 0x32B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32B00000"
+
+# 0x32C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32C00000"
+
+# 0x32D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32D00000"
+
+# 0x32E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32E00000"
+
+# 0x32F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32F00000"
+
+# 0x330:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33000000"
+
+# 0x331:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33100000"
+
+# 0x332:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33200000"
+
+# 0x333:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33300000"
+
+# 0x334:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33400000"
+
+# 0x335:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33500000"
+
+# 0x336:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33600000"
+
+# 0x337:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33700000"
+
+# 0x338:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33800000"
+
+# 0x339:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33900000"
+
+# 0x33A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33A00000"
+
+# 0x33B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33B00000"
+
+# 0x33C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33C00000"
+
+# 0x33D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33D00000"
+
+# 0x33E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33E00000"
+
+# 0x33F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33F00000"
+
+# 0x340:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34000000"
+
+# 0x341:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34100000"
+
+# 0x342:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34200000"
+
+# 0x343:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34300000"
+
+# 0x344:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34400000"
+
+# 0x345:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34500000"
+
+# 0x346:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34600000"
+
+# 0x347:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34700000"
+
+# 0x348:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34800000"
+
+# 0x349:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34900000"
+
+# 0x34A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34A00000"
+
+# 0x34B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34B00000"
+
+# 0x34C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34C00000"
+
+# 0x34D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34D00000"
+
+# 0x34E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34E00000"
+
+# 0x34F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34F00000"
+
+# 0x350:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35000000"
+
+# 0x351:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35100000"
+
+# 0x352:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35200000"
+
+# 0x353:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35300000"
+
+# 0x354:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35400000"
+
+# 0x355:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35500000"
+
+# 0x356:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35600000"
+
+# 0x357:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35700000"
+
+# 0x358:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35800000"
+
+# 0x359:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35900000"
+
+# 0x35A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35A00000"
+
+# 0x35B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35B00000"
+
+# 0x35C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35C00000"
+
+# 0x35D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35D00000"
+
+# 0x35E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35E00000"
+
+# 0x35F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35F00000"
+
+# 0x360:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36000000"
+
+# 0x361:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36100000"
+
+# 0x362:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36200000"
+
+# 0x363:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36300000"
+
+# 0x364:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36400000"
+
+# 0x365:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36500000"
+
+# 0x366:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36600000"
+
+# 0x367:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36700000"
+
+# 0x368:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36800000"
+
+# 0x369:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36900000"
+
+# 0x36A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36A00000"
+
+# 0x36B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36B00000"
+
+# 0x36C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36C00000"
+
+# 0x36D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36D00000"
+
+# 0x36E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36E00000"
+
+# 0x36F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36F00000"
+
+# 0x370:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37000000"
+
+# 0x371:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37100000"
+
+# 0x372:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37200000"
+
+# 0x373:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37300000"
+
+# 0x374:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37400000"
+
+# 0x375:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37500000"
+
+# 0x376:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37600000"
+
+# 0x377:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37700000"
+
+# 0x378:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37800000"
+
+# 0x379:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37900000"
+
+# 0x37A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37A00000"
+
+# 0x37B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37B00000"
+
+# 0x37C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37C00000"
+
+# 0x37D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37D00000"
+
+# 0x37E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37E00000"
+
+# 0x37F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37F00000"
+
+# 0x380:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38000000"
+
+# 0x381:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38100000"
+
+# 0x382:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38200000"
+
+# 0x383:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38300000"
+
+# 0x384:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38400000"
+
+# 0x385:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38500000"
+
+# 0x386:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38600000"
+
+# 0x387:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38700000"
+
+# 0x388:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38800000"
+
+# 0x389:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38900000"
+
+# 0x38A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38A00000"
+
+# 0x38B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38B00000"
+
+# 0x38C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38C00000"
+
+# 0x38D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38D00000"
+
+# 0x38E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38E00000"
+
+# 0x38F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38F00000"
+
+# 0x390:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39000000"
+
+# 0x391:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39100000"
+
+# 0x392:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39200000"
+
+# 0x393:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39300000"
+
+# 0x394:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39400000"
+
+# 0x395:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39500000"
+
+# 0x396:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39600000"
+
+# 0x397:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39700000"
+
+# 0x398:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39800000"
+
+# 0x399:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39900000"
+
+# 0x39A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39A00000"
+
+# 0x39B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39B00000"
+
+# 0x39C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39C00000"
+
+# 0x39D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39D00000"
+
+# 0x39E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39E00000"
+
+# 0x39F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39F00000"
+
+# 0x3A0:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A000000"
+
+# 0x3A1:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A100000"
+
+# 0x3A2:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A200000"
+
+# 0x3A3:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A300000"
+
+# 0x3A4:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A400000"
+
+# 0x3A5:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A500000"
+
+# 0x3A6:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A600000"
+
+# 0x3A7:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A700000"
+
+# 0x3A8:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A800000"
+
+# 0x3A9:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A900000"
+
+# 0x3AA:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AA00000"
+
+# 0x3AB:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AB00000"
+
+# 0x3AC:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AC00000"
+
+# 0x3AD:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AD00000"
+
+# 0x3AE:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AE00000"
+
+# 0x3AF:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AF00000"
+
+# 0x3B0:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B000000"
+
+# 0x3B1:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B100000"
+
+# 0x3B2:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B200000"
+
+# 0x3B3:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B300000"
+
+# 0x3B4:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B400000"
+
+# 0x3B5:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B500000"
+
+# 0x3B6:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B600000"
+
+# 0x3B7:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B700000"
+
+# 0x3B8:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B800000"
+
+# 0x3B9:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B900000"
+
+# 0x3BA:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BA00000"
+
+# 0x3BB:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BB00000"
+
+# 0x3BC:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BC00000"
+
+# 0x3BD:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BD00000"
+
+# 0x3BE:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BE00000"
+
+# 0x3BF:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BF00000"
+
+# 0x3C0:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C000000"
+
+# 0x3C1:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C100000"
+
+# 0x3C2:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C200000"
+
+# 0x3C3:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C300000"
+
+# 0x3C4:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C400000"
+
+# 0x3C5:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C500000"
+
+# 0x3C6:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C600000"
+
+# 0x3C7:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C700000"
+
+# 0x3C8:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C800000"
+
+# 0x3C9:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C900000"
+
+# 0x3CA:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CA00000"
+
+# 0x3CB:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CB00000"
+
+# 0x3CC:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CC00000"
+
+# 0x3CD:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CD00000"
+
+# 0x3CE:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CE00000"
+
+# 0x3CF:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CF00000"
+
+# 0x3D0:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D000000"
+
+# 0x3D1:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D100000"
+
+# 0x3D2:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D200000"
+
+# 0x3D3:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D300000"
+
+# 0x3D4:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D400000"
+
+# 0x3D5:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D500000"
+
+# 0x3D6:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D600000"
+
+# 0x3D7:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D700000"
+
+# 0x3D8:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D800000"
+
+# 0x3D9:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D900000"
+
+# 0x3DA:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DA00000"
+
+# 0x3DB:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DB00000"
+
+# 0x3DC:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DC00000"
+
+# 0x3DD:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DD00000"
+
+# 0x3DE:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DE00000"
+
+# 0x3DF:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DF00000"
+
+# 0x3E0:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E000000"
+
+# 0x3E1:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E100000"
+
+# 0x3E2:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E200000"
+
+# 0x3E3:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E300000"
+
+# 0x3E4:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E400000"
+
+# 0x3E5:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E500000"
+
+# 0x3E6:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E600000"
+
+# 0x3E7:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E700000"
+
+# 0x3E8:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E800000"
+
+# 0x3E9:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E900000"
+
+# 0x3EA:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EA00000"
+
+# 0x3EB:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EB00000"
+
+# 0x3EC:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EC00000"
+
+# 0x3ED:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3ED00000"
+
+# 0x3EE:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EE00000"
+
+# 0x3EF:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EF00000"
+
+# 0x3F0:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F000000"
+
+# 0x3F1:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F100000"
+
+# 0x3F2:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F200000"
+
+# 0x3F3:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F300000"
+
+# 0x3F4:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F400000"
+
+# 0x3F5:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F500000"
+
+# 0x3F6:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F600000"
+
+# 0x3F7:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F700000"
+
+# 0x3F8:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F800000"
+
+# 0x3F9:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F900000"
+
+# 0x3FA:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FA00000"
+
+# 0x3FB:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FB00000"
+
+# 0x3FC:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FC00000"
+
+# 0x3FD:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FD00000"
+
+# 0x3FE:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FE00000"
+
+# 0x3FF: JMP 0x3FF
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FF303FF"
+
+# Assembled from itest.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
+# User 2
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
+
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0048"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0161"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "026C"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "036C"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "046F"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5A00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5B00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5F00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6A00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6B00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6F00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7A00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7B00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7F00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8A00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8B00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8F00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9A00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9B00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9F00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AA00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AB00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AC00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AD00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AE00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AF00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BA00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BB00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BC00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BD00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BE00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BF00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CA00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CB00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CC00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CD00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CE00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CF00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DA00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DB00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DC00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DD00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DE00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DF00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EA00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EB00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EC00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "ED00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EE00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EF00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FA00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FB00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FC00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FD00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FE00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FF00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10500"
+
+::chipscope::csejtag_target unlock $handle
+::chipscope::csejtag_target close $handle
+::chipscope::csejtag_session destroy $handle
+exit
diff --git a/lib/CPUs/JCpu/asm/make b/lib/CPUs/JCpu/asm/make
new file mode 100644
index 0000000..e7f598f
--- /dev/null
+++ b/lib/CPUs/JCpu/asm/make
@@ -0,0 +1,50 @@
+#!/bin/sh
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: rom-file generation for cpu_core
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+TARGET=$2
+DSTDIR=$1
+
+JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
+
+$JASM_HOME/jasm.rb $TARGET.jsm
+
+irom_tcl_snippet="$TARGET.irom.tcl.snip"
+irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
+irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
+xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
+xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
+xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
+
+$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
+$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
+
+$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
+$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
+
+cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
+cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
+$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
+
+rm -f *.snip
diff --git a/lib/CPUs/JCpu/asm/mul8x8.jsm b/lib/CPUs/JCpu/asm/mul8x8.jsm
new file mode 100644
index 0000000..c9b6c3b
--- /dev/null
+++ b/lib/CPUs/JCpu/asm/mul8x8.jsm
@@ -0,0 +1,29 @@
+; -------------------------------------------------
+; Constants
+; -------------------------------------------------
+
+; Chip register
+include "../../../jasm/cregs.inc.jsm"
+
+; -------------------------------------------------
+; Program
+; -------------------------------------------------
+				code
+				org		0x000
+reset:			jmp		init
+						
+; -------------------------------------------------
+; Main
+; -------------------------------------------------
+init:			mov		R0, 0x45
+				mov		R1, 0xF5
+				
+				call	mul8x8
+stop:			jmp		stop
+
+
+; -------------------------------------------------
+include "../../../jasm/mul8x8.inc.jsm"
+				
+				
+				
\ No newline at end of file
diff --git a/lib/CPUs/JCpu/asm/mul8x8.tcl b/lib/CPUs/JCpu/asm/mul8x8.tcl
new file mode 100644
index 0000000..6bec87e
--- /dev/null
+++ b/lib/CPUs/JCpu/asm/mul8x8.tcl
@@ -0,0 +1,154 @@
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: The ROM file for upload to target over JTAG 
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+# ---------------------------------------------------------------------
+# For Chipscope 9.1
+# ---------------------------------------------------------------------
+# Source JTAG/TCL frame work
+cd $env(CHIPSCOPE)\\bin\\nt
+source csejtag.tcl
+
+namespace import ::chipscope::*
+
+# Platform USB Cable
+set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
+# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
+
+# Create session
+set handle [::chipscope::csejtag_session create 0]
+
+# Open JTAG and lock
+set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
+set lock_result [::chipscope::csejtag_target lock $handle 1000]
+
+set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
+
+# Get Device ID
+set devtype "Virtex-4SX"
+set devid 2
+set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
+set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
+
+set CSE_OP $CSEJTAG_SHIFT_READWRITE
+set CSE_ES $CSEJTAG_RUN_TEST_IDLE
+
+# Write Program
+# JASM_ROM_INSERT_HERE
+# Assembled from mul8x8.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
+# User 1
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
+
+# 0x000: JMP 0x001
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030001"
+
+# 0x001: MOV R00, 0x45
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00103450"
+
+# 0x002: MOV R01, 0xF5
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203F51"
+
+# 0x003: CALL 0x005
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0033B005"
+
+# 0x004: JMP 0x004
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00430004"
+
+# 0x005: PUSH R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0053C002"
+
+# 0x006: PUSH R03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0063C003"
+
+# 0x007: PUSH R04
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0073C004"
+
+# 0x008: MOV R04, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00802014"
+
+# 0x009: MOV R01, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00903001"
+
+# 0x00A: MOV R02, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A03002"
+
+# 0x00B: MOV R03, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B03003"
+
+# 0x00C: CMP R04, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C0F014"
+
+# 0x00D: JEQ 0x015
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D39015"
+
+# 0x00E: SHR R04
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E1F004"
+
+# 0x00F: JNC 0x012
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F34012"
+
+# 0x010: ADD R02, R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01010002"
+
+# 0x011: ADDC R03, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01112013"
+
+# 0x012: SHL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0121E000"
+
+# 0x013: ROLC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01322001"
+
+# 0x014: JMP 0x00C
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143000C"
+
+# 0x015: ADD R00, R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01510020"
+
+# 0x016: ADDC R01, R03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01612031"
+
+# 0x017: POP R04
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0173D004"
+
+# 0x018: POP R03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
+
+# 0x019: POP R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193D002"
+
+# 0x01A: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A3E000"
+
+# Assembled from mul8x8.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
+# User 2
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
+
+
+::chipscope::csejtag_target unlock $handle
+::chipscope::csejtag_target close $handle
+::chipscope::csejtag_session destroy $handle
+exit
diff --git a/lib/CPUs/JCpu/asm/reti_issue.jsm b/lib/CPUs/JCpu/asm/reti_issue.jsm
new file mode 100644
index 0000000..78edc49
--- /dev/null
+++ b/lib/CPUs/JCpu/asm/reti_issue.jsm
@@ -0,0 +1,50 @@
+; -------------------------------------------------
+; Constants
+; -------------------------------------------------
+
+; Chip register
+cpu_revision:	equ		0x00	; RO
+cpu_control:	equ		0x01	; R/W
+cpu_status:		equ		0x02	; RO
+cpu_int_ctrl:	equ		0x03	; R/W
+
+; -------------------------------------------------
+; Program
+; -------------------------------------------------
+				code
+reset:			jmp		init
+		
+				org		0x001
+;				nop
+				reti
+				
+; -------------------------------------------------
+; Main
+; -------------------------------------------------
+init:			mov		R0, 0x05
+				cout	(cpu_int_ctrl), R0
+				mov		R0, 0x00
+loop:			nop
+				inc		R0
+				nop
+				call	subr
+				nop
+				push	R3
+				nop
+				push	R2
+				nop
+				push	R1
+				nop
+				push	R0
+				nop
+				pop		R0
+				nop
+				pop		R1
+				nop
+				pop		R2
+				nop
+				pop		R3
+				nop
+				jmp		loop
+
+subr:			ret				
diff --git a/lib/CPUs/JCpu/asm/reti_issue.tcl b/lib/CPUs/JCpu/asm/reti_issue.tcl
new file mode 100644
index 0000000..5da9c56
--- /dev/null
+++ b/lib/CPUs/JCpu/asm/reti_issue.tcl
@@ -0,0 +1,157 @@
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: The ROM file for upload to target over JTAG 
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+# ---------------------------------------------------------------------
+# For Chipscope 9.1
+# ---------------------------------------------------------------------
+# Source JTAG/TCL frame work
+cd $env(CHIPSCOPE)\\bin\\nt
+source csejtag.tcl
+
+namespace import ::chipscope::*
+
+# Platform USB Cable
+set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
+# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
+
+# Create session
+set handle [::chipscope::csejtag_session create 0]
+
+# Open JTAG and lock
+set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
+set lock_result [::chipscope::csejtag_target lock $handle 1000]
+
+set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
+
+# Get Device ID
+set devtype "Virtex-4SX"
+set devid 2
+set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
+set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
+
+set CSE_OP $CSEJTAG_SHIFT_READWRITE
+set CSE_ES $CSEJTAG_RUN_TEST_IDLE
+
+# Write Program
+# JASM_ROM_INSERT_HERE
+# Assembled from reti_issue.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
+# User 1
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
+
+# 0x000: JMP 0x002
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002"
+
+# 0x001: RETI
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000"
+
+# 0x002: MOV R00, 0x05
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203050"
+
+# 0x003: COUT (0x03), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00326030"
+
+# 0x004: MOV R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00403000"
+
+# 0x005: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
+
+# 0x006: INC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00611010"
+
+# 0x007: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
+
+# 0x008: CALL 0x01B
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0083B01B"
+
+# 0x009: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
+
+# 0x00A: PUSH R03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A3C003"
+
+# 0x00B: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
+
+# 0x00C: PUSH R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C3C002"
+
+# 0x00D: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
+
+# 0x00E: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E3C001"
+
+# 0x00F: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
+
+# 0x010: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103C000"
+
+# 0x011: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01100000"
+
+# 0x012: POP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0123D000"
+
+# 0x013: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01300000"
+
+# 0x014: POP R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143D001"
+
+# 0x015: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01500000"
+
+# 0x016: POP R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163D002"
+
+# 0x017: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01700000"
+
+# 0x018: POP R03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
+
+# 0x019: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01900000"
+
+# 0x01A: JMP 0x005
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A30005"
+
+# 0x01B: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B3E000"
+
+# Assembled from reti_issue.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
+# User 2
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
+
+
+::chipscope::csejtag_target unlock $handle
+::chipscope::csejtag_target close $handle
+::chipscope::csejtag_session destroy $handle
+exit
diff --git a/lib/CPUs/JCpu/doc/block_diagram.png b/lib/CPUs/JCpu/doc/block_diagram.png
new file mode 100644
index 0000000..14bbb54
Binary files /dev/null and b/lib/CPUs/JCpu/doc/block_diagram.png differ
diff --git a/lib/CPUs/JCpu/doc/memory_map.png b/lib/CPUs/JCpu/doc/memory_map.png
new file mode 100644
index 0000000..30a22a0
Binary files /dev/null and b/lib/CPUs/JCpu/doc/memory_map.png differ
diff --git a/lib/CPUs/JCpu/gpl-3.0.txt b/lib/CPUs/JCpu/gpl-3.0.txt
new file mode 100644
index 0000000..94a9ed0
--- /dev/null
+++ b/lib/CPUs/JCpu/gpl-3.0.txt
@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
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+ Everyone is permitted to copy and distribute verbatim copies
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+for enforcing compliance by third parties with this License.
+
+  An "entity transaction" is a transaction transferring control of an
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+organization, or merging organizations.  If propagation of a covered
+work results from an entity transaction, each party to that
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+give under the previous paragraph, plus a right to possession of the
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+the predecessor has it or can get it with reasonable efforts.
+
+  You may not impose any further restrictions on the exercise of the
+rights granted or affirmed under this License.  For example, you may
+not impose a license fee, royalty, or other charge for exercise of
+rights granted under this License, and you may not initiate litigation
+(including a cross-claim or counterclaim in a lawsuit) alleging that
+any patent claim is infringed by making, using, selling, offering for
+sale, or importing the Program or any portion of it.
+
+  11. Patents.
+
+  A "contributor" is a copyright holder who authorizes use under this
+License of the Program or a work on which the Program is based.  The
+work thus licensed is called the contributor's "contributor version".
+
+  A contributor's "essential patent claims" are all patent claims
+owned or controlled by the contributor, whether already acquired or
+hereafter acquired, that would be infringed by some manner, permitted
+by this License, of making, using, or selling its contributor version,
+but do not include claims that would be infringed only as a
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+patent license under the contributor's essential patent claims, to
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+sue for patent infringement).  To "grant" such a patent license to a
+party means to make such an agreement or commitment not to enforce a
+patent against the party.
+
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+and the Corresponding Source of the work is not available for anyone
+to copy, free of charge and under the terms of this License, through a
+publicly available network server or other readily accessible means,
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+available, or (2) arrange to deprive yourself of the benefit of the
+patent license for this particular work, or (3) arrange, in a manner
+consistent with the requirements of this License, to extend the patent
+license to downstream recipients.  "Knowingly relying" means you have
+actual knowledge that, but for the patent license, your conveying the
+covered work in a country, or your recipient's use of the covered work
+in a country, would infringe one or more identifiable patents in that
+country that you have reason to believe are valid.
+
+  If, pursuant to or in connection with a single transaction or
+arrangement, you convey, or propagate by procuring conveyance of, a
+covered work, and grant a patent license to some of the parties
+receiving the covered work authorizing them to use, propagate, modify
+or convey a specific copy of the covered work, then the patent license
+you grant is automatically extended to all recipients of the covered
+work and works based on it.
+
+  A patent license is "discriminatory" if it does not include within
+the scope of its coverage, prohibits the exercise of, or is
+conditioned on the non-exercise of one or more of the rights that are
+specifically granted under this License.  You may not convey a covered
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+in the business of distributing software, under which you make payment
+to the third party based on the extent of your activity of conveying
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+parties who would receive the covered work from you, a discriminatory
+patent license (a) in connection with copies of the covered work
+conveyed by you (or copies made from those copies), or (b) primarily
+for and in connection with specific products or compilations that
+contain the covered work, unless you entered into that arrangement,
+or that patent license was granted, prior to 28 March 2007.
+
+  Nothing in this License shall be construed as excluding or limiting
+any implied license or other defenses to infringement that may
+otherwise be available to you under applicable patent law.
+
+  12. No Surrender of Others' Freedom.
+
+  If conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License.  If you cannot convey a
+covered work so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you may
+not convey it at all.  For example, if you agree to terms that obligate you
+to collect a royalty for further conveying from those to whom you convey
+the Program, the only way you could satisfy both those terms and this
+License would be to refrain entirely from conveying the Program.
+
+  13. Use with the GNU Affero General Public License.
+
+  Notwithstanding any other provision of this License, you have
+permission to link or combine any covered work with a work licensed
+under version 3 of the GNU Affero General Public License into a single
+combined work, and to convey the resulting work.  The terms of this
+License will continue to apply to the part which is the covered work,
+but the special requirements of the GNU Affero General Public License,
+section 13, concerning interaction through a network will apply to the
+combination as such.
+
+  14. Revised Versions of this License.
+
+  The Free Software Foundation may publish revised and/or new versions of
+the GNU General Public License from time to time.  Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+  Each version is given a distinguishing version number.  If the
+Program specifies that a certain numbered version of the GNU General
+Public License "or any later version" applies to it, you have the
+option of following the terms and conditions either of that numbered
+version or of any later version published by the Free Software
+Foundation.  If the Program does not specify a version number of the
+GNU General Public License, you may choose any version ever published
+by the Free Software Foundation.
+
+  If the Program specifies that a proxy can decide which future
+versions of the GNU General Public License can be used, that proxy's
+public statement of acceptance of a version permanently authorizes you
+to choose that version for the Program.
+
+  Later license versions may give you additional or different
+permissions.  However, no additional obligations are imposed on any
+author or copyright holder as a result of your choosing to follow a
+later version.
+
+  15. Disclaimer of Warranty.
+
+  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
+APPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
+HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
+OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
+IS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
+ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+  16. Limitation of Liability.
+
+  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
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+GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
+USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
+DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
+PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
+EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGES.
+
+  17. Interpretation of Sections 15 and 16.
+
+  If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+                     END OF TERMS AND CONDITIONS
+
+            How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+  If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+    <program>  Copyright (C) <year>  <name of author>
+    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+  You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+<http://www.gnu.org/licenses/>.
+
+  The GNU General Public License does not permit incorporating your program
+into proprietary programs.  If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.  But first, please read
+<http://www.gnu.org/philosophy/why-not-lgpl.html>.
diff --git a/lib/CPUs/JCpu/sim/tb_cpu.fdo b/lib/CPUs/JCpu/sim/tb_cpu.fdo
new file mode 100644
index 0000000..36b8dc0
--- /dev/null
+++ b/lib/CPUs/JCpu/sim/tb_cpu.fdo
@@ -0,0 +1,22 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
+vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
+vcom -explicit  -93 "../src/core/reg_dual.vhd"
+vcom -explicit  -93 "../src/core/chipram.vhd"
+vcom -explicit  -93 "../src/core/chipreg.vhd"
+vcom -explicit  -93 "../src/core/pc.vhd"
+vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
+vcom -explicit  -93 "../src/core/int_ctrl.vhd"
+vcom -explicit  -93 "../src/core/alu.vhd"
+vcom -explicit  -93 "../src/core/cpu.vhd"
+vcom -explicit  -93 "../src/test_irom.vhdl"
+vcom -explicit  -93 "../src/core/tb_cpu.vhd"
+vsim -t 1ps   -lib work tb_cpu
+do {tb_cpu.wdo}
+view wave
+view structure
+view signals
+run 50us
diff --git a/lib/CPUs/JCpu/sim/tb_cpu.wdo b/lib/CPUs/JCpu/sim/tb_cpu.wdo
new file mode 100644
index 0000000..2ef036e
--- /dev/null
+++ b/lib/CPUs/JCpu/sim/tb_cpu.wdo
@@ -0,0 +1,107 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_cpu/rst
+add wave -noupdate -format Logic /tb_cpu/clk
+add wave -noupdate -format Logic /tb_cpu/ce
+add wave -noupdate -format Logic /tb_cpu/uut/cpu_active
+add wave -noupdate -format Logic /tb_cpu/int_in
+add wave -noupdate -format Logic /tb_cpu/int_ack
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr
+add wave -noupdate -format Logic /tb_cpu/xmem_we
+add wave -noupdate -format Logic /tb_cpu/xmem_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram
+add wave -noupdate -format Logic /tb_cpu/uut/io_sel
+add wave -noupdate -format Literal /tb_cpu/uut/iphase
+add wave -noupdate -divider CPU
+add wave -noupdate -format Literal /tb_cpu/reg
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Literal /tb_cpu/uut/cpu_status
+add wave -noupdate -format Literal /tb_cpu/uut/status_reg
+add wave -noupdate -format Literal /tb_cpu/uut/ctrl
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result
+add wave -noupdate -format Literal /tb_cpu/uut/alu_status
+add wave -noupdate -format Logic /tb_cpu/uut/pc_inc
+add wave -noupdate -format Logic /tb_cpu/uut/pc_load
+add wave -noupdate -format Logic /tb_cpu/uut/stk_we
+add wave -noupdate -format Logic /tb_cpu/uut/cmem_we
+add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase
+add wave -noupdate -format Logic /tb_cpu/uut/was_pcld
+add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc
+add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load
+add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push
+add wave -noupdate -format Logic /tb_cpu/uut/stk_push
+add wave -noupdate -format Logic /tb_cpu/uut/stk_pop
+add wave -noupdate -format Logic /tb_cpu/uut/status_save
+add wave -noupdate -format Logic /tb_cpu/uut/status_restore
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr
+add wave -noupdate -divider Stack
+add wave -noupdate -format Logic /tb_cpu/clk
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
+add wave -noupdate -divider Chipram
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
+add wave -noupdate -divider Sequencer
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem
+add wave -noupdate -divider {Chip register}
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout
+add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/clk
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
+add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {136355 ps} 0}
+configure wave -namecolwidth 166
+configure wave -valuecolwidth 101
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {93532 ps} {206468 ps}
diff --git a/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo b/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo
new file mode 100644
index 0000000..dd965ec
--- /dev/null
+++ b/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo
@@ -0,0 +1,21 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
+vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
+vcom -explicit  -93 "../src/core/reg_dual.vhd"
+vcom -explicit  -93 "../src/core/chipram.vhd"
+vcom -explicit  -93 "../src/core/pc.vhd"
+vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
+vcom -explicit  -93 "../src/core/int_ctrl.vhd"
+vcom -explicit  -93 "../src/core/alu.vhd"
+vcom -explicit  -93 "../src/core/cpu.vhd"
+vcom -explicit  -93 "../src/cpu_embedded.vhd"
+vcom -explicit  -93 "../src/tb_cpu_embedded.vhd"
+vcom -explicit  -93 "../src/test_irom.vhdl"
+vsim -t 1ps   -lib work tb_cpu_embedded
+do {tb_cpu_embedded.wdo}
+view wave
+view structure
+view signals
+run 10us
diff --git a/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo b/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo
new file mode 100644
index 0000000..caec2d7
--- /dev/null
+++ b/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo
@@ -0,0 +1,26 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_cpu_embedded/rst
+add wave -noupdate -format Logic /tb_cpu_embedded/clk
+add wave -noupdate -format Logic /tb_cpu_embedded/ce
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/sram
+add wave -noupdate -format Logic /tb_cpu_embedded/int_in
+add wave -noupdate -format Logic /tb_cpu_embedded/int_ack
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_data
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {2168142 ps} 0}
+configure wave -namecolwidth 143
+configure wave -valuecolwidth 101
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {10500 ns}
diff --git a/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo b/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo
new file mode 100644
index 0000000..77ca67d
--- /dev/null
+++ b/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo
@@ -0,0 +1,22 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
+vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
+vcom -explicit  -93 "../src/core/reg_dual.vhd"
+vcom -explicit  -93 "../src/core/chipram.vhd"
+vcom -explicit  -93 "../src/core/chipreg.vhd"
+vcom -explicit  -93 "../src/core/pc.vhd"
+vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
+vcom -explicit  -93 "../src/core/int_ctrl.vhd"
+vcom -explicit  -93 "../src/core/alu.vhd"
+vcom -explicit  -93 "../src/core/cpu.vhd"
+vcom -explicit  -93 "../src/itest_irom.vhdl"
+vcom -explicit  -93 "../src/tb_cpu_itest.vhd"
+vsim -t 1ps   -lib work tb_cpu
+do {tb_cpu_itest.wdo}
+view wave
+view structure
+view signals
+run 400us
diff --git a/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo b/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo
new file mode 100644
index 0000000..747f9d3
--- /dev/null
+++ b/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo
@@ -0,0 +1,123 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_cpu/rst
+add wave -noupdate -format Logic /tb_cpu/clk
+add wave -noupdate -format Logic /tb_cpu/ce
+add wave -noupdate -format Logic /tb_cpu/int_in
+add wave -noupdate -format Logic /tb_cpu/int_ack
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr
+add wave -noupdate -format Logic /tb_cpu/xmem_we
+add wave -noupdate -format Logic /tb_cpu/xmem_re
+add wave -noupdate -format Logic /tb_cpu/xmem_wait
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/reg
+add wave -noupdate -format Logic /tb_cpu/uut/io_sel
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_addr
+add wave -noupdate -divider CPU
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Literal /tb_cpu/uut/cpu_status
+add wave -noupdate -format Literal /tb_cpu/uut/status_reg
+add wave -noupdate -format Literal /tb_cpu/uut/ctrl
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result
+add wave -noupdate -format Literal /tb_cpu/uut/alu_status
+add wave -noupdate -format Logic /tb_cpu/uut/pc_inc
+add wave -noupdate -format Logic /tb_cpu/uut/pc_load
+add wave -noupdate -format Logic /tb_cpu/uut/cpu_active
+add wave -noupdate -format Logic /tb_cpu/uut/stk_we
+add wave -noupdate -format Logic /tb_cpu/uut/cmem_we
+add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase
+add wave -noupdate -format Logic /tb_cpu/uut/was_pcld
+add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc
+add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load
+add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push
+add wave -noupdate -format Logic /tb_cpu/uut/stk_push
+add wave -noupdate -format Logic /tb_cpu/uut/stk_pop
+add wave -noupdate -format Logic /tb_cpu/uut/status_save
+add wave -noupdate -format Logic /tb_cpu/uut/status_restore
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr
+add wave -noupdate -divider Stack
+add wave -noupdate -format Logic /tb_cpu/clk
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
+add wave -noupdate -divider Chipram
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
+add wave -noupdate -divider Sequencer
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem
+add wave -noupdate -divider {Chip register}
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout
+add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/clk
+add wave -noupdate -divider {Interrup Ctrl.}
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in
+add wave -noupdate -format Literal -expand /tb_cpu/uut/inst_int_ctrl/ctrl_in
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_sampled
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out
+add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {53866171 ps} 0}
+configure wave -namecolwidth 166
+configure wave -valuecolwidth 101
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {420 us}
diff --git a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo
new file mode 100644
index 0000000..f83b9b4
--- /dev/null
+++ b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo
@@ -0,0 +1,22 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
+vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
+vcom -explicit  -93 "../src/core/reg_dual.vhd"
+vcom -explicit  -93 "../src/core/chipram.vhd"
+vcom -explicit  -93 "../src/core/chipreg.vhd"
+vcom -explicit  -93 "../src/core/pc.vhd"
+vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
+vcom -explicit  -93 "../src/core/int_ctrl.vhd"
+vcom -explicit  -93 "../src/core/alu.vhd"
+vcom -explicit  -93 "../src/core/cpu.vhd"
+vcom -explicit  -93 "../src/irom_reti_issue.vhdl"
+vcom -explicit  -93 "../src/core/tb_cpu.vhd"
+vsim -t 1ps   -lib work tb_cpu
+do {tb_cpu_reti_issue.wdo}
+view wave
+view structure
+view signals
+run 50us
diff --git a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo
new file mode 100644
index 0000000..1e67acb
--- /dev/null
+++ b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo
@@ -0,0 +1,82 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Literal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
+add wave -noupdate -divider {Chip RAM}
+add wave -noupdate -format Literal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clka
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clkb
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_a
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_b
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
+add wave -noupdate -divider {Interrupt controller}
+add wave -noupdate -format Literal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/rst
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/clk
+add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/ctrl_in
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_reg
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request_clr
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
+add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/iphase_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_int_ctrl/pc_addr_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
+add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
+add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state_next
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
+add wave -noupdate -divider PC
+add wave -noupdate -format Literal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/rst
+add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/clk
+add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/inc
+add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/load
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_next
+add wave -noupdate -divider {Stack controller}
+add wave -noupdate -format Literal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/rst
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/clk
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {8115990 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {8048536 ps} {8340629 ps}
diff --git a/lib/CPUs/JCpu/sim/tb_mul8x8.fdo b/lib/CPUs/JCpu/sim/tb_mul8x8.fdo
new file mode 100644
index 0000000..f727dff
--- /dev/null
+++ b/lib/CPUs/JCpu/sim/tb_mul8x8.fdo
@@ -0,0 +1,21 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
+vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
+vcom -explicit  -93 "../src/core/reg_dual.vhd"
+vcom -explicit  -93 "../src/core/chipram.vhd"
+vcom -explicit  -93 "../src/core/pc.vhd"
+vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
+vcom -explicit  -93 "../src/core/int_ctrl.vhd"
+vcom -explicit  -93 "../src/core/alu.vhd"
+vcom -explicit  -93 "../src/core/cpu.vhd"
+vcom -explicit  -93 "../src/cpu_embedded.vhd"
+vcom -explicit  -93 "../src/tb_cpu_embedded.vhd"
+vcom -explicit  -93 "../src/mul8x8_irom.vhdl"
+vsim -t 1ps   -lib work tb_cpu_embedded
+do {tb_mul8x8.wdo}
+view wave
+view structure
+view signals
+run 10us
diff --git a/lib/CPUs/JCpu/sim/tb_mul8x8.wdo b/lib/CPUs/JCpu/sim/tb_mul8x8.wdo
new file mode 100644
index 0000000..355e0a4
--- /dev/null
+++ b/lib/CPUs/JCpu/sim/tb_mul8x8.wdo
@@ -0,0 +1,31 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/rst
+add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/clk
+add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/ce
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_addr
+add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/cpu_status
+add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/status_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op1
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_result
+add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/alu_status
+add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/mem
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {529679 ps} 0}
+configure wave -namecolwidth 143
+configure wave -valuecolwidth 101
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {9002500 ps} {10052500 ps}
diff --git a/lib/CPUs/JCpu/src/core/alu.vhd b/lib/CPUs/JCpu/src/core/alu.vhd
new file mode 100644
index 0000000..19b3478
--- /dev/null
+++ b/lib/CPUs/JCpu/src/core/alu.vhd
@@ -0,0 +1,236 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The arithmetic logic unit
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity alu is
+	Generic (
+		data_width : integer := 8
+	);
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		op_en		: in  STD_LOGIC;
+		cy_in		: in  STD_LOGIC;
+		op1_in		: in  unsigned (data_width-1 downto 0);
+		op2_in		: in  unsigned (data_width-1 downto 0);
+		opsel		: in  alu_op_t;
+		res_out		: out unsigned (data_width-1 downto 0);
+		stat_load	: in  STD_LOGIC;
+		stat_in		: in  alu_status_t;
+		stat_out	: out alu_status_t
+	);
+end alu;
+
+architecture Behavioral of alu is
+
+	signal sum_cy, sh_cy, sum_cy_in, sh_cy_in, left_shift, add_subn : STD_LOGIC;
+	signal result, sum_res, lf_res, sh_res, res_reg : unsigned (data_width-1 downto 0);
+	signal status, stat_reg : alu_status_t;
+	
+	--------------------------------------------------------------------------
+	function test_zero(arg : unsigned) return STD_LOGIC is
+	variable result : STD_LOGIC;
+	begin
+			result := '0';
+			for i in arg'range loop
+				result := result or To_X01(arg(i));
+			end loop;
+
+			return not result;
+	end test_zero;
+
+--------------------------------------------------------------------------
+begin
+
+--------------------------------------------------------------------------
+proc_logic_func: 
+	process (op1_in, op2_in, opsel)
+	begin
+		
+		case opsel is
+		when op1_and_op2 =>
+			lf_res <= op1_in and op2_in;
+		when op1_or_op2 =>
+			lf_res <= op1_in or op2_in;
+		when op1_xor_op2 =>
+			lf_res <= op1_in xor op2_in;
+		when others =>
+			lf_res <= (others => '-');
+		end case;
+
+	end process;	
+
+--------------------------------------------------------------------------
+proc_shift_func: 
+	process (op1_in, left_shift, sh_cy_in)
+	begin
+		if left_shift = '1' then
+			sh_res <= op1_in(op1_in'left-1 downto op1_in'right) & sh_cy_in;
+			sh_cy <= op1_in(op1_in'left);
+		else	
+			sh_res <= sh_cy_in & op1_in(op1_in'left downto op1_in'right+1);
+			sh_cy <= op1_in(op1_in'right);
+		end if;	
+		
+	end process;	
+
+--------------------------------------------------------------------------
+proc_alu_out:
+	process(opsel, op1_in, op2_in, res_reg, stat_reg, lf_res, sum_res, sh_res, sum_cy, sh_cy, cy_in)
+
+	begin
+		
+		case opsel is
+		
+		when op1_add_op2 | op1_sub_op2 | op1_addc_op2 | op1_subc_op2 =>
+			status.zero <= test_zero(res_reg);
+			status.carry <= sum_cy;
+			result <= sum_res;
+		when op1_and_op2 | op1_or_op2 | op1_xor_op2 =>
+			status.zero <= test_zero(res_reg);
+			status.carry <= stat_reg.carry;
+			result <= lf_res;
+		when shl_op | shr_op | rol_op | ror_op | rolc_op | rorc_op =>
+			status.zero <= test_zero(res_reg);
+			status.carry <= sh_cy;
+			result <= sh_res;
+		when swap_op =>
+			result <= op1_in(op1_in'left-op1_in'length/2 downto op1_in'right) & op1_in(op1_in'left downto op1_in'right+op1_in'length/2);
+			status <= stat_reg;
+		when others =>
+			result <= op2_in;
+			status.zero <= stat_reg.zero;
+			status.carry <= stat_reg.carry or cy_in;
+		end case;
+		
+	end process;
+
+--------------------------------------------------------------------------
+proc_alu_in:
+	process(opsel, op1_in, stat_reg)
+
+	begin
+		
+		add_subn <= '-';
+		sum_cy_in <= '-';
+		sh_cy_in <= '-';
+		left_shift <= '-';
+
+		case opsel is
+		
+		when op1_add_op2 =>
+			sum_cy_in <= '0';
+			add_subn <= '1';
+
+		when op1_sub_op2 =>
+			sum_cy_in <= '0';
+			add_subn <= '0';
+	
+		when op1_addc_op2 => 
+			sum_cy_in <= stat_reg.carry;
+			add_subn <= '1';
+
+		when op1_subc_op2 => 
+			sum_cy_in <= stat_reg.carry;
+			add_subn <= '0';
+
+		when shl_op =>
+			sh_cy_in <= '0';
+			left_shift <= '1';
+			
+		when shr_op =>
+			sh_cy_in <= '0';
+			left_shift <= '0';
+
+		when rol_op =>
+			sh_cy_in <= op1_in(op1_in'left);
+			left_shift <= '1';
+
+		when ror_op =>
+			sh_cy_in <= op1_in(op1_in'right);
+			left_shift <= '0';
+
+		when rolc_op =>
+			sh_cy_in <= stat_reg.carry;
+			left_shift <= '1';
+
+		when rorc_op =>
+			sh_cy_in <= stat_reg.carry;
+			left_shift <= '0';
+
+		when others => null;
+
+		end case;
+		
+	end process;
+
+--------------------------------------------------------------------------
+proc_res_reg:
+	process(clk, rst, op_en, stat_load, res_reg, stat_reg)
+	begin
+		if rst = '1' then
+			res_reg <= (others => '0');
+			stat_reg <= (others => '0');
+		elsif rising_edge(clk) then
+			if op_en = '1' then
+				res_reg <= result;
+				stat_reg <= status;
+			elsif stat_load = '1' then
+				stat_reg  <= stat_in;
+			end if;	
+		end if;
+		res_out <= res_reg;
+		stat_out <= stat_reg;
+
+	end process;
+
+--------------------------------------------------------------------------
+alu_addsub:
+	process(op1_in, op2_in, sum_cy_in, add_subn)
+	variable sum  : unsigned(data_width+1 downto 0);
+	variable op1, op2 : unsigned(data_width+1 downto 0);
+	begin
+		if add_subn = '1' then
+			op1 := '0' & op1_in & '1';
+			op2 := '0' & op2_in & sum_cy_in;
+			sum := op1 + op2; 
+		else
+			op1 := '0' & op1_in & not sum_cy_in;
+			op2 := '0' & op2_in & '1';
+			sum := op1 - op2; 
+		end if;
+
+		-- Form sum + carry
+		sum_res <= sum(data_width downto 1);
+		sum_cy <= sum(sum'left);
+		
+	end process;	
+
+--------------------------------------------------------------------------
+end Behavioral;
+
diff --git a/lib/CPUs/JCpu/src/core/chipram.vhd b/lib/CPUs/JCpu/src/core/chipram.vhd
new file mode 100644
index 0000000..a954a77
--- /dev/null
+++ b/lib/CPUs/JCpu/src/core/chipram.vhd
@@ -0,0 +1,85 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: On-chip RAM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity chipram is
+	Generic (
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end chipram;
+
+architecture Behavioral of chipram is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	shared variable RAM : RAMtype;
+	
+begin
+
+process (clka)
+begin
+if clka'event and clka = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) := din_a;
+		end if;
+		dout_a <= RAM(to_integer(addr_a));
+	end if;
+end if;
+end process;
+
+process (clkb)
+begin
+if clkb'event and clkb = '1' then
+	if en_b = '1' then
+		if we_b = '1' then
+			RAM(to_integer(addr_b)) := din_b;
+		end if;
+		dout_b <= RAM(to_integer(addr_b));
+	end if;
+end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/lib/CPUs/JCpu/src/core/chipreg.vhd b/lib/CPUs/JCpu/src/core/chipreg.vhd
new file mode 100644
index 0000000..483c627
--- /dev/null
+++ b/lib/CPUs/JCpu/src/core/chipreg.vhd
@@ -0,0 +1,123 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: On-Chip registers
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity chipreg is
+	Port (
+		rst			: in  STD_LOGIC; 
+		clk			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		din			: in  dmem_data_t;
+		dout		: out dmem_data_t;
+		ctrl_in		: in  creg_ctrl_in_t;
+		ctrl_out	: out creg_ctrl_out_t
+	);
+end chipreg;
+
+architecture Behavioral of chipreg is
+
+	signal reg_page_sel		: page_sel_t;
+	signal reg_int_ctrl		: int_ctrl_in_t;
+	signal reg_stk_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
+	signal reg_cmem_high	: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
+
+begin
+
+proc_assign_ctrl_lines:
+	process (clk)
+	begin
+		if rising_edge(clk) then
+			ctrl_out.page_sel	<= reg_page_sel;
+			ctrl_out.int_ctrl	<= reg_int_ctrl;
+			ctrl_out.stk_high	<= reg_stk_high;
+			ctrl_out.cmem_high	<= reg_cmem_high;
+		end if;
+	end process;
+
+proc_reg_write:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			reg_stk_high <= (others => '0');
+			reg_cmem_high <= (others => '0');
+			reg_page_sel <= (others => '0');
+			reg_int_ctrl.enable		<= '0';
+			reg_int_ctrl.polarity	<= '1';
+			reg_int_ctrl.edge_sens	<= '1';
+		elsif rising_edge(clk) then
+			reg_int_ctrl.request <= '0';
+			if we = '1' then
+				case addr is
+				when X"01" =>
+					reg_page_sel(page_sel_t'range)	<= din(page_sel_t'range);
+				when X"03" =>
+					reg_int_ctrl.enable		<= din(0);
+					reg_int_ctrl.polarity	<= din(1);
+					reg_int_ctrl.edge_sens	<= din(2);
+					reg_int_ctrl.request	<= din(7);
+				when X"04" =>
+					reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
+				when X"05" =>
+					reg_stk_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
+				when others => null;
+				end case;
+			end if;
+		end if;
+	end process;
+
+proc_reg_read:
+	process (clk)
+	begin
+		if rising_edge(clk) then
+			case addr is
+			when X"00" =>	-- Revison
+				dout <= to_unsigned(REVISION, dmem_data_t'length);
+			when X"01" =>	-- Control 0
+				dout <= (7 downto page_sel_t'length => '0') & reg_page_sel;
+			when X"02" =>	-- CPU status
+				dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero;
+			when X"03" =>	-- Interrupt control
+				dout <= "00000" & reg_int_ctrl.edge_sens & reg_int_ctrl.polarity & reg_int_ctrl.enable;
+			when X"04" =>	-- Upper stack bits out
+				dout <= "0000" & reg_cmem_high;
+			when X"05" =>	-- Upper cmem bits out
+				dout <= "0000" & reg_stk_high;
+			when others => 
+				if addr(0) = '0' then
+					dout <= X"DE";
+				else
+					dout <= X"AD";
+				end if;
+			end case;
+			
+		end if;
+	end process;
+
+end Behavioral;
+
diff --git a/lib/CPUs/JCpu/src/core/cpu.vhd b/lib/CPUs/JCpu/src/core/cpu.vhd
new file mode 100644
index 0000000..1184806
--- /dev/null
+++ b/lib/CPUs/JCpu/src/core/cpu.vhd
@@ -0,0 +1,566 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: JCPU top file 
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity cpu is
+	Generic (
+		use_instr_register	: boolean := false;
+		use_ctrl_rom		: boolean := true
+
+	);
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		int_in		: in  STD_LOGIC;
+		int_ack		: out STD_LOGIC;
+		xmem_wait	: in  STD_LOGIC;
+		xmem_we		: out STD_LOGIC;
+		xmem_re		: out STD_LOGIC;
+		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
+		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
+		io_sel		: out std_logic
+	);
+end cpu;
+
+architecture rtl of cpu is
+
+	COMPONENT stack_ctrl
+	GENERIC (
+		addr_width	: integer
+	);
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		push		: in  STD_LOGIC;
+		pop			: in  STD_LOGIC;
+		din			: in  inst_addr_t;
+		dout		: out inst_addr_t;
+		mem_we		: out  STD_LOGIC;
+		ptr_out		: out unsigned (addr_width-1 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT pc
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		inc			: in  STD_LOGIC;
+		load		: in  STD_LOGIC;
+		pc_in		: in  inst_addr_t;
+		pc_out		: out inst_addr_t;
+		pc_next		: out inst_addr_t
+	);
+	END COMPONENT;
+
+	COMPONENT dpath_ctrl
+	GENERIC (
+		use_rom		: boolean
+	);
+	Port (
+		inst_in		: in  inst_t;
+		iphase_in	: in  iphase_t;
+		status_in	: in  cpu_status_t;
+		ctrl_out	: out dpath_ctrl_out_t;
+		idout		: out inst_addr_t;
+		ddout		: out dmem_data_t
+	);
+	END COMPONENT;
+
+	COMPONENT int_ctrl
+	Port (
+		rst				: in  STD_LOGIC;
+		clk				: in  STD_LOGIC;
+		ctrl_in			: in  int_ctrl_in_t;
+		int_in			: in  STD_LOGIC;
+		int_exit		: in  STD_LOGIC;
+		iphase_in		: in  iphase_t;
+		int_ack_out		: out STD_LOGIC;
+		stat_save_out	: out STD_LOGIC; 
+		stat_rest_out	: out STD_LOGIC; 
+		pc_addr_out		: out inst_addr_t;
+		pc_load_out		: out STD_LOGIC;
+		stk_push_out	: out STD_LOGIC;
+		stk_pop_out		: out STD_LOGIC
+	);
+	END COMPONENT;
+
+	COMPONENT reg_dual
+	GENERIC (
+		addr_width	: integer;
+		data_width	: integer
+	);
+	Port (
+		clk			: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		ptr_a		: in  reg_ptr_t;
+		ptr_b		: in  reg_ptr_t;
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT chipram
+	GENERIC (
+		addr_width : integer;
+		data_width : integer
+	);
+	Port (
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT chipreg
+	Port (
+		rst			: in  STD_LOGIC; 
+		clk			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		din			: in  dmem_data_t;
+		dout		: out dmem_data_t;
+		ctrl_in		: in  creg_ctrl_in_t;
+		ctrl_out	: out creg_ctrl_out_t
+	);
+	END COMPONENT;
+
+	COMPONENT alu
+	GENERIC (
+		data_width : integer := 8
+	);
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		op_en		: in  STD_LOGIC;
+		cy_in		: in  STD_LOGIC;
+		op1_in		: in  unsigned (data_width-1 downto 0);
+		op2_in		: in  unsigned (data_width-1 downto 0);
+		opsel		: in  alu_op_t;
+		res_out		: out unsigned (data_width-1 downto 0);
+		stat_load	: in  STD_LOGIC;
+		stat_in		: in  alu_status_t;
+		stat_out	: out alu_status_t
+	);
+	END COMPONENT;
+
+	signal cpu_status, status_reg : cpu_status_t; -- := cpu_status_t(others => '0');
+	signal ctrl : dpath_ctrl_out_t;
+	signal stk_out : inst_addr_t;
+	signal stk_in : inst_addr_t;
+	signal stk_reg : inst_addr_t;
+	signal pc_in, pc_out, pc_next, idata, int_pc_addr : inst_addr_t;
+	signal iphase : iphase_t;
+	signal const_data, reg_a_dout, reg_b_dout : dmem_data_t;
+	signal reg_din : dmem_data_t;
+	signal alu_op1, alu_op2, alu_result : dmem_data_t;
+	signal alu_status : alu_status_t;
+	signal pc_inc, pc_load, cpu_active, stk_we, cmem_we, creg_we : STD_LOGIC;
+	signal ctrl_inst : inst_t;
+	signal ctrl_iphase : iphase_t;
+	signal was_pcld, was_pop2pc, int_pc_load, int_stk_push, int_stk_pop, stk_push, stk_pop : STD_LOGIC;
+	signal status_save, status_restore : STD_LOGIC;
+	signal creg_dout : dmem_data_t;
+	signal cmem_din, cmem_dout : inst_addr_t;
+	signal stk_addr, cmem_addr : unsigned(CHIPRAM_SIZE_BITS-1 downto 0);
+	signal stk_ptr : unsigned(STACK_SIZE_BITS-1 downto 0);
+	signal creg_ctrl_out : creg_ctrl_out_t;
+	signal creg_ctrl_in : creg_ctrl_in_t;
+	signal irq_out : std_logic;
+	signal xio_sel, cio_sel : std_logic; 
+	signal mem_data : dmem_data_t;
+	signal mem_addr : dmem_data_t;
+	
+begin
+	io_sel <= xio_sel;
+	instr_addr <= pc_out;
+	pc_inc <= cpu_active and ctrl.lines.pc_inc;
+	stk_addr <= '0' & stk_ptr;
+	cpu_status.alu <= alu_status;
+	cpu_status.xmem_wait <= xmem_wait;
+	creg_ctrl_in.alu <= alu_status;
+
+	xmem_dout <= mem_data;
+	xmem_addr <= mem_addr;
+	cmem_din <= creg_ctrl_out.cmem_high & mem_data;
+	cmem_addr <= '1' & creg_ctrl_out.page_sel & mem_addr(MIN(cmem_addr'length-creg_ctrl_out.page_sel'length-1, mem_addr'length)-1 downto 0);
+
+--------------------------------------------------------------------
+mem_ctrl_lines:
+	process(ctrl.lines)
+	begin
+		xio_sel <= '0';
+		xmem_re <= '0';
+		xmem_we <= '0';
+		cio_sel <= '0';
+		cmem_we <= '0';
+		creg_we <= '0';
+		
+		case ctrl.lines.mem_access is
+			when xmem_access =>
+				xmem_re <= ctrl.lines.mem_read;
+				xmem_we <= ctrl.lines.mem_write;
+			when xio_access =>
+				xio_sel <= '1';
+				xmem_re <= ctrl.lines.mem_read;
+				xmem_we <= ctrl.lines.mem_write;
+			when cmem_access =>
+				cmem_we <= ctrl.lines.mem_write;
+			when cio_access =>
+				cio_sel <= '1';
+				creg_we <= ctrl.lines.mem_write;
+			when others => null;
+		end case;
+	end process;
+
+iphase_counter:
+	process(rst, clk, ce)
+	variable pos : integer; 
+	begin
+		if rst = '1' then
+			iphase <= iphase_t'low;
+			cpu_active <= '0';
+		elsif rising_edge(clk) then
+			cpu_active <= '0';
+			if ce = '1' then
+				cpu_active <= '1';
+				if iphase = iphase_t'high then
+					iphase <= iphase_t'low;
+				else
+					iphase <= iphase + 1;
+				end if;
+			end if;	
+		end if;
+	end process;
+
+gen_instr_reg:
+if use_instr_register = true generate
+
+instr_reg:
+	process (rst, clk, ce)
+	begin
+		if rst = '1' then
+			ctrl_inst <= (others => '0');
+			ctrl_iphase <= 0;
+		elsif rising_edge(clk) and ce = '1' then
+			ctrl_inst <= instr_din;
+			ctrl_iphase <= iphase;
+		end if;
+	end process;
+
+end generate;
+	
+gen_instr_direct:
+if use_instr_register = false generate
+
+	ctrl_inst <= instr_din;
+	ctrl_iphase <= iphase;
+
+end generate;
+
+status_register:
+	process(clk, status_save)
+	begin
+		if rising_edge(clk) and status_save = '1' then
+			status_reg.alu <= alu_status;
+		end if;
+	end process;
+
+pc_pushpop:
+	process(ctrl.lines, int_pc_load, int_stk_push, int_stk_pop, was_pop2pc)
+	begin
+		pc_load <= ctrl.lines.pc_load or int_pc_load;
+		stk_push <= (ctrl.lines.stk_pushd or ctrl.lines.stk_push) or (int_stk_push and not was_pop2pc);
+		stk_pop <= ctrl.lines.stk_popd or int_stk_pop or (ctrl.lines.stk_pop and not int_pc_load);
+	end process;
+	
+lines_delay:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			was_pcld <= ctrl.lines.pc_load;
+			was_pop2pc <= ctrl.lines.stk_pop and ctrl.lines.pc_load;
+		end if;
+	end process;
+
+stk_mux:
+	process(ctrl.lines, was_pcld, int_stk_push, pc_next, idata, reg_a_dout, creg_ctrl_out)
+	begin
+		if was_pcld = '1' and int_stk_push = '1' then 
+			stk_in <= idata;
+		elsif ctrl.lines.stk_pushd = '1' then
+			stk_in <= creg_ctrl_out.stk_high & reg_a_dout;
+		else	
+			stk_in <= pc_next;
+		end if;	
+		
+	end process;
+
+pc_mux:
+	process(ctrl.lines, int_pc_load, int_stk_pop, idata, int_pc_addr, stk_out)
+	begin
+		
+		pc_in <= stk_out;
+		if int_pc_load = '1' then 
+			if int_stk_pop = '0' then
+				pc_in <= int_pc_addr;
+			end if;	
+		elsif ctrl.lines.pc_load = '1' then
+			if ctrl.lines.stk_pop = '0' then
+				pc_in <= idata;
+			end if;	
+		end if;	
+
+	end process;
+
+mem_data_mux:
+	process(ctrl.lines.ddata_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out)
+	begin
+		case ctrl.lines.ddata_src_sel is
+		when reg_a => 
+			mem_data <= reg_a_dout;
+		when reg_b =>
+			mem_data <= reg_b_dout;
+		when const =>
+			mem_data <= const_data;
+		when others =>
+			mem_data <= const_data;
+		end case;
+
+	end process;
+
+mem_addr_mux:
+	process(ctrl.lines.daddr_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out.page_sel)
+	begin
+		case ctrl.lines.daddr_src_sel is
+		when reg_a => 
+			mem_addr <= reg_a_dout;
+		when reg_b =>
+			mem_addr <= reg_b_dout;
+		when const =>
+			mem_addr <= const_data;
+		when others =>
+			mem_addr <= const_data;
+		end case;
+
+	end process;
+
+reg_in_mux:
+	process(ctrl.lines.reg_src_sel, cio_sel, xmem_din, alu_result, stk_out, cmem_dout, creg_dout)
+	variable data : dmem_data_t;
+	begin
+		case ctrl.lines.reg_src_sel is
+		when xmem_src =>
+			data := xmem_din;
+		when cmem_src =>
+			if cio_sel = '0' then
+				data := cmem_dout(dmem_data_t'range);
+			else
+				data := creg_dout(dmem_data_t'range);
+			end if;
+		when stk_src =>
+			data := stk_out(dmem_data_t'range);
+		when others =>
+			data := alu_result;
+		end case;
+
+		reg_din <= data;
+
+	end process;
+
+alu_op1_mux:
+	process(ctrl.lines.alu_op1_src_sel, reg_a_dout, reg_b_dout, const_data)
+	variable data : dmem_data_t;
+	begin
+		case ctrl.lines.alu_op1_src_sel is
+		when reg_a =>
+			data := reg_a_dout;
+		when reg_b =>
+			data := reg_b_dout;
+		when others =>
+			data := const_data;
+		end case;
+
+		alu_op1 <= data;
+
+	end process;
+
+alu_op2_mux:
+	process(ctrl.lines.alu_op2_src_sel, reg_a_dout, reg_b_dout, const_data)
+	variable data : dmem_data_t;
+	begin
+		case ctrl.lines.alu_op2_src_sel is
+		when reg_a =>
+			data := reg_a_dout;
+		when reg_b =>
+			data := reg_b_dout;
+		when others =>
+			data := const_data;
+		end case;
+
+		alu_op2 <= data;
+
+	end process;
+
+--------------------------------------------------------------------
+	inst_stack_ctrl: stack_ctrl
+	GENERIC MAP (
+		addr_width	=> STACK_SIZE_BITS
+	)
+	PORT MAP(
+		rst			=> rst,
+		clk			=> clk,
+		push		=> stk_push,
+		pop			=> stk_pop,
+		dout		=> stk_reg,
+		din			=> stk_in,
+		ptr_out		=> stk_ptr,
+		mem_we		=> stk_we
+	);
+
+	inst_pc: pc
+	PORT MAP(
+		rst			=> rst,
+		clk			=> clk,
+		inc			=> pc_inc,
+		load		=> pc_load,
+		pc_in		=> pc_in,
+		pc_out		=> pc_out,
+		pc_next		=> pc_next
+	);
+
+	inst_dpath_ctrl: dpath_ctrl
+	GENERIC MAP (
+		use_rom		=> use_ctrl_rom
+	)
+	PORT MAP(
+		inst_in		=> ctrl_inst,
+		iphase_in   => ctrl_iphase,
+		status_in	=> cpu_status,
+		ctrl_out	=> ctrl,
+		ddout		=> const_data,
+		idout		=> idata
+	);
+	
+	inst_int_ctrl: int_ctrl
+	PORT MAP(
+		rst				=> rst,
+		clk				=> clk,
+		ctrl_in			=> creg_ctrl_out.int_ctrl,
+		int_in			=> int_in,
+		int_ack_out		=> int_ack,
+		int_exit		=> ctrl.lines.int_exit,
+		iphase_in		=> ctrl_iphase,
+		stat_save_out	=> status_save,
+		stat_rest_out	=> status_restore,
+		pc_addr_out		=> int_pc_addr,
+		pc_load_out		=> int_pc_load,
+		stk_push_out	=> int_stk_push,
+		stk_pop_out		=> int_stk_pop
+		
+	);
+	
+	inst_reg_ab: reg_dual
+	GENERIC MAP (
+		addr_width	=> REG_SIZE_BITS,
+		data_width	=> DMEM_DATA_WIDTH
+	)
+	PORT MAP(
+		clk			=> clk,
+		we_a		=> ctrl.lines.reg_we,
+		ptr_a		=> ctrl.reg_a_ptr,
+		ptr_b		=> ctrl.reg_b_ptr,
+		din_a		=> reg_din,
+		dout_a		=> reg_a_dout,
+		dout_b		=> reg_b_dout
+	);
+
+	inst_chipram: chipram
+	GENERIC MAP (
+		addr_width	=> CHIPRAM_SIZE_BITS,
+		data_width	=> IMEM_ADDR_WIDTH
+	)
+	PORT MAP(
+		clka		=> clk,
+		clkb		=> clk,
+		en_a		=> cpu_active,
+		en_b		=> cpu_active,
+		we_a		=> stk_we,
+		we_b		=> cmem_we,
+		addr_a		=> stk_addr,
+		addr_b		=> cmem_addr,
+		din_a		=> stk_reg,
+		din_b		=> cmem_din,
+		dout_a		=> stk_out,
+		dout_b		=> cmem_dout
+	);
+
+	inst_chipreg: chipreg
+	PORT MAP(
+		rst			=> rst,
+		clk			=> clk,
+		we			=> creg_we,
+		addr		=> mem_addr,
+		din			=> mem_data,
+		dout		=> creg_dout,
+		ctrl_in		=> creg_ctrl_in,
+		ctrl_out	=> creg_ctrl_out
+	);
+
+	inst_alu: alu
+	GENERIC MAP (
+		data_width	=> DMEM_DATA_WIDTH
+	)
+	PORT MAP(
+		rst			=> rst,
+		clk			=> clk,
+		op_en		=> ctrl.lines.alu_load,
+		cy_in		=> ctrl.lines.alu_cy_in,
+		op1_in		=> alu_op1,
+		op2_in		=> alu_op2,
+		opsel		=> ctrl.lines.alu_opsel,
+		res_out		=> alu_result,
+		stat_load	=> status_restore,
+		stat_in		=> status_reg.alu,
+		stat_out	=> alu_status
+	);
+
+end rtl;
diff --git a/lib/CPUs/JCpu/src/core/cpu_pkg.vhd b/lib/CPUs/JCpu/src/core/cpu_pkg.vhd
new file mode 100644
index 0000000..4c4d56c
--- /dev/null
+++ b/lib/CPUs/JCpu/src/core/cpu_pkg.vhd
@@ -0,0 +1,904 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Types, constants and functions for JCPU
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+
+package cpu_pkg is
+
+	-- Revision of the CPU
+	constant REVISION : integer := 4;
+	
+	-- Chipram depth (valid values 9..floor(log2(BlockRamBytes)))
+	constant CHIPRAM_SIZE_BITS : integer := 10;
+	
+	-- Chipregister file depth
+	constant CHIPREG_SIZE_BITS : integer := 8;
+
+	-- Number of registers (16 registers fixed)
+	constant REG_SIZE_BITS : integer := 4;
+	
+	-- Instruction memory
+	constant IMEM_ADDR_WIDTH : integer := 12;
+	
+	-- Data memory
+	constant DMEM_DATA_WIDTH : integer := 8;
+	constant DMEM_ADDR_WIDTH : integer := 8;
+	
+	-- Instruction format
+	constant INST_OPCODE_WIDTH : integer := 6;
+	constant IMEM_DATA_WIDTH : integer := INST_OPCODE_WIDTH + DMEM_DATA_WIDTH + REG_SIZE_BITS;
+
+	-- Microcode ROM
+	constant MUCODE_ADDR_WIDTH : integer := 10;
+	
+	-- Stack depth (uses lower half of CHIPRAM)
+	constant STACK_SIZE_BITS : integer := CHIPRAM_SIZE_BITS-1;
+
+	--Types
+	subtype iphase_t is integer range 0 to 1;
+	type mem_access_t is (cmem_access, xmem_access, cio_access, xio_access);
+	type reg_src_t is (alu_src, stk_src, cmem_src, xmem_src);
+	type alu_src_t is (reg_a, reg_b, const);
+	type ddata_src_t is (reg_a, reg_b, const);
+	type daddr_src_t is (reg_a, reg_b, const);
+	subtype instr_name_t is string(1 to 12);
+	type instr_name_array_t is array (0 to 63) of instr_name_t;
+	subtype opcode_t is unsigned (INST_OPCODE_WIDTH-1 downto 0);
+	subtype inst_data_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+	subtype inst_addr_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+	subtype inst_t is unsigned (IMEM_DATA_WIDTH-1 downto 0);
+	subtype dmem_data_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
+	subtype dmem_addr_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
+	subtype reg_ptr_t is unsigned (3 downto 0);
+	type dmem_array_t is array (natural range <>) of dmem_data_t;
+	type instr_addr_array is array (integer range <>) of inst_addr_t;
+	subtype page_sel_t is unsigned (CHIPRAM_SIZE_BITS-DMEM_DATA_WIDTH-2 downto 0);
+	
+	type alu_op_t is
+	(
+		pass_op2,
+		op1_add_op2,
+		op1_sub_op2,
+		op1_addc_op2,
+		op1_subc_op2,
+		op1_and_op2,
+		op1_or_op2,
+		op1_xor_op2,
+		swap_op,
+		shl_op,
+		shr_op,
+		rol_op,
+		ror_op,
+		rolc_op,
+		rorc_op
+	);
+	
+	type alu_status_t is record
+		zero		: STD_LOGIC;
+		carry		: STD_LOGIC;
+	end record;
+
+	type cpu_status_t is record
+		alu			: alu_status_t;
+		xmem_wait	: STD_LOGIC;
+	end record;
+
+	type ctrl_lines_t is record
+		reg_we			: STD_LOGIC;
+		reg_src_sel		: reg_src_t;
+		alu_op1_src_sel	: alu_src_t;
+		alu_op2_src_sel	: alu_src_t;
+		alu_opsel		: alu_op_t;
+		alu_load		: STD_LOGIC;
+		alu_cy_in		: STD_LOGIC;
+		ddata_src_sel	: ddata_src_t;
+		daddr_src_sel	: daddr_src_t; 
+		pc_load			: STD_LOGIC;
+		pc_inc			: STD_LOGIC;
+		stk_push		: STD_LOGIC; 
+		stk_pop			: STD_LOGIC;
+		stk_pushd		: STD_LOGIC; 
+		stk_popd		: STD_LOGIC;
+		mem_access		: mem_access_t;
+		mem_read		: STD_LOGIC;
+		mem_write		: STD_LOGIC;
+		int_exit		: STD_LOGIC;
+	end record;
+
+	type dpath_ctrl_out_t is record
+		lines			: ctrl_lines_t;
+		reg_a_ptr		: reg_ptr_t;
+		reg_b_ptr		: reg_ptr_t;
+	end record;
+	
+	type int_ctrl_in_t is record
+		enable			: std_logic;
+		polarity		: std_logic;
+		edge_sens		: std_logic;
+		request			: std_logic;
+	end record;
+	
+	type creg_ctrl_out_t is record
+		page_sel		: page_sel_t;
+		int_ctrl		: int_ctrl_in_t;
+		stk_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
+		cmem_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
+	end record;
+	
+	type creg_ctrl_in_t is record
+		alu				: alu_status_t;
+	end record;
+
+	
+	type murom_t is array (0 to integer(2**MUCODE_ADDR_WIDTH)-1) of ctrl_lines_t;
+
+	constant instr_name_array : instr_name_array_t := 
+	(
+		"NOP         ", -- 00
+		"HALT        ", -- 01
+		"MOV|R|R     ", -- 02
+		"MOV|R|K     ", -- 03
+		"MOVX|R|Ri   ", -- 04
+		"MOVX|R|Ki   ", -- 05
+		"MOVX|Ri|R   ", -- 06
+		"MOVX|Ri|K   ", -- 07
+		"MOVX|Ki|R   ", -- 08
+		"MOVC|R|Ri   ", -- 09
+		"MOVC|R|Ki   ", -- 0A
+		"MOVC|Ri|R   ", -- 0B
+		"MOVC|Ri|K   ", -- 0C
+		"MOVC|Ki|R   ", -- 0D
+		"CMP|R|R     ", -- 0E
+		"CMP|R|K     ", -- 0F
+		"ADD|R|R     ", -- 10
+		"ADD|R|K     ", -- 11
+		"ADDC|R|R    ", -- 12
+		"ADDC|R|K    ", -- 13
+		"SUB|R|R     ", -- 14
+		"SUB|R|K     ", -- 15
+		"SUBC|R|R    ", -- 16
+		"SUBC|R|K    ", -- 17
+		"AND|R|R     ", -- 18
+		"AND|R|K     ", -- 19
+		"OR|R|R      ", -- 1A
+		"OR|R|K      ", -- 1B
+		"XOR|R|R     ", -- 1C
+		"XOR|R|K     ", -- 1D
+		"SHL|R       ", -- 1E
+		"SHR|R       ", -- 1F
+		"ROL|R       ", -- 20
+		"ROR|R       ", -- 21
+		"ROLC|R      ", -- 22
+		"RORC|R      ", -- 23
+		"XOUT|Ki|R   ", -- 24
+		"XOUT|Ri|K   ", -- 25
+		"COUT|Ki|R   ", -- 26
+		"COUT|Ri|K   ", -- 27
+		"XIN|R|Ki    ", -- 28
+		"CIN|R|Ki    ", -- 29
+		"SWAP|R      ", -- 2A
+		"SETC        ", -- 2B
+		"UNDEF       ", -- 2C
+		"UNDEF       ", -- 2D
+		"SUB|K|R     ", -- 2E
+		"SUBC|K|R    ", -- 2F
+		"JMP|K       ", -- 30
+		"JZ|K        ", -- 31
+		"JNZ|K       ", -- 32
+		"JC|K        ", -- 33
+		"JNC|K       ", -- 34
+		"JLT|K       ", -- 35
+		"JGT|K       ", -- 36
+		"JLE|K       ", -- 37
+		"JGE|K       ", -- 38
+		"JEQ|K       ", -- 39
+		"JNE|K       ", -- 3A
+		"CALL|K      ", -- 3B
+		"PUSH|R      ", -- 3C
+		"POP|R       ", -- 3D
+		"RET         ", -- 3E
+		"RETI        "  -- 3F
+	);
+	-- Functions
+	function Instr(opcode : opcode_t) return inst_t;
+	function Instr(opcode : opcode_t; data : inst_data_t) return inst_t;
+	function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t;
+	function Instr(opcode : opcode_t; reg_a : integer) return inst_t;
+	function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t;
+	function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t;
+	function ctrl_lines_default return ctrl_lines_t;
+	function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
+	function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
+	function gen_murom return murom_t;
+	function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned;
+	function MIN (X, Y: INTEGER) return INTEGER;
+	function MAX (X, Y: INTEGER) return INTEGER;
+
+end cpu_pkg;
+
+package body cpu_pkg is
+
+	function Instr(opcode : opcode_t) return inst_t is
+	variable inst : inst_t := (others => '0'); 
+	begin
+		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
+		return inst;
+
+	end Instr;
+
+	function Instr(opcode : opcode_t; data : inst_data_t) return inst_t is
+	variable inst : inst_t := (others => '0'); 
+	begin
+		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
+		inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_addr_t'length) := data;
+		return inst;
+
+	end Instr;
+
+	function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t is
+	variable inst : inst_t := (others => '0');
+	begin
+		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
+		inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_data_t'length) := data;
+		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg, reg_ptr_t'length));
+
+		return inst;
+
+	end Instr;
+
+	function Instr(opcode : opcode_t; reg_a : integer) return inst_t is
+	variable inst : inst_t := (others => '0');
+	begin
+		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
+		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
+
+		return inst;
+
+	end Instr;
+
+	function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t is
+	variable inst : inst_t := (others => '0');
+	begin
+		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
+		inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length));
+		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
+
+		return inst;
+
+	end Instr;
+
+	function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t is
+	variable inst : inst_t := (others => '0');
+	begin
+		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
+		inst(3*(reg_ptr_t'length)-1 downto 2*reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_c, reg_ptr_t'length));
+		inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length));
+		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
+
+		return inst;
+
+	end Instr;
+
+	function ctrl_lines_default return ctrl_lines_t is
+	variable result : ctrl_lines_t;
+	begin
+		result.pc_load := '0';
+		result.pc_inc := '0';
+		result.stk_push := '0';
+		result.stk_pop := '0';
+		result.stk_pushd := '0';
+		result.stk_popd := '0';
+		result.reg_we := '0';
+		result.reg_src_sel := alu_src;
+		result.ddata_src_sel := reg_a;
+		result.daddr_src_sel := reg_b;
+		result.alu_opsel := pass_op2;
+		result.alu_op1_src_sel := reg_a;
+		result.alu_op2_src_sel := reg_b;
+		result.alu_load := '0';
+		result.alu_cy_in := '0';
+		result.mem_access := cmem_access;
+		result.mem_read := '0';
+		result.mem_write := '0';
+		result.int_exit := '0';
+		return result;
+	
+	end ctrl_lines_default;
+
+	function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
+	variable instr_name : instr_name_t;
+	begin
+		instr_name := instr_name_array(to_integer(opcode));
+		return idecoder(instr_name, iphase, status);
+	end idecoder;
+
+	function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
+	variable result : ctrl_lines_t;
+	variable ze, cy, xmem_wait : STD_LOGIC;
+	
+	begin
+		ze			:= status.alu.zero;
+		cy			:= status.alu.carry;
+		xmem_wait	:= status.xmem_wait;
+		
+		result := ctrl_lines_default;
+		if iphase = 0 then
+			result.pc_inc := '1';
+		end if;
+
+		case instr_name is
+
+		when "HALT        " =>
+			result.pc_inc := '0';
+		when "SETC        " => -- carry <= 1
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := pass_op2;
+			result.alu_op2_src_sel := reg_b;
+			result.alu_load := '1';
+			result.alu_cy_in := '1';
+		when "MOV|R|R     " => -- R(a) <= R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := pass_op2;
+			result.alu_op2_src_sel := reg_b;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "MOV|R|K     " => -- R(a) <= #kk
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := pass_op2;
+			result.alu_op2_src_sel := const;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "MOVC|Ri|R   " => -- [R(b)] <= R(a)
+			result.mem_access := cmem_access;
+			result.daddr_src_sel := reg_b;
+			result.ddata_src_sel := reg_a;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+		when "MOVC|Ri|K   " => -- [R(a)] <= kk
+			result.mem_access := cmem_access;
+			result.daddr_src_sel := reg_a;
+			result.ddata_src_sel := const;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+		when "COUT|Ri|K   " => -- [R(a)] <= kk
+			result.mem_access := cio_access;
+			result.daddr_src_sel := reg_a;
+			result.ddata_src_sel := const;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+		when "MOVC|R|Ri   " => -- R(a) <= [R(b)]
+			result.mem_access := cmem_access;
+			result.reg_src_sel := cmem_src;
+			result.daddr_src_sel := reg_b;
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "MOVC|R|Ki   " => -- R(a) <= [#addr]
+			result.mem_access := cmem_access;
+			result.reg_src_sel := cmem_src;
+			result.daddr_src_sel := const;
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "CIN|R|Ki    " => -- R(a) <= [#addr]
+			result.mem_access := cio_access;
+			result.reg_src_sel := cmem_src;
+			result.daddr_src_sel := const;
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "MOVC|Ki|R   " => -- [#addr] <= R(a)
+			result.mem_access := cmem_access;
+			result.daddr_src_sel := const;
+			result.ddata_src_sel := reg_a;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+		when "COUT|Ki|R   " => -- [#addr] <= R(a)
+			result.mem_access := cio_access;
+			result.daddr_src_sel := const;
+			result.ddata_src_sel := reg_a;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+		when "MOVX|Ri|R   " => -- [R(b)] <= R(a)
+			result.mem_access := xmem_access;
+			result.daddr_src_sel := reg_b;
+			result.ddata_src_sel := reg_a;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+			if xmem_wait = '1' then
+				result.mem_write := '1';
+				result.pc_inc := '0';
+			end if;
+		when "MOVX|Ri|K   " => -- [R(a)] <= kk
+			result.mem_access := xmem_access;
+			result.daddr_src_sel := reg_a;
+			result.ddata_src_sel := const;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+			if xmem_wait = '1' then
+				result.mem_write := '1';
+				result.pc_inc := '0';
+			end if;
+		when "XOUT|Ri|K   " => -- [R(a)] <= kk
+			result.mem_access := xio_access;
+			result.daddr_src_sel := reg_a;
+			result.ddata_src_sel := const;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+			if xmem_wait = '1' then
+				result.pc_inc := '0';
+				result.mem_write := '1';
+			end if;
+		when "MOVX|R|Ri   " => -- R(a) <= [R(b)]
+			result.mem_access := xmem_access;
+			result.reg_src_sel := xmem_src;
+			result.daddr_src_sel := reg_b;
+			if iphase = 0 then
+				result.mem_read := '1';
+			end if;
+			if xmem_wait = '0' then
+				if iphase = 1 then
+					result.reg_we := '1';
+				end if;
+			else
+				result.pc_inc := '0';
+				result.mem_read := '1';
+			end if;
+		when "MOVX|R|Ki   " => -- R(a) <= [#addr]
+			result.mem_access := xmem_access;
+			result.reg_src_sel := xmem_src;
+			result.daddr_src_sel := const;
+			if iphase = 0 then
+				result.mem_read := '1';
+			end if;
+			if xmem_wait = '0' then
+				if iphase = 1 then
+					result.reg_we := '1';
+				end if;
+			else
+				result.pc_inc := '0';
+				result.mem_read := '1';
+			end if;
+		when "XIN|R|Ki    " => -- R(a) <= [#addr]
+			result.mem_access := xio_access;
+			result.reg_src_sel := xmem_src;
+			result.daddr_src_sel := const;
+			if iphase = 0 then
+				result.mem_read := '1';
+			end if;
+			if xmem_wait = '0' then
+				if iphase = 1 then
+					result.reg_we := '1';
+				end if;
+			else
+				result.pc_inc := '0';
+				result.mem_read := '1';
+			end if;
+		when "MOVX|Ki|R   " => -- [#addr] <= R(a)
+			result.mem_access := xmem_access;
+			result.daddr_src_sel := const;
+			result.ddata_src_sel := reg_a;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+			if xmem_wait = '1' then
+				result.pc_inc := '0';
+				result.mem_write := '1';
+			end if;
+		when "XOUT|Ki|R   " => -- [#addr] <= R(a)
+			result.mem_access := xio_access;
+			result.daddr_src_sel := const;
+			result.ddata_src_sel := reg_a;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+			if xmem_wait = '1' then
+				result.pc_inc := '0';
+				result.mem_write := '1';
+			end if;
+		when "ADD|R|R     " => -- R(a) <= R(a) + R(b)
+			result.alu_opsel := op1_add_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "ADD|R|K     " => -- R(a) <= R(a) + k
+			result.alu_opsel := op1_add_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "ADDC|R|R    " => -- R(a) <= R(a) + R(b)
+			result.alu_opsel := op1_addc_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "ADDC|R|K    " => -- R(a) <= R(a) + k
+			result.alu_opsel := op1_addc_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SUB|R|R     " => -- R(a) <= R(a) + R(b)
+			result.alu_opsel := op1_sub_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SUB|R|K     " => -- R(a) <= R(a) + k
+			result.alu_opsel := op1_sub_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SUB|K|R     " => -- R(a) <= k - R(a)
+			result.alu_opsel := op1_sub_op2;
+			result.alu_op1_src_sel := const;
+			result.alu_op2_src_sel := reg_a;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SUBC|R|R    " => -- R(a) <= R(a) + R(b)
+			result.alu_opsel := op1_subc_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SUBC|R|K    " => -- R(a) <= R(a) + k
+			result.alu_opsel := op1_subc_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SUBC|K|R    " => -- R(a) <= K - R(a)
+			result.alu_opsel := op1_subc_op2;
+			result.alu_op1_src_sel := const;
+			result.alu_op2_src_sel := reg_a;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "AND|R|R     " => -- R(a) <= R(a) and R(b)
+			result.alu_opsel := op1_and_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "AND|R|K     " => -- R(a) <= R(a) and k
+			result.alu_opsel := op1_and_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "OR|R|R      " => -- R(a) <= R(a) or R(b)
+			result.alu_opsel := op1_or_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "OR|R|K      " => -- R(a) <= R(a) or R(b)
+			result.alu_opsel := op1_or_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "XOR|R|R     " => -- R(a) <= R(a) xor R(b)
+			result.alu_opsel := op1_xor_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "XOR|R|K     " => -- R(a) <= R(a) xor R(b)
+			result.alu_opsel := op1_xor_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SWAP|R      " => -- R(a) <= R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := swap_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SHL|R       " => -- R(a) <= R(a) xor R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := shl_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SHR|R       " => -- R(a) <= R(a) xor R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := shr_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "ROL|R       " => -- R(a) <= R(a) xor R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := rol_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "ROR|R       " => -- R(a) <= R(a) xor R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := ror_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "ROLC|R      " => -- R(a) <= R(a) xor R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := rolc_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "RORC|R      " => -- R(a) <= R(a) xor R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := rorc_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "CMP|R|R     " => -- 
+			result.alu_opsel := op1_sub_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.alu_load := '1';
+		when "CMP|R|K     " => -- 
+			result.alu_opsel := op1_sub_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.alu_load := '1';
+		when "JMP|K       " => -- PC <= #addr
+			if iphase = 0 then
+				result.pc_load := '1';
+			end if;
+		when "JZ|K        " => -- PC <= #addr, zero
+			if iphase = 0 then
+				if ze = '1' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JNZ|K       " => -- PC <= #addr, !zero
+			if iphase = 0 then
+				if ze = '0' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JC|K        " => -- PC <= #addr, carry
+			if iphase = 0 then
+				if cy = '1' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JNC|K       " => -- PC <= #addr, !carry
+			if iphase = 0 then
+				if cy = '0' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JLT|K       " => -- PC <= #addr, !carry
+			if iphase = 0 then
+				if cy = '1' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JGT|K       " => -- 
+			if iphase = 0 then
+				if (cy or ze) = '0' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JLE|K       " => -- 
+			if iphase = 0 then
+				if (cy xor ze) = '1' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JGE|K       " => -- 
+			if iphase = 0 then
+				if (not cy or ze) = '1' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JEQ|K       " => -- 
+			if iphase = 0 then
+				if ze = '1' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JNE|K       " => -- 
+			if iphase = 0 then
+				if ze = '0' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "PUSH|R      " => -- push
+			if iphase = 0 then
+				result.stk_pushd := '1';
+			end if;
+		when "POP|R       " => -- pop
+			result.reg_src_sel := stk_src;
+			if iphase = 0 then
+				result.stk_popd := '1';
+			elsif iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "CALL|K      " => -- call
+			if iphase = 0 then
+				result.pc_load := '1';
+				result.stk_push := '1';
+			end if;
+		when "RET         " => -- return
+			if iphase = 0 then
+				result.pc_load := '1';
+				result.stk_pop := '1';
+			end if;
+		when "RETI        " => -- return
+			result.pc_inc := '0';
+			result.int_exit := '1';
+			
+		when others => null; -- nop
+		end case;
+
+		return result;
+
+	end idecoder;
+
+	function gen_murom return murom_t is
+	variable result : murom_t; 
+	variable opcode : opcode_t;
+	variable iphase : iphase_t;
+	variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
+	variable status : cpu_status_t;
+	variable pos : integer := 0;
+	
+	begin
+		for i in 0 to 2**addr'length-1 loop
+			addr := to_unsigned(i, addr'length);
+			opcode := addr(opcode'length-1 downto 0);
+			pos := opcode'length;
+			iphase := 0;
+			if addr(pos) = '1' then
+				iphase := 1;
+			end if;
+			pos := pos + 1;
+			status.alu.zero := addr(pos);
+			pos := pos + 1;
+			status.alu.carry := addr(pos);
+			pos := pos + 1;
+			status.xmem_wait := addr(pos);
+			
+			result(i) := idecoder(opcode, iphase, status);
+		end loop;
+
+		return result;
+	end gen_murom;
+
+	function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned is
+	variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
+	begin
+		addr := status.xmem_wait & status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode;
+		return addr;
+		
+	end get_muromaddr;
+
+	-------------------------------------------------------------
+	function MIN (X, Y: INTEGER) return INTEGER is
+	variable res : integer := X;
+	begin
+	if Y < X then
+		res := Y;
+	end if;
+
+	return res;
+
+	end MIN;
+
+	-------------------------------------------------------------
+	function MAX (X, Y: INTEGER) return INTEGER is
+	variable res : integer := X;
+	begin
+	if Y > X then
+		res := Y;
+	end if;
+
+	return res;
+	
+	end MAX;
+
+
+end cpu_pkg;
+
diff --git a/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd b/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd
new file mode 100644
index 0000000..1610d00
--- /dev/null
+++ b/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd
@@ -0,0 +1,87 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The datapath controller
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity dpath_ctrl is
+	Generic (
+		use_rom		: boolean := true
+	);
+	Port (
+		inst_in		: in  inst_t;
+		iphase_in	: in  iphase_t;
+		status_in	: in  cpu_status_t;
+		ctrl_out	: out dpath_ctrl_out_t;
+		idout		: out inst_addr_t;
+		ddout		: out dmem_data_t
+	);
+end dpath_ctrl;
+
+architecture Behavioral of dpath_ctrl is
+
+	signal opcode : opcode_t;
+	signal ctrl_lines : ctrl_lines_t;
+	signal dbg_iname : instr_name_t;
+	
+begin
+
+	idout <= inst_in(IMEM_ADDR_WIDTH-1 downto 0);
+	ddout <= inst_in(REG_SIZE_BITS+DMEM_DATA_WIDTH-1 downto REG_SIZE_BITS);
+	opcode <= inst_in(IMEM_DATA_WIDTH-1 downto IMEM_DATA_WIDTH-INST_OPCODE_WIDTH);
+
+	ctrl_out.reg_a_ptr <= inst_in(reg_ptr_t'length-1 downto 0);
+	ctrl_out.reg_b_ptr <= inst_in(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length);
+	ctrl_out.lines <= ctrl_lines;
+
+	-- pragma translate_off
+	dbg_iname <= instr_name_array(to_integer(opcode));
+	-- pragma translate_on
+
+gen_ctrl_rom:
+if use_rom = true generate
+
+	i_dec:
+		process(opcode, iphase_in, status_in)
+		constant rom_data : murom_t := gen_murom;
+		variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
+		begin
+			addr := get_muromaddr(opcode, iphase_in, status_in);
+			ctrl_lines <= rom_data(to_integer(addr));
+		end process;
+end generate;
+
+gen_ctrl:
+if use_rom = false generate
+	i_dec:
+		process (opcode, iphase_in, status_in)
+		begin
+			ctrl_lines <= idecoder(opcode, iphase_in, status_in);
+		end process;
+end generate;
+
+end Behavioral;
+
diff --git a/lib/CPUs/JCpu/src/core/int_ctrl.vhd b/lib/CPUs/JCpu/src/core/int_ctrl.vhd
new file mode 100644
index 0000000..2e54d67
--- /dev/null
+++ b/lib/CPUs/JCpu/src/core/int_ctrl.vhd
@@ -0,0 +1,177 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Interrupt controller 
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity int_ctrl is
+	Port (
+		rst				: in  STD_LOGIC;
+		clk				: in  STD_LOGIC;
+		ctrl_in			: in  int_ctrl_in_t;
+		int_in			: in  STD_LOGIC;
+		int_exit		: in  STD_LOGIC;
+		iphase_in		: in  iphase_t;
+		pc_addr_out		: out inst_addr_t;
+		int_ack_out		: out STD_LOGIC;
+		stat_save_out	: out STD_LOGIC; 
+		stat_rest_out	: out STD_LOGIC; 
+		pc_load_out		: out STD_LOGIC;
+		stk_push_out	: out STD_LOGIC;
+		stk_pop_out		: out STD_LOGIC
+	);
+end int_ctrl;
+
+architecture Behavioral of int_ctrl is
+
+	type int_state_t is (int_idle, int_inject, int_active, int_release);
+	type pin_state_t is (pin_s0, pin_s1, pin_s2);
+	
+	signal int_state, int_state_next : int_state_t;
+	signal pin_state, pin_state_next : pin_state_t;
+	signal pc_load, int_ack, stk_push, stk_pop : STD_LOGIC;
+	signal int_request : std_logic;
+	signal int_sampled : std_logic;
+	
+begin
+
+	int_ack_out		<= int_ack;
+	pc_load_out		<= pc_load;
+	stk_push_out	<= stk_push;
+	stk_pop_out		<= stk_pop;
+	
+-----------------------------------------------------------------------
+irg_ctrl_fsm:
+	process (int_state, iphase_in, int_request, int_exit)
+	begin
+
+		pc_addr_out <= to_unsigned(1, inst_addr_t'length);
+		int_state_next <= int_state;
+		int_ack <= '0';
+		pc_load <= '0';
+		stk_push <= '0';
+		stk_pop <= '0';
+
+		case int_state is
+		
+		when int_idle =>
+			if int_request = '1' and iphase_in = 1 then
+				int_state_next <= int_inject;
+			end if;
+		when int_inject =>
+			if iphase_in = 0 then
+				int_ack <= '1';
+				pc_load <= '1';
+			elsif iphase_in = 1 then
+				stk_push <= '1';
+				int_state_next <= int_active;
+			end if;
+		when int_active =>
+			if int_exit = '1' and iphase_in = 1 then
+				int_state_next <= int_release;
+			end if;
+		when int_release =>
+			if iphase_in = 0 then
+				stk_pop <= '1';
+				pc_load <= '1';
+			elsif iphase_in = 1 then
+				int_state_next <= int_idle;
+			end if;	
+		when others => 	
+			int_state_next <= int_idle;
+		end case;	
+			
+	end process;
+	
+irq_ctrl_states:
+	process (rst, clk, int_state_next)
+	begin
+		if rst = '1' then
+			int_state <= int_idle;
+		elsif rising_edge(clk) then
+			int_state <= int_state_next;
+		end if;
+	end process;
+
+-----------------------------------------------------------------------
+pin_sample:
+	process (clk)
+	begin
+		if rising_edge(clk) then
+			int_sampled <= int_in xor (not ctrl_in.polarity);
+		end if;
+	end process;
+
+-----------------------------------------------------------------------
+pin_fsm:
+	process (pin_state, int_sampled, int_ack, ctrl_in)
+	begin
+		int_request <= '0';
+		pin_state_next <= pin_state;
+		case pin_state is
+			when pin_s0 => 
+				if int_sampled = '1' or ctrl_in.request = '1' then
+					if ctrl_in.enable = '1' then
+						pin_state_next <= pin_s1;
+					end if;	
+				end if;
+			when pin_s1 => 
+				int_request <= '1';
+				if int_ack = '1' then
+					pin_state_next <= pin_s2;
+				end if;	
+			when pin_s2 =>
+				if ctrl_in.edge_sens = '0' then
+					pin_state_next <= pin_s0;
+				elsif int_sampled = '0'	then
+					pin_state_next <= pin_s0;
+				end if;
+			when others =>
+				pin_state_next <= pin_s0;
+			end case;	
+	end process;
+			
+pin_states:
+	process (rst, clk, pin_state_next)
+	begin
+		if rst = '1' then
+			pin_state <= pin_s0;
+		elsif rising_edge(clk) then
+			pin_state <= pin_state_next;
+		end if;
+	end process;
+
+-----------------------------------------------------------------------
+stat_save_restore:
+	process (clk, stk_push, stk_pop)
+	begin
+		if rising_edge(clk) then
+			stat_save_out <= stk_push;
+			stat_rest_out <= stk_pop;
+		end if;
+	end process;
+
+end Behavioral;
diff --git a/lib/CPUs/JCpu/src/core/pc.vhd b/lib/CPUs/JCpu/src/core/pc.vhd
new file mode 100644
index 0000000..6b1d575
--- /dev/null
+++ b/lib/CPUs/JCpu/src/core/pc.vhd
@@ -0,0 +1,70 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Programm counter
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity pc is
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		inc			: in  STD_LOGIC;
+		load		: in  STD_LOGIC;
+		pc_in		: in  inst_addr_t;
+		pc_out		: out inst_addr_t;
+		pc_next		: out inst_addr_t
+	);
+end pc;
+
+architecture Behavioral of pc is
+
+begin
+
+proc_pc:
+	process(rst, clk, inc, load, pc_in)
+	variable vpc, vpc_reg: inst_addr_t;
+	begin
+		if rst = '1' then
+			vpc_reg := (others => '0');
+		elsif rising_edge(clk) then
+			if inc = '1' or load = '1' then
+				vpc_reg := vpc;
+			elsif inc = '0'	then
+				pc_next <= vpc;		
+			end if;
+		end if;
+		
+		if load = '1' then
+			vpc := pc_in;	
+		else
+			vpc := vpc_reg + 1;
+		end if;	
+		pc_out <= vpc_reg;
+		
+	end process;
+
+end Behavioral;
+
diff --git a/lib/CPUs/JCpu/src/core/reg_dual.vhd b/lib/CPUs/JCpu/src/core/reg_dual.vhd
new file mode 100644
index 0000000..6b7e4d8
--- /dev/null
+++ b/lib/CPUs/JCpu/src/core/reg_dual.vhd
@@ -0,0 +1,81 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: On-Chip work registers
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity reg_dual is
+	Generic (
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clk			: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		ptr_a		: in  reg_ptr_t;
+		ptr_b		: in  reg_ptr_t;
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end reg_dual;
+
+architecture Behavioral of reg_dual is
+
+	constant depth : integer := 2**addr_width;
+	type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal addr_a, addr_b : unsigned (addr_width-1 downto 0) := (others => '0');
+
+	signal mem : mem_t;
+begin
+
+	addr_a <= TO_01(ptr_a(addr_width-1 downto 0));
+	addr_b <= TO_01(ptr_b(addr_width-1 downto 0));
+
+reg_in_ab:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if we_a = '1' then
+				mem(to_integer(addr_a)) <= din_a;
+			end if;
+		end if;	
+	end process;
+
+reg_out_a:
+	process(mem, addr_a)
+	begin
+		dout_a <= TO_01(mem(to_integer(addr_a)));
+	end process;
+
+reg_out_b:
+	process(mem, addr_b)
+	begin
+		dout_b <= TO_01(mem(to_integer(addr_b)));
+	end process;
+
+end Behavioral;
+
diff --git a/lib/CPUs/JCpu/src/core/stack_ctrl.vhd b/lib/CPUs/JCpu/src/core/stack_ctrl.vhd
new file mode 100644
index 0000000..7eccae3
--- /dev/null
+++ b/lib/CPUs/JCpu/src/core/stack_ctrl.vhd
@@ -0,0 +1,73 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The call/return/data stack
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity stack_ctrl is
+Generic (
+	addr_width : integer := 3
+);
+Port (
+	rst			: in  STD_LOGIC;
+	clk			: in  STD_LOGIC;
+	push		: in  STD_LOGIC;
+	pop			: in  STD_LOGIC;
+	ptr_out		: out unsigned (addr_width-1 downto 0);
+	din			: in  inst_addr_t;
+	dout		: out inst_addr_t;
+	mem_we		: out STD_LOGIC
+	);
+end stack_ctrl;
+
+architecture Behavioral of stack_ctrl is
+
+	signal ptr : unsigned (addr_width-1 downto 0);
+
+begin
+
+	ptr_out <= ptr;
+
+stk_ptr:
+	process(rst, clk, ptr, push, pop)
+	begin
+		if rst = '1' then
+			ptr <= (others => '0');
+			dout <= (others => '0');
+			mem_we <= '0';
+		elsif rising_edge(clk) then
+			mem_we <= push;
+			if push = '1' then
+				ptr <= ptr + 1;
+				dout <= din;
+			elsif pop = '1' then
+				ptr <= ptr - 1;
+			end if;
+		end if;
+	end process;
+
+end Behavioral;
+
diff --git a/lib/CPUs/JCpu/src/cpu_embedded.vhd b/lib/CPUs/JCpu/src/cpu_embedded.vhd
new file mode 100644
index 0000000..1990170
--- /dev/null
+++ b/lib/CPUs/JCpu/src/cpu_embedded.vhd
@@ -0,0 +1,109 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity cpu_embedded is
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		int_in		: in  STD_LOGIC;
+		int_ack		: out STD_LOGIC;
+		xmem_wait	: in  STD_LOGIC;
+		xmem_we		: out STD_LOGIC;
+		xmem_re		: out STD_LOGIC;
+		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
+		io_sel		: out STD_LOGIC
+	);
+end cpu_embedded;
+
+architecture rtl of cpu_embedded is
+
+	signal irom_data	: unsigned (IMEM_DATA_WIDTH-1 downto 0);
+	signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+
+	COMPONENT cpu
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		int_in		: in  STD_LOGIC;
+		int_ack		: out STD_LOGIC;
+		xmem_wait	: in  STD_LOGIC;
+		xmem_we		: out STD_LOGIC;
+		xmem_re		: out STD_LOGIC;
+		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
+		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_addr	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		io_sel		: out STD_LOGIC
+	);
+	END COMPONENT;
+
+
+	COMPONENT irom
+		Port (
+			clk			: in  STD_LOGIC;
+			ce			: in  STD_LOGIC;
+			addr		: in  inst_addr_t;
+			dout		: out inst_t
+		);
+	END COMPONENT;
+
+begin
+
+inst_cpu: cpu
+	PORT MAP(
+		rst => rst,
+		clk => clk,
+		ce => ce,
+		int_in => int_in,
+		int_ack => int_ack,
+		xmem_wait => xmem_wait,
+		xmem_we => xmem_we,
+		xmem_re => xmem_re,
+		instr_din => irom_data,
+		instr_addr => irom_addr,
+		xmem_din => xmem_din,
+		xmem_dout => xmem_dout,
+		xmem_addr => xmem_addr,
+		io_sel => io_sel
+	);
+
+inst_irom: irom
+	PORT MAP(
+		clk			=> clk,
+		ce			=> ce,
+		addr		=> irom_addr,
+		dout 		=> irom_data
+	);
+
+end rtl;
diff --git a/lib/CPUs/JCpu/src/dctest_irom.vhdl b/lib/CPUs/JCpu/src/dctest_irom.vhdl
new file mode 100644
index 0000000..7987a15
--- /dev/null
+++ b/lib/CPUs/JCpu/src/dctest_irom.vhdl
@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY irom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  inst_addr_t;
+	dout		: out inst_t
+	);
+END irom;
+
+ARCHITECTURE dctest OF irom IS 
+
+	type imem_rom_t is array (0 to 17) of inst_t;
+
+	-- Assembled from dctest.jsm
+	constant imem_rom : imem_rom_t :=
+	(
+		"110000" & X"010", -- 0x000: JMP 0x010
+		"110000" & X"011", -- 0x001: JMP 0x011
+		"000000" & X"000", -- 0x002:
+		"000000" & X"000", -- 0x003:
+		"000000" & X"000", -- 0x004:
+		"000000" & X"000", -- 0x005:
+		"000000" & X"000", -- 0x006:
+		"000000" & X"000", -- 0x007:
+		"000000" & X"000", -- 0x008:
+		"000000" & X"000", -- 0x009:
+		"000000" & X"000", -- 0x00A:
+		"000000" & X"000", -- 0x00B:
+		"000000" & X"000", -- 0x00C:
+		"000000" & X"000", -- 0x00D:
+		"000000" & X"000", -- 0x00E:
+		"000000" & X"000", -- 0x00F:
+		"110000" & X"010", -- 0x010: JMP 0x010
+		"111111" & X"000"  -- 0x011: RETI
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end dctest;
+
diff --git a/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl b/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl
new file mode 100644
index 0000000..223dd46
--- /dev/null
+++ b/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl
@@ -0,0 +1,1181 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY irom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  inst_addr_t;
+		dout		: out inst_t
+	);
+	
+END irom;
+
+ARCHITECTURE loadable OF irom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from dctest.jsm
+	type imem_rom_t is array (0 to 1023) of inst_t;
+	signal imem_rom : imem_rom_t :=
+	(
+		"110000" & X"010", -- 0x000: JMP 0x010
+		"110000" & X"011", -- 0x001: JMP 0x011
+		"000000" & X"000", -- 0x002:
+		"000000" & X"000", -- 0x003:
+		"000000" & X"000", -- 0x004:
+		"000000" & X"000", -- 0x005:
+		"000000" & X"000", -- 0x006:
+		"000000" & X"000", -- 0x007:
+		"000000" & X"000", -- 0x008:
+		"000000" & X"000", -- 0x009:
+		"000000" & X"000", -- 0x00A:
+		"000000" & X"000", -- 0x00B:
+		"000000" & X"000", -- 0x00C:
+		"000000" & X"000", -- 0x00D:
+		"000000" & X"000", -- 0x00E:
+		"000000" & X"000", -- 0x00F:
+		"110000" & X"010", -- 0x010: JMP 0x010
+		"111111" & X"000", -- 0x011: RETI
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
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+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
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+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
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+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
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+		"000000" & X"000",
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+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000"
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: inst_addr_t;
+	signal jtag_ld_dout		: inst_t;
+	signal jtag_ld_din		: inst_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (31 downto 0);
+	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
+	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;
diff --git a/lib/CPUs/JCpu/src/dctest_xrom.vhdl b/lib/CPUs/JCpu/src/dctest_xrom.vhdl
new file mode 100644
index 0000000..24fe36c
--- /dev/null
+++ b/lib/CPUs/JCpu/src/dctest_xrom.vhdl
@@ -0,0 +1,317 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY xrom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  dmem_addr_t;
+	dout		: out dmem_data_t
+	);
+END xrom;
+
+ARCHITECTURE dctest OF xrom IS 
+
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+
+	-- Assembled from dctest.jsm
+	constant xmem_rom : xmem_rom_t :=
+	(
+		X"00", -- 0x00
+		X"00", -- 0x01
+		X"00", -- 0x02
+		X"00", -- 0x03
+		X"01", -- 0x04
+		X"12", -- 0x05
+		X"41", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"48", -- 0x17
+		X"61", -- 0x18
+		X"6C", -- 0x19
+		X"6C", -- 0x1A
+		X"6F", -- 0x1B
+		X"0D", -- 0x1C
+		X"0A", -- 0x1D
+		X"00", -- 0x1E
+		X"4A", -- 0x1F
+		X"65", -- 0x20
+		X"6E", -- 0x21
+		X"73", -- 0x22
+		X"00", -- 0x23
+		X"57", -- 0x24
+		X"65", -- 0x25
+		X"6C", -- 0x26
+		X"63", -- 0x27
+		X"6F", -- 0x28
+		X"6D", -- 0x29
+		X"65", -- 0x2A
+		X"20", -- 0x2B
+		X"74", -- 0x2C
+		X"6F", -- 0x2D
+		X"20", -- 0x2E
+		X"4A", -- 0x2F
+		X"41", -- 0x30
+		X"53", -- 0x31
+		X"4D", -- 0x32
+		X"20", -- 0x33
+		X"43", -- 0x34
+		X"50", -- 0x35
+		X"55", -- 0x36
+		X"00", -- 0x37
+		X"52", -- 0x38
+		X"65", -- 0x39
+		X"61", -- 0x3A
+		X"64", -- 0x3B
+		X"79", -- 0x3C
+		X"00", -- 0x3D
+		X"54", -- 0x3E
+		X"65", -- 0x3F
+		X"73", -- 0x40
+		X"74", -- 0x41
+		X"69", -- 0x42
+		X"6E", -- 0x43
+		X"67", -- 0x44
+		X"00", -- 0x45
+		X"50", -- 0x46
+		X"61", -- 0x47
+		X"73", -- 0x48
+		X"73", -- 0x49
+		X"65", -- 0x4A
+		X"64", -- 0x4B
+		X"00", -- 0x4C
+		X"45", -- 0x4D
+		X"72", -- 0x4E
+		X"72", -- 0x4F
+		X"6F", -- 0x50
+		X"72", -- 0x51
+		X"00", -- 0x52
+		X"0D", -- 0x53
+		X"0A", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end dctest;
+
diff --git a/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl b/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl
new file mode 100644
index 0000000..802ba50
--- /dev/null
+++ b/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl
@@ -0,0 +1,413 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY xrom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		dout		: out dmem_data_t
+	);
+	
+END xrom;
+
+ARCHITECTURE loadable OF xrom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from dctest.jsm
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+	signal xmem_rom : xmem_rom_t :=
+	(
+		X"00", -- 0x00
+		X"00", -- 0x01
+		X"00", -- 0x02
+		X"00", -- 0x03
+		X"01", -- 0x04
+		X"12", -- 0x05
+		X"41", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"48", -- 0x17
+		X"61", -- 0x18
+		X"6C", -- 0x19
+		X"6C", -- 0x1A
+		X"6F", -- 0x1B
+		X"0D", -- 0x1C
+		X"0A", -- 0x1D
+		X"00", -- 0x1E
+		X"4A", -- 0x1F
+		X"65", -- 0x20
+		X"6E", -- 0x21
+		X"73", -- 0x22
+		X"00", -- 0x23
+		X"57", -- 0x24
+		X"65", -- 0x25
+		X"6C", -- 0x26
+		X"63", -- 0x27
+		X"6F", -- 0x28
+		X"6D", -- 0x29
+		X"65", -- 0x2A
+		X"20", -- 0x2B
+		X"74", -- 0x2C
+		X"6F", -- 0x2D
+		X"20", -- 0x2E
+		X"4A", -- 0x2F
+		X"41", -- 0x30
+		X"53", -- 0x31
+		X"4D", -- 0x32
+		X"20", -- 0x33
+		X"43", -- 0x34
+		X"50", -- 0x35
+		X"55", -- 0x36
+		X"00", -- 0x37
+		X"52", -- 0x38
+		X"65", -- 0x39
+		X"61", -- 0x3A
+		X"64", -- 0x3B
+		X"79", -- 0x3C
+		X"00", -- 0x3D
+		X"54", -- 0x3E
+		X"65", -- 0x3F
+		X"73", -- 0x40
+		X"74", -- 0x41
+		X"69", -- 0x42
+		X"6E", -- 0x43
+		X"67", -- 0x44
+		X"00", -- 0x45
+		X"50", -- 0x46
+		X"61", -- 0x47
+		X"73", -- 0x48
+		X"73", -- 0x49
+		X"65", -- 0x4A
+		X"64", -- 0x4B
+		X"00", -- 0x4C
+		X"45", -- 0x4D
+		X"72", -- 0x4E
+		X"72", -- 0x4F
+		X"6F", -- 0x50
+		X"72", -- 0x51
+		X"00", -- 0x52
+		X"0D", -- 0x53
+		X"0A", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: dmem_addr_t;
+	signal jtag_ld_dout		: dmem_data_t;
+	signal jtag_ld_din		: dmem_data_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (15 downto 0);
+	constant id : unsigned (15 downto 0) := X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
+	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;
diff --git a/lib/CPUs/JCpu/src/itest_irom.vhdl b/lib/CPUs/JCpu/src/itest_irom.vhdl
new file mode 100644
index 0000000..94609a3
--- /dev/null
+++ b/lib/CPUs/JCpu/src/itest_irom.vhdl
@@ -0,0 +1,1089 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.types_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY irom IS
+	Generic 
+	(
+		depth 	: integer := 4
+	);
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  addr_t;
+	dout		: out word_t
+	);
+END irom;
+
+ARCHITECTURE itest OF irom IS 
+
+	type imem_rom_t is array (0 to depth-1) of word_t;
+
+	-- Assembled from itest.jsm
+	constant imem_rom : imem_rom_t :=
+	(
+		"110000" & X"010", -- 0x000: JMP 0x010
+		"110000" & X"288", -- 0x001: JMP 0x288
+		"000000" & X"000", -- 0x002:
+		"000000" & X"000", -- 0x003:
+		"000000" & X"000", -- 0x004:
+		"000000" & X"000", -- 0x005:
+		"000000" & X"000", -- 0x006:
+		"000000" & X"000", -- 0x007:
+		"000000" & X"000", -- 0x008:
+		"000000" & X"000", -- 0x009:
+		"000000" & X"000", -- 0x00A:
+		"000000" & X"000", -- 0x00B:
+		"000000" & X"000", -- 0x00C:
+		"000000" & X"000", -- 0x00D:
+		"000000" & X"000", -- 0x00E:
+		"000000" & X"000", -- 0x00F:
+		"111011" & X"03B", -- 0x010: CALL 0x03B
+		"101001" & X"000", -- 0x011: CIN R00, (0x00)
+		"100100" & X"000", -- 0x012: XOUT (0x00), R00
+		"111011" & X"04C", -- 0x013: CALL 0x04C
+		"000011" & X"010", -- 0x014: MOV R00, 0x01
+		"100100" & X"010", -- 0x015: XOUT (0x01), R00
+		"111011" & X"08D", -- 0x016: CALL 0x08D
+		"000011" & X"020", -- 0x017: MOV R00, 0x02
+		"100100" & X"010", -- 0x018: XOUT (0x01), R00
+		"111011" & X"0C9", -- 0x019: CALL 0x0C9
+		"000011" & X"030", -- 0x01A: MOV R00, 0x03
+		"100100" & X"010", -- 0x01B: XOUT (0x01), R00
+		"111011" & X"0DB", -- 0x01C: CALL 0x0DB
+		"000011" & X"040", -- 0x01D: MOV R00, 0x04
+		"100100" & X"010", -- 0x01E: XOUT (0x01), R00
+		"111011" & X"0ED", -- 0x01F: CALL 0x0ED
+		"000011" & X"050", -- 0x020: MOV R00, 0x05
+		"100100" & X"010", -- 0x021: XOUT (0x01), R00
+		"111011" & X"0FF", -- 0x022: CALL 0x0FF
+		"000011" & X"060", -- 0x023: MOV R00, 0x06
+		"100100" & X"010", -- 0x024: XOUT (0x01), R00
+		"111011" & X"115", -- 0x025: CALL 0x115
+		"000011" & X"070", -- 0x026: MOV R00, 0x07
+		"100100" & X"010", -- 0x027: XOUT (0x01), R00
+		"111011" & X"12B", -- 0x028: CALL 0x12B
+		"000011" & X"080", -- 0x029: MOV R00, 0x08
+		"100100" & X"010", -- 0x02A: XOUT (0x01), R00
+		"111011" & X"137", -- 0x02B: CALL 0x137
+		"000011" & X"090", -- 0x02C: MOV R00, 0x09
+		"100100" & X"010", -- 0x02D: XOUT (0x01), R00
+		"111011" & X"15A", -- 0x02E: CALL 0x15A
+		"000011" & X"0A0", -- 0x02F: MOV R00, 0x0A
+		"100100" & X"010", -- 0x030: XOUT (0x01), R00
+		"111011" & X"22A", -- 0x031: CALL 0x22A
+		"000011" & X"0B0", -- 0x032: MOV R00, 0x0B
+		"100100" & X"010", -- 0x033: XOUT (0x01), R00
+		"111011" & X"24D", -- 0x034: CALL 0x24D
+		"000011" & X"0C0", -- 0x035: MOV R00, 0x0C
+		"100100" & X"010", -- 0x036: XOUT (0x01), R00
+		"111011" & X"278", -- 0x037: CALL 0x278
+		"000011" & X"FF0", -- 0x038: MOV R00, 0xFF
+		"100100" & X"010", -- 0x039: XOUT (0x01), R00
+		"110000" & X"2FF", -- 0x03A: JMP 0x2FF
+		"000011" & X"000", -- 0x03B: MOV R00, 0x00
+		"000011" & X"001", -- 0x03C: MOV R01, 0x00
+		"000011" & X"002", -- 0x03D: MOV R02, 0x00
+		"000011" & X"003", -- 0x03E: MOV R03, 0x00
+		"000011" & X"004", -- 0x03F: MOV R04, 0x00
+		"000011" & X"005", -- 0x040: MOV R05, 0x00
+		"000011" & X"006", -- 0x041: MOV R06, 0x00
+		"000011" & X"007", -- 0x042: MOV R07, 0x00
+		"000011" & X"008", -- 0x043: MOV R08, 0x00
+		"000011" & X"009", -- 0x044: MOV R09, 0x00
+		"000011" & X"00A", -- 0x045: MOV R10, 0x00
+		"000011" & X"00B", -- 0x046: MOV R11, 0x00
+		"000011" & X"00C", -- 0x047: MOV R12, 0x00
+		"000011" & X"00D", -- 0x048: MOV R13, 0x00
+		"000011" & X"00E", -- 0x049: MOV R14, 0x00
+		"000011" & X"00F", -- 0x04A: MOV R15, 0x00
+		"111110" & X"000", -- 0x04B: RET
+		"000011" & X"100", -- 0x04C: MOV R00, 0x10
+		"001111" & X"100", -- 0x04D: CMP R00, 0x10
+		"111010" & X"3FF", -- 0x04E: JNE 0x3FF
+		"010001" & X"010", -- 0x04F: ADD R00, 0x01
+		"000010" & X"001", -- 0x050: MOV R01, R00
+		"001111" & X"111", -- 0x051: CMP R01, 0x11
+		"111010" & X"3FF", -- 0x052: JNE 0x3FF
+		"010001" & X"011", -- 0x053: ADD R01, 0x01
+		"000010" & X"012", -- 0x054: MOV R02, R01
+		"001111" & X"122", -- 0x055: CMP R02, 0x12
+		"111010" & X"3FF", -- 0x056: JNE 0x3FF
+		"010001" & X"012", -- 0x057: ADD R02, 0x01
+		"000010" & X"023", -- 0x058: MOV R03, R02
+		"001111" & X"133", -- 0x059: CMP R03, 0x13
+		"111010" & X"3FF", -- 0x05A: JNE 0x3FF
+		"010001" & X"013", -- 0x05B: ADD R03, 0x01
+		"000010" & X"034", -- 0x05C: MOV R04, R03
+		"001111" & X"144", -- 0x05D: CMP R04, 0x14
+		"111010" & X"3FF", -- 0x05E: JNE 0x3FF
+		"010001" & X"014", -- 0x05F: ADD R04, 0x01
+		"000010" & X"045", -- 0x060: MOV R05, R04
+		"001111" & X"155", -- 0x061: CMP R05, 0x15
+		"111010" & X"3FF", -- 0x062: JNE 0x3FF
+		"010001" & X"015", -- 0x063: ADD R05, 0x01
+		"000010" & X"056", -- 0x064: MOV R06, R05
+		"001111" & X"166", -- 0x065: CMP R06, 0x16
+		"111010" & X"3FF", -- 0x066: JNE 0x3FF
+		"010001" & X"016", -- 0x067: ADD R06, 0x01
+		"000010" & X"067", -- 0x068: MOV R07, R06
+		"001111" & X"177", -- 0x069: CMP R07, 0x17
+		"111010" & X"3FF", -- 0x06A: JNE 0x3FF
+		"010001" & X"017", -- 0x06B: ADD R07, 0x01
+		"000010" & X"078", -- 0x06C: MOV R08, R07
+		"001111" & X"188", -- 0x06D: CMP R08, 0x18
+		"111010" & X"3FF", -- 0x06E: JNE 0x3FF
+		"010001" & X"018", -- 0x06F: ADD R08, 0x01
+		"000010" & X"089", -- 0x070: MOV R09, R08
+		"001111" & X"199", -- 0x071: CMP R09, 0x19
+		"111010" & X"3FF", -- 0x072: JNE 0x3FF
+		"010001" & X"019", -- 0x073: ADD R09, 0x01
+		"000010" & X"09A", -- 0x074: MOV R10, R09
+		"001111" & X"1AA", -- 0x075: CMP R10, 0x1A
+		"111010" & X"3FF", -- 0x076: JNE 0x3FF
+		"010001" & X"01A", -- 0x077: ADD R10, 0x01
+		"000010" & X"0AB", -- 0x078: MOV R11, R10
+		"001111" & X"1BB", -- 0x079: CMP R11, 0x1B
+		"111010" & X"3FF", -- 0x07A: JNE 0x3FF
+		"010001" & X"01B", -- 0x07B: ADD R11, 0x01
+		"000010" & X"0BC", -- 0x07C: MOV R12, R11
+		"001111" & X"1CC", -- 0x07D: CMP R12, 0x1C
+		"111010" & X"3FF", -- 0x07E: JNE 0x3FF
+		"010001" & X"01C", -- 0x07F: ADD R12, 0x01
+		"000010" & X"0CD", -- 0x080: MOV R13, R12
+		"001111" & X"1DD", -- 0x081: CMP R13, 0x1D
+		"111010" & X"3FF", -- 0x082: JNE 0x3FF
+		"010001" & X"01D", -- 0x083: ADD R13, 0x01
+		"000010" & X"0DE", -- 0x084: MOV R14, R13
+		"001111" & X"1EE", -- 0x085: CMP R14, 0x1E
+		"111010" & X"3FF", -- 0x086: JNE 0x3FF
+		"010001" & X"01E", -- 0x087: ADD R14, 0x01
+		"000010" & X"0EF", -- 0x088: MOV R15, R14
+		"001111" & X"1FF", -- 0x089: CMP R15, 0x1F
+		"111010" & X"3FF", -- 0x08A: JNE 0x3FF
+		"010001" & X"01F", -- 0x08B: ADD R15, 0x01
+		"111110" & X"000", -- 0x08C: RET
+		"000011" & X"000", -- 0x08D: MOV R00, 0x00
+		"001111" & X"000", -- 0x08E: TST R00
+		"110010" & X"3FF", -- 0x08F: JNZ 0x3FF
+		"110011" & X"3FF", -- 0x090: JC 0x3FF
+		"001111" & X"000", -- 0x091: CMP R00, 0x00
+		"111010" & X"3FF", -- 0x092: JNE 0x3FF
+		"110101" & X"3FF", -- 0x093: JLT 0x3FF
+		"110110" & X"3FF", -- 0x094: JGT 0x3FF
+		"110111" & X"097", -- 0x095: JLE 0x097
+		"110000" & X"3FF", -- 0x096: JMP 0x3FF
+		"111001" & X"099", -- 0x097: JEQ 0x099
+		"110000" & X"3FF", -- 0x098: JMP 0x3FF
+		"111000" & X"09B", -- 0x099: JGE 0x09B
+		"110000" & X"3FF", -- 0x09A: JMP 0x3FF
+		"001111" & X"550", -- 0x09B: CMP R00, 0x55
+		"111001" & X"3FF", -- 0x09C: JEQ 0x3FF
+		"110101" & X"09F", -- 0x09D: JLT 0x09F
+		"110000" & X"3FF", -- 0x09E: JMP 0x3FF
+		"110111" & X"0A1", -- 0x09F: JLE 0x0A1
+		"110000" & X"3FF", -- 0x0A0: JMP 0x3FF
+		"111000" & X"3FF", -- 0x0A1: JGE 0x3FF
+		"110110" & X"3FF", -- 0x0A2: JGT 0x3FF
+		"000011" & X"550", -- 0x0A3: MOV R00, 0x55
+		"001111" & X"000", -- 0x0A4: TST R00
+		"110001" & X"3FF", -- 0x0A5: JZ 0x3FF
+		"110011" & X"3FF", -- 0x0A6: JC 0x3FF
+		"001111" & X"AA0", -- 0x0A7: CMP R00, 0xAA
+		"111001" & X"3FF", -- 0x0A8: JEQ 0x3FF
+		"111010" & X"0AB", -- 0x0A9: JNE 0x0AB
+		"110000" & X"3FF", -- 0x0AA: JMP 0x3FF
+		"110101" & X"0AD", -- 0x0AB: JLT 0x0AD
+		"110000" & X"3FF", -- 0x0AC: JMP 0x3FF
+		"110111" & X"0AF", -- 0x0AD: JLE 0x0AF
+		"110000" & X"3FF", -- 0x0AE: JMP 0x3FF
+		"110110" & X"3FF", -- 0x0AF: JGT 0x3FF
+		"001111" & X"550", -- 0x0B0: CMP R00, 0x55
+		"111001" & X"0B3", -- 0x0B1: JEQ 0x0B3
+		"110000" & X"3FF", -- 0x0B2: JMP 0x3FF
+		"111010" & X"3FF", -- 0x0B3: JNE 0x3FF
+		"110101" & X"3FF", -- 0x0B4: JLT 0x3FF
+		"110111" & X"0B7", -- 0x0B5: JLE 0x0B7
+		"110000" & X"3FF", -- 0x0B6: JMP 0x3FF
+		"110110" & X"3FF", -- 0x0B7: JGT 0x3FF
+		"111000" & X"0BA", -- 0x0B8: JGE 0x0BA
+		"110000" & X"3FF", -- 0x0B9: JMP 0x3FF
+		"000011" & X"AA0", -- 0x0BA: MOV R00, 0xAA
+		"001111" & X"000", -- 0x0BB: TST R00
+		"110001" & X"3FF", -- 0x0BC: JZ 0x3FF
+		"110011" & X"3FF", -- 0x0BD: JC 0x3FF
+		"001111" & X"550", -- 0x0BE: CMP R00, 0x55
+		"111001" & X"3FF", -- 0x0BF: JEQ 0x3FF
+		"111010" & X"0C2", -- 0x0C0: JNE 0x0C2
+		"110000" & X"3FF", -- 0x0C1: JMP 0x3FF
+		"110110" & X"0C4", -- 0x0C2: JGT 0x0C4
+		"110000" & X"3FF", -- 0x0C3: JMP 0x3FF
+		"111000" & X"0C6", -- 0x0C4: JGE 0x0C6
+		"110000" & X"3FF", -- 0x0C5: JMP 0x3FF
+		"110101" & X"3FF", -- 0x0C6: JLT 0x3FF
+		"110111" & X"3FF", -- 0x0C7: JLE 0x3FF
+		"111110" & X"000", -- 0x0C8: RET
+		"000011" & X"000", -- 0x0C9: MOV R00, 0x00
+		"000011" & X"001", -- 0x0CA: MOV R01, 0x00
+		"000010" & X"002", -- 0x0CB: MOV R02, R00
+		"000010" & X"013", -- 0x0CC: MOV R03, R01
+		"010001" & X"010", -- 0x0CD: ADD R00, 0x01
+		"010011" & X"001", -- 0x0CE: ADDC R01, 0x00
+		"010001" & X"012", -- 0x0CF: ADD R02, 0x01
+		"001111" & X"002", -- 0x0D0: CMP R02, 0x00
+		"111010" & X"0D4", -- 0x0D1: JNE 0x0D4
+		"010001" & X"013", -- 0x0D2: ADD R03, 0x01
+		"001111" & X"023", -- 0x0D3: CMP R03, 0x02
+		"111010" & X"0CD", -- 0x0D4: JNE 0x0CD
+		"001110" & X"020", -- 0x0D5: CMP R00, R02
+		"111010" & X"3FF", -- 0x0D6: JNE 0x3FF
+		"001110" & X"031", -- 0x0D7: CMP R01, R03
+		"111010" & X"3FF", -- 0x0D8: JNE 0x3FF
+		"000011" & X"000", -- 0x0D9: MOV R00, 0x00
+		"111110" & X"000", -- 0x0DA: RET
+		"000011" & X"000", -- 0x0DB: MOV R00, 0x00
+		"000011" & X"031", -- 0x0DC: MOV R01, 0x03
+		"000010" & X"002", -- 0x0DD: MOV R02, R00
+		"000010" & X"013", -- 0x0DE: MOV R03, R01
+		"010101" & X"010", -- 0x0DF: SUB R00, 0x01
+		"010111" & X"001", -- 0x0E0: SUBC R01, 0x00
+		"010101" & X"012", -- 0x0E1: SUB R02, 0x01
+		"001111" & X"FF2", -- 0x0E2: CMP R02, 0xFF
+		"111010" & X"0E6", -- 0x0E3: JNE 0x0E6
+		"010101" & X"013", -- 0x0E4: SUB R03, 0x01
+		"001111" & X"003", -- 0x0E5: CMP R03, 0x00
+		"111010" & X"0DF", -- 0x0E6: JNE 0x0DF
+		"001110" & X"020", -- 0x0E7: CMP R00, R02
+		"111010" & X"3FF", -- 0x0E8: JNE 0x3FF
+		"001110" & X"031", -- 0x0E9: CMP R01, R03
+		"111010" & X"3FF", -- 0x0EA: JNE 0x3FF
+		"000011" & X"000", -- 0x0EB: MOV R00, 0x00
+		"111110" & X"000", -- 0x0EC: RET
+		"000011" & X"030", -- 0x0ED: MOV R00, 0x03
+		"000011" & X"051", -- 0x0EE: MOV R01, 0x05
+		"101110" & X"050", -- 0x0EF: SUB 0x05, R00
+		"010101" & X"031", -- 0x0F0: SUB R01, 0x03
+		"001110" & X"010", -- 0x0F1: CMP R00, R01
+		"111010" & X"3FF", -- 0x0F2: JNE 0x3FF
+		"000011" & X"030", -- 0x0F3: MOV R00, 0x03
+		"000011" & X"051", -- 0x0F4: MOV R01, 0x05
+		"010100" & X"010", -- 0x0F5: SUB R00, R01
+		"101111" & X"000", -- 0x0F6: SUBC 0x00, R00
+		"001111" & X"010", -- 0x0F7: CMP R00, 0x01
+		"111010" & X"3FF", -- 0x0F8: JNE 0x3FF
+		"010001" & X"000", -- 0x0F9: ADD R00, 0x00
+		"010110" & X"001", -- 0x0FA: SUBC R01, R00
+		"001111" & X"041", -- 0x0FB: CMP R01, 0x04
+		"111010" & X"3FF", -- 0x0FC: JNE 0x3FF
+		"000011" & X"000", -- 0x0FD: MOV R00, 0x00
+		"111110" & X"000", -- 0x0FE: RET
+		"000011" & X"010", -- 0x0FF: MOV R00, 0x01
+		"001101" & X"5A0", -- 0x100: MOVC (0x5A), R00
+		"010101" & X"010", -- 0x101: DEC R00
+		"001101" & X"000", -- 0x102: MOVC (0x00), R00
+		"001010" & X"5A1", -- 0x103: MOVC R01, (0x5A)
+		"001100" & X"A51", -- 0x104: MOVC (R01), 0xA5
+		"001001" & X"010", -- 0x105: MOVC R00, (R01)
+		"001001" & X"011", -- 0x106: MOVC R01, (R01)
+		"010001" & X"5A1", -- 0x107: ADD R01, 0x5A
+		"001001" & X"010", -- 0x108: MOVC R00, (R01)
+		"001011" & X"000", -- 0x109: MOVC (R00), R00
+		"001001" & X"002", -- 0x10A: MOVC R02, (R00)
+		"001110" & X"002", -- 0x10B: CMP R02, R00
+		"111010" & X"3FF", -- 0x10C: JNE 0x3FF
+		"001011" & X"021", -- 0x10D: MOVC (R01), R02
+		"001001" & X"022", -- 0x10E: MOVC R02, (R02)
+		"001110" & X"012", -- 0x10F: CMP R02, R01
+		"111010" & X"3FF", -- 0x110: JNE 0x3FF
+		"010101" & X"011", -- 0x111: DEC R01
+		"010001" & X"010", -- 0x112: INC R00
+		"110010" & X"109", -- 0x113: JNZ 0x109
+		"111110" & X"000", -- 0x114: RET
+		"000011" & X"010", -- 0x115: MOV R00, 0x01
+		"001000" & X"600", -- 0x116: MOVX (0x60), R00
+		"010101" & X"010", -- 0x117: DEC R00
+		"001000" & X"060", -- 0x118: MOVX (0x06), R00
+		"000101" & X"601", -- 0x119: MOVX R01, (0x60)
+		"000111" & X"A51", -- 0x11A: MOVX (R01), 0xA5
+		"000100" & X"010", -- 0x11B: MOVX R00, (R01)
+		"000100" & X"011", -- 0x11C: MOVX R01, (R01)
+		"010001" & X"5A1", -- 0x11D: ADD R01, 0x5A
+		"000100" & X"010", -- 0x11E: MOVX R00, (R01)
+		"000110" & X"000", -- 0x11F: MOVX (R00), R00
+		"000100" & X"002", -- 0x120: MOVX R02, (R00)
+		"001110" & X"002", -- 0x121: CMP R02, R00
+		"111010" & X"3FF", -- 0x122: JNE 0x3FF
+		"000110" & X"021", -- 0x123: MOVX (R01), R02
+		"000100" & X"022", -- 0x124: MOVX R02, (R02)
+		"001110" & X"012", -- 0x125: CMP R02, R01
+		"111010" & X"3FF", -- 0x126: JNE 0x3FF
+		"010101" & X"011", -- 0x127: DEC R01
+		"010001" & X"010", -- 0x128: INC R00
+		"110010" & X"11F", -- 0x129: JNZ 0x11F
+		"111110" & X"000", -- 0x12A: RET
+		"000011" & X"AA0", -- 0x12B: MOV R00, 0xAA
+		"000011" & X"001", -- 0x12C: MOV R01, 0x00
+		"111100" & X"000", -- 0x12D: PUSH R00
+		"010001" & X"010", -- 0x12E: INC R00
+		"010101" & X"011", -- 0x12F: DEC R01
+		"110010" & X"12D", -- 0x130: JNZ 0x12D
+		"111101" & X"000", -- 0x131: POP R00
+		"010101" & X"011", -- 0x132: DEC R01
+		"110010" & X"131", -- 0x133: JNZ 0x131
+		"001111" & X"AA0", -- 0x134: CMP R00, 0xAA
+		"111010" & X"3FF", -- 0x135: JNE 0x3FF
+		"111110" & X"000", -- 0x136: RET
+		"000011" & X"550", -- 0x137: MOV R00, 0x55
+		"111100" & X"000", -- 0x138: PUSH R00
+		"000011" & X"000", -- 0x139: MOV R00, 0x00
+		"000011" & X"FF1", -- 0x13A: MOV R01, 0xFF
+		"111011" & X"151", -- 0x13B: CALL 0x151
+		"111101" & X"000", -- 0x13C: POP R00
+		"001111" & X"550", -- 0x13D: CMP R00, 0x55
+		"111010" & X"3FF", -- 0x13E: JNE 0x3FF
+		"000011" & X"010", -- 0x13F: MOV R00, 0x01
+		"000011" & X"481", -- 0x140: MOV R01, 0x48
+		"100110" & X"050", -- 0x141: COUT (0x05), R00
+		"111100" & X"001", -- 0x142: PUSH R01
+		"000011" & X"000", -- 0x143: MOV R00, 0x00
+		"000011" & X"3B1", -- 0x144: MOV R01, 0x3B
+		"100110" & X"050", -- 0x145: COUT (0x05), R00
+		"111100" & X"001", -- 0x146: PUSH R01
+		"111110" & X"000", -- 0x147: RET
+		"000011" & X"010", -- 0x148: MOV R00, 0x01
+		"000011" & X"501", -- 0x149: MOV R01, 0x50
+		"100110" & X"050", -- 0x14A: COUT (0x05), R00
+		"111100" & X"001", -- 0x14B: PUSH R01
+		"000011" & X"000", -- 0x14C: MOV R00, 0x00
+		"000011" & X"3B1", -- 0x14D: MOV R01, 0x3B
+		"100110" & X"050", -- 0x14E: COUT (0x05), R00
+		"111100" & X"001", -- 0x14F: PUSH R01
+		"111110" & X"000", -- 0x150: RET
+		"001110" & X"010", -- 0x151: CMP R00, R01
+		"111001" & X"155", -- 0x152: JEQ 0x155
+		"010001" & X"010", -- 0x153: INC R00
+		"110000" & X"158", -- 0x154: JMP 0x158
+		"010101" & X"010", -- 0x155: DEC R00
+		"010101" & X"011", -- 0x156: DEC R01
+		"111110" & X"000", -- 0x157: RET
+		"111011" & X"151", -- 0x158: CALL 0x151
+		"110000" & X"155", -- 0x159: JMP 0x155
+		"000011" & X"A50", -- 0x15A: MOV R00, 0xA5
+		"000011" & X"5A1", -- 0x15B: MOV R01, 0x5A
+		"101010" & X"000", -- 0x15C: SWAP R00
+		"001111" & X"5A0", -- 0x15D: CMP R00, 0x5A
+		"111010" & X"3FF", -- 0x15E: JNE 0x3FF
+		"101010" & X"000", -- 0x15F: SWAP R00
+		"001111" & X"A50", -- 0x160: CMP R00, 0xA5
+		"111010" & X"3FF", -- 0x161: JNE 0x3FF
+		"000011" & X"D20", -- 0x162: MOV R00, 0xD2
+		"101010" & X"000", -- 0x163: SWAP R00
+		"001111" & X"2D0", -- 0x164: CMP R00, 0x2D
+		"111010" & X"3FF", -- 0x165: JNE 0x3FF
+		"101010" & X"001", -- 0x166: SWAP R01
+		"001111" & X"2D0", -- 0x167: CMP R00, 0x2D
+		"111010" & X"3FF", -- 0x168: JNE 0x3FF
+		"001111" & X"A51", -- 0x169: CMP R01, 0xA5
+		"111010" & X"3FF", -- 0x16A: JNE 0x3FF
+		"000011" & X"2D0", -- 0x16B: MOV R00, 0x2D
+		"011110" & X"000", -- 0x16C: SHL R00
+		"001111" & X"5A0", -- 0x16D: CMP R00, 0x5A
+		"111010" & X"3FF", -- 0x16E: JNE 0x3FF
+		"011110" & X"000", -- 0x16F: SHL R00
+		"001111" & X"B40", -- 0x170: CMP R00, 0xB4
+		"111010" & X"3FF", -- 0x171: JNE 0x3FF
+		"011110" & X"000", -- 0x172: SHL R00
+		"001111" & X"680", -- 0x173: CMP R00, 0x68
+		"111010" & X"3FF", -- 0x174: JNE 0x3FF
+		"011110" & X"000", -- 0x175: SHL R00
+		"001111" & X"D00", -- 0x176: CMP R00, 0xD0
+		"111010" & X"3FF", -- 0x177: JNE 0x3FF
+		"011110" & X"000", -- 0x178: SHL R00
+		"001111" & X"A00", -- 0x179: CMP R00, 0xA0
+		"111010" & X"3FF", -- 0x17A: JNE 0x3FF
+		"011110" & X"000", -- 0x17B: SHL R00
+		"001111" & X"400", -- 0x17C: CMP R00, 0x40
+		"111010" & X"3FF", -- 0x17D: JNE 0x3FF
+		"011110" & X"000", -- 0x17E: SHL R00
+		"001111" & X"800", -- 0x17F: CMP R00, 0x80
+		"111010" & X"3FF", -- 0x180: JNE 0x3FF
+		"011110" & X"000", -- 0x181: SHL R00
+		"001111" & X"000", -- 0x182: CMP R00, 0x00
+		"111010" & X"3FF", -- 0x183: JNE 0x3FF
+		"000011" & X"841", -- 0x184: MOV R01, 0x84
+		"011111" & X"001", -- 0x185: SHR R01
+		"001111" & X"421", -- 0x186: CMP R01, 0x42
+		"111010" & X"3FF", -- 0x187: JNE 0x3FF
+		"011111" & X"001", -- 0x188: SHR R01
+		"001111" & X"211", -- 0x189: CMP R01, 0x21
+		"111010" & X"3FF", -- 0x18A: JNE 0x3FF
+		"011111" & X"001", -- 0x18B: SHR R01
+		"001111" & X"101", -- 0x18C: CMP R01, 0x10
+		"111010" & X"3FF", -- 0x18D: JNE 0x3FF
+		"011111" & X"001", -- 0x18E: SHR R01
+		"001111" & X"081", -- 0x18F: CMP R01, 0x08
+		"111010" & X"3FF", -- 0x190: JNE 0x3FF
+		"011111" & X"001", -- 0x191: SHR R01
+		"001111" & X"041", -- 0x192: CMP R01, 0x04
+		"111010" & X"3FF", -- 0x193: JNE 0x3FF
+		"011111" & X"001", -- 0x194: SHR R01
+		"001111" & X"021", -- 0x195: CMP R01, 0x02
+		"111010" & X"3FF", -- 0x196: JNE 0x3FF
+		"011111" & X"001", -- 0x197: SHR R01
+		"001111" & X"011", -- 0x198: CMP R01, 0x01
+		"111010" & X"3FF", -- 0x199: JNE 0x3FF
+		"011111" & X"001", -- 0x19A: SHR R01
+		"001111" & X"001", -- 0x19B: CMP R01, 0x00
+		"111010" & X"3FF", -- 0x19C: JNE 0x3FF
+		"000011" & X"C50", -- 0x19D: MOV R00, 0xC5
+		"100000" & X"000", -- 0x19E: ROL R00
+		"001111" & X"8B0", -- 0x19F: CMP R00, 0x8B
+		"111010" & X"3FF", -- 0x1A0: JNE 0x3FF
+		"100000" & X"000", -- 0x1A1: ROL R00
+		"001111" & X"170", -- 0x1A2: CMP R00, 0x17
+		"111010" & X"3FF", -- 0x1A3: JNE 0x3FF
+		"100000" & X"000", -- 0x1A4: ROL R00
+		"001111" & X"2E0", -- 0x1A5: CMP R00, 0x2E
+		"111010" & X"3FF", -- 0x1A6: JNE 0x3FF
+		"100000" & X"000", -- 0x1A7: ROL R00
+		"001111" & X"5C0", -- 0x1A8: CMP R00, 0x5C
+		"111010" & X"3FF", -- 0x1A9: JNE 0x3FF
+		"100000" & X"000", -- 0x1AA: ROL R00
+		"001111" & X"B80", -- 0x1AB: CMP R00, 0xB8
+		"111010" & X"3FF", -- 0x1AC: JNE 0x3FF
+		"100000" & X"000", -- 0x1AD: ROL R00
+		"001111" & X"710", -- 0x1AE: CMP R00, 0x71
+		"111010" & X"3FF", -- 0x1AF: JNE 0x3FF
+		"100000" & X"000", -- 0x1B0: ROL R00
+		"001111" & X"E20", -- 0x1B1: CMP R00, 0xE2
+		"111010" & X"3FF", -- 0x1B2: JNE 0x3FF
+		"100000" & X"000", -- 0x1B3: ROL R00
+		"001111" & X"C50", -- 0x1B4: CMP R00, 0xC5
+		"111010" & X"3FF", -- 0x1B5: JNE 0x3FF
+		"000011" & X"631", -- 0x1B6: MOV R01, 0x63
+		"100001" & X"001", -- 0x1B7: ROR R01
+		"001111" & X"B11", -- 0x1B8: CMP R01, 0xB1
+		"111010" & X"3FF", -- 0x1B9: JNE 0x3FF
+		"100001" & X"001", -- 0x1BA: ROR R01
+		"001111" & X"D81", -- 0x1BB: CMP R01, 0xD8
+		"111010" & X"3FF", -- 0x1BC: JNE 0x3FF
+		"100001" & X"001", -- 0x1BD: ROR R01
+		"001111" & X"6C1", -- 0x1BE: CMP R01, 0x6C
+		"111010" & X"3FF", -- 0x1BF: JNE 0x3FF
+		"100001" & X"001", -- 0x1C0: ROR R01
+		"001111" & X"361", -- 0x1C1: CMP R01, 0x36
+		"111010" & X"3FF", -- 0x1C2: JNE 0x3FF
+		"100001" & X"001", -- 0x1C3: ROR R01
+		"001111" & X"1B1", -- 0x1C4: CMP R01, 0x1B
+		"111010" & X"3FF", -- 0x1C5: JNE 0x3FF
+		"100001" & X"001", -- 0x1C6: ROR R01
+		"001111" & X"8D1", -- 0x1C7: CMP R01, 0x8D
+		"111010" & X"3FF", -- 0x1C8: JNE 0x3FF
+		"100001" & X"001", -- 0x1C9: ROR R01
+		"001111" & X"C61", -- 0x1CA: CMP R01, 0xC6
+		"111010" & X"3FF", -- 0x1CB: JNE 0x3FF
+		"100001" & X"001", -- 0x1CC: ROR R01
+		"001111" & X"631", -- 0x1CD: CMP R01, 0x63
+		"111010" & X"3FF", -- 0x1CE: JNE 0x3FF
+		"011100" & X"000", -- 0x1CF: XOR R00, R00
+		"000011" & X"C50", -- 0x1D0: MOV R00, 0xC5
+		"100010" & X"000", -- 0x1D1: ROLC R00
+		"111100" & X"000", -- 0x1D2: PUSH R00
+		"100010" & X"000", -- 0x1D3: ROLC R00
+		"111100" & X"000", -- 0x1D4: PUSH R00
+		"100010" & X"000", -- 0x1D5: ROLC R00
+		"111100" & X"000", -- 0x1D6: PUSH R00
+		"100010" & X"000", -- 0x1D7: ROLC R00
+		"111100" & X"000", -- 0x1D8: PUSH R00
+		"100010" & X"000", -- 0x1D9: ROLC R00
+		"111100" & X"000", -- 0x1DA: PUSH R00
+		"100010" & X"000", -- 0x1DB: ROLC R00
+		"111100" & X"000", -- 0x1DC: PUSH R00
+		"100010" & X"000", -- 0x1DD: ROLC R00
+		"111100" & X"000", -- 0x1DE: PUSH R00
+		"100010" & X"000", -- 0x1DF: ROLC R00
+		"111100" & X"000", -- 0x1E0: PUSH R00
+		"100010" & X"000", -- 0x1E1: ROLC R00
+		"001111" & X"C50", -- 0x1E2: CMP R00, 0xC5
+		"111010" & X"3FF", -- 0x1E3: JNE 0x3FF
+		"111101" & X"000", -- 0x1E4: POP R00
+		"001111" & X"620", -- 0x1E5: CMP R00, 0x62
+		"111010" & X"3FF", -- 0x1E6: JNE 0x3FF
+		"111101" & X"000", -- 0x1E7: POP R00
+		"001111" & X"B10", -- 0x1E8: CMP R00, 0xB1
+		"111010" & X"3FF", -- 0x1E9: JNE 0x3FF
+		"111101" & X"000", -- 0x1EA: POP R00
+		"001111" & X"580", -- 0x1EB: CMP R00, 0x58
+		"111010" & X"3FF", -- 0x1EC: JNE 0x3FF
+		"111101" & X"000", -- 0x1ED: POP R00
+		"001111" & X"AC0", -- 0x1EE: CMP R00, 0xAC
+		"111010" & X"3FF", -- 0x1EF: JNE 0x3FF
+		"111101" & X"000", -- 0x1F0: POP R00
+		"001111" & X"560", -- 0x1F1: CMP R00, 0x56
+		"111010" & X"3FF", -- 0x1F2: JNE 0x3FF
+		"111101" & X"000", -- 0x1F3: POP R00
+		"001111" & X"2B0", -- 0x1F4: CMP R00, 0x2B
+		"111010" & X"3FF", -- 0x1F5: JNE 0x3FF
+		"111101" & X"000", -- 0x1F6: POP R00
+		"001111" & X"150", -- 0x1F7: CMP R00, 0x15
+		"111010" & X"3FF", -- 0x1F8: JNE 0x3FF
+		"111101" & X"000", -- 0x1F9: POP R00
+		"001111" & X"8A0", -- 0x1FA: CMP R00, 0x8A
+		"111010" & X"3FF", -- 0x1FB: JNE 0x3FF
+		"011100" & X"011", -- 0x1FC: XOR R01, R01
+		"000011" & X"631", -- 0x1FD: MOV R01, 0x63
+		"100011" & X"001", -- 0x1FE: RORC R01
+		"111100" & X"001", -- 0x1FF: PUSH R01
+		"100011" & X"001", -- 0x200: RORC R01
+		"111100" & X"001", -- 0x201: PUSH R01
+		"100011" & X"001", -- 0x202: RORC R01
+		"111100" & X"001", -- 0x203: PUSH R01
+		"100011" & X"001", -- 0x204: RORC R01
+		"111100" & X"001", -- 0x205: PUSH R01
+		"100011" & X"001", -- 0x206: RORC R01
+		"111100" & X"001", -- 0x207: PUSH R01
+		"100011" & X"001", -- 0x208: RORC R01
+		"111100" & X"001", -- 0x209: PUSH R01
+		"100011" & X"001", -- 0x20A: RORC R01
+		"111100" & X"001", -- 0x20B: PUSH R01
+		"100011" & X"001", -- 0x20C: RORC R01
+		"111100" & X"001", -- 0x20D: PUSH R01
+		"100011" & X"001", -- 0x20E: RORC R01
+		"001111" & X"631", -- 0x20F: CMP R01, 0x63
+		"111010" & X"3FF", -- 0x210: JNE 0x3FF
+		"111101" & X"001", -- 0x211: POP R01
+		"001111" & X"C61", -- 0x212: CMP R01, 0xC6
+		"111010" & X"3FF", -- 0x213: JNE 0x3FF
+		"111101" & X"001", -- 0x214: POP R01
+		"001111" & X"8C1", -- 0x215: CMP R01, 0x8C
+		"111010" & X"3FF", -- 0x216: JNE 0x3FF
+		"111101" & X"001", -- 0x217: POP R01
+		"001111" & X"191", -- 0x218: CMP R01, 0x19
+		"111010" & X"3FF", -- 0x219: JNE 0x3FF
+		"111101" & X"001", -- 0x21A: POP R01
+		"001111" & X"331", -- 0x21B: CMP R01, 0x33
+		"111010" & X"3FF", -- 0x21C: JNE 0x3FF
+		"111101" & X"001", -- 0x21D: POP R01
+		"001111" & X"661", -- 0x21E: CMP R01, 0x66
+		"111010" & X"3FF", -- 0x21F: JNE 0x3FF
+		"111101" & X"001", -- 0x220: POP R01
+		"001111" & X"CC1", -- 0x221: CMP R01, 0xCC
+		"111010" & X"3FF", -- 0x222: JNE 0x3FF
+		"111101" & X"001", -- 0x223: POP R01
+		"001111" & X"981", -- 0x224: CMP R01, 0x98
+		"111010" & X"3FF", -- 0x225: JNE 0x3FF
+		"111101" & X"001", -- 0x226: POP R01
+		"001111" & X"311", -- 0x227: CMP R01, 0x31
+		"111010" & X"3FF", -- 0x228: JNE 0x3FF
+		"111110" & X"000", -- 0x229: RET
+		"000011" & X"A50", -- 0x22A: MOV R00, 0xA5
+		"101010" & X"000", -- 0x22B: SWAP R00
+		"111100" & X"000", -- 0x22C: PUSH R00
+		"011001" & X"0F0", -- 0x22D: AND R00, 0x0F
+		"001111" & X"0A0", -- 0x22E: CMP R00, 0x0A
+		"111010" & X"3FF", -- 0x22F: JNE 0x3FF
+		"111101" & X"000", -- 0x230: POP R00
+		"111100" & X"000", -- 0x231: PUSH R00
+		"011001" & X"0F0", -- 0x232: AND R00, 0x0F
+		"001111" & X"0A0", -- 0x233: CMP R00, 0x0A
+		"111101" & X"001", -- 0x234: POP R01
+		"111010" & X"3FF", -- 0x235: JNE 0x3FF
+		"101010" & X"001", -- 0x236: SWAP R01
+		"000011" & X"0F2", -- 0x237: MOV R02, 0x0F
+		"011000" & X"021", -- 0x238: AND R01, R02
+		"001111" & X"051", -- 0x239: CMP R01, 0x05
+		"111010" & X"3FF", -- 0x23A: JNE 0x3FF
+		"000011" & X"050", -- 0x23B: MOV R00, 0x05
+		"000011" & X"A02", -- 0x23C: MOV R02, 0xA0
+		"101010" & X"000", -- 0x23D: SWAP R00
+		"011010" & X"002", -- 0x23E: OR R02, R00
+		"001111" & X"F02", -- 0x23F: CMP R02, 0xF0
+		"111010" & X"3FF", -- 0x240: JNE 0x3FF
+		"101010" & X"000", -- 0x241: SWAP R00
+		"011011" & X"500", -- 0x242: OR R00, 0x50
+		"001111" & X"550", -- 0x243: CMP R00, 0x55
+		"111010" & X"3FF", -- 0x244: JNE 0x3FF
+		"000011" & X"011", -- 0x245: MOV R01, 0x01
+		"000011" & X"010", -- 0x246: MOV R00, 0x01
+		"011101" & X"010", -- 0x247: XOR R00, 0x01
+		"110010" & X"3FF", -- 0x248: JNZ 0x3FF
+		"011100" & X"010", -- 0x249: XOR R00, R01
+		"001111" & X"010", -- 0x24A: CMP R00, 0x01
+		"111010" & X"3FF", -- 0x24B: JNE 0x3FF
+		"111110" & X"000", -- 0x24C: RET
+		"000011" & X"030", -- 0x24D: MOV R00, 0x03
+		"100110" & X"030", -- 0x24E: COUT (0x03), R00
+		"101000" & X"020", -- 0x24F: XIN R00, (0x02)
+		"011011" & X"010", -- 0x250: OR R00, 0x01
+		"100100" & X"020", -- 0x251: XOUT (0x02), R00
+		"000000" & X"000", -- 0x252: NOP
+		"000000" & X"000", -- 0x253: NOP
+		"000000" & X"000", -- 0x254: NOP
+		"000000" & X"000", -- 0x255: NOP
+		"000000" & X"000", -- 0x256: NOP
+		"000000" & X"000", -- 0x257: NOP
+		"101000" & X"020", -- 0x258: XIN R00, (0x02)
+		"011001" & X"FE0", -- 0x259: AND R00, 0xFE
+		"100100" & X"020", -- 0x25A: XOUT (0x02), R00
+		"000000" & X"000", -- 0x25B: NOP
+		"000000" & X"000", -- 0x25C: NOP
+		"000000" & X"000", -- 0x25D: NOP
+		"000000" & X"000", -- 0x25E: NOP
+		"101001" & X"030", -- 0x25F: CIN R00, (0x03)
+		"011011" & X"800", -- 0x260: OR R00, 0x80
+		"100110" & X"030", -- 0x261: COUT (0x03), R00
+		"000000" & X"000", -- 0x262: NOP
+		"101001" & X"030", -- 0x263: CIN R00, (0x03)
+		"011011" & X"800", -- 0x264: OR R00, 0x80
+		"100110" & X"030", -- 0x265: COUT (0x03), R00
+		"000000" & X"000", -- 0x266: NOP
+		"101001" & X"030", -- 0x267: CIN R00, (0x03)
+		"011011" & X"800", -- 0x268: OR R00, 0x80
+		"100110" & X"030", -- 0x269: COUT (0x03), R00
+		"000000" & X"000", -- 0x26A: NOP
+		"101001" & X"030", -- 0x26B: CIN R00, (0x03)
+		"011011" & X"800", -- 0x26C: OR R00, 0x80
+		"100110" & X"030", -- 0x26D: COUT (0x03), R00
+		"000000" & X"000", -- 0x26E: NOP
+		"000000" & X"000", -- 0x26F: NOP
+		"000000" & X"000", -- 0x270: NOP
+		"000000" & X"000", -- 0x271: NOP
+		"000000" & X"000", -- 0x272: NOP
+		"000000" & X"000", -- 0x273: NOP
+		"000000" & X"000", -- 0x274: NOP
+		"000000" & X"000", -- 0x275: NOP
+		"000000" & X"000", -- 0x276: NOP
+		"111110" & X"000", -- 0x277: RET
+		"010101" & X"000", -- 0x278: SUB R00, 0x00
+		"110011" & X"3FF", -- 0x279: JC 0x3FF
+		"101011" & X"000", -- 0x27A: SETC
+		"110100" & X"3FF", -- 0x27B: JNC 0x3FF
+		"000000" & X"000", -- 0x27C: NOP
+		"010101" & X"000", -- 0x27D: SUB R00, 0x00
+		"110011" & X"3FF", -- 0x27E: JC 0x3FF
+		"000011" & X"000", -- 0x27F: MOV R00, 0x00
+		"010101" & X"000", -- 0x280: CLRC
+		"110011" & X"3FF", -- 0x281: JC 0x3FF
+		"101011" & X"000", -- 0x282: SETC
+		"110100" & X"3FF", -- 0x283: JNC 0x3FF
+		"000000" & X"000", -- 0x284: NOP
+		"010101" & X"000", -- 0x285: CLRC
+		"110011" & X"3FF", -- 0x286: JC 0x3FF
+		"111110" & X"000", -- 0x287: RET
+		"010001" & X"01E", -- 0x288: INC R14
+		"111111" & X"000", -- 0x289: RETI
+		"000000" & X"000", -- 0x28A:
+		"000000" & X"000", -- 0x28B:
+		"000000" & X"000", -- 0x28C:
+		"000000" & X"000", -- 0x28D:
+		"000000" & X"000", -- 0x28E:
+		"000000" & X"000", -- 0x28F:
+		"000000" & X"000", -- 0x290:
+		"000000" & X"000", -- 0x291:
+		"000000" & X"000", -- 0x292:
+		"000000" & X"000", -- 0x293:
+		"000000" & X"000", -- 0x294:
+		"000000" & X"000", -- 0x295:
+		"000000" & X"000", -- 0x296:
+		"000000" & X"000", -- 0x297:
+		"000000" & X"000", -- 0x298:
+		"000000" & X"000", -- 0x299:
+		"000000" & X"000", -- 0x29A:
+		"000000" & X"000", -- 0x29B:
+		"000000" & X"000", -- 0x29C:
+		"000000" & X"000", -- 0x29D:
+		"000000" & X"000", -- 0x29E:
+		"000000" & X"000", -- 0x29F:
+		"000000" & X"000", -- 0x2A0:
+		"000000" & X"000", -- 0x2A1:
+		"000000" & X"000", -- 0x2A2:
+		"000000" & X"000", -- 0x2A3:
+		"000000" & X"000", -- 0x2A4:
+		"000000" & X"000", -- 0x2A5:
+		"000000" & X"000", -- 0x2A6:
+		"000000" & X"000", -- 0x2A7:
+		"000000" & X"000", -- 0x2A8:
+		"000000" & X"000", -- 0x2A9:
+		"000000" & X"000", -- 0x2AA:
+		"000000" & X"000", -- 0x2AB:
+		"000000" & X"000", -- 0x2AC:
+		"000000" & X"000", -- 0x2AD:
+		"000000" & X"000", -- 0x2AE:
+		"000000" & X"000", -- 0x2AF:
+		"000000" & X"000", -- 0x2B0:
+		"000000" & X"000", -- 0x2B1:
+		"000000" & X"000", -- 0x2B2:
+		"000000" & X"000", -- 0x2B3:
+		"000000" & X"000", -- 0x2B4:
+		"000000" & X"000", -- 0x2B5:
+		"000000" & X"000", -- 0x2B6:
+		"000000" & X"000", -- 0x2B7:
+		"000000" & X"000", -- 0x2B8:
+		"000000" & X"000", -- 0x2B9:
+		"000000" & X"000", -- 0x2BA:
+		"000000" & X"000", -- 0x2BB:
+		"000000" & X"000", -- 0x2BC:
+		"000000" & X"000", -- 0x2BD:
+		"000000" & X"000", -- 0x2BE:
+		"000000" & X"000", -- 0x2BF:
+		"000000" & X"000", -- 0x2C0:
+		"000000" & X"000", -- 0x2C1:
+		"000000" & X"000", -- 0x2C2:
+		"000000" & X"000", -- 0x2C3:
+		"000000" & X"000", -- 0x2C4:
+		"000000" & X"000", -- 0x2C5:
+		"000000" & X"000", -- 0x2C6:
+		"000000" & X"000", -- 0x2C7:
+		"000000" & X"000", -- 0x2C8:
+		"000000" & X"000", -- 0x2C9:
+		"000000" & X"000", -- 0x2CA:
+		"000000" & X"000", -- 0x2CB:
+		"000000" & X"000", -- 0x2CC:
+		"000000" & X"000", -- 0x2CD:
+		"000000" & X"000", -- 0x2CE:
+		"000000" & X"000", -- 0x2CF:
+		"000000" & X"000", -- 0x2D0:
+		"000000" & X"000", -- 0x2D1:
+		"000000" & X"000", -- 0x2D2:
+		"000000" & X"000", -- 0x2D3:
+		"000000" & X"000", -- 0x2D4:
+		"000000" & X"000", -- 0x2D5:
+		"000000" & X"000", -- 0x2D6:
+		"000000" & X"000", -- 0x2D7:
+		"000000" & X"000", -- 0x2D8:
+		"000000" & X"000", -- 0x2D9:
+		"000000" & X"000", -- 0x2DA:
+		"000000" & X"000", -- 0x2DB:
+		"000000" & X"000", -- 0x2DC:
+		"000000" & X"000", -- 0x2DD:
+		"000000" & X"000", -- 0x2DE:
+		"000000" & X"000", -- 0x2DF:
+		"000000" & X"000", -- 0x2E0:
+		"000000" & X"000", -- 0x2E1:
+		"000000" & X"000", -- 0x2E2:
+		"000000" & X"000", -- 0x2E3:
+		"000000" & X"000", -- 0x2E4:
+		"000000" & X"000", -- 0x2E5:
+		"000000" & X"000", -- 0x2E6:
+		"000000" & X"000", -- 0x2E7:
+		"000000" & X"000", -- 0x2E8:
+		"000000" & X"000", -- 0x2E9:
+		"000000" & X"000", -- 0x2EA:
+		"000000" & X"000", -- 0x2EB:
+		"000000" & X"000", -- 0x2EC:
+		"000000" & X"000", -- 0x2ED:
+		"000000" & X"000", -- 0x2EE:
+		"000000" & X"000", -- 0x2EF:
+		"000000" & X"000", -- 0x2F0:
+		"000000" & X"000", -- 0x2F1:
+		"000000" & X"000", -- 0x2F2:
+		"000000" & X"000", -- 0x2F3:
+		"000000" & X"000", -- 0x2F4:
+		"000000" & X"000", -- 0x2F5:
+		"000000" & X"000", -- 0x2F6:
+		"000000" & X"000", -- 0x2F7:
+		"000000" & X"000", -- 0x2F8:
+		"000000" & X"000", -- 0x2F9:
+		"000000" & X"000", -- 0x2FA:
+		"000000" & X"000", -- 0x2FB:
+		"000000" & X"000", -- 0x2FC:
+		"000000" & X"000", -- 0x2FD:
+		"000000" & X"000", -- 0x2FE:
+		"110000" & X"2FF", -- 0x2FF: JMP 0x2FF
+		"000000" & X"000", -- 0x300:
+		"000000" & X"000", -- 0x301:
+		"000000" & X"000", -- 0x302:
+		"000000" & X"000", -- 0x303:
+		"000000" & X"000", -- 0x304:
+		"000000" & X"000", -- 0x305:
+		"000000" & X"000", -- 0x306:
+		"000000" & X"000", -- 0x307:
+		"000000" & X"000", -- 0x308:
+		"000000" & X"000", -- 0x309:
+		"000000" & X"000", -- 0x30A:
+		"000000" & X"000", -- 0x30B:
+		"000000" & X"000", -- 0x30C:
+		"000000" & X"000", -- 0x30D:
+		"000000" & X"000", -- 0x30E:
+		"000000" & X"000", -- 0x30F:
+		"000000" & X"000", -- 0x310:
+		"000000" & X"000", -- 0x311:
+		"000000" & X"000", -- 0x312:
+		"000000" & X"000", -- 0x313:
+		"000000" & X"000", -- 0x314:
+		"000000" & X"000", -- 0x315:
+		"000000" & X"000", -- 0x316:
+		"000000" & X"000", -- 0x317:
+		"000000" & X"000", -- 0x318:
+		"000000" & X"000", -- 0x319:
+		"000000" & X"000", -- 0x31A:
+		"000000" & X"000", -- 0x31B:
+		"000000" & X"000", -- 0x31C:
+		"000000" & X"000", -- 0x31D:
+		"000000" & X"000", -- 0x31E:
+		"000000" & X"000", -- 0x31F:
+		"000000" & X"000", -- 0x320:
+		"000000" & X"000", -- 0x321:
+		"000000" & X"000", -- 0x322:
+		"000000" & X"000", -- 0x323:
+		"000000" & X"000", -- 0x324:
+		"000000" & X"000", -- 0x325:
+		"000000" & X"000", -- 0x326:
+		"000000" & X"000", -- 0x327:
+		"000000" & X"000", -- 0x328:
+		"000000" & X"000", -- 0x329:
+		"000000" & X"000", -- 0x32A:
+		"000000" & X"000", -- 0x32B:
+		"000000" & X"000", -- 0x32C:
+		"000000" & X"000", -- 0x32D:
+		"000000" & X"000", -- 0x32E:
+		"000000" & X"000", -- 0x32F:
+		"000000" & X"000", -- 0x330:
+		"000000" & X"000", -- 0x331:
+		"000000" & X"000", -- 0x332:
+		"000000" & X"000", -- 0x333:
+		"000000" & X"000", -- 0x334:
+		"000000" & X"000", -- 0x335:
+		"000000" & X"000", -- 0x336:
+		"000000" & X"000", -- 0x337:
+		"000000" & X"000", -- 0x338:
+		"000000" & X"000", -- 0x339:
+		"000000" & X"000", -- 0x33A:
+		"000000" & X"000", -- 0x33B:
+		"000000" & X"000", -- 0x33C:
+		"000000" & X"000", -- 0x33D:
+		"000000" & X"000", -- 0x33E:
+		"000000" & X"000", -- 0x33F:
+		"000000" & X"000", -- 0x340:
+		"000000" & X"000", -- 0x341:
+		"000000" & X"000", -- 0x342:
+		"000000" & X"000", -- 0x343:
+		"000000" & X"000", -- 0x344:
+		"000000" & X"000", -- 0x345:
+		"000000" & X"000", -- 0x346:
+		"000000" & X"000", -- 0x347:
+		"000000" & X"000", -- 0x348:
+		"000000" & X"000", -- 0x349:
+		"000000" & X"000", -- 0x34A:
+		"000000" & X"000", -- 0x34B:
+		"000000" & X"000", -- 0x34C:
+		"000000" & X"000", -- 0x34D:
+		"000000" & X"000", -- 0x34E:
+		"000000" & X"000", -- 0x34F:
+		"000000" & X"000", -- 0x350:
+		"000000" & X"000", -- 0x351:
+		"000000" & X"000", -- 0x352:
+		"000000" & X"000", -- 0x353:
+		"000000" & X"000", -- 0x354:
+		"000000" & X"000", -- 0x355:
+		"000000" & X"000", -- 0x356:
+		"000000" & X"000", -- 0x357:
+		"000000" & X"000", -- 0x358:
+		"000000" & X"000", -- 0x359:
+		"000000" & X"000", -- 0x35A:
+		"000000" & X"000", -- 0x35B:
+		"000000" & X"000", -- 0x35C:
+		"000000" & X"000", -- 0x35D:
+		"000000" & X"000", -- 0x35E:
+		"000000" & X"000", -- 0x35F:
+		"000000" & X"000", -- 0x360:
+		"000000" & X"000", -- 0x361:
+		"000000" & X"000", -- 0x362:
+		"000000" & X"000", -- 0x363:
+		"000000" & X"000", -- 0x364:
+		"000000" & X"000", -- 0x365:
+		"000000" & X"000", -- 0x366:
+		"000000" & X"000", -- 0x367:
+		"000000" & X"000", -- 0x368:
+		"000000" & X"000", -- 0x369:
+		"000000" & X"000", -- 0x36A:
+		"000000" & X"000", -- 0x36B:
+		"000000" & X"000", -- 0x36C:
+		"000000" & X"000", -- 0x36D:
+		"000000" & X"000", -- 0x36E:
+		"000000" & X"000", -- 0x36F:
+		"000000" & X"000", -- 0x370:
+		"000000" & X"000", -- 0x371:
+		"000000" & X"000", -- 0x372:
+		"000000" & X"000", -- 0x373:
+		"000000" & X"000", -- 0x374:
+		"000000" & X"000", -- 0x375:
+		"000000" & X"000", -- 0x376:
+		"000000" & X"000", -- 0x377:
+		"000000" & X"000", -- 0x378:
+		"000000" & X"000", -- 0x379:
+		"000000" & X"000", -- 0x37A:
+		"000000" & X"000", -- 0x37B:
+		"000000" & X"000", -- 0x37C:
+		"000000" & X"000", -- 0x37D:
+		"000000" & X"000", -- 0x37E:
+		"000000" & X"000", -- 0x37F:
+		"000000" & X"000", -- 0x380:
+		"000000" & X"000", -- 0x381:
+		"000000" & X"000", -- 0x382:
+		"000000" & X"000", -- 0x383:
+		"000000" & X"000", -- 0x384:
+		"000000" & X"000", -- 0x385:
+		"000000" & X"000", -- 0x386:
+		"000000" & X"000", -- 0x387:
+		"000000" & X"000", -- 0x388:
+		"000000" & X"000", -- 0x389:
+		"000000" & X"000", -- 0x38A:
+		"000000" & X"000", -- 0x38B:
+		"000000" & X"000", -- 0x38C:
+		"000000" & X"000", -- 0x38D:
+		"000000" & X"000", -- 0x38E:
+		"000000" & X"000", -- 0x38F:
+		"000000" & X"000", -- 0x390:
+		"000000" & X"000", -- 0x391:
+		"000000" & X"000", -- 0x392:
+		"000000" & X"000", -- 0x393:
+		"000000" & X"000", -- 0x394:
+		"000000" & X"000", -- 0x395:
+		"000000" & X"000", -- 0x396:
+		"000000" & X"000", -- 0x397:
+		"000000" & X"000", -- 0x398:
+		"000000" & X"000", -- 0x399:
+		"000000" & X"000", -- 0x39A:
+		"000000" & X"000", -- 0x39B:
+		"000000" & X"000", -- 0x39C:
+		"000000" & X"000", -- 0x39D:
+		"000000" & X"000", -- 0x39E:
+		"000000" & X"000", -- 0x39F:
+		"000000" & X"000", -- 0x3A0:
+		"000000" & X"000", -- 0x3A1:
+		"000000" & X"000", -- 0x3A2:
+		"000000" & X"000", -- 0x3A3:
+		"000000" & X"000", -- 0x3A4:
+		"000000" & X"000", -- 0x3A5:
+		"000000" & X"000", -- 0x3A6:
+		"000000" & X"000", -- 0x3A7:
+		"000000" & X"000", -- 0x3A8:
+		"000000" & X"000", -- 0x3A9:
+		"000000" & X"000", -- 0x3AA:
+		"000000" & X"000", -- 0x3AB:
+		"000000" & X"000", -- 0x3AC:
+		"000000" & X"000", -- 0x3AD:
+		"000000" & X"000", -- 0x3AE:
+		"000000" & X"000", -- 0x3AF:
+		"000000" & X"000", -- 0x3B0:
+		"000000" & X"000", -- 0x3B1:
+		"000000" & X"000", -- 0x3B2:
+		"000000" & X"000", -- 0x3B3:
+		"000000" & X"000", -- 0x3B4:
+		"000000" & X"000", -- 0x3B5:
+		"000000" & X"000", -- 0x3B6:
+		"000000" & X"000", -- 0x3B7:
+		"000000" & X"000", -- 0x3B8:
+		"000000" & X"000", -- 0x3B9:
+		"000000" & X"000", -- 0x3BA:
+		"000000" & X"000", -- 0x3BB:
+		"000000" & X"000", -- 0x3BC:
+		"000000" & X"000", -- 0x3BD:
+		"000000" & X"000", -- 0x3BE:
+		"000000" & X"000", -- 0x3BF:
+		"000000" & X"000", -- 0x3C0:
+		"000000" & X"000", -- 0x3C1:
+		"000000" & X"000", -- 0x3C2:
+		"000000" & X"000", -- 0x3C3:
+		"000000" & X"000", -- 0x3C4:
+		"000000" & X"000", -- 0x3C5:
+		"000000" & X"000", -- 0x3C6:
+		"000000" & X"000", -- 0x3C7:
+		"000000" & X"000", -- 0x3C8:
+		"000000" & X"000", -- 0x3C9:
+		"000000" & X"000", -- 0x3CA:
+		"000000" & X"000", -- 0x3CB:
+		"000000" & X"000", -- 0x3CC:
+		"000000" & X"000", -- 0x3CD:
+		"000000" & X"000", -- 0x3CE:
+		"000000" & X"000", -- 0x3CF:
+		"000000" & X"000", -- 0x3D0:
+		"000000" & X"000", -- 0x3D1:
+		"000000" & X"000", -- 0x3D2:
+		"000000" & X"000", -- 0x3D3:
+		"000000" & X"000", -- 0x3D4:
+		"000000" & X"000", -- 0x3D5:
+		"000000" & X"000", -- 0x3D6:
+		"000000" & X"000", -- 0x3D7:
+		"000000" & X"000", -- 0x3D8:
+		"000000" & X"000", -- 0x3D9:
+		"000000" & X"000", -- 0x3DA:
+		"000000" & X"000", -- 0x3DB:
+		"000000" & X"000", -- 0x3DC:
+		"000000" & X"000", -- 0x3DD:
+		"000000" & X"000", -- 0x3DE:
+		"000000" & X"000", -- 0x3DF:
+		"000000" & X"000", -- 0x3E0:
+		"000000" & X"000", -- 0x3E1:
+		"000000" & X"000", -- 0x3E2:
+		"000000" & X"000", -- 0x3E3:
+		"000000" & X"000", -- 0x3E4:
+		"000000" & X"000", -- 0x3E5:
+		"000000" & X"000", -- 0x3E6:
+		"000000" & X"000", -- 0x3E7:
+		"000000" & X"000", -- 0x3E8:
+		"000000" & X"000", -- 0x3E9:
+		"000000" & X"000", -- 0x3EA:
+		"000000" & X"000", -- 0x3EB:
+		"000000" & X"000", -- 0x3EC:
+		"000000" & X"000", -- 0x3ED:
+		"000000" & X"000", -- 0x3EE:
+		"000000" & X"000", -- 0x3EF:
+		"000000" & X"000", -- 0x3F0:
+		"000000" & X"000", -- 0x3F1:
+		"000000" & X"000", -- 0x3F2:
+		"000000" & X"000", -- 0x3F3:
+		"000000" & X"000", -- 0x3F4:
+		"000000" & X"000", -- 0x3F5:
+		"000000" & X"000", -- 0x3F6:
+		"000000" & X"000", -- 0x3F7:
+		"000000" & X"000", -- 0x3F8:
+		"000000" & X"000", -- 0x3F9:
+		"000000" & X"000", -- 0x3FA:
+		"000000" & X"000", -- 0x3FB:
+		"000000" & X"000", -- 0x3FC:
+		"000000" & X"000", -- 0x3FD:
+		"000000" & X"000", -- 0x3FE:
+		"110000" & X"3FF"  -- 0x3FF: JMP 0x3FF
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end itest;
+
diff --git a/lib/CPUs/JCpu/src/itest_irom_ld.vhdl b/lib/CPUs/JCpu/src/itest_irom_ld.vhdl
new file mode 100644
index 0000000..d4371a1
--- /dev/null
+++ b/lib/CPUs/JCpu/src/itest_irom_ld.vhdl
@@ -0,0 +1,1181 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY irom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  inst_addr_t;
+		dout		: out inst_t
+	);
+	
+END irom;
+
+ARCHITECTURE loadable OF irom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from itest.jsm
+	type imem_rom_t is array (0 to 1023) of inst_t;
+	signal imem_rom : imem_rom_t :=
+	(
+		"110000" & X"010", -- 0x000: JMP 0x010
+		"110000" & X"288", -- 0x001: JMP 0x288
+		"000000" & X"000", -- 0x002:
+		"000000" & X"000", -- 0x003:
+		"000000" & X"000", -- 0x004:
+		"000000" & X"000", -- 0x005:
+		"000000" & X"000", -- 0x006:
+		"000000" & X"000", -- 0x007:
+		"000000" & X"000", -- 0x008:
+		"000000" & X"000", -- 0x009:
+		"000000" & X"000", -- 0x00A:
+		"000000" & X"000", -- 0x00B:
+		"000000" & X"000", -- 0x00C:
+		"000000" & X"000", -- 0x00D:
+		"000000" & X"000", -- 0x00E:
+		"000000" & X"000", -- 0x00F:
+		"111011" & X"03B", -- 0x010: CALL 0x03B
+		"101001" & X"000", -- 0x011: CIN R00, (0x00)
+		"100100" & X"000", -- 0x012: XOUT (0x00), R00
+		"111011" & X"04C", -- 0x013: CALL 0x04C
+		"000011" & X"010", -- 0x014: MOV R00, 0x01
+		"100100" & X"010", -- 0x015: XOUT (0x01), R00
+		"111011" & X"08D", -- 0x016: CALL 0x08D
+		"000011" & X"020", -- 0x017: MOV R00, 0x02
+		"100100" & X"010", -- 0x018: XOUT (0x01), R00
+		"111011" & X"0C9", -- 0x019: CALL 0x0C9
+		"000011" & X"030", -- 0x01A: MOV R00, 0x03
+		"100100" & X"010", -- 0x01B: XOUT (0x01), R00
+		"111011" & X"0DB", -- 0x01C: CALL 0x0DB
+		"000011" & X"040", -- 0x01D: MOV R00, 0x04
+		"100100" & X"010", -- 0x01E: XOUT (0x01), R00
+		"111011" & X"0ED", -- 0x01F: CALL 0x0ED
+		"000011" & X"050", -- 0x020: MOV R00, 0x05
+		"100100" & X"010", -- 0x021: XOUT (0x01), R00
+		"111011" & X"0FF", -- 0x022: CALL 0x0FF
+		"000011" & X"060", -- 0x023: MOV R00, 0x06
+		"100100" & X"010", -- 0x024: XOUT (0x01), R00
+		"111011" & X"115", -- 0x025: CALL 0x115
+		"000011" & X"070", -- 0x026: MOV R00, 0x07
+		"100100" & X"010", -- 0x027: XOUT (0x01), R00
+		"111011" & X"12B", -- 0x028: CALL 0x12B
+		"000011" & X"080", -- 0x029: MOV R00, 0x08
+		"100100" & X"010", -- 0x02A: XOUT (0x01), R00
+		"111011" & X"137", -- 0x02B: CALL 0x137
+		"000011" & X"090", -- 0x02C: MOV R00, 0x09
+		"100100" & X"010", -- 0x02D: XOUT (0x01), R00
+		"111011" & X"15A", -- 0x02E: CALL 0x15A
+		"000011" & X"0A0", -- 0x02F: MOV R00, 0x0A
+		"100100" & X"010", -- 0x030: XOUT (0x01), R00
+		"111011" & X"22A", -- 0x031: CALL 0x22A
+		"000011" & X"0B0", -- 0x032: MOV R00, 0x0B
+		"100100" & X"010", -- 0x033: XOUT (0x01), R00
+		"111011" & X"24D", -- 0x034: CALL 0x24D
+		"000011" & X"0C0", -- 0x035: MOV R00, 0x0C
+		"100100" & X"010", -- 0x036: XOUT (0x01), R00
+		"111011" & X"278", -- 0x037: CALL 0x278
+		"000011" & X"FF0", -- 0x038: MOV R00, 0xFF
+		"100100" & X"010", -- 0x039: XOUT (0x01), R00
+		"110000" & X"2FF", -- 0x03A: JMP 0x2FF
+		"000011" & X"000", -- 0x03B: MOV R00, 0x00
+		"000011" & X"001", -- 0x03C: MOV R01, 0x00
+		"000011" & X"002", -- 0x03D: MOV R02, 0x00
+		"000011" & X"003", -- 0x03E: MOV R03, 0x00
+		"000011" & X"004", -- 0x03F: MOV R04, 0x00
+		"000011" & X"005", -- 0x040: MOV R05, 0x00
+		"000011" & X"006", -- 0x041: MOV R06, 0x00
+		"000011" & X"007", -- 0x042: MOV R07, 0x00
+		"000011" & X"008", -- 0x043: MOV R08, 0x00
+		"000011" & X"009", -- 0x044: MOV R09, 0x00
+		"000011" & X"00A", -- 0x045: MOV R10, 0x00
+		"000011" & X"00B", -- 0x046: MOV R11, 0x00
+		"000011" & X"00C", -- 0x047: MOV R12, 0x00
+		"000011" & X"00D", -- 0x048: MOV R13, 0x00
+		"000011" & X"00E", -- 0x049: MOV R14, 0x00
+		"000011" & X"00F", -- 0x04A: MOV R15, 0x00
+		"111110" & X"000", -- 0x04B: RET
+		"000011" & X"100", -- 0x04C: MOV R00, 0x10
+		"001111" & X"100", -- 0x04D: CMP R00, 0x10
+		"111010" & X"3FF", -- 0x04E: JNE 0x3FF
+		"010001" & X"010", -- 0x04F: ADD R00, 0x01
+		"000010" & X"001", -- 0x050: MOV R01, R00
+		"001111" & X"111", -- 0x051: CMP R01, 0x11
+		"111010" & X"3FF", -- 0x052: JNE 0x3FF
+		"010001" & X"011", -- 0x053: ADD R01, 0x01
+		"000010" & X"012", -- 0x054: MOV R02, R01
+		"001111" & X"122", -- 0x055: CMP R02, 0x12
+		"111010" & X"3FF", -- 0x056: JNE 0x3FF
+		"010001" & X"012", -- 0x057: ADD R02, 0x01
+		"000010" & X"023", -- 0x058: MOV R03, R02
+		"001111" & X"133", -- 0x059: CMP R03, 0x13
+		"111010" & X"3FF", -- 0x05A: JNE 0x3FF
+		"010001" & X"013", -- 0x05B: ADD R03, 0x01
+		"000010" & X"034", -- 0x05C: MOV R04, R03
+		"001111" & X"144", -- 0x05D: CMP R04, 0x14
+		"111010" & X"3FF", -- 0x05E: JNE 0x3FF
+		"010001" & X"014", -- 0x05F: ADD R04, 0x01
+		"000010" & X"045", -- 0x060: MOV R05, R04
+		"001111" & X"155", -- 0x061: CMP R05, 0x15
+		"111010" & X"3FF", -- 0x062: JNE 0x3FF
+		"010001" & X"015", -- 0x063: ADD R05, 0x01
+		"000010" & X"056", -- 0x064: MOV R06, R05
+		"001111" & X"166", -- 0x065: CMP R06, 0x16
+		"111010" & X"3FF", -- 0x066: JNE 0x3FF
+		"010001" & X"016", -- 0x067: ADD R06, 0x01
+		"000010" & X"067", -- 0x068: MOV R07, R06
+		"001111" & X"177", -- 0x069: CMP R07, 0x17
+		"111010" & X"3FF", -- 0x06A: JNE 0x3FF
+		"010001" & X"017", -- 0x06B: ADD R07, 0x01
+		"000010" & X"078", -- 0x06C: MOV R08, R07
+		"001111" & X"188", -- 0x06D: CMP R08, 0x18
+		"111010" & X"3FF", -- 0x06E: JNE 0x3FF
+		"010001" & X"018", -- 0x06F: ADD R08, 0x01
+		"000010" & X"089", -- 0x070: MOV R09, R08
+		"001111" & X"199", -- 0x071: CMP R09, 0x19
+		"111010" & X"3FF", -- 0x072: JNE 0x3FF
+		"010001" & X"019", -- 0x073: ADD R09, 0x01
+		"000010" & X"09A", -- 0x074: MOV R10, R09
+		"001111" & X"1AA", -- 0x075: CMP R10, 0x1A
+		"111010" & X"3FF", -- 0x076: JNE 0x3FF
+		"010001" & X"01A", -- 0x077: ADD R10, 0x01
+		"000010" & X"0AB", -- 0x078: MOV R11, R10
+		"001111" & X"1BB", -- 0x079: CMP R11, 0x1B
+		"111010" & X"3FF", -- 0x07A: JNE 0x3FF
+		"010001" & X"01B", -- 0x07B: ADD R11, 0x01
+		"000010" & X"0BC", -- 0x07C: MOV R12, R11
+		"001111" & X"1CC", -- 0x07D: CMP R12, 0x1C
+		"111010" & X"3FF", -- 0x07E: JNE 0x3FF
+		"010001" & X"01C", -- 0x07F: ADD R12, 0x01
+		"000010" & X"0CD", -- 0x080: MOV R13, R12
+		"001111" & X"1DD", -- 0x081: CMP R13, 0x1D
+		"111010" & X"3FF", -- 0x082: JNE 0x3FF
+		"010001" & X"01D", -- 0x083: ADD R13, 0x01
+		"000010" & X"0DE", -- 0x084: MOV R14, R13
+		"001111" & X"1EE", -- 0x085: CMP R14, 0x1E
+		"111010" & X"3FF", -- 0x086: JNE 0x3FF
+		"010001" & X"01E", -- 0x087: ADD R14, 0x01
+		"000010" & X"0EF", -- 0x088: MOV R15, R14
+		"001111" & X"1FF", -- 0x089: CMP R15, 0x1F
+		"111010" & X"3FF", -- 0x08A: JNE 0x3FF
+		"010001" & X"01F", -- 0x08B: ADD R15, 0x01
+		"111110" & X"000", -- 0x08C: RET
+		"000011" & X"000", -- 0x08D: MOV R00, 0x00
+		"001111" & X"000", -- 0x08E: TST R00
+		"110010" & X"3FF", -- 0x08F: JNZ 0x3FF
+		"110011" & X"3FF", -- 0x090: JC 0x3FF
+		"001111" & X"000", -- 0x091: CMP R00, 0x00
+		"111010" & X"3FF", -- 0x092: JNE 0x3FF
+		"110101" & X"3FF", -- 0x093: JLT 0x3FF
+		"110110" & X"3FF", -- 0x094: JGT 0x3FF
+		"110111" & X"097", -- 0x095: JLE 0x097
+		"110000" & X"3FF", -- 0x096: JMP 0x3FF
+		"111001" & X"099", -- 0x097: JEQ 0x099
+		"110000" & X"3FF", -- 0x098: JMP 0x3FF
+		"111000" & X"09B", -- 0x099: JGE 0x09B
+		"110000" & X"3FF", -- 0x09A: JMP 0x3FF
+		"001111" & X"550", -- 0x09B: CMP R00, 0x55
+		"111001" & X"3FF", -- 0x09C: JEQ 0x3FF
+		"110101" & X"09F", -- 0x09D: JLT 0x09F
+		"110000" & X"3FF", -- 0x09E: JMP 0x3FF
+		"110111" & X"0A1", -- 0x09F: JLE 0x0A1
+		"110000" & X"3FF", -- 0x0A0: JMP 0x3FF
+		"111000" & X"3FF", -- 0x0A1: JGE 0x3FF
+		"110110" & X"3FF", -- 0x0A2: JGT 0x3FF
+		"000011" & X"550", -- 0x0A3: MOV R00, 0x55
+		"001111" & X"000", -- 0x0A4: TST R00
+		"110001" & X"3FF", -- 0x0A5: JZ 0x3FF
+		"110011" & X"3FF", -- 0x0A6: JC 0x3FF
+		"001111" & X"AA0", -- 0x0A7: CMP R00, 0xAA
+		"111001" & X"3FF", -- 0x0A8: JEQ 0x3FF
+		"111010" & X"0AB", -- 0x0A9: JNE 0x0AB
+		"110000" & X"3FF", -- 0x0AA: JMP 0x3FF
+		"110101" & X"0AD", -- 0x0AB: JLT 0x0AD
+		"110000" & X"3FF", -- 0x0AC: JMP 0x3FF
+		"110111" & X"0AF", -- 0x0AD: JLE 0x0AF
+		"110000" & X"3FF", -- 0x0AE: JMP 0x3FF
+		"110110" & X"3FF", -- 0x0AF: JGT 0x3FF
+		"001111" & X"550", -- 0x0B0: CMP R00, 0x55
+		"111001" & X"0B3", -- 0x0B1: JEQ 0x0B3
+		"110000" & X"3FF", -- 0x0B2: JMP 0x3FF
+		"111010" & X"3FF", -- 0x0B3: JNE 0x3FF
+		"110101" & X"3FF", -- 0x0B4: JLT 0x3FF
+		"110111" & X"0B7", -- 0x0B5: JLE 0x0B7
+		"110000" & X"3FF", -- 0x0B6: JMP 0x3FF
+		"110110" & X"3FF", -- 0x0B7: JGT 0x3FF
+		"111000" & X"0BA", -- 0x0B8: JGE 0x0BA
+		"110000" & X"3FF", -- 0x0B9: JMP 0x3FF
+		"000011" & X"AA0", -- 0x0BA: MOV R00, 0xAA
+		"001111" & X"000", -- 0x0BB: TST R00
+		"110001" & X"3FF", -- 0x0BC: JZ 0x3FF
+		"110011" & X"3FF", -- 0x0BD: JC 0x3FF
+		"001111" & X"550", -- 0x0BE: CMP R00, 0x55
+		"111001" & X"3FF", -- 0x0BF: JEQ 0x3FF
+		"111010" & X"0C2", -- 0x0C0: JNE 0x0C2
+		"110000" & X"3FF", -- 0x0C1: JMP 0x3FF
+		"110110" & X"0C4", -- 0x0C2: JGT 0x0C4
+		"110000" & X"3FF", -- 0x0C3: JMP 0x3FF
+		"111000" & X"0C6", -- 0x0C4: JGE 0x0C6
+		"110000" & X"3FF", -- 0x0C5: JMP 0x3FF
+		"110101" & X"3FF", -- 0x0C6: JLT 0x3FF
+		"110111" & X"3FF", -- 0x0C7: JLE 0x3FF
+		"111110" & X"000", -- 0x0C8: RET
+		"000011" & X"000", -- 0x0C9: MOV R00, 0x00
+		"000011" & X"001", -- 0x0CA: MOV R01, 0x00
+		"000010" & X"002", -- 0x0CB: MOV R02, R00
+		"000010" & X"013", -- 0x0CC: MOV R03, R01
+		"010001" & X"010", -- 0x0CD: ADD R00, 0x01
+		"010011" & X"001", -- 0x0CE: ADDC R01, 0x00
+		"010001" & X"012", -- 0x0CF: ADD R02, 0x01
+		"001111" & X"002", -- 0x0D0: CMP R02, 0x00
+		"111010" & X"0D4", -- 0x0D1: JNE 0x0D4
+		"010001" & X"013", -- 0x0D2: ADD R03, 0x01
+		"001111" & X"023", -- 0x0D3: CMP R03, 0x02
+		"111010" & X"0CD", -- 0x0D4: JNE 0x0CD
+		"001110" & X"020", -- 0x0D5: CMP R00, R02
+		"111010" & X"3FF", -- 0x0D6: JNE 0x3FF
+		"001110" & X"031", -- 0x0D7: CMP R01, R03
+		"111010" & X"3FF", -- 0x0D8: JNE 0x3FF
+		"000011" & X"000", -- 0x0D9: MOV R00, 0x00
+		"111110" & X"000", -- 0x0DA: RET
+		"000011" & X"000", -- 0x0DB: MOV R00, 0x00
+		"000011" & X"031", -- 0x0DC: MOV R01, 0x03
+		"000010" & X"002", -- 0x0DD: MOV R02, R00
+		"000010" & X"013", -- 0x0DE: MOV R03, R01
+		"010101" & X"010", -- 0x0DF: SUB R00, 0x01
+		"010111" & X"001", -- 0x0E0: SUBC R01, 0x00
+		"010101" & X"012", -- 0x0E1: SUB R02, 0x01
+		"001111" & X"FF2", -- 0x0E2: CMP R02, 0xFF
+		"111010" & X"0E6", -- 0x0E3: JNE 0x0E6
+		"010101" & X"013", -- 0x0E4: SUB R03, 0x01
+		"001111" & X"003", -- 0x0E5: CMP R03, 0x00
+		"111010" & X"0DF", -- 0x0E6: JNE 0x0DF
+		"001110" & X"020", -- 0x0E7: CMP R00, R02
+		"111010" & X"3FF", -- 0x0E8: JNE 0x3FF
+		"001110" & X"031", -- 0x0E9: CMP R01, R03
+		"111010" & X"3FF", -- 0x0EA: JNE 0x3FF
+		"000011" & X"000", -- 0x0EB: MOV R00, 0x00
+		"111110" & X"000", -- 0x0EC: RET
+		"000011" & X"030", -- 0x0ED: MOV R00, 0x03
+		"000011" & X"051", -- 0x0EE: MOV R01, 0x05
+		"101110" & X"050", -- 0x0EF: SUB 0x05, R00
+		"010101" & X"031", -- 0x0F0: SUB R01, 0x03
+		"001110" & X"010", -- 0x0F1: CMP R00, R01
+		"111010" & X"3FF", -- 0x0F2: JNE 0x3FF
+		"000011" & X"030", -- 0x0F3: MOV R00, 0x03
+		"000011" & X"051", -- 0x0F4: MOV R01, 0x05
+		"010100" & X"010", -- 0x0F5: SUB R00, R01
+		"101111" & X"000", -- 0x0F6: SUBC 0x00, R00
+		"001111" & X"010", -- 0x0F7: CMP R00, 0x01
+		"111010" & X"3FF", -- 0x0F8: JNE 0x3FF
+		"010001" & X"000", -- 0x0F9: ADD R00, 0x00
+		"010110" & X"001", -- 0x0FA: SUBC R01, R00
+		"001111" & X"041", -- 0x0FB: CMP R01, 0x04
+		"111010" & X"3FF", -- 0x0FC: JNE 0x3FF
+		"000011" & X"000", -- 0x0FD: MOV R00, 0x00
+		"111110" & X"000", -- 0x0FE: RET
+		"000011" & X"010", -- 0x0FF: MOV R00, 0x01
+		"001101" & X"5A0", -- 0x100: MOVC (0x5A), R00
+		"010101" & X"010", -- 0x101: DEC R00
+		"001101" & X"000", -- 0x102: MOVC (0x00), R00
+		"001010" & X"5A1", -- 0x103: MOVC R01, (0x5A)
+		"001100" & X"A51", -- 0x104: MOVC (R01), 0xA5
+		"001001" & X"010", -- 0x105: MOVC R00, (R01)
+		"001001" & X"011", -- 0x106: MOVC R01, (R01)
+		"010001" & X"5A1", -- 0x107: ADD R01, 0x5A
+		"001001" & X"010", -- 0x108: MOVC R00, (R01)
+		"001011" & X"000", -- 0x109: MOVC (R00), R00
+		"001001" & X"002", -- 0x10A: MOVC R02, (R00)
+		"001110" & X"002", -- 0x10B: CMP R02, R00
+		"111010" & X"3FF", -- 0x10C: JNE 0x3FF
+		"001011" & X"021", -- 0x10D: MOVC (R01), R02
+		"001001" & X"022", -- 0x10E: MOVC R02, (R02)
+		"001110" & X"012", -- 0x10F: CMP R02, R01
+		"111010" & X"3FF", -- 0x110: JNE 0x3FF
+		"010101" & X"011", -- 0x111: DEC R01
+		"010001" & X"010", -- 0x112: INC R00
+		"110010" & X"109", -- 0x113: JNZ 0x109
+		"111110" & X"000", -- 0x114: RET
+		"000011" & X"010", -- 0x115: MOV R00, 0x01
+		"001000" & X"600", -- 0x116: MOVX (0x60), R00
+		"010101" & X"010", -- 0x117: DEC R00
+		"001000" & X"060", -- 0x118: MOVX (0x06), R00
+		"000101" & X"601", -- 0x119: MOVX R01, (0x60)
+		"000111" & X"A51", -- 0x11A: MOVX (R01), 0xA5
+		"000100" & X"010", -- 0x11B: MOVX R00, (R01)
+		"000100" & X"011", -- 0x11C: MOVX R01, (R01)
+		"010001" & X"5A1", -- 0x11D: ADD R01, 0x5A
+		"000100" & X"010", -- 0x11E: MOVX R00, (R01)
+		"000110" & X"000", -- 0x11F: MOVX (R00), R00
+		"000100" & X"002", -- 0x120: MOVX R02, (R00)
+		"001110" & X"002", -- 0x121: CMP R02, R00
+		"111010" & X"3FF", -- 0x122: JNE 0x3FF
+		"000110" & X"021", -- 0x123: MOVX (R01), R02
+		"000100" & X"022", -- 0x124: MOVX R02, (R02)
+		"001110" & X"012", -- 0x125: CMP R02, R01
+		"111010" & X"3FF", -- 0x126: JNE 0x3FF
+		"010101" & X"011", -- 0x127: DEC R01
+		"010001" & X"010", -- 0x128: INC R00
+		"110010" & X"11F", -- 0x129: JNZ 0x11F
+		"111110" & X"000", -- 0x12A: RET
+		"000011" & X"AA0", -- 0x12B: MOV R00, 0xAA
+		"000011" & X"001", -- 0x12C: MOV R01, 0x00
+		"111100" & X"000", -- 0x12D: PUSH R00
+		"010001" & X"010", -- 0x12E: INC R00
+		"010101" & X"011", -- 0x12F: DEC R01
+		"110010" & X"12D", -- 0x130: JNZ 0x12D
+		"111101" & X"000", -- 0x131: POP R00
+		"010101" & X"011", -- 0x132: DEC R01
+		"110010" & X"131", -- 0x133: JNZ 0x131
+		"001111" & X"AA0", -- 0x134: CMP R00, 0xAA
+		"111010" & X"3FF", -- 0x135: JNE 0x3FF
+		"111110" & X"000", -- 0x136: RET
+		"000011" & X"550", -- 0x137: MOV R00, 0x55
+		"111100" & X"000", -- 0x138: PUSH R00
+		"000011" & X"000", -- 0x139: MOV R00, 0x00
+		"000011" & X"FF1", -- 0x13A: MOV R01, 0xFF
+		"111011" & X"151", -- 0x13B: CALL 0x151
+		"111101" & X"000", -- 0x13C: POP R00
+		"001111" & X"550", -- 0x13D: CMP R00, 0x55
+		"111010" & X"3FF", -- 0x13E: JNE 0x3FF
+		"000011" & X"010", -- 0x13F: MOV R00, 0x01
+		"000011" & X"481", -- 0x140: MOV R01, 0x48
+		"100110" & X"050", -- 0x141: COUT (0x05), R00
+		"111100" & X"001", -- 0x142: PUSH R01
+		"000011" & X"000", -- 0x143: MOV R00, 0x00
+		"000011" & X"3B1", -- 0x144: MOV R01, 0x3B
+		"100110" & X"050", -- 0x145: COUT (0x05), R00
+		"111100" & X"001", -- 0x146: PUSH R01
+		"111110" & X"000", -- 0x147: RET
+		"000011" & X"010", -- 0x148: MOV R00, 0x01
+		"000011" & X"501", -- 0x149: MOV R01, 0x50
+		"100110" & X"050", -- 0x14A: COUT (0x05), R00
+		"111100" & X"001", -- 0x14B: PUSH R01
+		"000011" & X"000", -- 0x14C: MOV R00, 0x00
+		"000011" & X"3B1", -- 0x14D: MOV R01, 0x3B
+		"100110" & X"050", -- 0x14E: COUT (0x05), R00
+		"111100" & X"001", -- 0x14F: PUSH R01
+		"111110" & X"000", -- 0x150: RET
+		"001110" & X"010", -- 0x151: CMP R00, R01
+		"111001" & X"155", -- 0x152: JEQ 0x155
+		"010001" & X"010", -- 0x153: INC R00
+		"110000" & X"158", -- 0x154: JMP 0x158
+		"010101" & X"010", -- 0x155: DEC R00
+		"010101" & X"011", -- 0x156: DEC R01
+		"111110" & X"000", -- 0x157: RET
+		"111011" & X"151", -- 0x158: CALL 0x151
+		"110000" & X"155", -- 0x159: JMP 0x155
+		"000011" & X"A50", -- 0x15A: MOV R00, 0xA5
+		"000011" & X"5A1", -- 0x15B: MOV R01, 0x5A
+		"101010" & X"000", -- 0x15C: SWAP R00
+		"001111" & X"5A0", -- 0x15D: CMP R00, 0x5A
+		"111010" & X"3FF", -- 0x15E: JNE 0x3FF
+		"101010" & X"000", -- 0x15F: SWAP R00
+		"001111" & X"A50", -- 0x160: CMP R00, 0xA5
+		"111010" & X"3FF", -- 0x161: JNE 0x3FF
+		"000011" & X"D20", -- 0x162: MOV R00, 0xD2
+		"101010" & X"000", -- 0x163: SWAP R00
+		"001111" & X"2D0", -- 0x164: CMP R00, 0x2D
+		"111010" & X"3FF", -- 0x165: JNE 0x3FF
+		"101010" & X"001", -- 0x166: SWAP R01
+		"001111" & X"2D0", -- 0x167: CMP R00, 0x2D
+		"111010" & X"3FF", -- 0x168: JNE 0x3FF
+		"001111" & X"A51", -- 0x169: CMP R01, 0xA5
+		"111010" & X"3FF", -- 0x16A: JNE 0x3FF
+		"000011" & X"2D0", -- 0x16B: MOV R00, 0x2D
+		"011110" & X"000", -- 0x16C: SHL R00
+		"001111" & X"5A0", -- 0x16D: CMP R00, 0x5A
+		"111010" & X"3FF", -- 0x16E: JNE 0x3FF
+		"011110" & X"000", -- 0x16F: SHL R00
+		"001111" & X"B40", -- 0x170: CMP R00, 0xB4
+		"111010" & X"3FF", -- 0x171: JNE 0x3FF
+		"011110" & X"000", -- 0x172: SHL R00
+		"001111" & X"680", -- 0x173: CMP R00, 0x68
+		"111010" & X"3FF", -- 0x174: JNE 0x3FF
+		"011110" & X"000", -- 0x175: SHL R00
+		"001111" & X"D00", -- 0x176: CMP R00, 0xD0
+		"111010" & X"3FF", -- 0x177: JNE 0x3FF
+		"011110" & X"000", -- 0x178: SHL R00
+		"001111" & X"A00", -- 0x179: CMP R00, 0xA0
+		"111010" & X"3FF", -- 0x17A: JNE 0x3FF
+		"011110" & X"000", -- 0x17B: SHL R00
+		"001111" & X"400", -- 0x17C: CMP R00, 0x40
+		"111010" & X"3FF", -- 0x17D: JNE 0x3FF
+		"011110" & X"000", -- 0x17E: SHL R00
+		"001111" & X"800", -- 0x17F: CMP R00, 0x80
+		"111010" & X"3FF", -- 0x180: JNE 0x3FF
+		"011110" & X"000", -- 0x181: SHL R00
+		"001111" & X"000", -- 0x182: CMP R00, 0x00
+		"111010" & X"3FF", -- 0x183: JNE 0x3FF
+		"000011" & X"841", -- 0x184: MOV R01, 0x84
+		"011111" & X"001", -- 0x185: SHR R01
+		"001111" & X"421", -- 0x186: CMP R01, 0x42
+		"111010" & X"3FF", -- 0x187: JNE 0x3FF
+		"011111" & X"001", -- 0x188: SHR R01
+		"001111" & X"211", -- 0x189: CMP R01, 0x21
+		"111010" & X"3FF", -- 0x18A: JNE 0x3FF
+		"011111" & X"001", -- 0x18B: SHR R01
+		"001111" & X"101", -- 0x18C: CMP R01, 0x10
+		"111010" & X"3FF", -- 0x18D: JNE 0x3FF
+		"011111" & X"001", -- 0x18E: SHR R01
+		"001111" & X"081", -- 0x18F: CMP R01, 0x08
+		"111010" & X"3FF", -- 0x190: JNE 0x3FF
+		"011111" & X"001", -- 0x191: SHR R01
+		"001111" & X"041", -- 0x192: CMP R01, 0x04
+		"111010" & X"3FF", -- 0x193: JNE 0x3FF
+		"011111" & X"001", -- 0x194: SHR R01
+		"001111" & X"021", -- 0x195: CMP R01, 0x02
+		"111010" & X"3FF", -- 0x196: JNE 0x3FF
+		"011111" & X"001", -- 0x197: SHR R01
+		"001111" & X"011", -- 0x198: CMP R01, 0x01
+		"111010" & X"3FF", -- 0x199: JNE 0x3FF
+		"011111" & X"001", -- 0x19A: SHR R01
+		"001111" & X"001", -- 0x19B: CMP R01, 0x00
+		"111010" & X"3FF", -- 0x19C: JNE 0x3FF
+		"000011" & X"C50", -- 0x19D: MOV R00, 0xC5
+		"100000" & X"000", -- 0x19E: ROL R00
+		"001111" & X"8B0", -- 0x19F: CMP R00, 0x8B
+		"111010" & X"3FF", -- 0x1A0: JNE 0x3FF
+		"100000" & X"000", -- 0x1A1: ROL R00
+		"001111" & X"170", -- 0x1A2: CMP R00, 0x17
+		"111010" & X"3FF", -- 0x1A3: JNE 0x3FF
+		"100000" & X"000", -- 0x1A4: ROL R00
+		"001111" & X"2E0", -- 0x1A5: CMP R00, 0x2E
+		"111010" & X"3FF", -- 0x1A6: JNE 0x3FF
+		"100000" & X"000", -- 0x1A7: ROL R00
+		"001111" & X"5C0", -- 0x1A8: CMP R00, 0x5C
+		"111010" & X"3FF", -- 0x1A9: JNE 0x3FF
+		"100000" & X"000", -- 0x1AA: ROL R00
+		"001111" & X"B80", -- 0x1AB: CMP R00, 0xB8
+		"111010" & X"3FF", -- 0x1AC: JNE 0x3FF
+		"100000" & X"000", -- 0x1AD: ROL R00
+		"001111" & X"710", -- 0x1AE: CMP R00, 0x71
+		"111010" & X"3FF", -- 0x1AF: JNE 0x3FF
+		"100000" & X"000", -- 0x1B0: ROL R00
+		"001111" & X"E20", -- 0x1B1: CMP R00, 0xE2
+		"111010" & X"3FF", -- 0x1B2: JNE 0x3FF
+		"100000" & X"000", -- 0x1B3: ROL R00
+		"001111" & X"C50", -- 0x1B4: CMP R00, 0xC5
+		"111010" & X"3FF", -- 0x1B5: JNE 0x3FF
+		"000011" & X"631", -- 0x1B6: MOV R01, 0x63
+		"100001" & X"001", -- 0x1B7: ROR R01
+		"001111" & X"B11", -- 0x1B8: CMP R01, 0xB1
+		"111010" & X"3FF", -- 0x1B9: JNE 0x3FF
+		"100001" & X"001", -- 0x1BA: ROR R01
+		"001111" & X"D81", -- 0x1BB: CMP R01, 0xD8
+		"111010" & X"3FF", -- 0x1BC: JNE 0x3FF
+		"100001" & X"001", -- 0x1BD: ROR R01
+		"001111" & X"6C1", -- 0x1BE: CMP R01, 0x6C
+		"111010" & X"3FF", -- 0x1BF: JNE 0x3FF
+		"100001" & X"001", -- 0x1C0: ROR R01
+		"001111" & X"361", -- 0x1C1: CMP R01, 0x36
+		"111010" & X"3FF", -- 0x1C2: JNE 0x3FF
+		"100001" & X"001", -- 0x1C3: ROR R01
+		"001111" & X"1B1", -- 0x1C4: CMP R01, 0x1B
+		"111010" & X"3FF", -- 0x1C5: JNE 0x3FF
+		"100001" & X"001", -- 0x1C6: ROR R01
+		"001111" & X"8D1", -- 0x1C7: CMP R01, 0x8D
+		"111010" & X"3FF", -- 0x1C8: JNE 0x3FF
+		"100001" & X"001", -- 0x1C9: ROR R01
+		"001111" & X"C61", -- 0x1CA: CMP R01, 0xC6
+		"111010" & X"3FF", -- 0x1CB: JNE 0x3FF
+		"100001" & X"001", -- 0x1CC: ROR R01
+		"001111" & X"631", -- 0x1CD: CMP R01, 0x63
+		"111010" & X"3FF", -- 0x1CE: JNE 0x3FF
+		"011100" & X"000", -- 0x1CF: XOR R00, R00
+		"000011" & X"C50", -- 0x1D0: MOV R00, 0xC5
+		"100010" & X"000", -- 0x1D1: ROLC R00
+		"111100" & X"000", -- 0x1D2: PUSH R00
+		"100010" & X"000", -- 0x1D3: ROLC R00
+		"111100" & X"000", -- 0x1D4: PUSH R00
+		"100010" & X"000", -- 0x1D5: ROLC R00
+		"111100" & X"000", -- 0x1D6: PUSH R00
+		"100010" & X"000", -- 0x1D7: ROLC R00
+		"111100" & X"000", -- 0x1D8: PUSH R00
+		"100010" & X"000", -- 0x1D9: ROLC R00
+		"111100" & X"000", -- 0x1DA: PUSH R00
+		"100010" & X"000", -- 0x1DB: ROLC R00
+		"111100" & X"000", -- 0x1DC: PUSH R00
+		"100010" & X"000", -- 0x1DD: ROLC R00
+		"111100" & X"000", -- 0x1DE: PUSH R00
+		"100010" & X"000", -- 0x1DF: ROLC R00
+		"111100" & X"000", -- 0x1E0: PUSH R00
+		"100010" & X"000", -- 0x1E1: ROLC R00
+		"001111" & X"C50", -- 0x1E2: CMP R00, 0xC5
+		"111010" & X"3FF", -- 0x1E3: JNE 0x3FF
+		"111101" & X"000", -- 0x1E4: POP R00
+		"001111" & X"620", -- 0x1E5: CMP R00, 0x62
+		"111010" & X"3FF", -- 0x1E6: JNE 0x3FF
+		"111101" & X"000", -- 0x1E7: POP R00
+		"001111" & X"B10", -- 0x1E8: CMP R00, 0xB1
+		"111010" & X"3FF", -- 0x1E9: JNE 0x3FF
+		"111101" & X"000", -- 0x1EA: POP R00
+		"001111" & X"580", -- 0x1EB: CMP R00, 0x58
+		"111010" & X"3FF", -- 0x1EC: JNE 0x3FF
+		"111101" & X"000", -- 0x1ED: POP R00
+		"001111" & X"AC0", -- 0x1EE: CMP R00, 0xAC
+		"111010" & X"3FF", -- 0x1EF: JNE 0x3FF
+		"111101" & X"000", -- 0x1F0: POP R00
+		"001111" & X"560", -- 0x1F1: CMP R00, 0x56
+		"111010" & X"3FF", -- 0x1F2: JNE 0x3FF
+		"111101" & X"000", -- 0x1F3: POP R00
+		"001111" & X"2B0", -- 0x1F4: CMP R00, 0x2B
+		"111010" & X"3FF", -- 0x1F5: JNE 0x3FF
+		"111101" & X"000", -- 0x1F6: POP R00
+		"001111" & X"150", -- 0x1F7: CMP R00, 0x15
+		"111010" & X"3FF", -- 0x1F8: JNE 0x3FF
+		"111101" & X"000", -- 0x1F9: POP R00
+		"001111" & X"8A0", -- 0x1FA: CMP R00, 0x8A
+		"111010" & X"3FF", -- 0x1FB: JNE 0x3FF
+		"011100" & X"011", -- 0x1FC: XOR R01, R01
+		"000011" & X"631", -- 0x1FD: MOV R01, 0x63
+		"100011" & X"001", -- 0x1FE: RORC R01
+		"111100" & X"001", -- 0x1FF: PUSH R01
+		"100011" & X"001", -- 0x200: RORC R01
+		"111100" & X"001", -- 0x201: PUSH R01
+		"100011" & X"001", -- 0x202: RORC R01
+		"111100" & X"001", -- 0x203: PUSH R01
+		"100011" & X"001", -- 0x204: RORC R01
+		"111100" & X"001", -- 0x205: PUSH R01
+		"100011" & X"001", -- 0x206: RORC R01
+		"111100" & X"001", -- 0x207: PUSH R01
+		"100011" & X"001", -- 0x208: RORC R01
+		"111100" & X"001", -- 0x209: PUSH R01
+		"100011" & X"001", -- 0x20A: RORC R01
+		"111100" & X"001", -- 0x20B: PUSH R01
+		"100011" & X"001", -- 0x20C: RORC R01
+		"111100" & X"001", -- 0x20D: PUSH R01
+		"100011" & X"001", -- 0x20E: RORC R01
+		"001111" & X"631", -- 0x20F: CMP R01, 0x63
+		"111010" & X"3FF", -- 0x210: JNE 0x3FF
+		"111101" & X"001", -- 0x211: POP R01
+		"001111" & X"C61", -- 0x212: CMP R01, 0xC6
+		"111010" & X"3FF", -- 0x213: JNE 0x3FF
+		"111101" & X"001", -- 0x214: POP R01
+		"001111" & X"8C1", -- 0x215: CMP R01, 0x8C
+		"111010" & X"3FF", -- 0x216: JNE 0x3FF
+		"111101" & X"001", -- 0x217: POP R01
+		"001111" & X"191", -- 0x218: CMP R01, 0x19
+		"111010" & X"3FF", -- 0x219: JNE 0x3FF
+		"111101" & X"001", -- 0x21A: POP R01
+		"001111" & X"331", -- 0x21B: CMP R01, 0x33
+		"111010" & X"3FF", -- 0x21C: JNE 0x3FF
+		"111101" & X"001", -- 0x21D: POP R01
+		"001111" & X"661", -- 0x21E: CMP R01, 0x66
+		"111010" & X"3FF", -- 0x21F: JNE 0x3FF
+		"111101" & X"001", -- 0x220: POP R01
+		"001111" & X"CC1", -- 0x221: CMP R01, 0xCC
+		"111010" & X"3FF", -- 0x222: JNE 0x3FF
+		"111101" & X"001", -- 0x223: POP R01
+		"001111" & X"981", -- 0x224: CMP R01, 0x98
+		"111010" & X"3FF", -- 0x225: JNE 0x3FF
+		"111101" & X"001", -- 0x226: POP R01
+		"001111" & X"311", -- 0x227: CMP R01, 0x31
+		"111010" & X"3FF", -- 0x228: JNE 0x3FF
+		"111110" & X"000", -- 0x229: RET
+		"000011" & X"A50", -- 0x22A: MOV R00, 0xA5
+		"101010" & X"000", -- 0x22B: SWAP R00
+		"111100" & X"000", -- 0x22C: PUSH R00
+		"011001" & X"0F0", -- 0x22D: AND R00, 0x0F
+		"001111" & X"0A0", -- 0x22E: CMP R00, 0x0A
+		"111010" & X"3FF", -- 0x22F: JNE 0x3FF
+		"111101" & X"000", -- 0x230: POP R00
+		"111100" & X"000", -- 0x231: PUSH R00
+		"011001" & X"0F0", -- 0x232: AND R00, 0x0F
+		"001111" & X"0A0", -- 0x233: CMP R00, 0x0A
+		"111101" & X"001", -- 0x234: POP R01
+		"111010" & X"3FF", -- 0x235: JNE 0x3FF
+		"101010" & X"001", -- 0x236: SWAP R01
+		"000011" & X"0F2", -- 0x237: MOV R02, 0x0F
+		"011000" & X"021", -- 0x238: AND R01, R02
+		"001111" & X"051", -- 0x239: CMP R01, 0x05
+		"111010" & X"3FF", -- 0x23A: JNE 0x3FF
+		"000011" & X"050", -- 0x23B: MOV R00, 0x05
+		"000011" & X"A02", -- 0x23C: MOV R02, 0xA0
+		"101010" & X"000", -- 0x23D: SWAP R00
+		"011010" & X"002", -- 0x23E: OR R02, R00
+		"001111" & X"F02", -- 0x23F: CMP R02, 0xF0
+		"111010" & X"3FF", -- 0x240: JNE 0x3FF
+		"101010" & X"000", -- 0x241: SWAP R00
+		"011011" & X"500", -- 0x242: OR R00, 0x50
+		"001111" & X"550", -- 0x243: CMP R00, 0x55
+		"111010" & X"3FF", -- 0x244: JNE 0x3FF
+		"000011" & X"011", -- 0x245: MOV R01, 0x01
+		"000011" & X"010", -- 0x246: MOV R00, 0x01
+		"011101" & X"010", -- 0x247: XOR R00, 0x01
+		"110010" & X"3FF", -- 0x248: JNZ 0x3FF
+		"011100" & X"010", -- 0x249: XOR R00, R01
+		"001111" & X"010", -- 0x24A: CMP R00, 0x01
+		"111010" & X"3FF", -- 0x24B: JNE 0x3FF
+		"111110" & X"000", -- 0x24C: RET
+		"000011" & X"030", -- 0x24D: MOV R00, 0x03
+		"100110" & X"030", -- 0x24E: COUT (0x03), R00
+		"101000" & X"020", -- 0x24F: XIN R00, (0x02)
+		"011011" & X"010", -- 0x250: OR R00, 0x01
+		"100100" & X"020", -- 0x251: XOUT (0x02), R00
+		"000000" & X"000", -- 0x252: NOP
+		"000000" & X"000", -- 0x253: NOP
+		"000000" & X"000", -- 0x254: NOP
+		"000000" & X"000", -- 0x255: NOP
+		"000000" & X"000", -- 0x256: NOP
+		"000000" & X"000", -- 0x257: NOP
+		"101000" & X"020", -- 0x258: XIN R00, (0x02)
+		"011001" & X"FE0", -- 0x259: AND R00, 0xFE
+		"100100" & X"020", -- 0x25A: XOUT (0x02), R00
+		"000000" & X"000", -- 0x25B: NOP
+		"000000" & X"000", -- 0x25C: NOP
+		"000000" & X"000", -- 0x25D: NOP
+		"000000" & X"000", -- 0x25E: NOP
+		"101001" & X"030", -- 0x25F: CIN R00, (0x03)
+		"011011" & X"800", -- 0x260: OR R00, 0x80
+		"100110" & X"030", -- 0x261: COUT (0x03), R00
+		"000000" & X"000", -- 0x262: NOP
+		"101001" & X"030", -- 0x263: CIN R00, (0x03)
+		"011011" & X"800", -- 0x264: OR R00, 0x80
+		"100110" & X"030", -- 0x265: COUT (0x03), R00
+		"000000" & X"000", -- 0x266: NOP
+		"101001" & X"030", -- 0x267: CIN R00, (0x03)
+		"011011" & X"800", -- 0x268: OR R00, 0x80
+		"100110" & X"030", -- 0x269: COUT (0x03), R00
+		"000000" & X"000", -- 0x26A: NOP
+		"101001" & X"030", -- 0x26B: CIN R00, (0x03)
+		"011011" & X"800", -- 0x26C: OR R00, 0x80
+		"100110" & X"030", -- 0x26D: COUT (0x03), R00
+		"000000" & X"000", -- 0x26E: NOP
+		"000000" & X"000", -- 0x26F: NOP
+		"000000" & X"000", -- 0x270: NOP
+		"000000" & X"000", -- 0x271: NOP
+		"000000" & X"000", -- 0x272: NOP
+		"000000" & X"000", -- 0x273: NOP
+		"000000" & X"000", -- 0x274: NOP
+		"000000" & X"000", -- 0x275: NOP
+		"000000" & X"000", -- 0x276: NOP
+		"111110" & X"000", -- 0x277: RET
+		"010101" & X"000", -- 0x278: SUB R00, 0x00
+		"110011" & X"3FF", -- 0x279: JC 0x3FF
+		"101011" & X"000", -- 0x27A: SETC
+		"110100" & X"3FF", -- 0x27B: JNC 0x3FF
+		"000000" & X"000", -- 0x27C: NOP
+		"010101" & X"000", -- 0x27D: SUB R00, 0x00
+		"110011" & X"3FF", -- 0x27E: JC 0x3FF
+		"000011" & X"000", -- 0x27F: MOV R00, 0x00
+		"010101" & X"000", -- 0x280: CLRC
+		"110011" & X"3FF", -- 0x281: JC 0x3FF
+		"101011" & X"000", -- 0x282: SETC
+		"110100" & X"3FF", -- 0x283: JNC 0x3FF
+		"000000" & X"000", -- 0x284: NOP
+		"010101" & X"000", -- 0x285: CLRC
+		"110011" & X"3FF", -- 0x286: JC 0x3FF
+		"111110" & X"000", -- 0x287: RET
+		"010001" & X"01E", -- 0x288: INC R14
+		"111111" & X"000", -- 0x289: RETI
+		"000000" & X"000", -- 0x28A:
+		"000000" & X"000", -- 0x28B:
+		"000000" & X"000", -- 0x28C:
+		"000000" & X"000", -- 0x28D:
+		"000000" & X"000", -- 0x28E:
+		"000000" & X"000", -- 0x28F:
+		"000000" & X"000", -- 0x290:
+		"000000" & X"000", -- 0x291:
+		"000000" & X"000", -- 0x292:
+		"000000" & X"000", -- 0x293:
+		"000000" & X"000", -- 0x294:
+		"000000" & X"000", -- 0x295:
+		"000000" & X"000", -- 0x296:
+		"000000" & X"000", -- 0x297:
+		"000000" & X"000", -- 0x298:
+		"000000" & X"000", -- 0x299:
+		"000000" & X"000", -- 0x29A:
+		"000000" & X"000", -- 0x29B:
+		"000000" & X"000", -- 0x29C:
+		"000000" & X"000", -- 0x29D:
+		"000000" & X"000", -- 0x29E:
+		"000000" & X"000", -- 0x29F:
+		"000000" & X"000", -- 0x2A0:
+		"000000" & X"000", -- 0x2A1:
+		"000000" & X"000", -- 0x2A2:
+		"000000" & X"000", -- 0x2A3:
+		"000000" & X"000", -- 0x2A4:
+		"000000" & X"000", -- 0x2A5:
+		"000000" & X"000", -- 0x2A6:
+		"000000" & X"000", -- 0x2A7:
+		"000000" & X"000", -- 0x2A8:
+		"000000" & X"000", -- 0x2A9:
+		"000000" & X"000", -- 0x2AA:
+		"000000" & X"000", -- 0x2AB:
+		"000000" & X"000", -- 0x2AC:
+		"000000" & X"000", -- 0x2AD:
+		"000000" & X"000", -- 0x2AE:
+		"000000" & X"000", -- 0x2AF:
+		"000000" & X"000", -- 0x2B0:
+		"000000" & X"000", -- 0x2B1:
+		"000000" & X"000", -- 0x2B2:
+		"000000" & X"000", -- 0x2B3:
+		"000000" & X"000", -- 0x2B4:
+		"000000" & X"000", -- 0x2B5:
+		"000000" & X"000", -- 0x2B6:
+		"000000" & X"000", -- 0x2B7:
+		"000000" & X"000", -- 0x2B8:
+		"000000" & X"000", -- 0x2B9:
+		"000000" & X"000", -- 0x2BA:
+		"000000" & X"000", -- 0x2BB:
+		"000000" & X"000", -- 0x2BC:
+		"000000" & X"000", -- 0x2BD:
+		"000000" & X"000", -- 0x2BE:
+		"000000" & X"000", -- 0x2BF:
+		"000000" & X"000", -- 0x2C0:
+		"000000" & X"000", -- 0x2C1:
+		"000000" & X"000", -- 0x2C2:
+		"000000" & X"000", -- 0x2C3:
+		"000000" & X"000", -- 0x2C4:
+		"000000" & X"000", -- 0x2C5:
+		"000000" & X"000", -- 0x2C6:
+		"000000" & X"000", -- 0x2C7:
+		"000000" & X"000", -- 0x2C8:
+		"000000" & X"000", -- 0x2C9:
+		"000000" & X"000", -- 0x2CA:
+		"000000" & X"000", -- 0x2CB:
+		"000000" & X"000", -- 0x2CC:
+		"000000" & X"000", -- 0x2CD:
+		"000000" & X"000", -- 0x2CE:
+		"000000" & X"000", -- 0x2CF:
+		"000000" & X"000", -- 0x2D0:
+		"000000" & X"000", -- 0x2D1:
+		"000000" & X"000", -- 0x2D2:
+		"000000" & X"000", -- 0x2D3:
+		"000000" & X"000", -- 0x2D4:
+		"000000" & X"000", -- 0x2D5:
+		"000000" & X"000", -- 0x2D6:
+		"000000" & X"000", -- 0x2D7:
+		"000000" & X"000", -- 0x2D8:
+		"000000" & X"000", -- 0x2D9:
+		"000000" & X"000", -- 0x2DA:
+		"000000" & X"000", -- 0x2DB:
+		"000000" & X"000", -- 0x2DC:
+		"000000" & X"000", -- 0x2DD:
+		"000000" & X"000", -- 0x2DE:
+		"000000" & X"000", -- 0x2DF:
+		"000000" & X"000", -- 0x2E0:
+		"000000" & X"000", -- 0x2E1:
+		"000000" & X"000", -- 0x2E2:
+		"000000" & X"000", -- 0x2E3:
+		"000000" & X"000", -- 0x2E4:
+		"000000" & X"000", -- 0x2E5:
+		"000000" & X"000", -- 0x2E6:
+		"000000" & X"000", -- 0x2E7:
+		"000000" & X"000", -- 0x2E8:
+		"000000" & X"000", -- 0x2E9:
+		"000000" & X"000", -- 0x2EA:
+		"000000" & X"000", -- 0x2EB:
+		"000000" & X"000", -- 0x2EC:
+		"000000" & X"000", -- 0x2ED:
+		"000000" & X"000", -- 0x2EE:
+		"000000" & X"000", -- 0x2EF:
+		"000000" & X"000", -- 0x2F0:
+		"000000" & X"000", -- 0x2F1:
+		"000000" & X"000", -- 0x2F2:
+		"000000" & X"000", -- 0x2F3:
+		"000000" & X"000", -- 0x2F4:
+		"000000" & X"000", -- 0x2F5:
+		"000000" & X"000", -- 0x2F6:
+		"000000" & X"000", -- 0x2F7:
+		"000000" & X"000", -- 0x2F8:
+		"000000" & X"000", -- 0x2F9:
+		"000000" & X"000", -- 0x2FA:
+		"000000" & X"000", -- 0x2FB:
+		"000000" & X"000", -- 0x2FC:
+		"000000" & X"000", -- 0x2FD:
+		"000000" & X"000", -- 0x2FE:
+		"110000" & X"2FF", -- 0x2FF: JMP 0x2FF
+		"000000" & X"000", -- 0x300:
+		"000000" & X"000", -- 0x301:
+		"000000" & X"000", -- 0x302:
+		"000000" & X"000", -- 0x303:
+		"000000" & X"000", -- 0x304:
+		"000000" & X"000", -- 0x305:
+		"000000" & X"000", -- 0x306:
+		"000000" & X"000", -- 0x307:
+		"000000" & X"000", -- 0x308:
+		"000000" & X"000", -- 0x309:
+		"000000" & X"000", -- 0x30A:
+		"000000" & X"000", -- 0x30B:
+		"000000" & X"000", -- 0x30C:
+		"000000" & X"000", -- 0x30D:
+		"000000" & X"000", -- 0x30E:
+		"000000" & X"000", -- 0x30F:
+		"000000" & X"000", -- 0x310:
+		"000000" & X"000", -- 0x311:
+		"000000" & X"000", -- 0x312:
+		"000000" & X"000", -- 0x313:
+		"000000" & X"000", -- 0x314:
+		"000000" & X"000", -- 0x315:
+		"000000" & X"000", -- 0x316:
+		"000000" & X"000", -- 0x317:
+		"000000" & X"000", -- 0x318:
+		"000000" & X"000", -- 0x319:
+		"000000" & X"000", -- 0x31A:
+		"000000" & X"000", -- 0x31B:
+		"000000" & X"000", -- 0x31C:
+		"000000" & X"000", -- 0x31D:
+		"000000" & X"000", -- 0x31E:
+		"000000" & X"000", -- 0x31F:
+		"000000" & X"000", -- 0x320:
+		"000000" & X"000", -- 0x321:
+		"000000" & X"000", -- 0x322:
+		"000000" & X"000", -- 0x323:
+		"000000" & X"000", -- 0x324:
+		"000000" & X"000", -- 0x325:
+		"000000" & X"000", -- 0x326:
+		"000000" & X"000", -- 0x327:
+		"000000" & X"000", -- 0x328:
+		"000000" & X"000", -- 0x329:
+		"000000" & X"000", -- 0x32A:
+		"000000" & X"000", -- 0x32B:
+		"000000" & X"000", -- 0x32C:
+		"000000" & X"000", -- 0x32D:
+		"000000" & X"000", -- 0x32E:
+		"000000" & X"000", -- 0x32F:
+		"000000" & X"000", -- 0x330:
+		"000000" & X"000", -- 0x331:
+		"000000" & X"000", -- 0x332:
+		"000000" & X"000", -- 0x333:
+		"000000" & X"000", -- 0x334:
+		"000000" & X"000", -- 0x335:
+		"000000" & X"000", -- 0x336:
+		"000000" & X"000", -- 0x337:
+		"000000" & X"000", -- 0x338:
+		"000000" & X"000", -- 0x339:
+		"000000" & X"000", -- 0x33A:
+		"000000" & X"000", -- 0x33B:
+		"000000" & X"000", -- 0x33C:
+		"000000" & X"000", -- 0x33D:
+		"000000" & X"000", -- 0x33E:
+		"000000" & X"000", -- 0x33F:
+		"000000" & X"000", -- 0x340:
+		"000000" & X"000", -- 0x341:
+		"000000" & X"000", -- 0x342:
+		"000000" & X"000", -- 0x343:
+		"000000" & X"000", -- 0x344:
+		"000000" & X"000", -- 0x345:
+		"000000" & X"000", -- 0x346:
+		"000000" & X"000", -- 0x347:
+		"000000" & X"000", -- 0x348:
+		"000000" & X"000", -- 0x349:
+		"000000" & X"000", -- 0x34A:
+		"000000" & X"000", -- 0x34B:
+		"000000" & X"000", -- 0x34C:
+		"000000" & X"000", -- 0x34D:
+		"000000" & X"000", -- 0x34E:
+		"000000" & X"000", -- 0x34F:
+		"000000" & X"000", -- 0x350:
+		"000000" & X"000", -- 0x351:
+		"000000" & X"000", -- 0x352:
+		"000000" & X"000", -- 0x353:
+		"000000" & X"000", -- 0x354:
+		"000000" & X"000", -- 0x355:
+		"000000" & X"000", -- 0x356:
+		"000000" & X"000", -- 0x357:
+		"000000" & X"000", -- 0x358:
+		"000000" & X"000", -- 0x359:
+		"000000" & X"000", -- 0x35A:
+		"000000" & X"000", -- 0x35B:
+		"000000" & X"000", -- 0x35C:
+		"000000" & X"000", -- 0x35D:
+		"000000" & X"000", -- 0x35E:
+		"000000" & X"000", -- 0x35F:
+		"000000" & X"000", -- 0x360:
+		"000000" & X"000", -- 0x361:
+		"000000" & X"000", -- 0x362:
+		"000000" & X"000", -- 0x363:
+		"000000" & X"000", -- 0x364:
+		"000000" & X"000", -- 0x365:
+		"000000" & X"000", -- 0x366:
+		"000000" & X"000", -- 0x367:
+		"000000" & X"000", -- 0x368:
+		"000000" & X"000", -- 0x369:
+		"000000" & X"000", -- 0x36A:
+		"000000" & X"000", -- 0x36B:
+		"000000" & X"000", -- 0x36C:
+		"000000" & X"000", -- 0x36D:
+		"000000" & X"000", -- 0x36E:
+		"000000" & X"000", -- 0x36F:
+		"000000" & X"000", -- 0x370:
+		"000000" & X"000", -- 0x371:
+		"000000" & X"000", -- 0x372:
+		"000000" & X"000", -- 0x373:
+		"000000" & X"000", -- 0x374:
+		"000000" & X"000", -- 0x375:
+		"000000" & X"000", -- 0x376:
+		"000000" & X"000", -- 0x377:
+		"000000" & X"000", -- 0x378:
+		"000000" & X"000", -- 0x379:
+		"000000" & X"000", -- 0x37A:
+		"000000" & X"000", -- 0x37B:
+		"000000" & X"000", -- 0x37C:
+		"000000" & X"000", -- 0x37D:
+		"000000" & X"000", -- 0x37E:
+		"000000" & X"000", -- 0x37F:
+		"000000" & X"000", -- 0x380:
+		"000000" & X"000", -- 0x381:
+		"000000" & X"000", -- 0x382:
+		"000000" & X"000", -- 0x383:
+		"000000" & X"000", -- 0x384:
+		"000000" & X"000", -- 0x385:
+		"000000" & X"000", -- 0x386:
+		"000000" & X"000", -- 0x387:
+		"000000" & X"000", -- 0x388:
+		"000000" & X"000", -- 0x389:
+		"000000" & X"000", -- 0x38A:
+		"000000" & X"000", -- 0x38B:
+		"000000" & X"000", -- 0x38C:
+		"000000" & X"000", -- 0x38D:
+		"000000" & X"000", -- 0x38E:
+		"000000" & X"000", -- 0x38F:
+		"000000" & X"000", -- 0x390:
+		"000000" & X"000", -- 0x391:
+		"000000" & X"000", -- 0x392:
+		"000000" & X"000", -- 0x393:
+		"000000" & X"000", -- 0x394:
+		"000000" & X"000", -- 0x395:
+		"000000" & X"000", -- 0x396:
+		"000000" & X"000", -- 0x397:
+		"000000" & X"000", -- 0x398:
+		"000000" & X"000", -- 0x399:
+		"000000" & X"000", -- 0x39A:
+		"000000" & X"000", -- 0x39B:
+		"000000" & X"000", -- 0x39C:
+		"000000" & X"000", -- 0x39D:
+		"000000" & X"000", -- 0x39E:
+		"000000" & X"000", -- 0x39F:
+		"000000" & X"000", -- 0x3A0:
+		"000000" & X"000", -- 0x3A1:
+		"000000" & X"000", -- 0x3A2:
+		"000000" & X"000", -- 0x3A3:
+		"000000" & X"000", -- 0x3A4:
+		"000000" & X"000", -- 0x3A5:
+		"000000" & X"000", -- 0x3A6:
+		"000000" & X"000", -- 0x3A7:
+		"000000" & X"000", -- 0x3A8:
+		"000000" & X"000", -- 0x3A9:
+		"000000" & X"000", -- 0x3AA:
+		"000000" & X"000", -- 0x3AB:
+		"000000" & X"000", -- 0x3AC:
+		"000000" & X"000", -- 0x3AD:
+		"000000" & X"000", -- 0x3AE:
+		"000000" & X"000", -- 0x3AF:
+		"000000" & X"000", -- 0x3B0:
+		"000000" & X"000", -- 0x3B1:
+		"000000" & X"000", -- 0x3B2:
+		"000000" & X"000", -- 0x3B3:
+		"000000" & X"000", -- 0x3B4:
+		"000000" & X"000", -- 0x3B5:
+		"000000" & X"000", -- 0x3B6:
+		"000000" & X"000", -- 0x3B7:
+		"000000" & X"000", -- 0x3B8:
+		"000000" & X"000", -- 0x3B9:
+		"000000" & X"000", -- 0x3BA:
+		"000000" & X"000", -- 0x3BB:
+		"000000" & X"000", -- 0x3BC:
+		"000000" & X"000", -- 0x3BD:
+		"000000" & X"000", -- 0x3BE:
+		"000000" & X"000", -- 0x3BF:
+		"000000" & X"000", -- 0x3C0:
+		"000000" & X"000", -- 0x3C1:
+		"000000" & X"000", -- 0x3C2:
+		"000000" & X"000", -- 0x3C3:
+		"000000" & X"000", -- 0x3C4:
+		"000000" & X"000", -- 0x3C5:
+		"000000" & X"000", -- 0x3C6:
+		"000000" & X"000", -- 0x3C7:
+		"000000" & X"000", -- 0x3C8:
+		"000000" & X"000", -- 0x3C9:
+		"000000" & X"000", -- 0x3CA:
+		"000000" & X"000", -- 0x3CB:
+		"000000" & X"000", -- 0x3CC:
+		"000000" & X"000", -- 0x3CD:
+		"000000" & X"000", -- 0x3CE:
+		"000000" & X"000", -- 0x3CF:
+		"000000" & X"000", -- 0x3D0:
+		"000000" & X"000", -- 0x3D1:
+		"000000" & X"000", -- 0x3D2:
+		"000000" & X"000", -- 0x3D3:
+		"000000" & X"000", -- 0x3D4:
+		"000000" & X"000", -- 0x3D5:
+		"000000" & X"000", -- 0x3D6:
+		"000000" & X"000", -- 0x3D7:
+		"000000" & X"000", -- 0x3D8:
+		"000000" & X"000", -- 0x3D9:
+		"000000" & X"000", -- 0x3DA:
+		"000000" & X"000", -- 0x3DB:
+		"000000" & X"000", -- 0x3DC:
+		"000000" & X"000", -- 0x3DD:
+		"000000" & X"000", -- 0x3DE:
+		"000000" & X"000", -- 0x3DF:
+		"000000" & X"000", -- 0x3E0:
+		"000000" & X"000", -- 0x3E1:
+		"000000" & X"000", -- 0x3E2:
+		"000000" & X"000", -- 0x3E3:
+		"000000" & X"000", -- 0x3E4:
+		"000000" & X"000", -- 0x3E5:
+		"000000" & X"000", -- 0x3E6:
+		"000000" & X"000", -- 0x3E7:
+		"000000" & X"000", -- 0x3E8:
+		"000000" & X"000", -- 0x3E9:
+		"000000" & X"000", -- 0x3EA:
+		"000000" & X"000", -- 0x3EB:
+		"000000" & X"000", -- 0x3EC:
+		"000000" & X"000", -- 0x3ED:
+		"000000" & X"000", -- 0x3EE:
+		"000000" & X"000", -- 0x3EF:
+		"000000" & X"000", -- 0x3F0:
+		"000000" & X"000", -- 0x3F1:
+		"000000" & X"000", -- 0x3F2:
+		"000000" & X"000", -- 0x3F3:
+		"000000" & X"000", -- 0x3F4:
+		"000000" & X"000", -- 0x3F5:
+		"000000" & X"000", -- 0x3F6:
+		"000000" & X"000", -- 0x3F7:
+		"000000" & X"000", -- 0x3F8:
+		"000000" & X"000", -- 0x3F9:
+		"000000" & X"000", -- 0x3FA:
+		"000000" & X"000", -- 0x3FB:
+		"000000" & X"000", -- 0x3FC:
+		"000000" & X"000", -- 0x3FD:
+		"000000" & X"000", -- 0x3FE:
+		"110000" & X"3FF"  -- 0x3FF: JMP 0x3FF
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: inst_addr_t;
+	signal jtag_ld_dout		: inst_t;
+	signal jtag_ld_din		: inst_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (31 downto 0);
+	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
+	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;
diff --git a/lib/CPUs/JCpu/src/itest_xrom.vhdl b/lib/CPUs/JCpu/src/itest_xrom.vhdl
new file mode 100644
index 0000000..4206abc
--- /dev/null
+++ b/lib/CPUs/JCpu/src/itest_xrom.vhdl
@@ -0,0 +1,317 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY xrom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  dmem_addr_t;
+	dout		: out dmem_data_t
+	);
+END xrom;
+
+ARCHITECTURE itest OF xrom IS 
+
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+
+	-- Assembled from itest.jsm
+	constant xmem_rom : xmem_rom_t :=
+	(
+		X"48", -- 0x00
+		X"61", -- 0x01
+		X"6C", -- 0x02
+		X"6C", -- 0x03
+		X"6F", -- 0x04
+		X"00", -- 0x05
+		X"00", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"00", -- 0x17
+		X"00", -- 0x18
+		X"00", -- 0x19
+		X"00", -- 0x1A
+		X"00", -- 0x1B
+		X"00", -- 0x1C
+		X"00", -- 0x1D
+		X"00", -- 0x1E
+		X"00", -- 0x1F
+		X"00", -- 0x20
+		X"00", -- 0x21
+		X"00", -- 0x22
+		X"00", -- 0x23
+		X"00", -- 0x24
+		X"00", -- 0x25
+		X"00", -- 0x26
+		X"00", -- 0x27
+		X"00", -- 0x28
+		X"00", -- 0x29
+		X"00", -- 0x2A
+		X"00", -- 0x2B
+		X"00", -- 0x2C
+		X"00", -- 0x2D
+		X"00", -- 0x2E
+		X"00", -- 0x2F
+		X"00", -- 0x30
+		X"00", -- 0x31
+		X"00", -- 0x32
+		X"00", -- 0x33
+		X"00", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end itest;
+
diff --git a/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl b/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl
new file mode 100644
index 0000000..60a84ac
--- /dev/null
+++ b/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl
@@ -0,0 +1,413 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY xrom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		dout		: out dmem_data_t
+	);
+	
+END xrom;
+
+ARCHITECTURE loadable OF xrom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from itest.jsm
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+	signal xmem_rom : xmem_rom_t :=
+	(
+		X"48", -- 0x00
+		X"61", -- 0x01
+		X"6C", -- 0x02
+		X"6C", -- 0x03
+		X"6F", -- 0x04
+		X"00", -- 0x05
+		X"00", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"00", -- 0x17
+		X"00", -- 0x18
+		X"00", -- 0x19
+		X"00", -- 0x1A
+		X"00", -- 0x1B
+		X"00", -- 0x1C
+		X"00", -- 0x1D
+		X"00", -- 0x1E
+		X"00", -- 0x1F
+		X"00", -- 0x20
+		X"00", -- 0x21
+		X"00", -- 0x22
+		X"00", -- 0x23
+		X"00", -- 0x24
+		X"00", -- 0x25
+		X"00", -- 0x26
+		X"00", -- 0x27
+		X"00", -- 0x28
+		X"00", -- 0x29
+		X"00", -- 0x2A
+		X"00", -- 0x2B
+		X"00", -- 0x2C
+		X"00", -- 0x2D
+		X"00", -- 0x2E
+		X"00", -- 0x2F
+		X"00", -- 0x30
+		X"00", -- 0x31
+		X"00", -- 0x32
+		X"00", -- 0x33
+		X"00", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: dmem_addr_t;
+	signal jtag_ld_dout		: dmem_data_t;
+	signal jtag_ld_din		: dmem_data_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (15 downto 0);
+	constant id : unsigned (15 downto 0) := X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
+	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;
diff --git a/lib/CPUs/JCpu/src/mul8x8_irom.vhdl b/lib/CPUs/JCpu/src/mul8x8_irom.vhdl
new file mode 100644
index 0000000..3b0de3b
--- /dev/null
+++ b/lib/CPUs/JCpu/src/mul8x8_irom.vhdl
@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY irom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  inst_addr_t;
+	dout		: out inst_t
+	);
+END irom;
+
+ARCHITECTURE mul8x8 OF irom IS 
+
+	type imem_rom_t is array (0 to 26) of inst_t;
+
+	-- Assembled from mul8x8.jsm
+	constant imem_rom : imem_rom_t :=
+	(
+		"110000" & X"001", -- 0x000: JMP 0x001
+		"000011" & X"450", -- 0x001: MOV R00, 0x45
+		"000011" & X"F51", -- 0x002: MOV R01, 0xF5
+		"111011" & X"005", -- 0x003: CALL 0x005
+		"110000" & X"004", -- 0x004: JMP 0x004
+		"111100" & X"002", -- 0x005: PUSH R02
+		"111100" & X"003", -- 0x006: PUSH R03
+		"111100" & X"004", -- 0x007: PUSH R04
+		"000010" & X"014", -- 0x008: MOV R04, R01
+		"000011" & X"001", -- 0x009: MOV R01, 0x00
+		"000011" & X"002", -- 0x00A: MOV R02, 0x00
+		"000011" & X"003", -- 0x00B: MOV R03, 0x00
+		"001111" & X"014", -- 0x00C: CMP R04, 0x01
+		"111001" & X"015", -- 0x00D: JEQ 0x015
+		"011111" & X"004", -- 0x00E: SHR R04
+		"110100" & X"012", -- 0x00F: JNC 0x012
+		"010000" & X"002", -- 0x010: ADD R02, R00
+		"010010" & X"013", -- 0x011: ADDC R03, R01
+		"011110" & X"000", -- 0x012: SHL R00
+		"100010" & X"001", -- 0x013: ROLC R01
+		"110000" & X"00C", -- 0x014: JMP 0x00C
+		"010000" & X"020", -- 0x015: ADD R00, R02
+		"010010" & X"031", -- 0x016: ADDC R01, R03
+		"111101" & X"004", -- 0x017: POP R04
+		"111101" & X"003", -- 0x018: POP R03
+		"111101" & X"002", -- 0x019: POP R02
+		"111110" & X"000"  -- 0x01A: RET
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end mul8x8;
+
diff --git a/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl b/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl
new file mode 100644
index 0000000..4303d08
--- /dev/null
+++ b/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl
@@ -0,0 +1,1181 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY irom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  inst_addr_t;
+		dout		: out inst_t
+	);
+	
+END irom;
+
+ARCHITECTURE loadable OF irom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from mul8x8.jsm
+	type imem_rom_t is array (0 to 1023) of inst_t;
+	signal imem_rom : imem_rom_t :=
+	(
+		"110000" & X"001", -- 0x000: JMP 0x001
+		"000011" & X"450", -- 0x001: MOV R00, 0x45
+		"000011" & X"F51", -- 0x002: MOV R01, 0xF5
+		"111011" & X"005", -- 0x003: CALL 0x005
+		"110000" & X"004", -- 0x004: JMP 0x004
+		"111100" & X"002", -- 0x005: PUSH R02
+		"111100" & X"003", -- 0x006: PUSH R03
+		"111100" & X"004", -- 0x007: PUSH R04
+		"000010" & X"014", -- 0x008: MOV R04, R01
+		"000011" & X"001", -- 0x009: MOV R01, 0x00
+		"000011" & X"002", -- 0x00A: MOV R02, 0x00
+		"000011" & X"003", -- 0x00B: MOV R03, 0x00
+		"001111" & X"014", -- 0x00C: CMP R04, 0x01
+		"111001" & X"015", -- 0x00D: JEQ 0x015
+		"011111" & X"004", -- 0x00E: SHR R04
+		"110100" & X"012", -- 0x00F: JNC 0x012
+		"010000" & X"002", -- 0x010: ADD R02, R00
+		"010010" & X"013", -- 0x011: ADDC R03, R01
+		"011110" & X"000", -- 0x012: SHL R00
+		"100010" & X"001", -- 0x013: ROLC R01
+		"110000" & X"00C", -- 0x014: JMP 0x00C
+		"010000" & X"020", -- 0x015: ADD R00, R02
+		"010010" & X"031", -- 0x016: ADDC R01, R03
+		"111101" & X"004", -- 0x017: POP R04
+		"111101" & X"003", -- 0x018: POP R03
+		"111101" & X"002", -- 0x019: POP R02
+		"111110" & X"000", -- 0x01A: RET
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000"
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: inst_addr_t;
+	signal jtag_ld_dout		: inst_t;
+	signal jtag_ld_din		: inst_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (31 downto 0);
+	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
+	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;
diff --git a/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl b/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl
new file mode 100644
index 0000000..508e8cf
--- /dev/null
+++ b/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl
@@ -0,0 +1,317 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY xrom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  dmem_addr_t;
+	dout		: out dmem_data_t
+	);
+END xrom;
+
+ARCHITECTURE mul8x8 OF xrom IS 
+
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+
+	-- Assembled from mul8x8.jsm
+	constant xmem_rom : xmem_rom_t :=
+	(
+		X"00", -- 0x00
+		X"00", -- 0x01
+		X"00", -- 0x02
+		X"00", -- 0x03
+		X"00", -- 0x04
+		X"00", -- 0x05
+		X"00", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"00", -- 0x17
+		X"00", -- 0x18
+		X"00", -- 0x19
+		X"00", -- 0x1A
+		X"00", -- 0x1B
+		X"00", -- 0x1C
+		X"00", -- 0x1D
+		X"00", -- 0x1E
+		X"00", -- 0x1F
+		X"00", -- 0x20
+		X"00", -- 0x21
+		X"00", -- 0x22
+		X"00", -- 0x23
+		X"00", -- 0x24
+		X"00", -- 0x25
+		X"00", -- 0x26
+		X"00", -- 0x27
+		X"00", -- 0x28
+		X"00", -- 0x29
+		X"00", -- 0x2A
+		X"00", -- 0x2B
+		X"00", -- 0x2C
+		X"00", -- 0x2D
+		X"00", -- 0x2E
+		X"00", -- 0x2F
+		X"00", -- 0x30
+		X"00", -- 0x31
+		X"00", -- 0x32
+		X"00", -- 0x33
+		X"00", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end mul8x8;
+
diff --git a/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl b/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl
new file mode 100644
index 0000000..a75d090
--- /dev/null
+++ b/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl
@@ -0,0 +1,413 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY xrom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		dout		: out dmem_data_t
+	);
+	
+END xrom;
+
+ARCHITECTURE loadable OF xrom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from mul8x8.jsm
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+	signal xmem_rom : xmem_rom_t :=
+	(
+		X"00", -- 0x00
+		X"00", -- 0x01
+		X"00", -- 0x02
+		X"00", -- 0x03
+		X"00", -- 0x04
+		X"00", -- 0x05
+		X"00", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"00", -- 0x17
+		X"00", -- 0x18
+		X"00", -- 0x19
+		X"00", -- 0x1A
+		X"00", -- 0x1B
+		X"00", -- 0x1C
+		X"00", -- 0x1D
+		X"00", -- 0x1E
+		X"00", -- 0x1F
+		X"00", -- 0x20
+		X"00", -- 0x21
+		X"00", -- 0x22
+		X"00", -- 0x23
+		X"00", -- 0x24
+		X"00", -- 0x25
+		X"00", -- 0x26
+		X"00", -- 0x27
+		X"00", -- 0x28
+		X"00", -- 0x29
+		X"00", -- 0x2A
+		X"00", -- 0x2B
+		X"00", -- 0x2C
+		X"00", -- 0x2D
+		X"00", -- 0x2E
+		X"00", -- 0x2F
+		X"00", -- 0x30
+		X"00", -- 0x31
+		X"00", -- 0x32
+		X"00", -- 0x33
+		X"00", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: dmem_addr_t;
+	signal jtag_ld_dout		: dmem_data_t;
+	signal jtag_ld_din		: dmem_data_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (15 downto 0);
+	constant id : unsigned (15 downto 0) := X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
+	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;
diff --git a/lib/CPUs/JCpu/src/reti_issue_irom.vhdl b/lib/CPUs/JCpu/src/reti_issue_irom.vhdl
new file mode 100644
index 0000000..9355a7d
--- /dev/null
+++ b/lib/CPUs/JCpu/src/reti_issue_irom.vhdl
@@ -0,0 +1,89 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY irom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  inst_addr_t;
+	dout		: out inst_t
+	);
+END irom;
+
+ARCHITECTURE reti_issue OF irom IS 
+
+	type imem_rom_t is array (0 to 27) of inst_t;
+
+	-- Assembled from reti_issue.jsm
+	constant imem_rom : imem_rom_t :=
+	(
+		"110000" & X"002", -- 0x000: JMP 0x002
+		"111111" & X"000", -- 0x001: RETI
+		"000011" & X"050", -- 0x002: MOV R00, 0x05
+		"100110" & X"030", -- 0x003: COUT (0x03), R00
+		"000011" & X"000", -- 0x004: MOV R00, 0x00
+		"000000" & X"000", -- 0x005: NOP
+		"010001" & X"010", -- 0x006: INC R00
+		"000000" & X"000", -- 0x007: NOP
+		"111011" & X"01B", -- 0x008: CALL 0x01B
+		"000000" & X"000", -- 0x009: NOP
+		"111100" & X"003", -- 0x00A: PUSH R03
+		"000000" & X"000", -- 0x00B: NOP
+		"111100" & X"002", -- 0x00C: PUSH R02
+		"000000" & X"000", -- 0x00D: NOP
+		"111100" & X"001", -- 0x00E: PUSH R01
+		"000000" & X"000", -- 0x00F: NOP
+		"111100" & X"000", -- 0x010: PUSH R00
+		"000000" & X"000", -- 0x011: NOP
+		"111101" & X"000", -- 0x012: POP R00
+		"000000" & X"000", -- 0x013: NOP
+		"111101" & X"001", -- 0x014: POP R01
+		"000000" & X"000", -- 0x015: NOP
+		"111101" & X"002", -- 0x016: POP R02
+		"000000" & X"000", -- 0x017: NOP
+		"111101" & X"003", -- 0x018: POP R03
+		"000000" & X"000", -- 0x019: NOP
+		"110000" & X"005", -- 0x01A: JMP 0x005
+		"111110" & X"000"  -- 0x01B: RET
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end reti_issue;
+
diff --git a/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl b/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl
new file mode 100644
index 0000000..d1b4bd1
--- /dev/null
+++ b/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl
@@ -0,0 +1,1181 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY irom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  inst_addr_t;
+		dout		: out inst_t
+	);
+	
+END irom;
+
+ARCHITECTURE loadable OF irom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from reti_issue.jsm
+	type imem_rom_t is array (0 to 1023) of inst_t;
+	signal imem_rom : imem_rom_t :=
+	(
+		"110000" & X"002", -- 0x000: JMP 0x002
+		"111111" & X"000", -- 0x001: RETI
+		"000011" & X"050", -- 0x002: MOV R00, 0x05
+		"100110" & X"030", -- 0x003: COUT (0x03), R00
+		"000011" & X"000", -- 0x004: MOV R00, 0x00
+		"000000" & X"000", -- 0x005: NOP
+		"010001" & X"010", -- 0x006: INC R00
+		"000000" & X"000", -- 0x007: NOP
+		"111011" & X"01B", -- 0x008: CALL 0x01B
+		"000000" & X"000", -- 0x009: NOP
+		"111100" & X"003", -- 0x00A: PUSH R03
+		"000000" & X"000", -- 0x00B: NOP
+		"111100" & X"002", -- 0x00C: PUSH R02
+		"000000" & X"000", -- 0x00D: NOP
+		"111100" & X"001", -- 0x00E: PUSH R01
+		"000000" & X"000", -- 0x00F: NOP
+		"111100" & X"000", -- 0x010: PUSH R00
+		"000000" & X"000", -- 0x011: NOP
+		"111101" & X"000", -- 0x012: POP R00
+		"000000" & X"000", -- 0x013: NOP
+		"111101" & X"001", -- 0x014: POP R01
+		"000000" & X"000", -- 0x015: NOP
+		"111101" & X"002", -- 0x016: POP R02
+		"000000" & X"000", -- 0x017: NOP
+		"111101" & X"003", -- 0x018: POP R03
+		"000000" & X"000", -- 0x019: NOP
+		"110000" & X"005", -- 0x01A: JMP 0x005
+		"111110" & X"000", -- 0x01B: RET
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
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+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000",
+		"000000" & X"000"
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: inst_addr_t;
+	signal jtag_ld_dout		: inst_t;
+	signal jtag_ld_din		: inst_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (31 downto 0);
+	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
+	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;
diff --git a/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl b/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl
new file mode 100644
index 0000000..a7a33f9
--- /dev/null
+++ b/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl
@@ -0,0 +1,317 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY xrom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  dmem_addr_t;
+	dout		: out dmem_data_t
+	);
+END xrom;
+
+ARCHITECTURE reti_issue OF xrom IS 
+
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+
+	-- Assembled from reti_issue.jsm
+	constant xmem_rom : xmem_rom_t :=
+	(
+		X"00", -- 0x00
+		X"00", -- 0x01
+		X"00", -- 0x02
+		X"00", -- 0x03
+		X"00", -- 0x04
+		X"00", -- 0x05
+		X"00", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"00", -- 0x17
+		X"00", -- 0x18
+		X"00", -- 0x19
+		X"00", -- 0x1A
+		X"00", -- 0x1B
+		X"00", -- 0x1C
+		X"00", -- 0x1D
+		X"00", -- 0x1E
+		X"00", -- 0x1F
+		X"00", -- 0x20
+		X"00", -- 0x21
+		X"00", -- 0x22
+		X"00", -- 0x23
+		X"00", -- 0x24
+		X"00", -- 0x25
+		X"00", -- 0x26
+		X"00", -- 0x27
+		X"00", -- 0x28
+		X"00", -- 0x29
+		X"00", -- 0x2A
+		X"00", -- 0x2B
+		X"00", -- 0x2C
+		X"00", -- 0x2D
+		X"00", -- 0x2E
+		X"00", -- 0x2F
+		X"00", -- 0x30
+		X"00", -- 0x31
+		X"00", -- 0x32
+		X"00", -- 0x33
+		X"00", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end reti_issue;
+
diff --git a/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl b/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl
new file mode 100644
index 0000000..244c1b5
--- /dev/null
+++ b/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl
@@ -0,0 +1,413 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY xrom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		dout		: out dmem_data_t
+	);
+	
+END xrom;
+
+ARCHITECTURE loadable OF xrom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from reti_issue.jsm
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+	signal xmem_rom : xmem_rom_t :=
+	(
+		X"00", -- 0x00
+		X"00", -- 0x01
+		X"00", -- 0x02
+		X"00", -- 0x03
+		X"00", -- 0x04
+		X"00", -- 0x05
+		X"00", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"00", -- 0x17
+		X"00", -- 0x18
+		X"00", -- 0x19
+		X"00", -- 0x1A
+		X"00", -- 0x1B
+		X"00", -- 0x1C
+		X"00", -- 0x1D
+		X"00", -- 0x1E
+		X"00", -- 0x1F
+		X"00", -- 0x20
+		X"00", -- 0x21
+		X"00", -- 0x22
+		X"00", -- 0x23
+		X"00", -- 0x24
+		X"00", -- 0x25
+		X"00", -- 0x26
+		X"00", -- 0x27
+		X"00", -- 0x28
+		X"00", -- 0x29
+		X"00", -- 0x2A
+		X"00", -- 0x2B
+		X"00", -- 0x2C
+		X"00", -- 0x2D
+		X"00", -- 0x2E
+		X"00", -- 0x2F
+		X"00", -- 0x30
+		X"00", -- 0x31
+		X"00", -- 0x32
+		X"00", -- 0x33
+		X"00", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: dmem_addr_t;
+	signal jtag_ld_dout		: dmem_data_t;
+	signal jtag_ld_din		: dmem_data_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (15 downto 0);
+	constant id : unsigned (15 downto 0) := X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
+	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;
diff --git a/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd b/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd
new file mode 100644
index 0000000..ede20d5
--- /dev/null
+++ b/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd
@@ -0,0 +1,129 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for embedded cpu with rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY tb_cpu_embedded IS
+END tb_cpu_embedded;
+
+ARCHITECTURE behavior OF tb_cpu_embedded IS 
+
+	COMPONENT cpu_embedded
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		int_in		: in  STD_LOGIC;
+		int_ack		: out  STD_LOGIC;
+		xmem_wait	: in STD_LOGIC;
+		xmem_we		: out STD_LOGIC;
+		xmem_re		: out STD_LOGIC;
+		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
+		io_sel		: out STD_LOGIC
+	);
+	END COMPONENT;
+
+	constant CLK_PERIOD : time := 10 ns;
+	type sram_t is array (integer range <>) of dmem_data_t;
+	signal rst : std_logic := '1';
+	signal clk : std_logic := '1';
+	signal ce  : std_logic := '0';
+	signal int_in : std_logic := '0';
+	signal int_ack : std_logic;
+	signal xmem_wait : std_logic := '0';
+	signal xmem_din : dmem_data_t := (others => '-');
+	signal xmem_dout : dmem_data_t;
+	signal xmem_addr : dmem_addr_t;
+	signal xmem_we : std_logic;
+	signal xmem_re : std_logic;
+	signal io_sel : std_logic;
+	signal sram : sram_t(0 to 2**dmem_addr_t'length-1);
+	
+
+BEGIN
+
+uut: cpu_embedded
+	PORT MAP(
+		rst => rst,
+		clk => clk,
+		ce => ce,
+		int_in => int_in,
+		int_ack => int_ack,
+		xmem_wait => xmem_wait,
+		xmem_we => xmem_we,
+		xmem_re => xmem_re,
+		xmem_din => xmem_din,
+		xmem_dout => xmem_dout,
+		xmem_addr => xmem_addr,
+		io_sel => io_sel
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		rst <= '0';
+		wait for 2*CLK_PERIOD;
+	
+		wait until rising_edge(clk);
+		ce <= '1';
+	
+		wait for 1000*CLK_PERIOD;
+
+		assert false report "Test finished" severity error;
+		wait; 
+	
+	end process;
+
+SRAM_RW: process(rst, clk, xmem_addr, xmem_dout, xmem_we)
+	begin
+		if (rst = '1') then
+			xmem_din <= X"00";
+		elsif rising_edge(clk) then
+			if io_sel = '0' then
+				if xmem_we = '1' then	
+					sram(to_integer(xmem_addr)) <= xmem_dout;
+				end if;	
+				xmem_din <= to_01(sram(to_integer(xmem_addr)));
+			else
+				xmem_din <= X"FF";
+			end if;	
+		end if;
+	end process;
+	
+END;
diff --git a/lib/CPUs/JCpu/src/tb_cpu_itest.vhd b/lib/CPUs/JCpu/src/tb_cpu_itest.vhd
new file mode 100644
index 0000000..80d8c43
--- /dev/null
+++ b/lib/CPUs/JCpu/src/tb_cpu_itest.vhd
@@ -0,0 +1,218 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Formal test of correct function of JCPU,
+--            also writes 'opc.lst' for JASM-assembler
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.cpu_pkg.all;
+use work.PCK_FIO.all;
+
+ENTITY tb_cpu IS
+END tb_cpu;
+
+ARCHITECTURE behavior OF tb_cpu IS 
+
+	COMPONENT cpu
+	Generic (
+		use_instr_register	: boolean;
+		use_ctrl_rom		: boolean
+	);
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		int_in		: in  STD_LOGIC;
+		int_ack		: out  STD_LOGIC;
+		xmem_wait	: in   STD_LOGIC;
+		xmem_we		: out  STD_LOGIC;
+		xmem_re		: out  STD_LOGIC;
+		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
+		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_addr	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		io_sel		: out  STD_LOGIC
+		
+	);
+	END COMPONENT;
+
+	COMPONENT irom
+		Port (
+			clk			: in  STD_LOGIC;
+			ce			: in  STD_LOGIC;
+			addr		: in  inst_addr_t;
+			dout		: out inst_t
+		);
+	END COMPONENT;
+
+	constant CLK_PERIOD : time := 10 ns;
+	type prom_t is array (integer range <>) of inst_t;
+	type sram_t is array (integer range <>) of dmem_data_t;
+	signal rst : std_logic := '1';
+	signal clk : std_logic := '1';
+	signal ce  : std_logic := '0';
+	signal int_in : std_logic := '0';
+	signal int_ack : std_logic;
+	signal xmem_wait : std_logic := '1';
+	signal irom_data	: unsigned (IMEM_DATA_WIDTH-1 downto 0) := (others => '-');
+	signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+	signal xmem_din : dmem_data_t := (others => '-');
+	signal xmem_dout : dmem_data_t;
+	signal xmem_addr : unsigned (DMEM_DATA_WIDTH-1 downto 0);
+	signal xmem_we : std_logic;
+	signal xmem_re : std_logic;
+	signal io_sel : std_logic;
+	signal sram : sram_t(0 to 2**DMEM_DATA_WIDTH-1);
+	
+	type reg_t is record
+		revision : dmem_data_t;
+		testid : dmem_data_t;
+		interrupt : std_logic;
+	end record;	
+	
+	signal reg : reg_t;
+	
+
+BEGIN
+
+	int_in <= reg.interrupt;
+uut: cpu
+	GENERIC MAP
+	(	
+		use_instr_register	=> false,
+		use_ctrl_rom		=> true
+	)
+	PORT MAP(
+		rst => rst,
+		clk => clk,
+		ce => ce,
+		int_in => int_in,
+		int_ack => int_ack,
+		xmem_wait => xmem_wait,
+		xmem_we => xmem_we,
+		xmem_re => xmem_re,
+		instr_din => irom_data,
+		instr_addr => irom_addr,
+		xmem_din => xmem_din,
+		xmem_dout => xmem_dout,
+		xmem_addr => xmem_addr,
+		io_sel => io_sel
+	);
+
+the_irom: irom
+	PORT MAP(
+		clk			=> clk,
+		ce			=> ce,
+		addr		=> irom_addr,
+		dout 		=> irom_data
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+XWAIT_GEN:process(rst, clk)
+	variable cnt : unsigned(3 downto 0);
+	begin	
+	if (rst = '1') then
+		cnt := (others => '1');
+	elsif rising_edge(clk) then
+		if cnt /= "0000" then
+			cnt := cnt - 1;
+		else
+			cnt := (others => '1');
+			xmem_wait <= not xmem_wait;
+		end if;
+	end if;
+	end process;
+
+STIMULUS: process
+	file RESULT:        text open write_mode is "../tools/opc.list"; 
+	variable L:         line;
+
+	begin
+
+		for i in 0 to instr_name_array'length-1 loop
+			fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i));
+		end loop;	
+
+		wait for 3*CLK_PERIOD;
+		rst <= '0';
+		wait for 2*CLK_PERIOD;
+	
+		wait until rising_edge(clk);
+		ce <= '1';
+	
+		assert false report "Test finished" severity error;
+		wait; 
+	
+	end process;
+
+SRAM_RW: process(rst, clk)
+	begin
+		if (rst = '1') then
+			reg.revision <= (others => '0');
+			reg.testid <= (others => '0');
+			reg.interrupt <= '0';
+		elsif rising_edge(clk) then
+			if int_ack = '1' then
+--				reg.interrupt <= '0';
+			end if;	
+			if xmem_we = '1' then	
+				if io_sel = '0' then
+					sram(to_integer(xmem_addr)) <= xmem_dout;
+				else	
+					case xmem_addr is
+						when X"00" =>
+							reg.revision <= xmem_dout;
+						when X"01" =>
+							reg.testid <= xmem_dout;
+						when X"02" =>
+							reg.interrupt <= xmem_dout(0);
+						when others => null;
+					end case;
+				end if;	
+			else
+				if io_sel = '0' then
+					xmem_din <= to_01(sram(to_integer(xmem_addr)));
+				else
+					case xmem_addr is
+						when X"00" =>
+							xmem_din <= reg.revision;
+						when X"01" =>
+							xmem_din <= reg.testid;
+						when others =>
+							xmem_din <= X"BC";
+					end case;
+				end if;				
+			end if;	
+		end if;
+	end process;
+	
+END;
diff --git a/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj b/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj
new file mode 100644
index 0000000..18718bf
--- /dev/null
+++ b/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj
@@ -0,0 +1,10 @@
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu_pkg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\stack_ctrl.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\reg_dual.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\pc.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\int_ctrl.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\dpath_ctrl.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipreg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipram.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\alu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu.vhd"
diff --git a/lib/CPUs/JCpu/tools/eval_scan.rb b/lib/CPUs/JCpu/tools/eval_scan.rb
new file mode 100644
index 0000000..0c38397
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/eval_scan.rb
@@ -0,0 +1,42 @@
+#!/usr/bin/env ruby
+
+str1 = %Q!lbl:		dc		"Hallo", ", ", 0, 1, " der","Jens"!
+
+i=0;
+
+def get_stri_lit (str)
+	res = [""];
+	state = "out"
+	
+	j = 0;
+	k = 0;
+	for i in (0..str.length-1)
+		c = str[i];
+		nstate = state
+		case state 
+		when "out"
+			if c == "\""[0]
+				nstate = "in"
+			end
+		when "in"	
+			if c == "\""[0]
+				nstate = "out"
+				if j > 0
+					k = k + 1;
+					res[k] = ""
+				end	
+			else
+				res[k] = res[k] + format("%c", c);
+				j = j + 1;
+			end
+		end
+		state = nstate
+	end;
+	return res
+end		
+	
+get_stri_lit(str1).each do |word|
+	puts word
+end	
+ 	
+ 
\ No newline at end of file
diff --git a/lib/CPUs/JCpu/tools/insrom.rb b/lib/CPUs/JCpu/tools/insrom.rb
new file mode 100644
index 0000000..6713f9f
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/insrom.rb
@@ -0,0 +1,46 @@
+#!/usr/bin/env ruby
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: Insertion of code fragments into templates
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+arg = $*
+rom_filename = arg[0].to_s
+tpl_filename = arg[1].to_s
+
+subst_pattern = "JASM_ROM_INSERT_HERE"
+
+# --------------------------------------------------------
+# Open file
+# --------------------------------------------------------
+romfile = File.open(rom_filename, "r")
+tplfile = File.open(tpl_filename, "r")
+re = Regexp.new(subst_pattern)
+
+while (line = tplfile.gets)
+	puts line
+	line.scan(re).each do |word|
+		romfile.each do |raw_line|
+			puts raw_line
+		end	
+	end
+end
diff --git a/lib/CPUs/JCpu/tools/irom.vhd.tpl b/lib/CPUs/JCpu/tools/irom.vhd.tpl
new file mode 100644
index 0000000..5f11f86
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/irom.vhd.tpl
@@ -0,0 +1,32 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+
diff --git a/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl b/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl
new file mode 100644
index 0000000..eaa41f3
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl
@@ -0,0 +1,151 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY irom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  inst_addr_t;
+		dout		: out inst_t
+	);
+	
+END irom;
+
+ARCHITECTURE loadable OF irom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: inst_addr_t;
+	signal jtag_ld_dout		: inst_t;
+	signal jtag_ld_din		: inst_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (31 downto 0);
+	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
+	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;
diff --git a/lib/CPUs/JCpu/tools/jasm.bak.rb b/lib/CPUs/JCpu/tools/jasm.bak.rb
new file mode 100644
index 0000000..4c9feb0
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/jasm.bak.rb
@@ -0,0 +1,494 @@
+#!/usr/bin/env ruby
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: A small assembler for the JCPU
+
+# Copyright (C) 2007 J. Ahrensfeld
+
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+# For questions and ideas, please contact the author at jens@jayfield.org
+
+# ---------------------------------------------------------------------
+
+arg = $*
+MAX_SIZE_ROM = 1024
+PROJECT_NAME = arg.to_s.gsub(/\..*/, "")
+ENTITY_NAME = "rom"
+ENTITY_DATA_TYPE = "inst_t"
+ENTITY_ADDR_TYPE = "inst_addr_t"
+OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
+
+# --------------------------------------------------------
+# Open file
+# --------------------------------------------------------
+filename = arg.to_s
+if !File.exists?(filename)
+	STDERR.puts "#{filename} does not exist"
+	exit 1
+end
+
+# --------------------------------------------------------
+# Pass 1
+# --------------------------------------------------------
+lc = 0	# Line counter
+pc = 0	# Program counter
+chip_dc = [0,0,0,0]	# chip data counter
+xmem_dc = 0	# xmem data counter
+curr_segment = "UNDEF";
+page = 0
+
+label_list=[[],[]]
+instr_list=[nil]
+file = File.open(filename, "r")
+file.each do |raw_line|
+	lc += 1
+
+	# Make all upper case
+	iline = "#{raw_line}".strip.upcase
+	
+	# Remove comments
+	iline = iline.gsub(/;.*/, "")
+	
+	# Split instruction at spaces
+	iline_member = iline.split(" ")
+
+	if iline_member[0] == nil
+		next
+	end	
+	
+	mc = 0;
+	label = nil
+	clean_line = nil
+	if (iline_member[0] =~ /\w+:/)
+		mc += 1
+		label = iline_member[0].delete(":")
+		if label_list.rindex(label) != nil
+			STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
+			exit 1
+		end
+	end
+	
+	case iline_member[mc]
+	when nil
+		value = format("0x%3.3X",pc)
+	when "EQU"
+		if 0 == (iline_member[mc+1] =~ /\d+/)
+			value = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
+		else 	
+			value = iline_member[mc+1]
+		end 	
+	when "ORG", "CODE"
+		pc = eval(iline_member[mc+1..iline_member.nitems].to_s)
+		value = format("0x%3.3X",pc)
+	when "CDATA", "CMEM"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: CDATA needs argument!", lc)
+			exit 1
+		end 	
+		curr_segment = "CMEM";
+		page = iline_member[mc+1].to_i(16)
+	when "XDATA", "XMEM"
+		curr_segment = "XMEM";
+	when "DC"
+		len = 0;
+		iline.split("DC")[1].delete("0x").scan(/[0-9A-Fa-f]+/).each do |byte| 
+			len += 1
+		end	
+		if curr_segment == "CMEM"
+			STDERR.puts format("Error in line %d: CDATA cannot be initialized!", lc)
+			exit 1
+		else
+			value = format("0x%2.2X",xmem_dc)
+			puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
+			xmem_dc += len
+		end	
+	when "DB"
+		len = iline_member[mc+1].to_i
+		if curr_segment == "CMEM"
+			value = format("0x%2.2X",chip_dc[page])
+			puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, chip_dc[page], curr_segment, page);
+			chip_dc[page] += len
+		else
+			value = format("0x%2.2X",xmem_dc)
+			puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
+			xmem_dc += len
+		end	
+	else
+		op_line = iline_member[mc+1..iline_member.nitems].to_s
+		value = format("0x%3.3X",pc)
+		opc = iline_member[mc]
+		if iline_member[mc+1] != nil
+			op1 = op_line.gsub(/,+.*$/, "")
+		end	
+		if iline_member[mc+2] != nil
+			op2 = op_line.scan(/,.+$/).to_s.delete(", ")
+		end	
+		if instr_list[pc] == nil
+			instr_list[pc] = [lc, pc, opc , op1 , op2]
+			pc += 1
+		else
+			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, pc)
+			exit 1
+		end
+	end;	
+
+	# Push labels
+	if label	
+		label_list = label_list + [label, value]
+	end
+end
+file.close
+
+# --------------------------------------------------------
+def instr(opcode)
+	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
+end	
+
+def tcl_bits(pc, opcode)
+	return format("%10.10B%6.6B%12.12B",pc, opcode ,0)
+end
+
+def instr_k(opcode, k)
+	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
+end	
+
+def tcl_bits_k(pc, opcode, k)
+	return format("%10.10B%6.6B%12.12B",pc, opcode ,k)
+end
+
+def instr_r(opcode, r)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
+end	
+
+def tcl_bits_r(pc, opcode, r)
+	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode ,0,r)
+end
+
+def instr_kr(opcode, k, r)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
+end	
+
+def tcl_bits_kr(pc, opcode, k, r)
+	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
+end
+
+def instr_rk(opcode, r, k)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
+end	
+
+def tcl_bits_rk(pc, opcode, r, k)
+	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
+end
+
+def instr_rr(opcode, ra, rb)
+	return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
+end	
+
+def tcl_bits_rr(pc, opcode, ra, rb)
+	return format("%10.10B%6.6B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
+end
+
+# --------------------------------------------------------
+# Read mnemonic set
+# --------------------------------------------------------
+filename = OPC_LIST_NAME
+if !File.exists?(filename)
+	STDERR.puts "#{filename} does not exist"
+	exit 1
+end
+
+mnemo_list = []
+num_opcodes = 0
+file = File.open(filename, "r")
+file.each do |raw_line|
+	mnemo_list[num_opcodes] = raw_line.split(" ")[1]
+	num_opcodes += 1
+end
+
+# --------------------------------------------------------
+# Pass 2
+# --------------------------------------------------------
+pc = 0
+opc_start = 2
+num_errors = 0
+vhdl_trans_list = [nil]
+vhdl_comment_list = [nil]
+vhdl_tcl_list = [nil]
+instr_list.each do |instruct|
+		
+	# puts instruct
+	if instruct == nil
+		vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
+		vhdl_comment_list[pc] = format("0x%3.3X:", pc)
+		vhdl_tcl_list[pc] = tcl_bits(pc, 0)
+		pc += 1
+		next
+	end
+		
+	# determine arglen of instruction
+	ilen = 0
+	if instruct[opc_start+1] == nil
+		arglen = 0
+	elsif instruct[opc_start+2] == nil
+		arglen = 1
+	elsif instruct[opc_start+3] == nil
+		arglen = 2
+	end	
+	
+	# Symbol substitution
+	error = false
+	for i in (1..3)
+		subst_pos = opc_start+i
+		if instruct[subst_pos] == nil
+			next
+		end	
+		expr_token = ""
+		expr_subst = nil
+		is_direct = true;
+		
+#		instruct[subst_pos] = instruct[subst_pos].delete(" ")
+
+		# checks R0 .. R16, Mnemonics
+		instr_str = instruct[subst_pos]
+		if 0 == (instr_str =~ /\(.+\)/)
+			instr_str = instr_str.delete("()")
+			is_direct = false;
+		end	
+
+		expr_token = instr_str.split(/\+|\-|\*|\//)[0]
+		if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
+			idx = label_list.rindex(expr_token)
+			if idx != nil
+				expr_subst = label_list[idx+1]
+				instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
+			else
+				STDERR.puts format("Error in line %d: Symbol \"%s\" not found", instruct[0], expr_token)
+				error = true
+			end
+		end	
+		
+		if expr_subst != nil
+			if 0 == (expr_subst =~ /\d+/) 
+				if is_direct == true
+					instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
+				else
+					instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
+				end	
+			else
+				if 0 != (expr_subst =~ /R[0-9]+/)
+					STDERR.puts format("Error in line %d: Invalid expression \"%s\"", instruct[0], expr_subst)
+					error = true
+				end
+			end
+		end	
+	end
+	
+	# Parse operands
+	reg = [0,0]
+	kk = 0
+	format = instruct[opc_start]
+	for i in (0..1)
+		if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
+			# Check indirect addressing
+			reg[i] = instruct[opc_start+i+1].delete("R()").to_i
+			format += "|R"
+			if reg[i] > 15
+				STDERR.puts format("Error in line %d: Invalid register \"R%d\" specified", instruct[0], reg[i])
+				error = true
+			end
+		else
+			if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
+				kk = instruct[opc_start+i+1].delete("()").to_i(16)
+				format += "|K"
+			end
+		end
+		if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
+			format += "i";
+		end
+	end 
+	
+	# Output instruction
+	opcode = mnemo_list.rindex(format).to_i
+	mnemo = instruct[2];
+
+	case format
+	when "NOP", "HALT", "RET", "RETI"
+		vhdl_trans_list[pc] = instr(opcode)
+		vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
+		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
+	when "MOVC|R|Ri", "MOVX|R|Ri"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
+		minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
+	when "MOV|R|R", "SUB|R|R", "ADD|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
+		minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
+	when "MOVC|Ri|R", "MOVX|Ri|R"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
+		minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
+	when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
+	when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
+	when "MOV|R|K", "SUB|R|K", "ADD|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
+	when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
+		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
+		minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
+	when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
+		vhdl_trans_list[pc] = instr_k(opcode, kk)
+		vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
+		minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
+	when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R"
+		vhdl_trans_list[pc] = instr_r(opcode, reg[0])
+		vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+	when "TST|R"
+		kk = 0
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("CMP|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "INC|R"
+		kk = 1
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("ADD|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "DEC|R"
+		kk = 1
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("SUB|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	else
+		STDERR.puts format("Error in line %d: Not yet implemented %s", instruct[0], format)
+		error = true
+	end
+
+	if error
+		num_errors += 1
+		break
+	end
+	vhdl_comment_list[pc] = minstr_comment
+
+	puts vhdl_trans_list[pc] + " -- " + minstr_comment
+	
+	pc += 1
+end
+
+# --------------------------------------------------------
+# Output ROM file
+# --------------------------------------------------------
+if num_errors == 0
+
+	filename = format("rom_%s.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("ENTITY %s IS\n", ENTITY_NAME)
+	file.puts format("\tPort (\n")
+	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\taddr\t\t: in  %s;\n", ENTITY_ADDR_TYPE)
+	file.puts format("\tdout\t\t: out %s\n", ENTITY_DATA_TYPE)
+	file.puts format("\t);\n")
+	file.puts format("END %s;\n", ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("\ttype instruction_rom_t is array (0 to %d) of %s;\n", pc-1, ENTITY_DATA_TYPE)
+	file.puts format("\n")
+	file.puts format("\tconstant instruction_rom : instruction_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..pc-2)
+		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
+	end;
+	file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
+	file.puts format("\t);\n")
+	file.puts format("\n")
+	file.puts format("begin")
+	file.puts format("\n")
+	file.puts format("PROM_READ:")
+	file.puts format("\tprocess(clk, ce)\n")
+	file.puts format("\tbegin\n")
+	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
+	file.puts format("\t\t\tdout <= instruction_rom(to_integer(addr));\n")
+	file.puts format("\t\tend if;\n")
+	file.puts format("\tend process;\n")
+	file.puts format("\n")
+	file.puts format("end %s;\n", PROJECT_NAME)
+	puts format("ROM file written to \"%s\"\n",filename)
+	file.close
+end
+if num_errors == 0
+
+	filename = format("preinit_%s.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("\tsignal instruction_rom : instruction_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..pc-2)
+		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
+	end;
+	if pc < (MAX_SIZE_ROM-1)
+		file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
+		for i in (pc..(MAX_SIZE_ROM-2))
+			file.puts "\t\t" + instr(0) + ",\n"
+		end;
+		file.puts "\t\t" + instr(0) + "\n"
+	else
+		file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
+	end	
+	file.puts format("\t);\n")
+	puts format("PREINIT file written to \"%s\"\n",filename)
+	file.close
+end
+if num_errors == 0
+	filename = format("rom_%s.tcl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+	for i in (0..pc-1)
+		# Chipscope 8.1
+#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
+
+		# Chipscope 9.1
+		file.puts format("\# %s", vhdl_comment_list[i]) 
+		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
+	end;
+	puts format("TCL snippet written to \"%s\"\n",filename)
+	file.close
+end
+
+# --------------------------------------------------------
+# Output final statistics
+# --------------------------------------------------------
+if num_errors == 0
+	puts "Program uses #{pc} instruction addresses"
+	puts "No errors found"
+	exit 0
+else
+	puts "#{num_errors} errors found"
+	exit 1
+end	
diff --git a/lib/CPUs/JCpu/tools/jasm.rb b/lib/CPUs/JCpu/tools/jasm.rb
new file mode 100644
index 0000000..fdad0bb
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/jasm.rb
@@ -0,0 +1,814 @@
+#!/usr/bin/env ruby
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: A small assembler for the JCPU
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+arg = $*
+FILE_SUFFIX = "jsm"
+IROM_MAX_SIZE = 1024
+IROM_ENTITY_NAME = "irom"
+IROM_DATA_TYPE = "inst_t"
+IROM_ADDR_TYPE = "inst_addr_t"
+XROM_MAX_SIZE = 256
+XROM_DATA_TYPE = "dmem_data_t"
+XROM_ADDR_TYPE = "dmem_addr_t"
+XROM_ENTITY_NAME = "xrom"
+OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
+
+# --------------------------------------------------------
+class Parser
+	def curr_segment
+		@curr_segment
+	end	
+	def curr_segment=(arg)
+		@curr_segment=arg
+	end	
+	def add_label(labelname, addr)
+		@label_list = @label_list + [labelname, addr]
+	end
+	def	getLabelIdByName(label)
+		return @label_list.rindex(label)
+	end
+	def	getLabelNameById(id)
+		return @label_list[id]
+	end
+	def put_instr(name, lc, opc , op1 , op2)
+		if get_instr != nil
+			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, @pc)
+			exit 1
+		end
+		@instr_list[@pc] = [lc, @pc, opc , op1 , op2, name]
+	end
+	def	get_instr
+		return @instr_list[@pc]
+	end
+	def put_xmem(value, lc)
+		if get_xmem != nil
+			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, xmem_dc, curr_segment)
+			exit 1
+		end
+		@xmem[xmem_dc] = value
+		@xmem_dc = xmem_dc + 1
+	end	
+	def get_xmem
+		return @xmem[xmem_dc]
+	end	
+	def xmem
+		return @xmem
+	end	
+	def put_cmem(value, lc)
+		if get_cmem(page) != nil
+			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, cmem_dc, curr_segment)
+			exit 1
+		end
+		@cmem[page][cmem_dc] = value
+		@cmem_dc[page] = cmem_dc + 1
+	end	
+	def get_cmem(pg)
+		return @cmem[pg][cmem_dc]
+	end	
+	def cmem(page)
+		return @cmem[page]
+	end	
+	def	cmem_dc=(addr)
+		@cmem_dc[page] = addr
+	end	
+	def	cmem_dc
+		@cmem_dc[page]
+	end	
+	def	xmem_dc=(addr)
+		@xmem_dc = addr
+	end	
+	def	xmem_dc
+		@xmem_dc
+	end	
+	def page=(page)
+		@page = page;
+	end	
+	def page
+		@page;
+	end	
+	def pc=(pc)
+		@pc = pc;
+		if (pc > @pc_max)
+			@pc_max = pc
+		end	
+	end	
+	def pc
+		@pc;
+	end	
+	def pc_max
+		@pc_max;
+	end	
+	def	instr_list
+		@instr_list
+	end
+	def	label_list
+		@label_list
+	end
+	
+	def initialize()
+		@pc_max = 0
+		@pc = 0					# Program counter
+		@cmem_dc = [0,0,0,0]	# chip data counter
+		@xmem_dc = 0			# xmem data counter
+		@curr_segment = "UNDEF";
+		@page = 0
+		@label_list=[[],[]]
+		@instr_list=[nil]
+		@cmem = [[],[]];
+		@xmem = [];
+	end
+	def method_missing(name, *args)
+		puts "I don't know the method #{name}"
+	end
+end	
+
+# --------------------------------------------------------
+def parse(name, obj)
+
+lc = 0	# Line counter
+file = File.open(name, "r")
+
+file.each do |raw_line|
+	lc += 1
+
+	# Make all upper case
+	iline = "#{raw_line}".strip
+	
+	# Remove comments
+	iline = iline.gsub(/;.*/, "")
+	
+	# Split instruction at spaces
+	iline_member = iline.split(" ")
+
+	if iline_member[0] == nil
+		next
+	end	
+	
+	mc = 0;
+	label = nil
+	clean_line = nil
+	if (iline_member[0] =~ /\w+:/)
+		mc += 1
+		label = iline_member[0].delete(":")
+		if obj.getLabelIdByName(label) != nil
+			STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
+			exit 1
+		end
+	end
+	
+	token = iline_member[mc]
+	if token
+		token = token.upcase
+	end
+	
+	case token
+	when nil
+		if obj.curr_segment == "CMEM"
+			curr_addr = format("0x%3.3X",obj.cmem_dc)
+		elsif obj.curr_segment == "XMEM"
+			curr_addr = format("0x%3.3X",obj.xmem_dc)
+		elsif obj.curr_segment == "CODE"
+			curr_addr = format("0x%3.3X",obj.pc)
+		else
+			STDERR.puts format("Error in line %d: Undefined segment", lc)
+			exit 1
+		end
+	when "INCLUDE"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		inc_name = iline_member[mc+1].delete("\"")
+		puts format("Inserting \"%s\" into \"%s\" at line %d", inc_name, name, lc);
+		parse(inc_name, obj)
+	when "EQU"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		if 0 == (iline_member[mc+1] =~ /\d+/)
+			curr_addr = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
+		else 	
+			curr_addr = iline_member[mc+1]
+		end 	
+	when "ORG"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		offset = eval(iline_member[mc+1..iline_member.nitems].to_s)
+		case obj.curr_segment
+			when "CODE"
+			obj.pc = offset
+			curr_addr = format("0x%3.3X",obj.pc)
+			when "CMEM"
+			obj.cmem_dc = offset
+			when "XMEM"
+			obj.xmem_dc = offset
+			
+		end	
+	when "CODE"
+		curr_addr = format("0x%3.3X",obj.pc)
+		obj.curr_segment = "CODE";
+	when "CDATA", "CMEM"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		obj.curr_segment = "CMEM";
+		obj.page = iline_member[mc+1].to_i(16)
+	when "XDATA", "XMEM"
+		obj.curr_segment = "XMEM";
+	when "DC"
+		len = 0;
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		if obj.curr_segment == "CMEM"
+			STDERR.puts format("Error in line %d: %s cannot be initialized!", lc, obj.curr_segment)
+			exit 1
+		elsif obj.curr_segment == "XMEM"
+			curr_addr = format("0x%2.2X",obj.xmem_dc)
+			dc_old = obj.xmem_dc;
+			val_array = raw_line.split(/dc|DC|Dc|dC/)[1].delete("\t").gsub(/;.*/, "").split(",")
+			
+			# Parse string literals
+			val_array.each do |item| 
+				if 0 == (item =~ /.*\".*\"/)
+					str = item.delete("\"")
+					puts item
+					for nn in (0..str.length-1)
+						if str[nn] > 31
+							obj.put_xmem(str[nn], lc);
+						 	puts "S: " + str[nn].to_s
+							len += 1
+						end	
+					end;
+				else
+					argument = item
+					puts "B: " + argument
+					obj.put_xmem(eval(argument), lc);
+					len += 1
+				end	
+			end	
+			puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, dc_old, obj.curr_segment);
+		else	
+			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
+			exit 1
+		end	
+	when "DB"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		len = eval(iline_member[mc+1]).to_i
+		if obj.curr_segment == "CMEM"
+			curr_addr = format("0x%2.2X",obj.cmem_dc)
+			puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, obj.cmem_dc, obj.curr_segment, obj.page);
+			for nn in (1..len)
+				obj.put_cmem(0, lc)
+			end	
+		elsif obj.curr_segment == "XMEM"
+			curr_addr = format("0x%2.2X",obj.xmem_dc)
+			puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, obj.xmem_dc, obj.curr_segment);
+			for nn in (1..len)
+				obj.put_xmem(0, lc)
+			end	
+		else	
+			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
+			exit 1
+		end	
+	else
+		if obj.curr_segment != "CODE"
+			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
+			exit 1
+		end			
+
+		op_line = iline_member[mc+1..iline_member.nitems].to_s
+		curr_addr = format("0x%3.3X",obj.pc)
+		opc = token
+		if iline_member[mc+1] != nil
+			op1 = op_line.gsub(/,+.*$/, "")
+		end	
+		if iline_member[mc+2] != nil
+			op2 = op_line.scan(/,.+$/).to_s.delete(", ")
+		end	
+		obj.put_instr(name, lc, opc, op1, op2)
+		obj.pc = obj.pc + 1
+	end;	
+
+	# Push labels
+	if label	
+		obj.add_label(label, curr_addr)
+	end
+end
+file.close
+return obj
+end
+
+# --------------------------------------------------------
+# Instruction formatting
+# --------------------------------------------------------
+def instr(opcode)
+	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
+end	
+
+def tcl_bits(pc, opcode)
+	return format("%12.12B%8.8B%12.12B",pc, opcode ,0)
+end
+
+def instr_k(opcode, k)
+	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
+end	
+
+def tcl_bits_k(pc, opcode, k)
+	return format("%12.12B%8.8B%12.12B",pc, opcode ,k)
+end
+
+def instr_r(opcode, r)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
+end	
+
+def tcl_bits_r(pc, opcode, r)
+	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode ,0,r)
+end
+
+def instr_kr(opcode, k, r)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
+end	
+
+def tcl_bits_kr(pc, opcode, k, r)
+	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
+end
+
+def instr_rk(opcode, r, k)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
+end	
+
+def tcl_bits_rk(pc, opcode, r, k)
+	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
+end
+
+def instr_rr(opcode, ra, rb)
+	return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
+end	
+
+def tcl_bits_rr(pc, opcode, ra, rb)
+	return format("%12.12B%8.8B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
+end
+
+# --------------------------------------------------------
+# Open file
+# --------------------------------------------------------
+filename = arg.to_s
+if !File.exists?(filename)
+	STDERR.puts "#{filename} does not exist"
+	exit 1
+end
+PROJECT_NAME = File.basename(filename, "." + FILE_SUFFIX)
+
+# --------------------------------------------------------
+# Pass 1
+# --------------------------------------------------------
+first_pass = Parser.new();
+parse(filename, first_pass)
+
+# --------------------------------------------------------
+# Read mnemonic set
+# --------------------------------------------------------
+filename = OPC_LIST_NAME
+if !File.exists?(filename)
+	STDERR.puts "#{filename} does not exist"
+	exit 1
+end
+
+mnemo_list = []
+num_opcodes = 0
+file = File.open(filename, "r")
+file.each do |raw_line|
+	mnemo_list[num_opcodes] = raw_line.split(" ")[1]
+	num_opcodes += 1
+end
+
+# --------------------------------------------------------
+# Pass 2
+# --------------------------------------------------------
+pc = 0
+opc_start = 2
+num_errors = 0
+vhdl_trans_list = [nil]
+vhdl_comment_list = [nil]
+vhdl_tcl_list = [nil]
+
+# ToDo: Use class-methods
+label_list = first_pass.label_list
+instr_list = first_pass.instr_list
+
+instr_list.each do |instruct|
+		
+	# puts instruct
+	if instruct == nil
+		vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
+		vhdl_comment_list[pc] = format("0x%3.3X:", pc)
+		vhdl_tcl_list[pc] = tcl_bits(pc, 0)
+		pc += 1
+		next
+	end
+		
+	# determine arglen of instruction
+	ilen = 0
+	if instruct[opc_start+1] == nil
+		arglen = 0
+	elsif instruct[opc_start+2] == nil
+		arglen = 1
+	elsif instruct[opc_start+3] == nil
+		arglen = 2
+	end	
+	
+	# Symbol substitution
+	error = false
+	for i in (1..2)
+		subst_pos = opc_start+i
+		if instruct[subst_pos] == nil
+			next
+		end	
+		expr_token = ""
+		expr_subst = nil
+		is_direct = true;
+		
+		# checks R0 .. R16, Mnemonics
+		instruct[subst_pos] = instruct[subst_pos].gsub(/'low/, "")
+		if (nil != (instruct[subst_pos] =~ /'high/))
+			instruct[subst_pos]= format("%s/256", instruct[subst_pos].gsub(/'high/, ""))
+		end	
+		instr_str = instruct[subst_pos]
+		if 0 == (instr_str =~ /\(.+\)/)
+			instr_str = instr_str.delete("()")
+			is_direct = false;
+		end	
+
+		expr_token = instr_str.split(/\+|\-|\*|\/|\||\&/)[0]
+		if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
+			idx = label_list.rindex(expr_token)
+			if idx != nil
+				expr_subst = label_list[idx+1]
+				instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
+			else
+				STDERR.puts format("%s: Error in line %d: Symbol \"%s\" not found", instruct[5], instruct[0], expr_token)
+				error = true
+			end
+		end	
+		
+		if expr_subst != nil
+			if 0 == (expr_subst =~ /\d+/) 
+				if is_direct == true
+					instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
+				else
+					instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
+				end	
+			else
+				if 0 != (expr_subst =~ /R[0-9]+/)
+					STDERR.puts format("%s: Error in line %d: Invalid expression \"%s\"", instruct[5], instruct[0], expr_subst)
+					error = true
+				end
+			end
+		end	
+	end
+	
+	# Parse operands
+	reg = [0,0]
+	kk = 0
+	format = instruct[opc_start]
+	for i in (0..1)
+		if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
+			# Check indirect addressing
+			reg[i] = instruct[opc_start+i+1].delete("R()").to_i
+			format += "|R"
+			if reg[i] > 15
+				STDERR.puts format("%s: Error in line %d: Invalid register \"R%d\" specified", instruct[5], instruct[0], reg[i])
+				error = true
+			end
+		else
+			if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
+				kk = eval(instruct[opc_start+i+1].delete("()"))
+				format += "|K"
+			end
+		end
+		if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
+			format += "i";
+		end
+	end 
+	
+	if error
+		num_errors += 1
+		break
+	end
+
+	# Output instruction
+	opcode = mnemo_list.rindex(format).to_i
+	mnemo = instruct[2];
+
+	case format
+	# Native instructions
+	when "NOP", "HALT", "RET", "RETI", "SETC"
+		vhdl_trans_list[pc] = instr(opcode)
+		vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
+		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
+	when "MOVC|R|Ri", "MOVX|R|Ri"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
+		minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
+	when "MOV|R|R", "SUB|R|R", "SUBC|R|R", "ADD|R|R", "ADDC|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
+		minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
+	when "MOVC|Ri|R", "MOVX|Ri|R"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
+		minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
+	when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
+		kk = kk % 256;
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
+	when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
+	when "MOV|R|K", "SUB|R|K", "SUBC|R|K", "ADD|R|K", "ADDC|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
+		kk = kk % 256;
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
+	when "SUB|K|R", "SUBC|K|R"
+		kk = kk % 256;
+		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
+		minstr_comment = format("0x%3.3X: %s 0x%2.2d, R%2.2X", pc, mnemo, kk, reg[1])
+	when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
+		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
+		minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
+	when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
+		vhdl_trans_list[pc] = instr_k(opcode, kk)
+		vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
+		minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
+	when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R", "SWAP|R"
+		vhdl_trans_list[pc] = instr_r(opcode, reg[0])
+		vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+	# Synthetic instructions
+	when "CLRC"
+		kk = 0;
+		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
+		opcode = mnemo_list.rindex("SUB|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "TST|R"
+		kk = 0
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("CMP|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "NEG|R"
+		kk = 0
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("SUB|K|R").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "NOT|R"
+		kk = 0
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("XOR|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "INC|R"
+		kk = 1
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("ADD|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "DEC|R"
+		kk = 1
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("SUB|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	else
+		STDERR.puts format("%s: Error in line %d: Not yet implemented %s", instruct[5], instruct[0], format)
+		error = true
+	end
+
+	if error
+		num_errors += 1
+		break
+	end
+
+	vhdl_comment_list[pc] = minstr_comment
+
+	puts vhdl_trans_list[pc] + " -- " + minstr_comment
+	
+	pc += 1
+end
+
+# --------------------------------------------------------
+# Output ROM file
+# --------------------------------------------------------
+if num_errors == 0
+
+	# I-ROM VHDL-ROM
+	filename = format("%s.irom.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("ENTITY %s IS\n", IROM_ENTITY_NAME)
+	file.puts format("\tPort (\n")
+	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\taddr\t\t: in  %s;\n", IROM_ADDR_TYPE)
+	file.puts format("\tdout\t\t: out %s\n", IROM_DATA_TYPE)
+	file.puts format("\t);\n")
+	file.puts format("END %s;\n", IROM_ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, IROM_ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", [IROM_MAX_SIZE, pc].min-1 , IROM_DATA_TYPE)
+	file.puts format("\n")
+	file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("\tconstant imem_rom : imem_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..[IROM_MAX_SIZE, pc].min-2)
+		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
+	end;
+	file.puts "\t\t" + vhdl_trans_list[pc-1] + "  -- " + vhdl_comment_list[pc-1] + "\n"
+	file.puts format("\t);\n")
+	file.puts format("\n")
+	file.puts format("begin")
+	file.puts format("\n")
+	file.puts format("PROM_READ:")
+	file.puts format("\tprocess(clk, ce)\n")
+	file.puts format("\tbegin\n")
+	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
+	file.puts format("\t\t\tdout <= imem_rom(to_integer(addr));\n")
+	file.puts format("\t\tend if;\n")
+	file.puts format("\tend process;\n")
+	file.puts format("\n")
+	file.puts format("end %s;\n", PROJECT_NAME)
+	puts format("I-ROM file written to \"%s\"\n",filename)
+	file.close
+
+	# I-ROM VHDL-ROM (loadable)
+	filename = format("%s.irom_ld.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", IROM_MAX_SIZE-1, IROM_DATA_TYPE)
+	file.puts format("\tsignal imem_rom : imem_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..pc-2)
+		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
+	end;
+	if pc < (IROM_MAX_SIZE-1)
+		file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
+		for i in (pc..(IROM_MAX_SIZE-2))
+			file.puts "\t\t" + instr(0) + ",\n"
+		end;
+		file.puts "\t\t" + instr(0) + "\n"
+	else
+		file.puts "\t\t" + vhdl_trans_list[pc-1] + "  -- " + vhdl_comment_list[pc-1] + "\n"
+	end	
+	file.puts format("\t);\n")
+	puts format("I-ROM (loadable) file written to \"%s\"\n",filename)
+	file.close
+
+	# I-ROM TCL-Loader
+	filename = format("%s.irom.tcl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+	file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("# ---------------------------------------------------------------");
+	file.puts format("# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA");
+	file.puts format("# User 1")
+	file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n")
+	for i in (0..pc-1)
+		# Chipscope 8.1
+#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
+
+		# Chipscope 9.1
+		file.puts format("\# %s", vhdl_comment_list[i]) 
+		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
+	end;
+	puts format("I-ROM TCL-loader written to \"%s\"\n",filename)
+	file.close
+
+	# X-ROM VHDL-ROM
+	filename = format("%s.xrom.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("ENTITY %s IS\n", XROM_ENTITY_NAME)
+	file.puts format("\tPort (\n")
+	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\taddr\t\t: in  %s;\n", XROM_ADDR_TYPE)
+	file.puts format("\tdout\t\t: out %s\n", XROM_DATA_TYPE)
+	file.puts format("\t);\n")
+	file.puts format("END %s;\n", XROM_ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, XROM_ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
+	file.puts format("\n")
+	file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("\tconstant xmem_rom : xmem_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..XROM_MAX_SIZE-2)
+		file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i)
+	end;
+	i = XROM_MAX_SIZE-1
+	file.puts format("\t\tX\"%2.2X\"  -- 0x%2.2X\n", first_pass.xmem[i], i)
+	file.puts format("\t);\n")
+	file.puts format("\n")
+	file.puts format("begin")
+	file.puts format("\n")
+	file.puts format("PROM_READ:")
+	file.puts format("\tprocess(clk, ce)\n")
+	file.puts format("\tbegin\n")
+	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
+	file.puts format("\t\t\tdout <= xmem_rom(to_integer(addr));\n")
+	file.puts format("\t\tend if;\n")
+	file.puts format("\tend process;\n")
+	file.puts format("\n")
+	file.puts format("end %s;\n", PROJECT_NAME)
+	puts format("X-ROM file written to \"%s\"\n",filename)
+	file.close
+
+	# X-ROM VHDL-ROM (loadable)
+	filename = format("%s.xrom_ld.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
+	file.puts format("\tsignal xmem_rom : xmem_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..XROM_MAX_SIZE-2)
+		file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i)
+	end;
+	i = XROM_MAX_SIZE-1
+	file.puts format("\t\tX\"%2.2X\"  -- 0x%2.2X\n", first_pass.xmem[i], i)
+	file.puts format("\t);\n")
+	puts format("X-ROM (loadable) file written to \"%s\"\n",filename)
+	file.close
+
+	# X-ROM TCL-Loader
+	filename = format("%s.xrom.tcl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+	file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("# ---------------------------------------------------------------");
+	file.puts format("# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA");
+	file.puts format("# User 2")
+	file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n")
+	for i in (0..first_pass.xmem.length-1)
+		# Chipscope 8.1
+#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
+
+		# Chipscope 9.1
+		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%2.2X%2.2X\"\n", 16, i, first_pass.xmem[i]);
+	end;
+	puts format("X-ROM TCL-loader written to \"%s\"\n",filename)
+	file.close
+
+end
+
+# --------------------------------------------------------
+# Output final statistics
+# --------------------------------------------------------
+if num_errors == 0
+	puts "Program uses #{first_pass.pc_max} instruction addresses"
+	puts "No errors found"
+	exit 0
+else
+	puts "#{num_errors} errors found"
+	exit 1
+end	
+
diff --git a/lib/CPUs/JCpu/tools/lib/cg.inc.jsm b/lib/CPUs/JCpu/tools/lib/cg.inc.jsm
new file mode 100644
index 0000000..01c36c4
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/lib/cg.inc.jsm
@@ -0,0 +1,72 @@
+; -------------------------------------------------
+; lcd.inc.jsm
+; -------------------------------------------------
+; needs xio-address equates for
+; reg_cg_char_addr:	equ		0xXX	; RW
+; reg_cg_line_addr:	equ		0xXX	; RW
+; reg_cg_data:		equ		0xXX	; RW
+; reg_cg_ctrl:		equ		0xXX	; WO
+
+; needs delay.inc.jsm
+
+; -------------------------------------------------
+cg_clr_line:	push	R0
+				mov		R0, 2
+				xout	(reg_cg_ctrl), R0	
+				pop		R0
+				ret
+				
+; -------------------------------------------------
+cg_clr_screen:	push	R0
+				mov		R0, 1
+				xout	(reg_cg_ctrl), R0	
+				pop		R0
+				ret
+				
+; -------------------------------------------------
+; R0 : char address
+; R1 : line address
+cg_set_addr:	call	cg_wait_rdy
+				xout	(reg_cg_line_addr), R1
+				xout	(reg_cg_char_addr), R0
+				ret
+
+; -------------------------------------------------
+; R0 : character
+cg_putchar:		call	cg_wait_rdy
+				xout	(reg_cg_data), R0
+				ret				
+
+; -------------------------------------------------
+; R1 : ptr to string
+cg_puts:		push	R0
+cg_p_lp:		movx	R0, (R1)
+				inc		R1
+				tst		R0
+				jz		ex_cgp
+				call	cg_putchar
+				jmp		cg_p_lp
+ex_cgp:			pop		R0
+				ret				
+
+; -------------------------------------------------
+; R1 : ptr to string
+cg_clr_puts:	call	cg_clr_line
+				call	cg_puts
+				ret				
+
+; -------------------------------------------------
+; R1 : ptr to string
+cg_puts_clr:	call	cg_puts
+				call	cg_clr_line
+				ret				
+
+; -------------------------------------------------
+cg_wait_rdy:	push	R0
+cg_wr_lp:		xin		R0, (reg_hwstat)
+				and		R0, 0x02
+				jz		cg_wr_lp
+				pop		R0
+				ret
+
+; -------------------------------------------------
diff --git a/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm b/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm
new file mode 100644
index 0000000..06d39d9
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm
@@ -0,0 +1,7 @@
+; JCPU On-Chip register
+cpu_revision:		equ		0x00	; RO
+cpu_control:		equ		0x01	; R/W
+cpu_status:			equ		0x02	; RO
+cpu_int_ctrl:		equ		0x03	; RW
+cpu_cmem_high:		equ		0x04	; RW
+cpu_stack_high:		equ		0x05	; RW
diff --git a/lib/CPUs/JCpu/tools/lib/delays.inc.jsm b/lib/CPUs/JCpu/tools/lib/delays.inc.jsm
new file mode 100644
index 0000000..6f002ee
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/lib/delays.inc.jsm
@@ -0,0 +1,64 @@
+; -------------------------------------------------
+; Delays
+; -------------------------------------------------
+delay1s:		push	R15
+				mov		R15, 10
+loop1s:			call 	delay100ms		
+				dec		R15
+				jnz		loop1s
+				pop		R15
+				ret
+
+delay100ms:		push	R15
+				mov		R15, 10
+loop100ms:		call 	delay10ms		
+				dec		R15
+				jnz		loop100ms
+				pop		R15
+				ret
+			
+delay10ms:		push	R15
+				mov		R15, 10
+loop10ms:		call	delay1ms		
+				dec		R15
+				jnz		loop10ms
+				pop		R15
+				ret
+		
+delay1ms:		push	R15
+				mov		R15, 10
+loop1ms:		call	delay100us
+				dec		R15
+				jnz		loop1ms
+				pop		R15
+				ret
+
+delay100us:		push	R15
+				mov		R15, 10
+loop100us:		call	delay10us
+				dec		R15
+				jnz		loop100us
+				pop		R15
+				ret
+
+delay10us:		push	R15
+				mov		R15, 99
+loop10us:		nop
+				nop
+				nop
+				dec		R15
+				jnz		loop10us
+				pop		R15
+				ret
+
+delay1us:		push	R15
+				mov		R15, 9
+loop1us:		nop
+				nop
+				nop
+				dec		R15
+				jnz		loop1us
+				pop		R15
+				ret
+				
+; -------------------------------------------------
diff --git a/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm b/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm
new file mode 100644
index 0000000..d2883fa
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm
@@ -0,0 +1,208 @@
+; -------------------------------------------------
+; lcd.inc.jsm
+; -------------------------------------------------
+; needs xmem-address definition for
+; - lcd_port (LCD-Base)
+
+; needs delay.inc.jsm
+
+; -------------------------------------------------
+lcd_cmd:		equ		0x00
+lcd_rd:			equ		0x20
+lcd_data:		equ		0x40
+lcd_enable:		equ		0x80
+
+LCD_CMD_Z1:		equ		0x80
+LCD_CMD_Z2:		equ		0xC0
+LCD_CMD_CLEAR:	equ		0x01
+
+; -------------------------------------------------
+; Init LCD
+; -------------------------------------------------
+LCD_init:		mov		R2, 0x00		
+				mov		R0, 0x03
+				call	_write_lcd
+				call	delay10ms
+				mov		R2, 0x00		
+				mov		R0, 0x03
+				call	_write_lcd
+				call	delay10ms
+
+				mov		R2, 0x00		
+				mov		R0, 0x02
+				call	_write_lcd
+				call	delay1ms
+
+				; 1. Function set: 4-Bit mode, two display lines
+				mov		R0, 0x28
+				call	LCD_writecmd
+
+				; 2. Display on, no cursor
+				mov		R0, 0x0C		
+				call	LCD_writecmd
+
+				; 3. Cursor shift during write
+				mov		R0, 0x06
+				call	LCD_writecmd
+
+				; 4. Display clear
+				mov		R0, 0x01
+				call	LCD_writecmd
+
+				ret
+				
+; -------------------------------------------------
+; LCD_waitbsy
+; -------------------------------------------------
+LCD_waitbsy:	push	R0
+bsy_loop:		call	LCD_readstat
+				and		R0, 0x80
+				jz		ex_bsy
+				call	delay1us
+				jmp		bsy_loop
+ex_bsy:			pop		R0
+				ret
+
+; -------------------------------------------------
+; LCD_writecmd
+; -------------------------------------------------
+; R0 = cmd
+LCD_writeaddr:
+LCD_writecmd:	push	R2
+				mov		R2, lcd_cmd
+				call	LCD_write
+				pop		R2
+				ret
+
+; -------------------------------------------------
+; LCD_putsx
+; -------------------------------------------------
+; R1 = address of null-terminated string in XMEM
+LCD_putsx:		push	R0
+putsx_loop:		movx	R0, (R1)
+				inc		R1
+				tst		R0
+				jz		putsx_ex
+				call	LCD_writechar
+				jmp		putsx_loop
+putsx_ex:		pop		R0
+				ret
+				
+; -------------------------------------------------
+; LCD_putsc
+; -------------------------------------------------
+; R1 = address of null-terminated string in CMEM
+LCD_putsc:		push	R0
+putsc_loop:		movc	R0, (R1)
+				inc		R1
+				tst		R0
+				jz		putsc_ex
+				call	LCD_writechar
+				jmp		putsc_loop
+putsc_ex:		pop		R0
+				ret
+				
+; -------------------------------------------------
+; LCD_writechar
+; -------------------------------------------------
+; R0 = char
+LCD_writedata:
+LCD_writechar:	push	R2
+				mov		R2, lcd_data
+				call	LCD_write
+				pop		R2
+				ret
+				
+; -------------------------------------------------
+; LCD_write
+; -------------------------------------------------
+; R0 = input
+; R2 = register
+LCD_write:		call	LCD_waitbsy
+				push	R0
+				swap	R0
+				call	_write_lcd
+				pop		R0
+				call	_write_lcd
+				ret
+
+; -------------------------------------------------
+; LCD_readstat
+; -------------------------------------------------
+; R0 = status
+LCD_readstat:	push	R2
+				mov		R2, lcd_cmd
+				call	LCD_read
+				pop		R2
+				ret
+
+; -------------------------------------------------
+; LCD_read
+; -------------------------------------------------
+; R0 = output
+; R2 = register
+LCD_read:		call	_read_lcd
+				swap	R0
+				push	R0
+				call	_read_lcd
+				pop		R2
+				or		R0, R2
+				ret
+				
+; -------------------------------------------------
+; _write
+; -------------------------------------------------
+; R0 = input
+_write_lcd:		push	R1
+
+				and		R0, 0x0F
+				mov		R1, R0
+				or		R1, R2
+				xout	(lcd_port), R1
+				call	delay1us
+
+				mov		R1, R0
+				or		R1, R2
+				or		R1, lcd_enable
+				xout	(lcd_port), R1
+				call	delay1us
+
+				mov		R1, R0
+				or		R1, R2
+				xout	(lcd_port), R1
+				call	delay1us
+
+				or		R1, lcd_rd
+				xout	(lcd_port), R1
+
+				pop		R1
+				ret
+
+; -------------------------------------------------
+; _read
+; -------------------------------------------------
+; R0 = output
+_read_lcd:		push	R1
+
+				mov		R1, lcd_rd
+				or		R1, R2
+				xout	(lcd_port), R1
+				call	delay1us
+
+				mov		R1, lcd_rd
+				or		R1, R2
+				or		R1, lcd_enable
+				xout	(lcd_port), R1
+				call	delay1us
+				xin		R0, (lcd_port)
+				and		R0, 0x0F
+
+				mov		R1, lcd_rd
+				or		R1, R2
+				xout	(lcd_port), R1
+				call	delay1us
+
+				pop		R1
+				ret
+
+				
\ No newline at end of file
diff --git a/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm b/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm
new file mode 100644
index 0000000..2f66e2a
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm
@@ -0,0 +1,42 @@
+; -------------------------------------------------
+; mul8x8.inc.jsm
+; -------------------------------------------------
+
+; -------------------------------------------------
+; Parameter:
+; R0 : operand 1
+; R1 : operand 2
+; Return:
+; R0 : product low
+; R1 : product high
+mul8x8:			push	R2
+				push	R3
+				push	R4
+				
+				mov		R4, R1
+				mov		R1, 0
+				mov		R2, 0
+				mov		R3, 0
+				
+loop1:			cmp		R4, 0x01
+				jeq		ende1
+
+				shr		R4
+				jnc		next1
+
+				add		R2, R0
+				addc	R3, R1
+
+next1:			shl		R0
+				rolc	R1
+				jmp		loop1
+				
+ende1:			add		R0, R2
+				addc	R1, R3
+				
+				pop		R4
+				pop		R3
+				pop		R2
+				ret
+
+; -------------------------------------------------
diff --git a/lib/CPUs/JCpu/tools/lib/uart.inc.jsm b/lib/CPUs/JCpu/tools/lib/uart.inc.jsm
new file mode 100644
index 0000000..1733305
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/lib/uart.inc.jsm
@@ -0,0 +1,32 @@
+; -------------------------------------------------
+; uart.inc.jsm
+; -------------------------------------------------
+; needs xmem-address definition for
+; - uart_status (Status register)
+; - uart_data	(Data register)
+
+; -------------------------------------------------
+; sout
+; -------------------------------------------------
+; R0 = input
+sout:			push 	R1
+sout1:			xin		R1, (uart_status)
+				and		R1, 0x02
+				jnz		sout1
+				xout	(uart_data), R0
+				pop		R1
+				ret
+
+; -------------------------------------------------
+; sin
+; -------------------------------------------------
+; R0 = output
+sin:			push 	R1
+sin1:			xin		R1, (uart_status)
+				and		R1, 0x10
+				jnz		sin1
+				xin		R0, (uart_data)
+				pop		R1
+				ret
+
+; -------------------------------------------------
diff --git a/lib/CPUs/JCpu/tools/lib/utils.inc.jsm b/lib/CPUs/JCpu/tools/lib/utils.inc.jsm
new file mode 100644
index 0000000..f354d7c
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/lib/utils.inc.jsm
@@ -0,0 +1,32 @@
+; -------------------------------------------------
+; utils.inc.jsm
+; -------------------------------------------------
+
+
+; -------------------------------------------------
+; Parameter
+; R0 : Bin value in lower nibble
+; Return
+; R0 : Hex character representing lower nibble
+nibble2hex:		and		R0, 0x0F
+				cmp		R0, 0x0A
+				jlt		isNum1
+				add		R0, 0x07
+isNum1:			add		R0, 0x30
+				ret
+
+; -------------------------------------------------
+; Parameter
+; R0 : Bin value
+; Return
+; R0 : Hex character high
+; R1 : Hex character low
+bin2hex:		push	R0
+				call	nibble2hex
+				mov		R1, R0
+				pop		R0
+				swap	R0
+				call	nibble2hex
+				ret
+
+; -------------------------------------------------
diff --git a/lib/CPUs/JCpu/tools/opc.list b/lib/CPUs/JCpu/tools/opc.list
new file mode 100644
index 0000000..59b3cfa
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/opc.list
@@ -0,0 +1,64 @@
+0 NOP         
+1 HALT        
+2 MOV|R|R     
+3 MOV|R|K     
+4 MOVX|R|Ri   
+5 MOVX|R|Ki   
+6 MOVX|Ri|R   
+7 MOVX|Ri|K   
+8 MOVX|Ki|R   
+9 MOVC|R|Ri   
+10 MOVC|R|Ki   
+11 MOVC|Ri|R   
+12 MOVC|Ri|K   
+13 MOVC|Ki|R   
+14 CMP|R|R     
+15 CMP|R|K     
+16 ADD|R|R     
+17 ADD|R|K     
+18 ADDC|R|R    
+19 ADDC|R|K    
+20 SUB|R|R     
+21 SUB|R|K     
+22 SUBC|R|R    
+23 SUBC|R|K    
+24 AND|R|R     
+25 AND|R|K     
+26 OR|R|R      
+27 OR|R|K      
+28 XOR|R|R     
+29 XOR|R|K     
+30 SHL|R       
+31 SHR|R       
+32 ROL|R       
+33 ROR|R       
+34 ROLC|R      
+35 RORC|R      
+36 XOUT|Ki|R   
+37 XOUT|Ri|K   
+38 COUT|Ki|R   
+39 COUT|Ri|K   
+40 XIN|R|Ki    
+41 CIN|R|Ki    
+42 SWAP|R      
+43 SETC        
+44 UNDEF       
+45 UNDEF       
+46 SUB|K|R     
+47 SUBC|K|R    
+48 JMP|K       
+49 JZ|K        
+50 JNZ|K       
+51 JC|K        
+52 JNC|K       
+53 JLT|K       
+54 JGT|K       
+55 JLE|K       
+56 JGE|K       
+57 JEQ|K       
+58 JNE|K       
+59 CALL|K      
+60 PUSH|R      
+61 POP|R       
+62 RET         
+63 RETI        
diff --git a/lib/CPUs/JCpu/tools/regx.rb b/lib/CPUs/JCpu/tools/regx.rb
new file mode 100644
index 0000000..47775c9
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/regx.rb
@@ -0,0 +1,20 @@
+#!/usr/bin/env ruby
+
+st = "\033[7m"
+en = "\033[m"
+
+ while TRUE
+   print "str> "
+   STDOUT.flush
+   str = gets
+   break if not str
+   str.chop!
+   print "pat> "
+   STDOUT.flush
+   re = gets
+   break if not re
+   re.chop!
+   str.gsub! re, "#{st}\\&#{en}"
+   print str, "\n"
+end
+print "\n"
diff --git a/lib/CPUs/JCpu/tools/rom.tcl.tpl b/lib/CPUs/JCpu/tools/rom.tcl.tpl
new file mode 100644
index 0000000..9f5c0dc
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/rom.tcl.tpl
@@ -0,0 +1,61 @@
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: The ROM file for upload to target over JTAG 
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+# ---------------------------------------------------------------------
+# For Chipscope 9.1
+# ---------------------------------------------------------------------
+# Source JTAG/TCL frame work
+cd $env(CHIPSCOPE)\\bin\\nt
+source csejtag.tcl
+
+namespace import ::chipscope::*
+
+# Platform USB Cable
+set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
+# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
+
+# Create session
+set handle [::chipscope::csejtag_session create 0]
+
+# Open JTAG and lock
+set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
+set lock_result [::chipscope::csejtag_target lock $handle 1000]
+
+set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
+
+# Get Device ID
+set devtype "Virtex-4SX"
+set devid 2
+set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
+set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
+
+set CSE_OP $CSEJTAG_SHIFT_READWRITE
+set CSE_ES $CSEJTAG_RUN_TEST_IDLE
+
+# Write Program
+# JASM_ROM_INSERT_HERE
+
+::chipscope::csejtag_target unlock $handle
+::chipscope::csejtag_target close $handle
+::chipscope::csejtag_session destroy $handle
+exit
diff --git a/lib/CPUs/JCpu/tools/templates.rb b/lib/CPUs/JCpu/tools/templates.rb
new file mode 100644
index 0000000..632f11c
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/templates.rb
@@ -0,0 +1,44 @@
+#!/usr/bin/env ruby
+
+
+template = <<'END'
+		-- (tv #1342) read output FIFO
+		(
+			cycles		=>	1,
+			cm_i		=>	bus_read_init(addr => ADDR_KS_OFIFO_DOUT),
+			sep			=>	msg(""),
+			cm_o 		=>	bus_no_ack,
+			irq			=>	(others => '0')
+		),
+
+		-- (tv #1343) wait while FIFO is read
+		(
+			cycles		=>	2,
+			cm_i		=>	bus_wait_ack,
+			sep			=>	msg(""),
+			cm_o 		=>	bus_no_ack,
+			irq			=>	(others => '0')
+		),
+
+		-- (tv #1343) wait for ack
+		(
+			cycles		=>	1,
+			cm_i		=>	bus_wait_ack,
+			sep			=>	msg(""),
+			cm_o 		=>	bus_read_ack(dat => #{exp_data}),
+			irq			=>	(others => '0')
+		),
+
+END
+
+puts "KS-128 testvectors:\n"
+puts "\n" * 3
+
+
+0.upto(10) { |sk_no|
+	3.downto(0) { |sl_no|
+		exp_data = "slice_32(TC1_SUBKEYS(#{sk_no}), #{sl_no})"
+		t = template.gsub(/"/, '\\"')
+		puts eval("format(\"#{t}\")")
+	}
+}
diff --git a/lib/CPUs/JCpu/tools/xrom.vhd.tpl b/lib/CPUs/JCpu/tools/xrom.vhd.tpl
new file mode 100644
index 0000000..5f11f86
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/xrom.vhd.tpl
@@ -0,0 +1,32 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+
diff --git a/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl b/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl
new file mode 100644
index 0000000..696487f
--- /dev/null
+++ b/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl
@@ -0,0 +1,151 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY xrom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		dout		: out dmem_data_t
+	);
+	
+END xrom;
+
+ARCHITECTURE loadable OF xrom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: dmem_addr_t;
+	signal jtag_ld_dout		: dmem_data_t;
+	signal jtag_ld_din		: dmem_data_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (15 downto 0);
+	constant id : unsigned (15 downto 0) := X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
+	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;
diff --git a/lib/CPUs/MIPS/sim/compile_simprim.do b/lib/CPUs/MIPS/sim/compile_simprim.do
new file mode 100644
index 0000000..16b23bb
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/compile_simprim.do
@@ -0,0 +1,6 @@
+vlib simprim
+
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd
diff --git a/lib/CPUs/MIPS/sim/compile_unisim.do b/lib/CPUs/MIPS/sim/compile_unisim.do
new file mode 100644
index 0000000..d35d8c9
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/compile_unisim.do
@@ -0,0 +1,6 @@
+vlib unisim
+
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd
diff --git a/lib/CPUs/MIPS/sim/tb_eval_muldiv.fdo b/lib/CPUs/MIPS/sim/tb_eval_muldiv.fdo
new file mode 100644
index 0000000..3b3c920
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_eval_muldiv.fdo
@@ -0,0 +1,13 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/tb_eval_muldiv.vhd"
+vsim -t 1ps   -lib work tb_eval_muldiv
+do {tb_eval_muldiv.wdo}
+view wave
+
+view structure
+view signals
+run 2400ns
diff --git a/lib/CPUs/MIPS/sim/tb_eval_muldiv.wdo b/lib/CPUs/MIPS/sim/tb_eval_muldiv.wdo
new file mode 100644
index 0000000..e742ca4
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_eval_muldiv.wdo
@@ -0,0 +1,27 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_eval_muldiv/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op1_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op2_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp0
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp1
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp2
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp3
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result_reg
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {693234 ps} 0} {{Cursor 2} {290409 ps} 0}
+configure wave -namecolwidth 149
+configure wave -valuecolwidth 171
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {2520 ns}
diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded.fdo b/lib/CPUs/MIPS/sim/tb_mips_embedded.fdo
new file mode 100644
index 0000000..49ea3ab
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_embedded.fdo
@@ -0,0 +1,22 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/core/mips_idecode_rom.vhd"
+vcom -explicit  -93 "../src/core/mips_reg.vhd"
+vcom -explicit  -93 "../src/core/mips_shifter.vhd"
+vcom -explicit  -93 "../src/core/mips_alu.vhd"
+vcom -explicit  -93 "../src/core/mips_bcu.vhd"
+vcom -explicit  -93 "../src/core/mips_pipeline.vhd"
+vcom -explicit  -93 "../src/core/mips_top.vhd"
+vcom -explicit  -93 "../src/ram.vhd"
+vcom -explicit  -93 "../asm/fibonacci.vhd"
+vcom -explicit  -93 "../src/mips_embedded.vhd"
+vcom -explicit  -93 "../src/tb_mips_embedded.vhd"
+vsim -t 1ps   -lib work tb_mips_embedded
+do {tb_mips_embedded.wdo}
+view wave
+view structure
+view signals
+run 20us
diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded.wdo b/lib/CPUs/MIPS/sim/tb_mips_embedded.wdo
new file mode 100644
index 0000000..7115717
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_embedded.wdo
@@ -0,0 +1,41 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mips_embedded/rst
+add wave -noupdate -format Logic /tb_mips_embedded/clk
+add wave -noupdate -format Logic /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/exception
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/pc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_ram/sram
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_dout
+add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_re
+add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_din
+add wave -noupdate -format Logic /tb_mips_embedded/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/id_stage
+add wave -noupdate -format Logic /tb_mips_embedded/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/ex_stage
+add wave -noupdate -format Logic /tb_mips_embedded/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/mem_stage
+add wave -noupdate -format Logic /tb_mips_embedded/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/wb_stage
+add wave -noupdate -format Logic /tb_mips_embedded/clk
+add wave -noupdate -format Literal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/hdu
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {624000 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {2520 ns}
diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.fdo b/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.fdo
new file mode 100644
index 0000000..97872a0
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.fdo
@@ -0,0 +1,31 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/core/mips_idecode_rom.vhd"
+vcom -explicit  -93 "../src/core/mips_reg.vhd"
+vcom -explicit  -93 "../src/core/mips_shifter.vhd"
+vcom -explicit  -93 "../src/core/mips_alu.vhd"
+vcom -explicit  -93 "../src/core/mips_bcu.vhd"
+vcom -explicit  -93 "../src/core/mips_pipeline.vhd"
+vcom -explicit  -93 "../src/core/mips_muldiv.vhd"
+vcom -explicit  -93 "../src/core/mips_cop.vhd"
+vcom -explicit  -93 "../src/core/mips_bui.vhd"
+vcom -explicit  -93 "../src/core/mips_top.vhd"
+vcom -explicit  -93 "../src/core/dcache.vhd"
+vcom -explicit  -93 "../asm/testbench.ROM.vhd"
+vcom -explicit  -93 "../src/mips_embedded.vhd"
+vcom -explicit  -93 "../src/mips_embedded_syn.vhd"
+vcom -explicit  -93 "../../../uart/bbfifo_16x8.vhd"
+vcom -explicit  -93 "../../../uart/kcuart_rx.vhd"
+vcom -explicit  -93 "../../../uart/kcuart_tx.vhd"
+vcom -explicit  -93 "../../../uart/uart_rx.vhd"
+vcom -explicit  -93 "../../../uart/uart_tx.vhd"
+vcom -explicit  -93 "../src/tb_mips_embedded_syn.vhd"
+vsim -t 1ps   -lib work tb_mips_embedded_syn
+do {tb_mips_embedded_syn.wdo}
+view wave
+view structure
+view signals
+run 100us
diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.tdo b/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.tdo
new file mode 100644
index 0000000..f9e8902
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.tdo
@@ -0,0 +1,13 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+
+vcom -explicit  -93 "../syn/ise9/netgen/par/mips_embedded_syn_timesim.vhd"
+vcom -explicit  -93 "../src/tb_mips_embedded_syn.vhd"
+vsim -t 1ps -sdfmax "/uut=../syn/ise9/netgen/par/mips_embedded_syn_timesim.sdf"  -lib work tb_mips_embedded_syn
+do {tb_mips_embedded_syn.wdo}
+view wave
+#add wave *
+view structure
+view signals
+run 2400ns
diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.wdo b/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.wdo
new file mode 100644
index 0000000..9b1276c
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.wdo
@@ -0,0 +1,112 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_rx
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_tx
+add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_rst_n_in
+add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_clk_in
+add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_led
+add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_dip
+add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_btn
+add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_error
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_rst
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_run
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_rx
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_tx
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_ctrl
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_baud
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/uart_status_port
+add wave -noupdate -format Literal -radix decimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_sec
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_rdy
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_en
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_re
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_dout
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_bui/s
+add wave -noupdate -divider DMEM
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_dout
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_en
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_we
+add wave -noupdate -divider IMEM
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/imem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_din
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_en
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc_run
+add wave -noupdate -divider PC
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/hdu
+add wave -noupdate -divider Stages
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/halt
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_reg_dual_a/reg_mem
+add wave -noupdate -divider Cop
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ir_valid
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_id
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_ex
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_ex_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_out
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_entered
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/epc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cause
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/events
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/eflags
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/badvaddr
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/rst
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exception
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_save
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_rest
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_strobe
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ip
+add wave -noupdate -divider Stages
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/id_stage
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_dout
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/ex_stage
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/mem_stage
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/wb_stage
+add wave -noupdate -divider Muldiv
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/result
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/start
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/busy
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/hilo_sel
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_hi
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_lo
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1121030000 ps} 0} {{Cursor 2} {1436367 ps} 0} {{Cursor 3} {1122030000 ps} 0}
+configure wave -namecolwidth 179
+configure wave -valuecolwidth 89
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {1351336 ps} {1583596 ps}
diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo
new file mode 100644
index 0000000..b272e38
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo
@@ -0,0 +1,15 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/core/mips_muldiv.vhd"
+vcom -explicit  -93 "../src/tb_mips_muldiv.vhd"
+vsim -t 1ps   -lib work tb_mips_muldiv
+do {tb_mips_muldiv.wdo}
+view wave
+
+view structure
+view signals
+run 5000us
diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.ndo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.ndo
new file mode 100644
index 0000000..70cb8bb
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_muldiv.ndo
@@ -0,0 +1,19 @@
+## NOTE: Do not edit this file.
+## Auto generated by Project Navigator for Post-Translate Simulation
+##
+vlib work
+## Compile Post-Translate Model
+vcom -explicit  -93 "../syn/eval_muldiv/netgen/translate/muldiv_translate.vhd"
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/tb_mips_muldiv.vhd"
+
+vsim -t 1ps  -lib work tb_mips_muldiv
+#do {tb_mips_muldiv.udo}
+view wave
+add wave *
+view structure
+view signals
+run 1000ns
+## End
diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.sdo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.sdo
new file mode 100644
index 0000000..9546784
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_muldiv.sdo
@@ -0,0 +1,19 @@
+## NOTE: Do not edit this file.
+## Auto generated by Project Navigator for Post-Translate Simulation
+##
+vlib work
+## Compile Post-Translate Model
+vcom -explicit  -93 "../syn/eval_muldiv/netgen/synthesis/muldiv_synthesis.vhd"
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/tb_mips_muldiv.vhd"
+
+vsim -t 1ps  -lib work tb_mips_muldiv
+do {tb_mips_muldiv.wdo}
+view wave
+#add wave *
+view structure
+view signals
+run 1000ns
+## End
diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo
new file mode 100644
index 0000000..2fc4121
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo
@@ -0,0 +1,79 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mips_muldiv/rst
+add wave -noupdate -format Logic /tb_mips_muldiv/clk
+add wave -noupdate -format Logic /tb_mips_muldiv/mul_divn
+add wave -noupdate -format Logic /tb_mips_muldiv/start
+add wave -noupdate -format Logic /tb_mips_muldiv/busy
+add wave -noupdate -format Logic /tb_mips_muldiv/s_un
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
+add wave -noupdate -format Logic /tb_mips_muldiv/hilo_sel
+add wave -noupdate -format Logic /tb_mips_muldiv/hilo_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/result
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_result
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_lo
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/pre_sum_vld
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/mul_en
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/sum_en
+add wave -noupdate -divider FSM
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
+add wave -noupdate -divider {Multiplier internals}
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_muldiv/uut/pprod
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyi
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyo
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op1
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_res
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op1
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_res
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_reg
+add wave -noupdate -divider {Divider internals}
+add wave -noupdate -format Logic /tb_mips_muldiv/busy
+add wave -noupdate -format Logic /tb_mips_muldiv/s_un
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_start
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_add_cyi
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op1
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_res
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m_n
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_q
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_qbit
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_en
+add wave -noupdate -divider FSM
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {4999822285 ps} 0} {{Cursor 2} {1278050000 ps} 0}
+configure wave -namecolwidth 149
+configure wave -valuecolwidth 171
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {5250 us}
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.fdo b/lib/CPUs/MIPS/sim/tb_mips_top.fdo
new file mode 100644
index 0000000..811b0b8
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_top.fdo
@@ -0,0 +1,22 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/core/mips_idecode_rom.vhd"
+vcom -explicit  -93 "../src/core/mips_reg.vhd"
+vcom -explicit  -93 "../src/core/mips_shifter.vhd"
+vcom -explicit  -93 "../src/core/mips_alu.vhd"
+vcom -explicit  -93 "../src/core/mips_bcu.vhd"
+vcom -explicit  -93 "../src/core/mips_pipeline.vhd"
+vcom -explicit  -93 "../src/core/mips_top.vhd"
+vcom -explicit  -93 "../asm/fibonacci.vhd"
+vcom -explicit  -93 "../src/ram.vhd"
+vcom -explicit  -93 "../src/tb_mips_top.vhd"
+vsim -t 1ps   -lib work tb_mips_top
+do {tb_mips_top.wdo}
+view wave
+view structure
+view signals
+run 40000ns
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.mdo b/lib/CPUs/MIPS/sim/tb_mips_top.mdo
new file mode 100644
index 0000000..1ba3832
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_top.mdo
@@ -0,0 +1,18 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+## Compile Post-Map Model
+vcom -explicit  -93 "../syn/ise9/netgen/map/mips_top_map.vhd"
+vsim -t 1ps -sdfmax "/mips_top=../syn/ise9/netgen/map/mips_top_map.sdf"  -lib work mips_top
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/irom_hello.vhd"
+vcom -explicit  -93 "../src/tb_mips_top.vhd"
+vsim -t 1ps   -lib work tb_mips_top
+do {tb_mips_top.mwdo}
+view wave
+#add wave *
+view structure
+view signals
+run 2400ns
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.mwdo b/lib/CPUs/MIPS/sim/tb_mips_top.mwdo
new file mode 100644
index 0000000..b24adae
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_top.mwdo
@@ -0,0 +1,31 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mips_top/rst
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Logic /tb_mips_top/ce
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr
+add wave -noupdate -format Logic /tb_mips_top/dmem_we
+add wave -noupdate -format Logic /tb_mips_top/dmem_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_op2
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_result
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {77481 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {729730 ps}
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.sdo b/lib/CPUs/MIPS/sim/tb_mips_top.sdo
new file mode 100644
index 0000000..25435ef
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_top.sdo
@@ -0,0 +1,16 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../syn/ise9/netgen/synthesis/mips_top_synthesis.vhd"
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/irom_hello.vhd"
+vcom -explicit  -93 "../src/tb_mips_top.vhd"
+vsim -t 1ps   -lib work tb_mips_top
+#do {tb_mips_top.wdo}
+view wave
+add wave *
+view structure
+view signals
+run 2400ns
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo
new file mode 100644
index 0000000..833e5af
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_top.wdo
@@ -0,0 +1,51 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mips_top/rst
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Logic /tb_mips_top/cpu_halt
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout
+add wave -noupdate -format Logic /tb_mips_top/dmem_re
+add wave -noupdate -format Logic /tb_mips_top/dmem_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_ram/sram
+add wave -noupdate -divider ALU
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -divider PC
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/exception
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/stall
+add wave -noupdate -divider PC
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/if_stage
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
+add wave -noupdate -format Logic /tb_mips_top/clk
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 188
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {42 us}
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.mdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.mdo
new file mode 100644
index 0000000..91b4dc0
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_top_syn.mdo
@@ -0,0 +1,17 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+## Compile Post-Map Model
+vcom -explicit  -93 "../syn/ise9/netgen/map/mips_top_syn_map.vhd"
+vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/map/mips_top_syn_map.sdf"  -lib work mips_top_syn
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/irom_hello.vhd"
+vcom -explicit  -93 "../src/tb_mips_top_syn.vhd"
+vsim -t 1ps   -lib work tb_mips_top_syn
+do {tb_mips_top_syn.wdo}
+view wave
+#add wave *
+view structure
+view signals
+run 2400ns
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.tdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.tdo
new file mode 100644
index 0000000..cc7c65d
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_top_syn.tdo
@@ -0,0 +1,17 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+## Compile Post-Map Model
+vcom -explicit  -93 "../syn/ise9/netgen/par/mips_top_syn_timesim.vhd"
+vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/par/mips_top_syn_timesim.sdf"  -lib work mips_top_syn
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/irom_hello.vhd"
+vcom -explicit  -93 "../src/tb_mips_top_syn.vhd"
+vsim -t 1ps   -lib work tb_mips_top_syn
+do {tb_mips_top_syn.wdo}
+view wave
+#add wave *
+view structure
+view signals
+run 2400ns
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo
new file mode 100644
index 0000000..eafadd7
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo
@@ -0,0 +1,31 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mips_top_syn/rst
+add wave -noupdate -format Logic /tb_mips_top_syn/clk
+add wave -noupdate -format Logic /tb_mips_top_syn/ce
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_addr
+add wave -noupdate -format Logic /tb_mips_top_syn/dmem_we
+add wave -noupdate -format Logic /tb_mips_top_syn/dmem_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_id_stage_boff
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_stage_ex_inst_alu_sum_res
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top_syn/sram
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {118199 ps} 0}
+configure wave -namecolwidth 188
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {2520 ns}
diff --git a/lib/CPUs/MIPS/src/core/dcache.vhd b/lib/CPUs/MIPS/src/core/dcache.vhd
new file mode 100644
index 0000000..367c9d5
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/dcache.vhd
@@ -0,0 +1,430 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use IEEE.MATH_REAL.ALL;
+
+library work;
+use work.mips_types.all;
+
+ENTITY dcache IS
+	Generic
+	(
+		cache_size	: natural := 2048;	-- words
+		line_size	: natural := 8		-- words
+	);
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		rst			: in  STD_LOGIC;
+		en			: in  STD_LOGIC;
+		cpu_en		: in  STD_LOGIC;
+		cpu_r_wn	: in  STD_LOGIC;
+		cpu_we		: in  unsigned(3 downto 0);
+		cpu_addr	: in  word_t;
+		cpu_din		: in  word_t;
+		cpu_dout	: out word_t;
+		cpu_busy	: out STD_LOGIC;
+		mem_req		: out STD_LOGIC;
+		mem_gnt		: in  STD_LOGIC;
+		mem_en		: out STD_LOGIC;
+		mem_addr	: out word_t;
+		mem_din		: in  word_t;
+		mem_valid	: in  STD_LOGIC;
+		mem_rdy		: in  STD_LOGIC
+	);
+END dcache;
+
+ARCHITECTURE behavior OF dcache IS
+
+COMPONENT dpram_1w1r
+	GENERIC
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	PORT (
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+END COMPONENT;
+
+COMPONENT dpram_2w2r is
+	GENERIC 
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	PORT
+	(
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+END COMPONENT;
+
+	function lg2(x : natural) return natural is
+	begin
+		return natural(ceil(log2(real(x))));
+	end lg2;	
+	
+	function po2(x : natural) return natural is
+	begin
+
+		return 2**lg2(x);
+	end po2;	
+
+	constant word_index_width	: natural := lg2(line_size);
+	constant cache_index_width	: natural := lg2(cache_size) - word_index_width;
+	constant tag_width			: natural := 32 - word_index_width - cache_index_width - 2;
+	constant tag_parity_width	: natural := 3;
+	constant tram_data_width	: natural := 2 + tag_parity_width + tag_width;
+	constant tram_addr_width	: natural := cache_index_width;
+	
+	subtype	tram_data_t is unsigned (tram_data_width-1 downto 0);
+
+	type dcache_entry_t is record
+		valid	: std_logic;
+		dirty	: std_logic;
+		tv_p	: unsigned(tag_parity_width-1 downto 0);
+		tag		: unsigned(tag_width-1 downto 0);
+	end record;
+	
+	alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
+	alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
+	alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
+	
+	function to_dcache_entry(x : tram_data_t) return dcache_entry_t is
+	variable result : dcache_entry_t;
+	begin
+		result.valid	:= x(0);
+		result.dirty	:= x(1);
+		result.tv_p		:= x(4 downto 2);
+		result.tag		:= x(tag_width+4 downto 5);
+		
+		return result;
+	end to_dcache_entry;
+
+	function to_tram_data(x : dcache_entry_t) return tram_data_t is
+	variable result : tram_data_t;
+	begin
+		result(0)										:= x.valid;
+		result(1)										:= x.dirty;
+		result(4 downto 2)								:= x.tv_p;
+		result(tag_width+4 downto 5)					:= x.tag;
+		
+		return result;
+	end to_tram_data;
+
+	type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache, wr_cache);
+	signal s, sn : cache_state_t;
+	
+	signal	cache_busy			: std_logic;
+	signal	cache_read_miss		: std_logic;
+	signal	cache_write_miss	: std_logic;
+	signal	tag_match			: std_logic;
+	signal  word_index_reg		: unsigned(word_index_width-1 downto 0);
+	signal  cache_index_reg		: unsigned(cache_index_width-1 downto 0);
+	signal  tag_index_reg		: unsigned(tag_width-1 downto 0);
+	
+	signal	cache_entry_in		: dcache_entry_t;
+	signal	cache_entry_out		: dcache_entry_t;
+	signal  cpu_dram_addr		: unsigned(lg2(cache_size)-1 downto 0);
+	signal  cpu_dram_dout		: word_t;
+	signal  cpu_dram_din		: word_t;
+	signal  cpu_data_reg		: word_t;
+	signal  cpu_we_reg			: unsigned(3 downto 0);
+	signal  ctrl_force_we		: unsigned(3 downto 0);
+	signal  cpu_was_write		: std_logic;
+	signal  ctrl_dram_addr		: unsigned(lg2(cache_size)-1 downto 0);
+	signal  ctrl_dram_din		: word_t;
+	signal	ctrl_dram_we		: unsigned(3 downto 0);
+	signal	cpu_dram_we			: unsigned(3 downto 0);
+	signal	dram_en				: std_logic;
+	signal	cpu_was_en			: std_logic;
+
+	signal  tram_addr_rd		: unsigned(cache_index_width-1 downto 0);
+	signal  tram_dout			: tram_data_t;
+	signal  tram_addr_wr		: unsigned(cache_index_width-1 downto 0);
+	signal  tram_din			: tram_data_t;
+	signal	tram_re				: std_logic;
+	signal	tram_we				: std_logic;
+	
+	signal	ram_index_count			: natural range 0 to 2**word_index_width-1;
+	signal	ram_index_count_rst		: std_logic;
+	signal	cache_index_count		: natural range 0 to 2**cache_index_width-1;
+	signal	cache_index_count_en	: std_logic;
+	signal	mem_index_count			: natural range 0 to 2**word_index_width-1;
+	signal	mem_index_count_en		: std_logic;
+	signal	mem_index_count_rst		: std_logic;
+	signal	cpu_reg_en				: std_logic;
+	signal	was_miss				: std_logic;
+	signal	data_write				: std_logic;
+	signal	cpu_we2					: std_logic;
+
+begin
+
+	
+cpu_index_reg:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				cache_index_reg	<= (others => '0');
+				tag_index_reg	<= (others => '0');
+				cpu_was_write	<= '0';
+			elsif cpu_reg_en = '1' and en = '1' then
+				word_index_reg	<= cpu_word_index;
+				cache_index_reg	<= cpu_cache_index;
+				tag_index_reg	<= cpu_tag;
+				cpu_data_reg	<= cpu_din;
+				cpu_we_reg		<= cpu_we;
+				cpu_was_write	<= not cpu_r_wn;
+			end if;
+		end if;
+	end process;	
+
+cpu_was_wr_reg:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			cpu_was_en	<= '0';
+			cpu_we2		<= '0';
+			if cpu_en = '1' and en = '1' then
+				cpu_we2		<= not cpu_r_wn;
+				cpu_was_en	<= '1';
+				cpu_dram_din	<= cpu_din;
+			end if;
+		end if;
+	end process;	
+
+inst_tag_ram : dpram_1w1r
+	GENERIC MAP (
+		addr_width	=> tram_addr_width,
+		data_width	=> tram_data_width
+	)
+	PORT MAP (
+		clka	=> clk,
+		clkb	=> clk,
+		en_a	=> '1',
+		en_b	=> tram_re,
+		we_a	=> tram_we,
+		addr_a	=> tram_addr_wr,
+		addr_b	=> tram_addr_rd,
+		din_a	=> tram_din,
+		dout_b	=> tram_dout
+	);
+
+gen_data_ram:
+	for i in 0 to 3 generate
+	begin
+	
+	inst_data_ram : dpram_2w2r
+		GENERIC MAP (
+			addr_width	=> lg2(cache_size),
+			data_width	=> word_t'length/4
+		)
+		PORT MAP (
+			clk_a	=> clk,
+			clk_b	=> clk,
+			en_a	=> '1',
+			en_b	=> dram_en,
+			we_a	=> ctrl_dram_we(i),
+			we_b	=> cpu_dram_we(i),
+			addr_a	=> ctrl_dram_addr,
+			addr_b	=> cpu_dram_addr,
+			din_a	=> ctrl_dram_din(8*(i+1)-1 downto 8*i),
+			din_b	=> cpu_dram_din(8*(i+1)-1 downto 8*i),
+			dout_a	=> open,
+			dout_b	=> cpu_dram_dout(8*(i+1)-1 downto 8*i)
+		);
+	end generate;	
+	
+cache_state_next:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				s	<= init;
+			else
+				s	<= sn;
+			end if;
+		end if;
+	end process;	
+
+	cpu_busy			<= cache_busy;
+	cpu_dout			<= cpu_dram_dout;
+	
+	tag_match			<= '1' when tag_index_reg = cache_entry_out.tag else '0';
+	cache_read_miss		<= not (tag_match and cache_entry_out.valid) and not cpu_was_write;
+	cache_write_miss	<= not (tag_match and cache_entry_out.valid and cpu_was_write);
+	tram_din			<= to_tram_data(cache_entry_in);
+	tram_addr_rd		<= cpu_cache_index when was_miss = '0' else cache_index_reg;
+	cache_entry_out		<= to_dcache_entry(tram_dout);
+	cpu_dram_addr		<= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_we2 = '0') else (cache_index_reg & word_index_reg);
+	mem_addr			<= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
+	ctrl_dram_addr		<= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
+	ctrl_dram_din		<= mem_din;
+	ctrl_dram_we		<= (3 downto 0 => (data_write and mem_valid)) or ctrl_force_we;
+	cpu_dram_we			<= cpu_we_reg when (cpu_we2 = '1' and cache_write_miss = '0') else (others => '0');
+	
+cache_state:
+	process(s, cache_read_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, cpu_r_wn, mem_gnt, mem_rdy, cpu_was_en, cpu_was_write, cpu_we_reg)
+	begin
+		cpu_reg_en				<= '0';
+		cache_busy 				<= '1';
+		tram_we					<= '0';
+		cache_index_count_en	<= '0';
+		ram_index_count_rst		<= '0';
+		mem_index_count_en		<= '0';
+		mem_index_count_rst		<= '0';
+		mem_req					<= '0';
+		mem_en					<= '0';
+		dram_en					<= '0';
+		tram_re					<= '0';
+		was_miss				<= '0';
+		data_write				<= '0';
+		tram_addr_wr			<= to_unsigned(cache_index_count, cache_index_width);
+		cache_entry_in.tv_p		<= (others => '0');
+		cache_entry_in.tag		<= tag_index_reg;
+		cache_entry_in.valid	<= '0';
+		cache_entry_in.dirty	<= '0';
+		ctrl_force_we			<= (others => '0');
+		sn	<= s;
+		
+		case s is
+		when init =>
+			sn <= flush;
+		when ready =>
+			cache_busy 		<= '0';
+			cpu_reg_en		<= '1';
+			dram_en			<= cpu_en or cpu_was_en;
+			tram_re			<= cpu_en;
+			if cpu_was_en = '1' then
+				if cache_read_miss = '1' then
+					sn						<= mem_request;
+					cpu_reg_en				<= '0';
+					cache_busy 				<= '1';
+				end if;	
+			end if;	
+		when flush =>
+			cache_index_count_en	<= '1';
+			tram_addr_wr			<= to_unsigned(cache_index_count, cache_index_width);
+			tram_we				<= '1';
+			cache_entry_in.valid	<= '0';
+			cache_entry_in.tag		<= (others => '0');
+			if cache_index_count = 0 then
+				sn	<= ready;
+				if cpu_en = '1' then
+					cpu_reg_en			<= '1';
+					dram_en			<= '1';
+					tram_re			<= '1';
+				end if;
+			end if;
+		when mem_request =>
+			ram_index_count_rst		<= '1';
+			mem_index_count_rst		<= '1';
+			mem_req		<= '1';
+			if mem_gnt = '1' then
+				sn <= mem_access;
+			end if;	
+		when mem_access =>
+			data_write	<= '1';
+			mem_req		<= '1';
+			if mem_rdy = '1' then
+				mem_index_count_en	<= '1';
+				mem_en				<= '1';
+				if mem_index_count = 2**word_index_width-1 then
+					sn			<= mem_data;
+				end if;	
+			end if;	
+		when mem_data =>
+			mem_req		<= '1';
+			data_write	<= '1';
+			if ram_index_count = 2**word_index_width-1 then
+				if mem_valid = '1' then
+					sn			<= upd_cache;
+				end if;	
+			end if;	
+		when upd_cache =>
+			mem_req					<= '1';
+			tram_addr_wr			<= cache_index_reg;
+			tram_we					<= '1';
+			cache_entry_in.valid	<= '1';
+			if cpu_was_write = '1' then
+				sn					<= wr_cache;
+			else	
+				sn					<= rd_cache;
+			end if;	
+			
+		when rd_cache =>
+			tram_re					<= '1';
+			dram_en					<= '1';
+			was_miss				<= '1';
+			sn	<= ready;
+
+		when wr_cache =>
+			tram_re					<= '1';
+			ctrl_force_we			<= cpu_we_reg;
+			sn	<= ready;
+		when others => 
+			sn	<= ready;
+		end case;
+	end process;
+
+cache_index_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if cache_index_count_en = '0' then
+				cache_index_count	<= 2**cache_index_width-1;
+			elsif cache_index_count /= 0 then
+				cache_index_count	<= cache_index_count - 1;
+			end if;
+		end if;
+	end process;	
+		
+ram_index_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if ram_index_count_rst = '1' then
+				ram_index_count	<= 0;
+			elsif data_write = '1' and mem_valid = '1' then
+				if ram_index_count /= 2**word_index_width-1 then
+					ram_index_count 	<= ram_index_count + 1;
+				end if;
+			end if;	
+		end if;
+	end process;	
+
+mem_index_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if mem_index_count_rst = '1' then
+				mem_index_count	<= 0;
+			elsif mem_index_count_en = '1' then
+				if mem_index_count /= 2**word_index_width-1 then
+					mem_index_count 	<= mem_index_count + 1;
+				end if;
+			end if;	
+		end if;
+	end process;	
+
+end behavior;
diff --git a/lib/CPUs/MIPS/src/core/icache.vhd b/lib/CPUs/MIPS/src/core/icache.vhd
new file mode 100644
index 0000000..d7e3026
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/icache.vhd
@@ -0,0 +1,356 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use IEEE.MATH_REAL.ALL;
+
+library work;
+use work.mips_types.all;
+
+ENTITY icache IS
+	Generic
+	(
+		cache_size	: natural := 2048;	-- words
+		line_size	: natural := 8		-- words
+	);
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		rst			: in  STD_LOGIC;
+		en			: in  STD_LOGIC;
+		cpu_en		: in  STD_LOGIC;
+		cpu_addr	: in  word_t;
+		cpu_dout	: out word_t;
+		cpu_busy	: out STD_LOGIC;
+		mem_req		: out STD_LOGIC;
+		mem_gnt		: in  STD_LOGIC;
+		mem_en		: out STD_LOGIC;
+		mem_addr	: out word_t;
+		mem_din		: in  word_t;
+		mem_valid	: in  STD_LOGIC;
+		mem_rdy		: in  STD_LOGIC
+	);
+END icache;
+
+ARCHITECTURE behavior OF icache IS
+
+COMPONENT dpram_1w1r
+	GENERIC
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	PORT (
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+END COMPONENT;
+
+	function lg2(x : natural) return natural is
+	begin
+		return natural(ceil(log2(real(x))));
+	end lg2;	
+	
+	function po2(x : natural) return natural is
+	begin
+
+		return 2**lg2(x);
+	end po2;	
+
+	constant word_index_width	: natural := lg2(line_size);
+	constant cache_index_width	: natural := lg2(cache_size) - word_index_width;
+	constant tag_width			: natural := 32 - word_index_width - cache_index_width - 2;
+	constant tag_parity_width	: natural := 3;
+	constant tag_ram_data_width	: natural := 1 + tag_parity_width + tag_width;
+	constant tag_ram_addr_width	: natural := cache_index_width;
+	
+	subtype	tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0);
+
+	type icache_entry_t is record
+		valid	: std_logic;
+		tv_p	: unsigned(tag_parity_width-1 downto 0);
+		tag		: unsigned(tag_width-1 downto 0);
+	end record;
+	
+	alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
+	alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
+	alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
+	
+	function to_icache_entry(x : tag_ram_data_t) return icache_entry_t is
+	variable result : icache_entry_t;
+	begin
+		result.valid	:= x(0);
+		result.tv_p		:= x(3 downto 1);
+		result.tag		:= x(tag_width+3 downto 4);
+		
+		return result;
+	end to_icache_entry;
+
+	function to_tag_ram_data(x : icache_entry_t) return tag_ram_data_t is
+	variable result : tag_ram_data_t;
+	begin
+		result(0)										:= x.valid;
+		result(3 downto 1)								:= x.tv_p;
+		result(tag_width+3 downto 4)					:= x.tag;
+		
+		return result;
+	end to_tag_ram_data;
+
+	type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache);
+	signal s, sn : cache_state_t;
+	
+	signal	cache_busy			: std_logic;
+	signal	cache_miss			: std_logic;
+	signal	tag_match			: std_logic;
+	signal  word_index_reg		: unsigned(word_index_width-1 downto 0);
+	signal  cache_index_reg		: unsigned(cache_index_width-1 downto 0);
+	signal  tag_index_reg		: unsigned(tag_width-1 downto 0);
+	
+	signal	cache_entry_in		: icache_entry_t;
+	signal	cache_entry_out		: icache_entry_t;
+	signal  data_ram_addr_rd	: unsigned(lg2(cache_size)-1 downto 0);
+	signal  data_ram_data_rd	: word_t;
+	signal  data_ram_addr_wr	: unsigned(lg2(cache_size)-1 downto 0);
+	signal  data_ram_data_wr	: word_t;
+	signal	data_ram_we			: std_logic;
+	signal	data_ram_re			: std_logic;
+
+	signal  tag_ram_addr_rd		: unsigned(cache_index_width-1 downto 0);
+	signal  tag_ram_data_rd		: tag_ram_data_t;
+	signal  tag_ram_addr_wr		: unsigned(cache_index_width-1 downto 0);
+	signal  tag_ram_data_wr		: tag_ram_data_t;
+	signal	tag_ram_re			: std_logic;
+	signal	tag_ram_we			: std_logic;
+	
+	signal	ram_index_count			: natural range 0 to 2**word_index_width-1;
+	signal	ram_index_count_rst		: std_logic;
+	signal	cache_index_count		: natural range 0 to 2**cache_index_width-1;
+	signal	cache_index_count_en	: std_logic;
+	signal	mem_index_count			: natural range 0 to 2**word_index_width-1;
+	signal	mem_index_count_en		: std_logic;
+	signal	mem_index_count_rst		: std_logic;
+	signal	cpu_reg_en				: std_logic;
+	signal	was_miss				: std_logic;
+	signal	data_write				: std_logic;
+
+begin
+
+	
+cpu_index_reg:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				cache_index_reg	<= (others => '0');
+				tag_index_reg	<= (others => '0');
+			elsif cpu_reg_en = '1' then
+				word_index_reg	<= cpu_word_index;
+				cache_index_reg	<= cpu_cache_index;
+				tag_index_reg	<= cpu_tag;
+			end if;
+		end if;
+	end process;	
+
+inst_tag_ram : dpram_1w1r
+	GENERIC MAP (
+		addr_width	=> tag_ram_addr_width,
+		data_width	=> tag_ram_data_width
+	)
+	PORT MAP (
+		clka	=> clk,
+		clkb	=> clk,
+		en_a	=> '1',
+		en_b	=> tag_ram_re,
+		we_a	=> tag_ram_we,
+		addr_a	=> tag_ram_addr_wr,
+		addr_b	=> tag_ram_addr_rd,
+		din_a	=> tag_ram_data_wr,
+		dout_b	=> tag_ram_data_rd
+	);
+
+inst_data_ram : dpram_1w1r
+	GENERIC MAP (
+		addr_width	=> lg2(cache_size),
+		data_width	=> word_t'length
+	)
+	PORT MAP (
+		clka	=> clk,
+		clkb	=> clk,
+		en_a	=> '1',
+		en_b	=> data_ram_re,
+		we_a	=> data_ram_we,
+		addr_a	=> data_ram_addr_wr,
+		addr_b	=> data_ram_addr_rd,
+		din_a	=> data_ram_data_wr,
+		dout_b	=> data_ram_data_rd
+	);
+	
+	
+cache_state_next:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				s	<= init;
+			else
+				s	<= sn;
+			end if;
+		end if;
+	end process;	
+
+	cpu_busy			<= cache_busy;
+	cpu_dout			<= data_ram_data_rd;
+	
+	tag_match			<= '1' when tag_index_reg = cache_entry_out.tag else '0';
+	cache_miss			<= not (tag_match and cache_entry_out.valid);
+	tag_ram_data_wr		<= to_tag_ram_data(cache_entry_in);
+	tag_ram_addr_rd		<= cpu_cache_index when was_miss = '0' else cache_index_reg;
+	cache_entry_out		<= to_icache_entry(tag_ram_data_rd);
+	data_ram_addr_rd	<= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (cache_index_reg & word_index_reg);
+	mem_addr			<= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
+	data_ram_addr_wr	<= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
+	data_ram_data_wr	<= mem_din;
+	data_ram_we			<= data_write and mem_valid;
+
+cache_state:
+	process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, mem_gnt, mem_rdy, en)
+	begin
+		cpu_reg_en				<= '0';
+		cache_busy 				<= '1';
+		tag_ram_we				<= '0';
+		cache_index_count_en	<= '0';
+		ram_index_count_rst		<= '0';
+		mem_index_count_en		<= '0';
+		mem_index_count_rst		<= '0';
+		mem_req					<= '0';
+		mem_en					<= '0';
+		data_ram_re				<= '0';
+		tag_ram_re				<= '0';
+		was_miss				<= '0';
+		data_write				<= '0';
+		tag_ram_addr_wr			<= to_unsigned(cache_index_count, cache_index_width);
+		cache_entry_in.tv_p		<= (others => '0');
+		cache_entry_in.tag		<= tag_index_reg;
+		cache_entry_in.valid	<= '0';
+		sn	<= s;
+		
+		case s is
+		when init =>
+			sn <= flush;
+		when ready =>
+			if en = '1' then
+				cache_busy 		<= '0';
+				if cache_miss = '1' then
+					sn						<= mem_request;
+					cpu_reg_en				<= '0';
+					cache_busy 				<= '1';
+				elsif cpu_en = '1' then
+					cpu_reg_en			<= '1';
+					data_ram_re			<= '1';
+					tag_ram_re			<= '1';
+				end if;	
+			end if;	
+		when flush =>
+			cache_index_count_en	<= '1';
+			tag_ram_addr_wr			<= to_unsigned(cache_index_count, cache_index_width);
+			tag_ram_we				<= '1';
+			cache_entry_in.valid	<= '0';
+			cache_entry_in.tag		<= (others => '0');
+			if cache_index_count = 0 then
+				sn	<= ready;
+				if cpu_en = '1' then
+					cpu_reg_en			<= '1';
+					data_ram_re			<= '1';
+					tag_ram_re			<= '1';
+				end if;
+			end if;
+		when mem_request =>
+			ram_index_count_rst		<= '1';
+			mem_index_count_rst		<= '1';
+			mem_req		<= '1';
+			if mem_gnt = '1' then
+				sn <= mem_access;
+			end if;	
+		when mem_access =>
+			data_write	<= '1';
+			mem_req		<= '1';
+			if mem_rdy = '1' then
+				mem_index_count_en	<= '1';
+				mem_en				<= '1';
+				if mem_index_count = 2**word_index_width-1 then
+					sn			<= mem_data;
+				end if;	
+			end if;	
+		when mem_data =>
+			mem_req		<= '1';
+			data_write	<= '1';
+			if ram_index_count = 2**word_index_width-1 then
+				if mem_valid = '1' then
+					sn			<= upd_cache;
+				end if;	
+			end if;	
+		when upd_cache =>
+			mem_req					<= '1';
+			tag_ram_addr_wr			<= cache_index_reg;
+			tag_ram_we				<= '1';
+			cache_entry_in.valid	<= '1';
+			sn						<= rd_cache;
+			
+		when rd_cache =>
+--			mem_req					<= '1';
+			tag_ram_re				<= '1';
+			data_ram_re				<= '1';
+			was_miss				<= '1';
+			sn	<= ready;
+		when others => 
+			sn	<= ready;
+		end case;
+	end process;
+
+cache_index_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if cache_index_count_en = '0' then
+				cache_index_count	<= 2**cache_index_width-1;
+			elsif cache_index_count /= 0 then
+				cache_index_count	<= cache_index_count - 1;
+			end if;
+		end if;
+	end process;	
+		
+ram_index_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if ram_index_count_rst = '1' then
+				ram_index_count	<= 0;
+			elsif data_write = '1' and mem_valid = '1' then
+				if ram_index_count /= 2**word_index_width-1 then
+					ram_index_count 	<= ram_index_count + 1;
+				end if;
+			end if;	
+		end if;
+	end process;	
+
+mem_index_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if mem_index_count_rst = '1' then
+				mem_index_count	<= 0;
+			elsif mem_index_count_en = '1' then
+				if mem_index_count /= 2**word_index_width-1 then
+					mem_index_count 	<= mem_index_count + 1;
+				end if;
+			end if;	
+		end if;
+	end process;	
+
+end behavior;
diff --git a/lib/CPUs/MIPS/src/core/mips_alu.vhd b/lib/CPUs/MIPS/src/core/mips_alu.vhd
new file mode 100644
index 0000000..a64b5a4
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/mips_alu.vhd
@@ -0,0 +1,184 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The arithmetic logic unit
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.mips_types.all;
+
+entity alu is
+	Generic 
+	(
+		data_width : integer := 8
+	);
+	Port 
+	(
+		op1_in		: in  unsigned (data_width-1 downto 0);
+		op2_in		: in  unsigned (data_width-1 downto 0);
+		op2_shifted	: in  unsigned (data_width-1 downto 0);
+		ctrl		: in  alu_ctrl_t;
+		result		: out unsigned (data_width-1 downto 0);
+		flags		: out alu_flags_t
+	);
+end alu;
+
+architecture Behavioral of alu is
+
+	signal sum_res			: unsigned (data_width-1 downto 0);
+	signal and_res			: unsigned (data_width-1 downto 0);
+	signal xor_res			: unsigned (data_width-1 downto 0);
+	signal nor_res			: unsigned (data_width-1 downto 0);
+	signal or_res			: unsigned (data_width-1 downto 0);
+	signal eq, sa, sb, sr, c, z	: STD_LOGIC;
+	signal lts, ltu			: STD_LOGIC;
+
+--------------------------------------------------------------------------
+begin
+
+	eq			<= '1' when op1_in = op2_in else '0' after 3 ns;
+	sa			<= op1_in(op1_in'left);
+	sb			<= op2_in(op2_in'left);
+	sr			<= sum_res(sum_res'left);
+	z			<= '1' when op1_in = (data_width-1 downto 0 => '0') else '0' after 2 ns;
+	
+	flags.uvf	<= (not ctrl.add) and ((sa and (not sb) and (not sr)) or ((not sa) and sb and sr));
+	flags.ovf	<= ctrl.add and ((sa and sb and (not sr)) or ((not sa) and (not sb) and sr));
+--	lts			<= (not eq) and (((not c) and sa and sb) or (((not sr) and sa) or (sa and (not sb)) or (sr and (not sb))));
+	lts			<= not eq and ((not c and sa) or (not sb and sa) or (not sb and sr));
+	
+	ltu			<= (not eq) and (not c);
+	flags.lts	<= lts;
+	flags.ltu	<= ltu;
+	flags.c		<= c;
+	
+--------------------------------------------------------------------------
+proc_op_and:
+	process(op1_in, op2_in)
+	variable x1, x2	: unsigned (data_width-1 downto 0);
+	begin
+		x1 := op1_in;
+		x2 := op2_in;
+
+		and_res <= (x1 and x2) after 1 ns;
+		
+	end process;
+
+--------------------------------------------------------------------------
+proc_proc_xor:
+	process(op1_in, op2_in)
+	variable x1, x2	: unsigned (data_width-1 downto 0);
+	begin
+		x1 := op1_in;
+		x2 := op2_in;
+		
+		xor_res <= (x1 xor x2) after 2 ns;
+		
+	end process;
+
+--------------------------------------------------------------------------
+proc_proc_nor:
+	process(op1_in, op2_in)
+	variable x1, x2	: unsigned (data_width-1 downto 0);
+	begin
+		x1 := op1_in;
+		x2 := op2_in;
+		
+		nor_res <= (x1 nor x2) after 1 ns;
+		
+	end process;
+
+--------------------------------------------------------------------------
+proc_proc_or:
+	process(op1_in, op2_in)
+	variable x1, x2	: unsigned (data_width-1 downto 0);
+	begin
+		x1 := op1_in;
+		x2 := op2_in;
+		
+		or_res <= (x1 or x2) after 1 ns;
+		
+	end process;
+
+--------------------------------------------------------------------------
+proc_alu_out:
+	process(ctrl, sum_res, and_res, xor_res, nor_res, or_res, op2_shifted, lts, ltu)
+	begin
+		
+		result		<= sum_res;
+		
+		case ctrl.outsel is
+		
+		when alu_adder =>
+			result 		<= sum_res;
+
+		when alu_and =>
+			result 		<= and_res;
+			
+		when alu_xor =>
+			result 		<= xor_res;
+
+		when alu_nor =>
+			result 		<= nor_res;
+
+		when alu_or =>
+			result 		<= or_res;
+
+		when alu_shift2 =>
+			result 		<= op2_shifted;
+
+		when alu_ltu =>
+			result		<= (data_width-1 downto 1 => '0') & ltu;
+
+		when alu_lts =>
+			result		<= (data_width-1 downto 1 => '0') & lts;
+
+		when others => null;
+
+		end case;
+		
+	end process;
+
+--------------------------------------------------------------------------
+alu_addsub:
+	process(op1_in, op2_in, ctrl)
+	variable sum  : unsigned(data_width+1 downto 0);
+	variable op1, op2 : unsigned(data_width+1 downto 0);
+	begin
+		
+		op1 := '0' & op1_in & not ctrl.add;
+		if (ctrl.add = '1') then
+			op2 := '0' & op2_in & '0';
+		else
+			op2 := '0' & not op2_in & '1';
+		end if;
+		sum := op1 + op2; 
+
+		-- Form sum + carry
+		sum_res <= unsigned(sum(data_width downto 1)) after 4 ns;
+		c <= sum(sum'left) after 4 ns;
+		
+	end process;	
+
+--------------------------------------------------------------------------
+end Behavioral;
diff --git a/lib/CPUs/MIPS/src/core/mips_bcu.vhd b/lib/CPUs/MIPS/src/core/mips_bcu.vhd
new file mode 100644
index 0000000..14e3f36
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/mips_bcu.vhd
@@ -0,0 +1,53 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The arithmetic logic unit
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.mips_types.all;
+
+entity bcu is
+	Generic 
+	(
+		data_width : integer := 8
+	);
+	Port 
+	(
+		op1_in		: in  unsigned (data_width-1 downto 0);
+		op2_in		: in  unsigned (data_width-1 downto 0);
+		flags		: out bcu_flags_t
+	);
+end bcu;
+
+architecture Behavioral of bcu is
+
+--------------------------------------------------------------------------
+begin
+
+	flags.eq	<= '1' when op1_in = op2_in else '0' after 3 ns;
+	flags.z		<= '1' when op1_in = (data_width-1 downto 0 => '0') else '0' after 2 ns;
+	flags.ltz	<= op1_in(op1_in'left) after 1 ns;
+
+--------------------------------------------------------------------------
+end Behavioral;
diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd
new file mode 100644
index 0000000..b1adabe
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/mips_bui.vhd
@@ -0,0 +1,396 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: JIPS top file 
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+
+entity bui is
+	Port
+	(
+		rst				: in  STD_LOGIC;
+		clk				: in  STD_LOGIC;
+		ce				: in  STD_LOGIC;
+		cpu_wait		: out STD_LOGIC;
+		cpu_imem_rdy	: out STD_LOGIC;
+		cpu_imem_en		: in  STD_LOGIC;
+		cpu_imem_addr	: in  word_t;
+		cpu_imem_din	: out word_t;
+		cpu_dmem_rdy	: out STD_LOGIC;
+		cpu_dmem_en		: in  STD_LOGIC;
+		cpu_dmem_re		: in  STD_LOGIC;
+		cpu_dmem_we		: in  unsigned(3 downto 0);
+		cpu_dmem_dout	: in  word_t;
+		cpu_dmem_din	: out word_t;
+		cpu_dmem_addr	: in  word_t;
+		mem_valid		: in  STD_LOGIC;
+		mem_rdy			: in  STD_LOGIC;
+		mem_addr		: out word_t;
+		mem_din			: in  word_t;
+		mem_dout		: out word_t;
+		mem_re			: out STD_LOGIC;
+		mem_we			: out unsigned(3 downto 0);
+		mem_ce			: out STD_LOGIC
+	);
+	
+end bui;
+
+architecture behavior of bui is
+
+COMPONENT icache
+	GENERIC
+	(
+		cache_size	: natural := 2048;	-- words
+		line_size	: natural := 8		-- words
+	);
+	PORT
+	(
+		clk			: in  STD_LOGIC;
+		rst			: in  STD_LOGIC;
+		en			: in  STD_LOGIC;
+		cpu_en		: in  STD_LOGIC;
+		cpu_addr	: in  word_t;
+		cpu_dout	: out word_t;
+		cpu_busy	: out STD_LOGIC;
+		mem_en		: out STD_LOGIC;
+		mem_req		: out STD_LOGIC;
+		mem_gnt		: in  STD_LOGIC;
+		mem_addr	: out word_t;
+		mem_din		: in  word_t;
+		mem_valid	: in  STD_LOGIC;
+		mem_rdy		: in  STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT dcache
+	GENERIC
+	(
+		cache_size	: natural := 2048;	-- words
+		line_size	: natural := 8		-- words
+	);
+	PORT
+	(
+		clk			: in  STD_LOGIC;
+		rst			: in  STD_LOGIC;
+		en			: in  STD_LOGIC;
+		cpu_en		: in  STD_LOGIC;
+		cpu_r_wn	: in  STD_LOGIC;
+		cpu_we		: in  unsigned(3 downto 0);
+		cpu_addr	: in  word_t;
+		cpu_din		: in  word_t;
+		cpu_dout	: out word_t;
+		cpu_busy	: out STD_LOGIC;
+		mem_req		: out STD_LOGIC;
+		mem_gnt		: in  STD_LOGIC;
+		mem_en		: out STD_LOGIC;
+		mem_addr	: out word_t;
+		mem_din		: in  word_t;
+		mem_valid	: in  STD_LOGIC;
+		mem_rdy		: in  STD_LOGIC
+	);
+END COMPONENT;
+
+	type bus_state_t is (init, ready, i_cache_bus_access, d_cache_bus_access, d_bus_start, d_bus_access, d_bus_finish);
+	
+	signal s, sn : bus_state_t;
+	signal dmem_re			: std_logic;
+	signal dmem_we			: unsigned(3 downto 0);
+	signal dcache_dout		: word_t;
+	signal dmem_dout		: word_t;
+	signal dmem_din			: word_t;
+	signal dmem_addr		: word_t;
+	signal imem_addr		: word_t;
+	signal imem_mem_out_en	: std_logic;
+	signal dmem_mem_out_en 	: std_logic;
+	signal imem_valid 		: std_logic;
+	signal dmem_valid 		: std_logic;
+	signal dmem_ack			: std_logic;
+	signal dcache_req		: std_logic;
+	signal dcache_busy1		: std_logic;
+	signal dcache_busy2		: std_logic;
+	signal icache_busy 		: std_logic;
+	signal bus_req	 		: std_logic;
+	signal bus_bsy	 		: std_logic;
+	signal icache_mem_en	: std_logic;
+	signal icache_mem_req	: std_logic;
+	signal icache_mem_gnt	: std_logic;
+	signal icache_mem_addr	: word_t;
+	signal dcache_mem_en	: std_logic;
+	signal dcache_mem_req	: std_logic;
+	signal dcache_mem_gnt	: std_logic;
+	signal dcache_mem_addr	: word_t;
+	signal contention		: std_logic;
+	signal dcached			: std_logic;
+	signal duncached_access	: std_logic;
+
+begin
+
+	mem_ce 			<= mem_rdy and bus_req;
+	contention		<= 	dcache_req and icache_mem_req;
+
+	cpu_imem_rdy	<= not icache_busy after 4.5 ns;
+--	cpu_imem_din	<= imem_din;
+--	cpu_wait		<= busy after 5.5 ns;
+	cpu_wait		<= '0';
+	cpu_dmem_rdy	<= not (dcache_busy1 or dcache_busy2) after 4.5 ns;
+	
+inst_icache : icache
+	GENERIC MAP
+	(
+		cache_size	=> 2048,	-- words
+		line_size	=> 8
+	)	
+	PORT MAP
+	(
+		clk			=> clk,
+		rst			=> rst,
+		en			=> '1',
+		cpu_en		=> cpu_imem_en,
+		cpu_addr	=> cpu_imem_addr,
+		cpu_dout	=> cpu_imem_din,
+		cpu_busy	=> icache_busy,
+		mem_en		=> icache_mem_en,
+		mem_req		=> icache_mem_req,
+		mem_gnt		=> icache_mem_gnt,
+		mem_addr	=> icache_mem_addr,
+		mem_din		=> mem_din,
+		mem_valid	=> imem_valid,
+		mem_rdy		=> mem_rdy
+	);
+
+inst_dcache : dcache
+	GENERIC MAP
+	(
+		cache_size	=> 2048,	-- words
+		line_size	=> 8
+	)
+	PORT MAP
+	(
+		clk			=> clk,
+		rst			=> rst,
+		en			=> dcached,
+		cpu_en		=> cpu_dmem_en,
+		cpu_r_wn	=> cpu_dmem_re,
+		cpu_we		=> cpu_dmem_we,
+		cpu_addr	=> cpu_dmem_addr,
+		cpu_din		=> cpu_dmem_dout,
+		cpu_dout	=> dcache_dout,
+		cpu_busy	=> dcache_busy2,
+		mem_req		=> dcache_mem_req,
+		mem_gnt		=> dcache_mem_gnt,
+		mem_en		=> dcache_mem_en,
+		mem_addr	=> dcache_mem_addr,
+		mem_din		=> mem_din,
+		mem_valid	=> dmem_valid,
+		mem_rdy		=> mem_rdy
+	);
+
+	dcached			<= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0';
+	cpu_dmem_din	<= dmem_din when duncached_access = '1' else dcache_dout; -- when dmem_valid = '1' else ram_dout after 0.5 ns;
+
+dcache_flags:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				dcache_busy1		<= '0';
+				dcache_req		<= '0';
+			else	
+				duncached_access <= '0';
+				if dmem_ack = '1' then
+					duncached_access <= '1';
+					dcache_req		<= '0';
+					if dmem_re = '1' then
+						if dmem_valid = '1' then
+							dcache_busy1		<= '0';
+						end if;	
+					else
+						dcache_busy1		<= '0';
+					end if;	
+				end if;	
+				if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then
+					dcache_req		<= '1';
+					dcache_busy1		<= '1';
+					if dcached = '1' and cpu_dmem_re = '1' then
+						dcache_req		<= '0';
+						dcache_busy1	<= '0';
+					end if;	
+				end if;
+			end if;
+		end if;
+	end process;	
+	
+dcache_regs:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then
+				dmem_dout		<= cpu_dmem_dout;
+				dmem_addr		<= cpu_dmem_addr;
+				dmem_re			<= cpu_dmem_re;
+				dmem_we			<= cpu_dmem_we;
+			end if;
+		end if;
+	end process;	
+	
+dcache_data:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				dmem_din		<= (others => '0');
+			elsif dmem_valid = '1' then
+				dmem_din		<= mem_din;
+			end if;
+		end if;
+	end process;	
+	
+bus_state_next:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				s	<= init;
+			elsif ce = '1' then
+				s	<= sn;
+			end if;
+		end if;
+	end process;	
+	
+bus_state:
+	process(s, icache_mem_en, icache_mem_req, dcache_mem_req, dcache_mem_en, dcache_req, dmem_re, mem_rdy, mem_valid)
+	begin
+		
+		imem_mem_out_en	<= '0';
+		dmem_mem_out_en	<= '0';
+		icache_mem_gnt	<= '0';
+		dcache_mem_gnt	<= '0';
+		imem_valid		<= '0';
+		dmem_valid		<= '0';
+		dmem_ack		<= '0';
+		bus_bsy			<= '1';
+		
+		sn				<= s;
+		case s is
+		when init =>
+			if mem_rdy = '1' then
+				sn		<= ready;
+			end if;	
+		when ready =>
+			bus_bsy		<= not mem_rdy;
+			if dcache_req = '1' then
+				if dcache_busy1 = '1' then
+					if mem_rdy = '1' then
+						dmem_mem_out_en	<= '1';
+						if dmem_re = '0' then
+							dmem_ack	<= '1';
+						else
+							sn			<= d_bus_access;
+						end if;
+					end if;
+				end if;	
+			elsif icache_mem_req = '1' then
+				sn				<= i_cache_bus_access;
+			elsif dcache_mem_req = '1' then
+				sn				<= d_cache_bus_access;
+			end if;
+		when i_cache_bus_access =>
+			icache_mem_gnt	<= '1';
+			if icache_mem_en = '1' then
+				imem_mem_out_en	<= '1';
+			elsif icache_mem_req = '0' then
+				sn				<= ready;
+			end if;	
+			imem_valid	<= mem_valid;
+		when d_cache_bus_access =>
+			dcache_mem_gnt	<= '1';
+			if dcache_mem_en = '1' then
+				dmem_mem_out_en	<= '1';
+			elsif dcache_mem_req = '0' then
+				sn				<= ready;
+			end if;	
+			dmem_valid	<= mem_valid;
+		when d_bus_access =>
+			if mem_valid = '1' then
+				dmem_ack	<= '1';
+				dmem_valid	<= '1';
+				sn			<= ready;
+			end if;
+		when d_bus_finish =>
+			if mem_rdy = '1' then
+				sn			<= ready;
+			end if;
+		when others =>
+			sn	<= ready;
+		end case;		
+				
+	end process;	
+
+bus_request:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				bus_req 	<= '0';
+			elsif dmem_mem_out_en = '1' or imem_mem_out_en = '1' then
+				bus_req		<= '1';
+			elsif mem_rdy = '1' then
+				bus_req 	<= '0';
+			end if;	
+		end if;
+	end process;	
+
+bus_out:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				mem_dout	<= (others => '0');
+				mem_addr	<= (others => '0');
+				mem_re		<= '0';
+				mem_we		<= (others => '0');
+			elsif dmem_mem_out_en = '1' then
+				if dcache_mem_gnt = '1' then
+					mem_addr	<= dcache_mem_addr;
+					mem_re		<= '1';
+					mem_we		<= (others => '0');
+				else
+					mem_dout	<= dmem_dout;
+					mem_addr	<= dmem_addr;
+					mem_re		<= dmem_re;
+					mem_we		<= dmem_we;
+				end if;
+			elsif imem_mem_out_en = '1' then
+				mem_addr	<= icache_mem_addr;
+				mem_re		<= '1';
+				mem_we		<= (others => '0');
+			end if;	
+		end if;
+	end process;	
+
+-------------------------------------------------------------------
+	
+end behavior;
diff --git a/lib/CPUs/MIPS/src/core/mips_cop.vhd b/lib/CPUs/MIPS/src/core/mips_cop.vhd
new file mode 100644
index 0000000..d37de20
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/mips_cop.vhd
@@ -0,0 +1,415 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The arithmetic logic unit
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.mips_types.all;
+use work.mips_instr.all;
+
+entity cop is
+	Port 
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		sdu			: in  sdu_t;
+		IR_valid	: in  STD_LOGIC;
+		IR			: in  word_t;
+		events		: in  event_t;
+		ctrl_in		: in  cop_ctrl_in_t;
+		ctrl_out	: out cop_ctrl_out_t;
+		din			: in  word_t;
+		dout		: out word_t
+	);
+end cop;
+
+architecture Behavioral of cop is
+
+	signal epc				: word_t;
+	signal cause			: word_t;
+	signal status			: word_t;
+	signal BadVAddr			: word_t;
+	signal exc_code			: unsigned(4 downto 0);
+	signal test_reg			: word_t;
+	signal test_reg_we		: STD_LOGIC;
+	signal stat_reg_we		: STD_LOGIC;
+	signal eflags_reg_we	: STD_LOGIC;
+	signal epc_reg_we		: STD_LOGIC;
+	signal code_reg_we		: STD_LOGIC;
+	signal ip_reg_we		: STD_LOGIC;
+	signal bd				: STD_LOGIC;
+	signal ip				: unsigned(7 downto 0);
+	signal im				: unsigned(7 downto 0);
+	signal status_save		: STD_LOGIC;
+	signal status_rest		: STD_LOGIC;
+	signal exception		: STD_LOGIC;
+	signal exception_end	: STD_LOGIC;
+	signal eflags			: exc_flags_t;
+	signal exc_enable		: STD_LOGIC;
+	signal cop_EX_en		: STD_LOGIC;
+
+	type cop_pipe_t is record
+		din			: word_t;
+		rs			: reg_ptr_t;
+		rd			: reg_ptr_t;
+		func		: func_t;
+		we			: std_logic;
+		re			: std_logic;
+		cs			: std_logic;
+	end record;
+	
+	signal cop_pipe_ID : cop_pipe_t;
+	signal cop_pipe_EX : cop_pipe_t;
+	
+	function eval_int(ip, im : unsigned) return STD_LOGIC is
+	variable result : STD_LOGIC;
+	begin
+			result := '0';
+			for i in ip'range loop
+				result := result or (ip(i) and im(i));
+			end loop;
+
+			return result;
+	end eval_int;
+
+	type exc_state_t is (exc_init, exc_idle, exc_commit_ID, exc_commit_EX, exc_commit_MEM);
+	signal exc_state, exc_staten : exc_state_t;
+	
+--------------------------------------------------------------------------
+begin
+
+	cop_pipe_ID.din					<= din;
+	cop_pipe_ID.cs					<= IR_valid;
+	cop_pipe_ID.rs					<= extract_rs(IR);
+	cop_pipe_ID.rd					<= extract_rd(IR);
+	cop_pipe_ID.func				<= extract_func(IR);
+	cop_pipe_ID.re					<= cop_pipe_ID.cs when cop_pipe_ID.rs = "00000" else '0';
+	cop_pipe_ID.we					<= cop_pipe_ID.cs when cop_pipe_ID.rs = "00100" else '0';
+	cop_EX_en						<= exc_enable and not status_save;
+	
+	ctrl_out.ee						<= exc_enable;
+	ctrl_out.ec						<= status_save;
+	ctrl_out.RE						<= status(25);
+	ctrl_out.user_mode				<= status(1);
+	ctrl_out.int					<= eflags.Int;
+
+	ctrl_out.cop_read				<= cop_pipe_EX.cs and cop_pipe_EX.re after 1 ns;
+	ctrl_out.reg_write				<= cop_pipe_ID.re after 1 ns;
+	
+	im				<= status(15 downto 8);
+	cause			<= bd & (30 downto 16 => '0') & ip & '0' & exc_code & "00";
+
+	eflags.Ov		<= events.alu_ovf or events.alu_uvf;
+	eflags.DAdEL	<= events.data_load_err;
+	eflags.DAdES	<= events.data_store_err;
+	eflags.IAdEL	<= events.inst_load_err;
+	eflags.IAdEK	<= events.inst_priv_addr and status(1);
+	eflags.Sys		<= events.syscall;
+	eflags.Bp		<= events.break;
+	eflags.RI		<= events.illegal;
+	eflags.Int		<= eval_int(ip, im) and status(0);
+
+	exception		<= eflags.Ov or eflags.Sys or eflags.Bp or eflags.RI or eflags.IAdEL or eflags.IAdEK or eflags.DAdEL or eflags.DAdES or eflags.Int after 1 ns;
+	
+exception_state:
+	process(exc_state, ctrl_in, exception, sdu)
+	begin
+	
+		exc_enable				<= '0';
+		ctrl_out.exc_commit		<= '0';
+		ctrl_out.exc_pending	<= '0';
+		epc_reg_we				<= '0';	
+		code_reg_we				<= '0';	
+		status_save				<= '0';
+		eflags_reg_we			<= '0';
+
+		exc_staten	<= exc_state;
+		
+		case exc_state is
+		
+		when exc_init =>
+			exc_staten <= exc_idle;
+		
+		when exc_idle =>
+			exc_enable	<= '1';
+			if exception = '1' then
+				status_save			<= '1';
+				eflags_reg_we		<= '1';
+				code_reg_we			<= '1';
+				exc_staten			<= exc_commit_ID;
+			end if;
+			
+		when exc_commit_ID =>
+			ctrl_out.exc_pending	<= '1';
+			ctrl_out.exc_commit		<= '1';
+			if sdu.ID_stall = '0' then
+				exc_staten				<= exc_commit_EX;
+			end if;
+			
+		when exc_commit_EX =>
+			ctrl_out.exc_pending	<= '1';
+			ctrl_out.exc_commit		<= '1';
+			if sdu.EX_stall = '0' then
+				exc_staten				<= exc_commit_MEM;
+			end if;
+
+		when exc_commit_MEM =>
+			ctrl_out.exc_pending	<= '1';
+			if sdu.MEM_stall = '0' then
+				epc_reg_we				<= '1';
+				exc_staten				<= exc_idle;
+			end if;
+
+		when others =>
+			exc_staten <= exc_idle;
+		
+		end case;
+	end process;	
+
+exception_state_next:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				exc_state <= exc_init;
+			else
+				exc_state <= exc_staten;
+			end if;	
+		end if;
+	end process;
+
+cop_exception_epc_write:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				bd			<= '0';
+				epc	<= (others => '0');
+			elsif epc_reg_we = '1' then
+				bd			<= '0';
+				epc			<= ctrl_in.epc_mem;
+				if ctrl_in.bd_wb = '1' then
+					bd			<= '1';
+					epc			<= ctrl_in.epc_wb;
+				end if;
+			end if;
+		end if;
+	end process;
+
+cop_exception_map:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				exc_code	<= (others => '0');
+				BadVAddr	<= (others => '0');
+			elsif code_reg_we = '1' then
+				if eflags.Ov = '1'	then
+					exc_code	<= "01100";
+				elsif eflags.Sys = '1'	then
+					exc_code	<= "01000";
+				elsif eflags.Bp = '1'	then
+					exc_code	<= "01001";
+				elsif eflags.RI = '1'	then
+					exc_code	<= "01010";
+				elsif eflags.IAdEL = '1'	then
+					exc_code	<= "00100";
+					BadVAddr	<= ctrl_in.imem_addr;
+				elsif eflags.IAdEK = '1'	then
+					exc_code	<= "00100";
+					BadVAddr	<= ctrl_in.imem_addr;
+				elsif eflags.DAdEL = '1'	then
+					exc_code	<= "00100";
+					BadVAddr	<= ctrl_in.dmem_addr;
+				elsif eflags.DAdES = '1'	then
+					exc_code	<= "00101";
+					BadVAddr	<= ctrl_in.dmem_addr;
+				elsif eflags.Int = '1' then
+					exc_code	<= "00000";
+				end if;
+			end if;
+		end if;
+	end process;
+
+	status_rest	<= exception_end and ctrl_in.exc_left;
+
+cop_status_restore:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				exception_end		<= '0';
+				ctrl_out.exc_exit	<= '0';
+			else
+				if cop_pipe_ID.func = "10000" and exception_end = '0' then		-- RFE
+					exception_end	<= cop_pipe_ID.cs;
+					ctrl_out.exc_exit <= cop_pipe_ID.cs;
+				elsif exception_end = '1' and ctrl_in.exc_left = '1' then
+					exception_end		<= '0';
+					ctrl_out.exc_exit	<= '0';
+				end if;	
+			end if;	
+		end if;
+	end process;
+
+cop_ip_reg_write:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				ip(1 downto 0) <= (others => '0');
+			elsif ip_reg_we = '1' then
+				ip(1 downto 0) <= cop_pipe_EX.din(9 downto 8);
+			end if;	
+			ip(7 downto 2)	<= events.Int;
+		end if;
+	end process;
+
+cop_exc_vector:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			ctrl_out.exc_vec		<= X"80000180";
+			if status(22) = '1' then
+				ctrl_out.exc_vec	<= X"BFC00180";
+			end if;
+		end if;
+	end process;
+
+cop_pipe:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				cop_pipe_EX.cs	<= '0';
+				cop_pipe_EX.we	<= '0';
+				cop_pipe_EX.re	<= '0';
+			else
+				if sdu.EX_stall = '0' then
+					cop_pipe_EX		<= cop_pipe_ID;
+				end if;
+			end if;
+		end if;
+	end process;
+
+cop_register_read:
+	process(clk)
+	variable reg : word_t;
+	begin
+		if rising_edge(clk) and cop_pipe_ID.re = '1' and sdu.ID_stall = '0' then
+			case cop_pipe_ID.rd is
+			when "01000" =>			-- BadVAddr
+				reg	:= BadVAddr;
+
+			when "01100" =>			-- Status
+				reg	:= status;
+
+			when "01101" =>			-- Cause
+				reg	:= cause;
+
+			when "01110" =>			-- EPC (Exception Program Counter)
+				reg	:= epc;
+
+			when "01111" =>			-- PRId (Processor Revision Register)
+				reg	:= X"000002" & to_unsigned(REVISION ,8);
+
+			when "11111" =>			-- test_reg
+				reg	:= test_reg;
+
+			when others =>
+				reg	:= X"DEADBEEF";
+
+			end case;	
+			dout	<= reg;
+		end if;
+	end process;
+
+cop_we_gen:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				test_reg_we	<= '0';
+				stat_reg_we	<= '0';
+				ip_reg_we	<= '0';
+			else
+				test_reg_we	<= '0';
+				stat_reg_we	<= '0';
+				ip_reg_we	<= '0';
+				if (cop_EX_en and cop_pipe_EX.we) = '1' then
+
+					case cop_pipe_EX.rd is
+
+					when "01100" =>
+						stat_reg_we	<= not status(1) or status(28);
+					when "01101" =>			
+						ip_reg_we	<= not status(1) or status(28);
+					when "11111" =>
+						test_reg_we	<= not status(1) or status(28);
+					when others => null;
+
+					end case;
+
+				end if;	
+			end if;	
+		end if;	
+	end process;
+
+cop_test_reg_write:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				test_reg	<= (others => '0');
+			else --if ce = '1' then
+				if test_reg_we = '1' then
+					test_reg	<= cop_pipe_EX.din;
+				end if;
+			end if;
+		end if;
+	end process;
+
+cop_status_reg_write:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				status	<= X"00400000";
+			else
+				if status_save = '1' then
+					status(5 downto 4)	<= status(3 downto 2);
+					status(3 downto 2)	<= status(1 downto 0);
+					status(1 downto 0)	<= "00";
+				elsif status_rest = '1' then
+					status(1 downto 0)	<= status(3 downto 2);
+					status(3 downto 2)	<= status(5 downto 4);
+				elsif stat_reg_we = '1' then
+					status				<= cop_pipe_EX.din;
+				end if;
+			end if;
+		end if;
+	end process;
+	
+--------------------------------------------------------------------------
+end Behavioral;
diff --git a/lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd b/lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd
new file mode 100644
index 0000000..720e65c
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd
@@ -0,0 +1,101 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The datapath controller
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+use work.mips_instr.all;
+
+entity idecode_rom is
+	Port
+	(
+		nop			: in  std_logic;
+		inst_in		: in  word_t;
+		ctrl_out	: out ctrl_lines_t
+	);
+end idecode_rom;
+
+architecture Behavioral of idecode_rom is
+
+	signal ctrl_special		: ctrl_lines_t;
+	signal ctrl_regimm		: ctrl_lines_t;
+	signal ctrl_opcode		: ctrl_lines_t;
+
+	signal rom_special : rom_special_t := gen_rom_special;
+	signal rom_regimm : rom_regimm_t := gen_rom_regimm;
+	signal rom_opcode : rom_opcode_t := gen_rom_opcode;
+
+	attribute rom_style : string;
+	
+	attribute rom_style of rom_special: signal is "distributed";
+	attribute rom_style of rom_regimm: signal is "distributed";
+	attribute rom_style of rom_opcode: signal is "distributed";
+
+begin
+
+i_dec_special:
+	process(inst_in, rom_special)
+	variable func : func_t;
+	begin
+		func := extract_func(inst_in);
+		ctrl_special <= rom_special(to_integer(func));
+	end process;
+
+i_dec_regimm:
+	process(inst_in, rom_regimm)
+	variable rt : reg_ptr_t;
+	begin
+		rt := extract_rt(inst_in);
+		ctrl_regimm <= rom_regimm(to_integer(rt));
+	end process;
+
+i_dec_opcode:
+	process(inst_in, rom_opcode)
+	variable opc : opcode_t;
+	begin
+		opc := extract_opc(inst_in);
+		ctrl_opcode <= rom_opcode(to_integer(opc));
+	end process;
+
+proc_decode:
+	process(inst_in, ctrl_special, ctrl_regimm, ctrl_opcode, nop)
+	variable opclass : opcode_t;
+	begin
+		opclass := extract_opc(inst_in);
+		ctrl_out <= ctrl_lines_default after 2 ns;
+		if nop = '0' then
+			case opclass is
+			when "000000" =>
+				ctrl_out	<= ctrl_special after 2 ns;
+			when "000001" =>
+				ctrl_out	<= ctrl_regimm after 2 ns;
+			when others =>
+				ctrl_out	<= ctrl_opcode after 2 ns;
+			end case;
+		end if;	
+	end process;
+
+end Behavioral;
diff --git a/lib/CPUs/MIPS/src/core/mips_instr.vhd b/lib/CPUs/MIPS/src/core/mips_instr.vhd
new file mode 100644
index 0000000..97a0c0b
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/mips_instr.vhd
@@ -0,0 +1,997 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: Types, constants and functions for JCPU
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+
+--------------------------------------------------------------------------
+package mips_instr is
+
+	function extract_opc(instr : word_t) return opcode_t;
+	function extract_rs(instr : word_t) return reg_ptr_t;
+	function extract_rt(instr : word_t) return reg_ptr_t;
+	function extract_rd(instr : word_t) return reg_ptr_t;
+	function extract_shamt(instr : word_t) return shamt_t;
+	function extract_func(instr : word_t) return func_t;
+	function extract_simm32(instr : word_t) return word_t;
+	function extract_uimm16(instr : word_t) return word_t;
+	function extract_jimm32(instr, pc : word_t) return word_t;
+	function extract_bimm18(instr, pc : word_t) return word_t;
+	function decode_op(instr : word_t) return op_t;
+	function ctrl_lines_default return ctrl_lines_t;
+	function special_ctrl_lines(func : func_t) return ctrl_lines_t;
+	function regimm_ctrl_lines(rt : reg_ptr_t) return ctrl_lines_t;
+	function opcode_ctrl_lines(opc : opcode_t) return ctrl_lines_t;
+	function gen_rom_opcode return rom_opcode_t;
+	function gen_rom_regimm return rom_regimm_t;
+	function gen_rom_special return rom_special_t;
+
+end mips_instr;
+
+--------------------------------------------------------------------------
+library work;
+use work.mips_types.all;
+
+package body mips_instr is
+
+	function extract_opc(instr : word_t) return opcode_t is
+	variable result : opcode_t;
+	begin
+		result := instr(31 downto 26);
+		
+		return result;
+
+	end extract_opc;
+	
+	function extract_rs(instr : word_t) return reg_ptr_t is
+	variable result : reg_ptr_t;
+	begin
+		result := instr(25 downto 21);
+		
+		return result;
+
+	end extract_rs;
+	
+	function extract_rt(instr : word_t) return reg_ptr_t is
+	variable result : reg_ptr_t;
+	begin
+		result := instr(20 downto 16);
+		
+		return result;
+
+	end extract_rt;
+
+	function extract_rd(instr : word_t) return reg_ptr_t is
+	variable result : reg_ptr_t;
+	begin
+		result := instr(15 downto 11);
+		
+		return result;
+
+	end extract_rd;
+
+	function extract_shamt(instr : word_t) return shamt_t is
+	variable result : shamt_t;
+	begin
+		result := instr(10 downto 6);
+		
+		return result;
+
+	end extract_shamt;
+
+	function extract_func(instr : word_t) return func_t is
+	variable result : func_t;
+	begin
+		result := instr(5 downto 0);
+		
+		return result;
+
+	end extract_func;
+
+	function extract_simm32(instr : word_t) return word_t is
+	variable result : word_t;
+	begin
+		result := (31 downto 16 => instr(15)) & instr(15 downto 0);
+		
+		return result;
+
+	end extract_simm32;
+
+	function extract_uimm16(instr : word_t) return word_t is
+	variable result : word_t;
+	begin
+		result := (31 downto 16 => '0') & instr(15 downto 0);
+		
+		return result;
+
+	end extract_uimm16;
+
+	function extract_jimm32(instr, pc : word_t) return word_t is
+	variable result : word_t;
+	begin
+		result := pc(31 downto 28) & instr(25 downto 0) & "00";
+		
+		return result;
+
+	end extract_jimm32;
+
+	function extract_bimm18(instr, pc : word_t) return word_t is
+	variable result : word_t;
+	begin
+		result := (31 downto 18 => instr(15)) & instr(15 downto 0) & "00";
+		
+		return result;
+
+	end extract_bimm18;
+
+	function decode_op(instr : word_t) return op_t is
+	variable result : op_t;
+	variable opc : natural range 0 to 63;
+	variable func : natural range 0 to 63;
+	variable rt : natural range 0 to 31;
+	
+	begin
+		
+		opc		:= to_integer(extract_opc(instr));
+		func	:= to_integer(extract_func(instr));
+		rt		:= to_integer(extract_rt(instr));
+		
+		result := op_sll;
+		
+		case opc is
+
+		when 0 =>
+			case func is
+
+			when 0 =>
+				result := op_sll;
+			
+			when 2 =>
+				result := op_srl;
+
+			when 3 =>
+				result := op_sra;
+
+			when 4 =>
+				result := op_sllv;
+
+			when 6 =>
+				result := op_srlv;
+
+			when 7 =>
+				result := op_srav;
+
+			when 8 =>
+				result := op_jr;
+
+			when 9 =>
+				result := op_jalr;
+
+			when 12 =>
+				result := op_syscall;
+
+			when 13 =>
+				result := op_break;
+
+			when 16 =>
+				result := op_mfhi;
+
+			when 17 =>
+				result := op_mthi;
+
+			when 18 =>
+				result := op_mflo;
+
+			when 19 =>
+				result := op_mtlo;
+
+			when 24 =>
+				result := op_mult;
+
+			when 25 =>
+				result := op_multu;
+
+			when 26 =>
+				result := op_div;
+
+			when 27 =>
+				result := op_divu;
+
+			when 32 =>
+				result := op_add;
+			
+			when 33 =>
+				result := op_addu;
+			
+			when 34 =>
+				result := op_sub;
+			
+			when 35 =>
+				result := op_subu;
+			
+			when 36 =>
+				result := op_and;
+			
+			when 37 =>
+				result := op_or;
+			
+			when 38 =>
+				result := op_xor;
+			
+			when 39 =>
+				result := op_nor;
+			
+			when 42 =>
+				result := op_slt;
+			
+			when 43 =>
+				result := op_sltu;
+				
+			when others => null; -- undef
+			
+			end case;
+			
+		when 1 =>
+			case rt is
+
+			when 0 =>
+				result := op_bltz;
+				
+			when 1 =>
+				result := op_bgez;
+			
+			when 16 =>
+				result := op_bltzal;
+
+			when 17 =>
+				result := op_bgezal;
+				
+			when others => null; -- undef
+			
+			end case;
+
+		when 2 =>
+			result	:= op_j;
+			
+		when 3 =>
+			result	:= op_jal;
+			
+		when 4 =>
+			result	:= op_beq;
+			
+		when 5 =>
+			result	:= op_bne;
+
+		when 6 =>
+			result	:= op_blez;
+
+		when 7 =>
+			result	:= op_bgtz;
+
+		when 8 =>
+			result	:= op_addi;
+
+		when 9 =>
+			result	:= op_addiu;
+
+		when 10 =>
+			result	:= op_slti;
+
+		when 11 =>
+			result	:= op_sltiu;
+
+		when 12 =>
+			result	:= op_andi;
+
+		when 13 =>
+			result	:= op_ori;
+
+		when 14 =>
+			result	:= op_xori;
+
+		when 15 =>
+			result	:= op_lui;
+
+		when 16 =>
+			result	:= op_cop0;
+
+		when 17 =>
+			result	:= op_cop1;
+
+		when 18 =>
+			result	:= op_cop2;
+
+		when 19 =>
+			result	:= op_cop3;
+
+		when 32 =>
+			result	:= op_lb;
+
+		when 33 =>
+			result	:= op_lh;
+
+		when 34 =>
+			result	:= op_lwl;
+
+		when 35 =>
+			result	:= op_lw;
+
+		when 36 =>
+			result	:= op_lbu;
+
+		when 37 =>
+			result	:= op_lhu;
+
+		when 38 =>
+			result	:= op_lwr;
+
+		when 40 =>
+			result	:= op_sb;
+
+		when 41 =>
+			result	:= op_sh;
+
+		when 42 =>
+			result	:= op_swl;
+
+		when 43 =>
+			result	:= op_sw;
+
+		when 46 =>
+			result	:= op_swr;
+
+		when 49 =>
+			result	:= op_lwc1;
+			
+		when 50 =>
+			result	:= op_lwc2;
+
+		when 51 =>
+			result	:= op_lwc3;
+
+		when 57 =>
+			result	:= op_swc1;
+			
+		when 58 =>
+			result	:= op_swc2;
+
+		when 59 =>
+			result	:= op_swc3;
+
+		when others => null; -- undef
+
+		end case;
+
+		return result;
+
+	end decode_op;
+
+	function ctrl_lines_default return ctrl_lines_t is
+	variable result : ctrl_lines_t;
+	begin
+		result.cop_instr_en				:= '0';
+		result.jump						:= '0';
+		result.jump_long				:= '0';
+		result.branch					:= '0';
+		result.bc_src					:= bc_eq_ne;
+		result.bc_not					:= '0';
+		result.alu.outsel				:= alu_adder;
+		result.alu.add					:= '1';
+		result.alu.shift_right			:= '0';
+		result.alu.shift_arith			:= '0';
+		result.shamt2_srcsel			:= sa_src_imm;
+		result.alu.op1_src				:= alu_src_reg;
+		result.alu.op2_src				:= alu_src_reg;
+		result.imm_src					:= src_imm16;
+		result.reg_write				:= '0';
+		result.dmem_we					:= '0';
+		result.dmem_en					:= '0';
+		result.wptr_srcsel				:= wptr_src_imm;
+		result.reg_link					:= '0';
+		result.shift_offset				:= "00";
+		result.shift_byp				:= '1';
+		result.byte_en_byp				:= '1';
+		result.sign_ext_byp				:= '1';
+		result.word4_en					:= '0';
+		result.word2_en					:= '0';
+		result.align_left				:= '0';
+		result.load_signed				:= '0';
+		result.mul_access				:= '0';
+		result.mul_hilo_we				:= '0';
+		result.mul_start				:= '0';
+		result.mul_s_un					:= '0';
+		result.mul_mul_divn				:= '0';
+		result.mul_hilo_sel				:= '1';
+		result.exc_break				:= '0';
+		result.exc_syscall				:= '0';
+		result.exc_illegal				:= '0';
+		result.except_en				:= '0';
+		result.alu_exc_en				:= '0';
+
+		return result;
+	
+	end ctrl_lines_default;
+
+
+	function special_ctrl_lines(func : func_t) return ctrl_lines_t is
+	variable result : ctrl_lines_t;
+	variable op : integer range 0 to 2**func_t'length-1;
+	begin
+	
+		result := ctrl_lines_default;
+		
+		op	:= to_integer(func);
+		case op is
+
+--		when op_add  =>
+		when 32 =>
+			result.alu.outsel		:= alu_adder;
+			result.alu.add			:= '1';
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_reg;
+			result.reg_write		:= '1';
+			result.alu_exc_en		:= '1';
+
+--		when op_addu =>
+		when 33 =>
+			result.alu.outsel		:= alu_adder;
+			result.alu.add			:= '1';
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_reg;
+			result.reg_write		:= '1';
+
+--		when op_and =>
+		when 36 =>
+			result.alu.outsel		:= alu_and;
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_reg;
+			result.reg_write		:= '1';
+
+--		when op_break =>
+		when 13 =>
+			result.exc_break		:= '1';
+			result.except_en		:= '1';
+
+--		when op_div =>
+		when 26 =>
+			result.mul_access		:= '1';
+			result.mul_start		:= '1';
+			result.mul_s_un			:= '1';
+			result.mul_mul_divn		:= '0';
+			
+--		when op_divu =>
+		when 27 =>
+			result.mul_access		:= '1';
+			result.mul_start		:= '1';
+			result.mul_s_un			:= '0';
+			result.mul_mul_divn		:= '0';
+
+--		when op_jalr =>
+		when 9 =>
+			result.jump_long		:= '1';
+			result.wptr_srcsel		:= wptr_src_imm;
+			result.reg_write		:= '1';
+			result.reg_link			:= '1';
+
+--		when op_jr =>
+		when 8 =>
+			result.jump_long		:= '1';
+
+--		when op_mfhi =>
+		when 16 =>
+			result.reg_write		:= '1';
+			result.mul_access		:= '1';
+			result.mul_hilo_sel		:= '1';
+
+--		when op_mflo =>
+		when 18 =>
+			result.reg_write		:= '1';
+			result.mul_access		:= '1';
+			result.mul_hilo_sel		:= '0';
+
+--		when op_mthi =>
+		when 17 =>
+			result.mul_hilo_we		:= '1';
+			result.mul_hilo_sel		:= '1';
+
+--		when op_mtlo =>
+		when 19 =>
+			result.mul_hilo_we		:= '1';
+			result.mul_hilo_sel		:= '0';
+
+--		when op_mult =>
+		when 24 =>
+			result.mul_access		:= '1';
+			result.mul_start		:= '1';
+			result.mul_s_un			:= '1';
+			result.mul_mul_divn		:= '1';
+			
+--		when op_multu =>
+		when 25 =>
+			result.mul_access		:= '1';
+			result.mul_start		:= '1';
+			result.mul_s_un			:= '0';
+			result.mul_mul_divn		:= '1';
+
+--		when op_or =>
+		when 37 =>
+			result.alu.outsel		:= alu_or;
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_reg;
+			result.reg_write		:= '1';
+
+--		when op_nor =>
+		when 39 =>
+			result.alu.outsel		:= alu_nor;
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_reg;
+			result.reg_write		:= '1';
+
+--		when op_sll =>
+		when 0 =>
+			result.alu.op2_src		:= alu_src_reg;
+			result.alu.outsel		:= alu_shift2;
+			result.alu.shift_right	:= '0';
+			result.shamt2_srcsel	:= sa_src_imm;
+			result.reg_write		:= '1';
+
+--		when op_sllv =>
+		when 4 =>
+			result.alu.op2_src		:= alu_src_reg;
+			result.alu.outsel		:= alu_shift2;
+			result.alu.shift_right	:= '0';
+			result.shamt2_srcsel	:= sa_src_reg;
+			result.reg_write		:= '1';
+
+--		when op_slt =>
+		when 42 =>
+			result.alu.outsel		:= alu_lts;
+			result.alu.add			:= '0';
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_reg;
+			result.reg_write		:= '1';
+
+--		when op_sltu =>
+		when 43 =>
+			result.alu.outsel		:= alu_ltu;
+			result.alu.add			:= '0';
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_reg;
+			result.reg_write		:= '1';
+
+--		when op_sra =>
+		when 3 =>
+			result.alu.op2_src		:= alu_src_reg;
+			result.alu.outsel		:= alu_shift2;
+			result.alu.shift_right	:= '1';
+			result.alu.shift_arith	:= '1';
+			result.shamt2_srcsel	:= sa_src_imm;
+			result.reg_write		:= '1';
+			
+--		when op_srav =>
+		when 7 =>
+			result.alu.op2_src		:= alu_src_reg;
+			result.alu.outsel		:= alu_shift2;
+			result.alu.shift_right	:= '1';
+			result.alu.shift_arith	:= '1';
+			result.shamt2_srcsel	:= sa_src_reg;
+			result.reg_write		:= '1';
+			
+--		when op_srl =>
+		when 2 =>
+			result.alu.op2_src		:= alu_src_reg;
+			result.alu.outsel		:= alu_shift2;
+			result.alu.shift_right	:= '1';
+			result.alu.shift_arith	:= '0';
+			result.shamt2_srcsel	:= sa_src_imm;
+			result.reg_write		:= '1';
+			
+--		when op_srlv =>
+		when 6 =>
+			result.alu.op2_src		:= alu_src_reg;
+			result.alu.outsel		:= alu_shift2;
+			result.alu.shift_right	:= '1';
+			result.alu.shift_arith	:= '0';
+			result.shamt2_srcsel	:= sa_src_reg;
+			result.reg_write		:= '1';
+			
+--		when op_sub =>
+		when 34 =>
+			result.alu.outsel		:= alu_adder;
+			result.alu.add			:= '0';
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_reg;
+			result.reg_write		:= '1';
+			result.alu_exc_en		:= '1';
+
+--		when op_subu =>
+		when 35 =>
+			result.alu.outsel		:= alu_adder;
+			result.alu.add			:= '0';
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_reg;
+			result.reg_write		:= '1';
+
+--		when op_syscall =>
+		when 12 =>
+			result.exc_syscall		:= '1';
+			result.except_en		:= '1';
+
+--		when op_xor =>
+		when 38 =>
+			result.alu.outsel		:= alu_xor;
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_reg;
+			result.reg_write		:= '1';
+
+		when others => 
+			result.exc_illegal		:= '1';
+
+		end case;
+		
+		return result;
+	
+	end special_ctrl_lines;
+	
+	function gen_rom_special return rom_special_t is
+	variable result : rom_special_t; 
+	variable func : func_t;
+	begin
+		
+		for i in 0 to 2**func_t'length-1 loop
+			func := to_unsigned(i, func_t'length);
+			result(i) := special_ctrl_lines(func);
+		end loop;
+
+		return result;
+	end gen_rom_special;
+
+	function regimm_ctrl_lines(rt : reg_ptr_t) return ctrl_lines_t is
+	variable result : ctrl_lines_t;
+	variable op : integer range 0 to 2**reg_ptr_t'length-1;
+	begin
+	
+		result := ctrl_lines_default;
+		
+		op	:= to_integer(rt);
+		case op is
+
+--		when op_bgez =>
+		when 1 =>
+			result.branch			:= '1';
+			result.bc_src			:= bc_ltz_gez;
+			result.bc_not			:= '1';
+
+--		when op_bgezal =>
+		when 17 =>
+			result.branch			:= '1';
+			result.bc_src			:= bc_ltz_gez;
+			result.bc_not			:= '1';
+			result.wptr_srcsel		:= wptr_src_const;
+			result.reg_write		:= '1';
+			result.reg_link			:= '1';
+
+--		when op_bltz =>
+		when 0 =>
+			result.branch			:= '1';
+			result.bc_src			:= bc_ltz_gez;
+			result.bc_not			:= '0';
+			
+--		when op_bltzal =>
+		when 16 =>
+			result.branch			:= '1';
+			result.bc_src			:= bc_ltz_gez;
+			result.bc_not			:= '0';
+			result.wptr_srcsel		:= wptr_src_const;
+			result.reg_write		:= '1';
+			result.reg_link			:= '1';
+
+		when others => 
+			result.exc_illegal		:= '1';
+
+		end case;
+		
+		return result;
+	
+	end regimm_ctrl_lines;
+
+	function gen_rom_regimm return rom_regimm_t is
+	variable result : rom_regimm_t; 
+	variable rt : reg_ptr_t;
+	begin
+		
+		for i in 0 to 2**reg_ptr_t'length-1 loop
+			rt := to_unsigned(i, reg_ptr_t'length);
+			result(i) := regimm_ctrl_lines(rt);
+		end loop;
+
+		return result;
+	end gen_rom_regimm;
+
+	function opcode_ctrl_lines(opc : opcode_t) return ctrl_lines_t is
+	variable result : ctrl_lines_t;
+	variable op : integer range 0 to 2**opcode_t'length-1;
+	begin
+	
+		result := ctrl_lines_default;
+
+		op	:= to_integer(opc);
+		case op is
+
+--		when op_addi =>
+		when 8 =>
+			result.imm_src			:= src_imm32;
+			result.alu.outsel		:= alu_adder;
+			result.alu.add			:= '1';
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_imm;
+			result.reg_write		:= '1';
+			result.alu_exc_en		:= '1';
+
+--		when op_addiu =>
+		when 9 =>
+			result.imm_src			:= src_imm32;
+			result.alu.outsel		:= alu_adder;
+			result.alu.add			:= '1';
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_imm;
+			result.reg_write		:= '1';
+
+--		when op_andi =>
+		when 12 =>
+			result.imm_src			:= src_imm16;
+			result.alu.outsel		:= alu_and;
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_imm;
+			result.reg_write		:= '1';
+
+--		when op_beq =>
+		when 4 =>
+			result.branch			:= '1';
+			result.bc_src			:= bc_eq_ne;
+			result.bc_not			:= '0';
+			
+--		when op_bgtz =>
+		when 7 =>
+			result.branch			:= '1';
+			result.bc_src			:= bc_lez_gtz;
+			result.bc_not			:= '1';
+			
+--		when op_blez =>
+		when 6 =>
+			result.branch			:= '1';
+			result.bc_src			:= bc_lez_gtz;
+			result.bc_not			:= '0';
+			
+--		when op_bne =>
+		when 5 =>
+			result.branch			:= '1';
+			result.bc_src			:= bc_eq_ne;
+			result.bc_not			:= '1';
+
+--		when op_cop =>			
+		when 16 | 17 | 18 | 19 =>			
+			result.cop_instr_en		:= '1';
+			
+--		when op_j =>
+		when 2 =>
+			result.jump				:= '1';
+
+--		when op_jal =>
+		when 3 =>
+			result.jump				:= '1';
+			result.wptr_srcsel		:= wptr_src_const;
+			result.reg_write		:= '1';
+			result.reg_link			:= '1';
+
+--		when op_lb =>
+		when 32 =>
+			result.imm_src			:= src_imm32;
+			result.dmem_en			:= '1';
+			result.reg_write		:= '1';
+			result.shift_byp		:= '0';
+			result.byte_en_byp		:= '1';
+			result.sign_ext_byp		:= '0';
+			result.load_signed		:= '1';
+			result.word4_en			:= '1';
+			
+--		when op_lbu =>
+		when 36 =>
+			result.imm_src			:= src_imm32;
+			result.dmem_en			:= '1';
+			result.reg_write		:= '1';
+			result.shift_byp		:= '0';
+			result.byte_en_byp		:= '1';
+			result.sign_ext_byp		:= '0';
+			result.load_signed		:= '0';
+			result.word4_en			:= '1';
+			
+--		when op_lh =>
+		when 33 =>
+			result.imm_src			:= src_imm32;
+			result.dmem_en			:= '1';
+			result.reg_write		:= '1';
+			result.shift_byp		:= '0';
+			result.sign_ext_byp		:= '0';
+			result.byte_en_byp		:= '1';
+			result.load_signed		:= '1';
+			result.word2_en			:= '1';
+			result.except_en		:= '1';
+			
+--		when op_lhu =>
+		when 37 =>
+			result.imm_src			:= src_imm32;
+			result.dmem_en			:= '1';
+			result.reg_write		:= '1';
+			result.shift_byp		:= '0';
+			result.sign_ext_byp		:= '0';
+			result.byte_en_byp		:= '1';
+			result.load_signed		:= '0';
+			result.word2_en			:= '1';
+			result.except_en		:= '1';
+			
+--		when op_lui =>
+		when 15 =>
+			result.imm_src			:= src_imm16_high;
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_imm;
+			result.alu.outsel		:= alu_adder;
+			result.reg_write		:= '1';
+			result.alu.add			:= '1';
+
+--		when op_lw =>
+		when 35 =>
+--			result.imm_src			:= src_imm32;
+			result.dmem_en			:= '1';
+			result.reg_write		:= '1';
+			result.except_en		:= '1';
+			
+--		when op_lwl =>
+		when 34 =>
+--			result.imm_src			:= src_imm32;
+			result.dmem_en			:= '1';
+			result.reg_write		:= '1';
+			result.shift_byp		:= '0';
+			result.byte_en_byp		:= '0';
+			result.shift_offset		:= "01";
+			result.align_left		:= '1';
+			
+--		when op_lwr =>
+		when 38 =>
+--			result.imm_src			:= src_imm32;
+			result.dmem_en			:= '1';
+			result.reg_write		:= '1';
+			result.shift_byp		:= '0';
+			result.byte_en_byp		:= '0';
+			result.shift_offset		:= "00";
+			result.align_left		:= '0';
+			
+--		when op_ori =>
+		when 13 =>
+			result.imm_src			:= src_imm16;
+			result.alu.outsel		:= alu_or;
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_imm;
+			result.reg_write		:= '1';
+
+--		when op_sb =>
+		when 40 =>
+			result.dmem_en			:= '1';
+			result.dmem_we			:= '1';
+--			result.imm_src			:= src_imm32;
+			result.shift_byp		:= '0';
+			result.byte_en_byp		:= '0';
+			result.word4_en			:= '1';
+			
+--		when op_sh =>
+		when 41 =>
+			result.dmem_en			:= '1';
+			result.dmem_we			:= '1';
+--			result.imm_src			:= src_imm32;
+			result.shift_byp		:= '0';
+			result.byte_en_byp		:= '0';
+			result.word2_en			:= '1';
+			result.except_en		:= '1';
+			
+--		when op_slti =>
+		when 10 =>
+			result.alu.outsel		:= alu_lts;
+			result.alu.add			:= '0';
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_imm;
+			result.imm_src			:= src_imm32;
+			result.reg_write		:= '1';
+
+--		when op_sltiu =>
+		when 11 =>
+			result.alu.outsel		:= alu_ltu;
+			result.alu.add			:= '0';
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_imm;
+			result.imm_src			:= src_imm32;
+			result.reg_write		:= '1';
+
+--		when op_sw =>
+		when 43 =>
+			result.dmem_en			:= '1';
+			result.dmem_we			:= '1';
+--			result.imm_src			:= src_imm32;
+			result.except_en		:= '1';
+			
+--		when op_swl =>
+		when 42 =>
+			result.dmem_en			:= '1';
+			result.dmem_we			:= '1';
+--			result.imm_src			:= src_imm32;
+			result.shift_byp		:= '0';
+			result.byte_en_byp		:= '0';
+			result.shift_offset		:= "01";
+			
+--		when op_swr =>
+		when 46 =>
+			result.dmem_en			:= '1';
+			result.dmem_we			:= '1';
+--			result.imm_src			:= src_imm32;
+			result.shift_byp		:= '0';
+			result.byte_en_byp		:= '0';
+			result.align_left		:= '1';
+			
+--		when op_xori =>
+		when 14 =>
+			result.imm_src			:= src_imm16;
+			result.alu.outsel		:= alu_xor;
+			result.alu.op1_src		:= alu_src_reg;
+			result.alu.op2_src		:= alu_src_imm;
+			result.reg_write		:= '1';
+
+		when others => 
+			result.exc_illegal		:= '1';
+
+		end case;
+		
+		return result;
+	
+	end opcode_ctrl_lines;
+
+	function gen_rom_opcode return rom_opcode_t is
+	variable result : rom_opcode_t; 
+	variable opc : opcode_t;
+	begin
+		
+		for i in 0 to 2**opcode_t'length-1 loop
+			opc := to_unsigned(i, opcode_t'length);
+			result(i) := opcode_ctrl_lines(opc);
+		end loop;
+
+		return result;
+	end gen_rom_opcode;
+
+end mips_instr;
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
diff --git a/lib/CPUs/MIPS/src/core/mips_muldiv.vhd b/lib/CPUs/MIPS/src/core/mips_muldiv.vhd
new file mode 100644
index 0000000..efce36b
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/mips_muldiv.vhd
@@ -0,0 +1,454 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The arithmetic logic unit
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.mips_types.all;
+
+entity muldiv is
+	Port 
+	(
+		rst			: in  std_logic;
+		clk			: in  std_logic;
+		hilo_we		: in  std_logic;
+		din_hi		: in  word_t;
+		din_lo		: in  word_t;
+		mul_divn	: in  std_logic;
+		start		: in  std_logic;
+		s_un		: in  std_logic;
+		hilo_sel	: in  std_logic;
+		busy		: out std_logic;
+		dout		: out word_t
+	);
+end muldiv;
+
+architecture Behavioral of muldiv is
+
+	subtype pprod_t is unsigned (39 downto 0);
+	subtype prod_t is unsigned (63 downto 0);
+	subtype byte_t is unsigned (7 downto 0);
+	
+	type pprod_array_t is array (natural range <>) of pprod_t;
+	type word_array_t is array (natural range <>) of word_t;
+	type byte_array_t is array (natural range <>) of byte_t;
+
+	signal pprod : pprod_array_t(0 to 3);
+	signal sign1 : std_logic;
+	signal sign2 : std_logic;
+	signal s1_r : std_logic;
+	signal s2_r : std_logic;
+	signal sr_r : std_logic;
+	signal cy : unsigned (3 downto 0);
+	signal mul_start : std_logic;
+	signal mul_en : std_logic;
+	signal sum_en : std_logic;
+	signal pre_sum_vld : std_logic;
+	signal pp_reg  : unsigned (63 downto 8);
+	signal pre_const : word_array_t(0 to 1);
+	signal result : prod_t;
+	signal add_op1 : unsigned (39 downto 0);
+	signal add_op2 : unsigned (39 downto 0);
+	signal add_res : unsigned (39 downto 0);
+	signal ppadd_op1 : word_array_t(0 to 3);
+	signal ppadd_op2 : word_array_t(0 to 3);
+	signal ppadd_res : word_array_t(0 to 3);
+	signal ppadd_cyi : unsigned (3 downto 0);
+	signal ppadd_cyo : unsigned (3 downto 0);
+
+	signal pp_op1_r : word_t;
+	signal pp_op1 : word_t;
+	signal pp_op2 : word_t;
+	signal pp_op2_r : byte_array_t(0 to 3);
+	signal bsy : std_logic;
+
+	signal div_add_res : unsigned (32 downto 0);
+	signal div_add_op1 : unsigned (32 downto 0);
+	signal div_add_op2 : unsigned (32 downto 0);
+	signal div_add_cyi : std_logic;
+	signal div_qbit : std_logic;
+	signal div_start : std_logic;
+	signal div_en : std_logic;
+
+	signal div_A : unsigned (32 downto 0);
+	signal div_M : unsigned (32 downto 0);
+	signal div_M_n : unsigned (32 downto 0);
+	signal div_Q : word_t;
+	
+	type md_state_t is (md_rdy, mul_pre1, mul_pre2, mul_pp, mul_sum, div_process, div_post1, div_post2, div_post3);
+	signal s, sn : md_state_t;
+	signal cycle_cnt : natural range 0 to 31;
+	signal cycle_cnt_preset : natural range 0 to 31;
+	signal cycle_cnt_load : std_logic;
+	signal div_fin_en : unsigned (2 downto 0);
+	
+--------------------------------------------------------------------------
+begin
+-- 9A0CD0570B88D78	
+
+	busy		<= bsy;
+
+	sign1		<= din_hi(din_hi'left) and s_un;
+	sign2		<= din_lo(din_lo'left) and s_un;
+	pp_op1		<= not din_hi when sign1 = '1' else din_hi;
+	pp_op2		<= not din_lo when sign2 = '1' else din_lo;
+	
+--------------------------------------------------------------------------
+md_state:
+	process(s, start, mul_divn, cycle_cnt)
+	begin
+		
+		bsy					<= '1';
+		cycle_cnt_load		<= '0';
+		cycle_cnt_preset	<= 7;
+	
+		mul_en		<= '0';
+		div_en		<= '0';
+		sum_en		<= '0';
+		pre_sum_vld	<= '0';
+		mul_start	<= '0';
+		div_start	<= '0';
+		div_fin_en	<= "000";
+		sn	<= s;
+		case s is
+		when md_rdy =>
+			bsy	<= '0';
+			if start = '1' then
+				if mul_divn = '1' then
+					sn	<= mul_pre1;
+					cycle_cnt_load <= '1';
+					cycle_cnt_preset <= 7;
+					mul_start	<= '1';
+				else
+					sn	<= div_process;
+					cycle_cnt_load <= '1';
+					cycle_cnt_preset <= 31;
+					div_start	<= '1';
+				end if;
+			end if;
+		when mul_pre1 =>
+			pre_sum_vld <= '1';
+			mul_en	<= '1';
+			sn	<= mul_pre2;
+		when mul_pre2 =>
+			pre_sum_vld <= '1';
+			mul_en	<= '1';
+			sn	<= mul_pp;
+		when mul_pp =>
+			mul_en	<= '1';
+			if cycle_cnt = 0 then
+				cycle_cnt_load <= '1';
+				cycle_cnt_preset <= 3;
+				sn	<= mul_sum;
+			end if;
+		when mul_sum =>
+			sum_en	<= '1';
+			if cycle_cnt = 0 then
+				bsy	<= '0';
+				sn	<= md_rdy;
+			end if;
+		when div_process =>
+			div_en	<= '1';
+			if cycle_cnt = 0 then
+				sn	<= div_post1;
+			end if;
+		when div_post1 =>
+			div_fin_en	<= "001";
+			sn	<= div_post2;
+		when div_post2 =>
+			div_fin_en	<= "010";
+			sn	<= div_post3;
+		when div_post3 =>
+			div_fin_en	<= "100";
+			sn	<= md_rdy;
+			bsy	<= '0';
+		when others =>
+			sn	<= md_rdy;
+		end case;		
+				
+	end process;	
+
+md_state_next:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				s	<= md_rdy;
+			else
+				s	<= sn;
+			end if;
+		end if;
+	end process;	
+	
+md_cycle_cnt:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				cycle_cnt		<= 0;
+			elsif cycle_cnt_load = '1' then
+				cycle_cnt	<= cycle_cnt_preset;
+			elsif cycle_cnt /= 0 then
+				cycle_cnt		<= cycle_cnt - 1;
+			end if;	
+		end if;
+	end process;	
+	
+proc_out_reg:
+	process(hilo_sel, result)
+	begin
+		if hilo_sel = '1' then
+			dout <= result(63 downto 32);
+		else	
+			dout <= result(31 downto 0);
+		end if;
+	end process;	
+	
+proc_in_reg:
+	process(clk)
+	variable pre_cond : unsigned(1 downto 0);
+	begin
+		if rising_edge(clk) then
+			if mul_start = '1' or div_start = '1' then
+				pp_op1_r		<= pp_op1;
+				pre_const(0)	<= (others => '0');
+				pre_const(1)	<= (others => '0');
+				pre_cond		:= (din_hi(din_hi'left) and s_un) & (din_lo(din_lo'left) and s_un);
+				s1_r			<= pre_cond(1);
+				s2_r			<= pre_cond(0);
+				sr_r			<= pre_cond(0) xor pre_cond(1);
+				case pre_cond is
+				when "01" =>
+					pre_const(0)	<= din_hi;
+					pre_const(1)	<= X"FFFF_FFFF";
+				when "10" =>	
+					pre_const(0) 	<= X"0000_0000";
+					pre_const(1)	<= X"FFFF_FFFF";
+				when "11" =>	
+					pre_const(0)	<= not din_hi;
+					pre_const(1)	<= X"0000_0001";
+				when others => null;
+				end case;
+			elsif pre_sum_vld = '1' then
+				pre_const(0) <= pre_const(1);
+			end if;
+		end if;
+	end process;	
+	
+proc_mul_sr:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if mul_start = '1' then
+				for i in 0 to 3 loop
+					cy(i) <= '0';
+					pprod(i) <= ppadd_res(i) & X"00";
+				end loop;	
+			elsif mul_en = '1' then
+				for i in 0 to 3 loop
+					cy(i) <= ppadd_cyo(i);
+					pprod(i) <= ppadd_res(i) & pprod(i)(8 downto 1);
+				end loop;
+			elsif sum_en = '1' then
+				for i in 1 to 3 loop
+					pprod(i-1) <= pprod(i);
+				end loop;
+			end if;
+		end if;
+	end process;	
+		
+gen_mul32x8pp:
+	for i in 0 to 3 generate
+	begin
+	
+	pp_adder_mux:
+		process(mul_start, pp_op1, pp_op2, pp_op1_r, pp_op2_r(i), s1_r, sign1, pprod(i), cy(i))
+		variable v2 : unsigned(7 downto 0);
+		begin
+			ppadd_cyi(i) <= '0';
+			ppadd_op1(i) <= (others => '0');
+			if mul_start = '1' then
+				ppadd_op2(i) <= (others => '0');
+				v2	:= pp_op2(8*(i+1)-1 downto 8*i);
+				if v2(0) = '1' then
+					ppadd_cyi(i) <= sign1;
+					ppadd_op1(i) <= pp_op1;
+				end if;
+			else
+				ppadd_op2(i) <= cy(i) & pprod(i)(39 downto 9);
+				v2 := pp_op2_r(i);
+				if v2(0) = '1' then
+					ppadd_cyi(i) <= s1_r;
+					ppadd_op1(i) <= pp_op1_r;
+				end if;
+			end if;	
+		end process;	
+
+	pp_adder:
+		process(ppadd_op1(i), ppadd_op2(i), ppadd_cyi(i))
+		variable sum_pp : unsigned(33 downto 0);
+		begin
+			sum_pp			:= ('0' & ppadd_op1(i) & ppadd_cyi(i)) + ('0' & ppadd_op2(i) & ppadd_cyi(i));
+			ppadd_res(i)	<= sum_pp(sum_pp'left-1 downto 1);
+			ppadd_cyo(i)	<= sum_pp(sum_pp'left);
+		end process;	
+
+	proc_mul_ctrl:
+		process(clk)
+		begin
+			if rising_edge(clk) then
+				if mul_start = '1' then
+					pp_op2_r(i) <= '0' & pp_op2(8*(i+1)-1 downto 8*i+1);
+				elsif mul_en = '1' then
+					pp_op2_r(i) <= '0' & pp_op2_r(i)(7 downto 1);
+				end if;
+			end if;
+		end process;	
+		
+	end generate;
+	
+comb_mul_adder:
+	process(add_op1, add_op2)
+	variable sum_mul : unsigned(39 downto 0);
+	begin
+		sum_mul		:= (add_op1) + (add_op2);
+		add_res		<= sum_mul(sum_mul'left downto 0);
+	end process;	
+
+comb_mul_adder_mux:
+	process(pre_const, pre_sum_vld, pp_reg, pprod, sr_r)
+	variable s_ext : std_logic;
+	begin
+		if pre_sum_vld = '1' then
+			add_op1 <= pp_reg(63 downto 24);
+			add_op2	<= pre_const(0) & X"00";
+		else
+			s_ext := pp_reg(63) and sr_r;
+			add_op1	<= (7 downto 0 => s_ext) & pp_reg(63 downto 32);
+			add_op2	<= pprod(0);
+		end if;	
+	end process;	
+
+comb_mul:
+	process(clk)
+	variable tmp : prod_t;
+	begin
+		if rising_edge(clk) then
+			if mul_start = '1' then
+				pp_reg	<= (others => '0');
+			elsif pre_sum_vld = '1' then
+				pp_reg	<= add_res & X"0000";
+			elsif sum_en = '1' then
+				tmp		:= add_res & pp_reg(31 downto 8);
+				pp_reg	<= tmp(63 downto 8);
+				result	<= tmp;
+				if sr_r = '1' then
+					result	<= not tmp;
+				end if;
+			elsif div_fin_en(1) = '1' then
+				result(63 downto 32)		<= div_A(31 downto 0);
+				if s1_r = '1' then
+					result(63 downto 32)	<= div_add_res(31 downto 0);
+				end if;	
+			elsif div_fin_en(2) = '1' then
+				result(31 downto 0)		<= div_Q;
+				if sr_r = '1' then
+					result(31 downto 0)	<= div_add_res(31 downto 0);
+				end if;
+			elsif hilo_we = '1' then
+				if hilo_sel = '1' then
+					result(63 downto 32) <= din_hi;
+				else	
+					result(31 downto 0) <= din_hi;
+				end if;
+			end if;
+		end if;
+	end process;	
+
+div_adder:
+	process(div_add_op1, div_add_op2, div_add_cyi)
+	variable sum_div : unsigned(33 downto 0);
+	begin
+		sum_div			:= (div_add_op1 & div_add_cyi) + (div_add_op2 & div_add_cyi);
+		div_add_res		<= sum_div(sum_div'left downto 1);
+	end process;	
+
+div_adder_mux:
+	process(div_start, div_en, div_fin_en, div_A, div_Q, pp_op1, sign1, s1_r, s2_r, sr_r, div_qbit, div_M, div_M_n)
+	begin
+	
+		div_add_cyi	<= s2_r xor div_qbit;
+		div_add_op1	<= div_A(31 downto 0) & div_Q(31);
+		div_add_op2	<= (others => '0');
+		if div_start = '1' then
+			div_add_op1	<= '0' & pp_op1;
+			div_add_cyi	<= sign1;
+		elsif div_en = '1' then
+			div_add_op2	<= div_M;
+			if div_qbit = '1' then
+				div_add_op2	<= div_M_n;
+			end if;
+		elsif div_fin_en(0) = '1' then
+			div_add_op2	<= div_M;
+			div_add_cyi	<= s2_r;
+			div_add_op1	<= '0' & div_A(31 downto 0);
+		elsif div_fin_en(1) = '1' then
+			div_add_cyi	<= s1_r;
+			div_add_op1	<= '0' & not div_A(31 downto 0);
+		elsif div_fin_en(2) = '1' then
+			div_add_cyi	<= sr_r;
+			div_add_op1	<= '0' & not div_Q;
+		end if;	
+	end process;	
+
+divide:
+	process(clk)
+	variable quo : std_logic;
+	begin
+		if rising_edge(clk) then
+			if div_start = '1' then
+				div_qbit	<= '1';
+				div_Q		<= div_add_res(31 downto 0);
+				div_A		<= (others => '0');
+				if sign2 = '1' then
+					div_M_n		<= '1' & din_lo;
+					div_M		<= '0' & not din_lo;
+				else
+					div_M_n		<= '1' & not din_lo;
+					div_M		<= '0' & din_lo;
+				end	if;
+			elsif div_en = '1' then
+				div_qbit	<= not div_add_res(32);
+				div_A		<= div_add_res(32 downto 0);
+				div_Q		<= div_Q(30 downto 0) & not div_add_res(32);
+			elsif div_fin_en(0) = '1' then
+				if div_A(32) = '1' then
+					div_A		<= '0' & div_add_res(31 downto 0);
+				end if;
+			end if;
+		end if;
+	end process;	
+
+--------------------------------------------------------------------------
+end Behavioral;
diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
new file mode 100644
index 0000000..fbdc1e8
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
@@ -0,0 +1,914 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The pipeline
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+use work.mips_instr.all;
+
+entity pipeline is
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		halt		: in  STD_LOGIC;
+		int			: in  unsigned(5 downto 0);
+		imem_rdy	: in  STD_LOGIC;
+		imem_en		: out STD_LOGIC;
+		imem_addr	: out word_t;
+		imem_data	: in  word_t;
+		dmem_rdy	: in  STD_LOGIC;
+		dmem_en		: out STD_LOGIC;
+		dmem_re		: out STD_LOGIC;
+		dmem_we		: out unsigned(3 downto 0);
+		dmem_addr	: out word_t;
+		dmem_din	: in  word_t;
+		dmem_dout	: out word_t
+	);
+end pipeline;
+
+architecture Behavioral of pipeline is
+
+--------------------------------------------------------------------------
+	COMPONENT reg_dual is
+	Generic
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port 
+	(
+		clk_w		: in  STD_LOGIC;
+		en			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		wptr		: in  unsigned (addr_width-1 downto 0);
+		din			: in  unsigned (data_width-1 downto 0);
+		rptr_a		: in  unsigned (addr_width-1 downto 0);
+		rptr_b		: in  unsigned (addr_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+	END COMPONENT;
+
+--------------------------------------------------------------------------
+	COMPONENT idecode_rom is
+	Port 
+	(
+		nop			: in  std_logic;
+		inst_in		: in  word_t;
+		ctrl_out	: out ctrl_lines_t
+	);
+	END COMPONENT;
+
+--------------------------------------------------------------------------
+	COMPONENT shifter is
+	Generic 
+	(
+		data_width : integer
+	);
+	Port 
+	(
+		shift_ctrl	: in  shift_ctrl_t;
+		din			: in  unsigned (data_width-1 downto 0);
+		dout		: out unsigned (data_width-1 downto 0)
+	);
+	END COMPONENT;
+	
+--------------------------------------------------------------------------
+	COMPONENT alu is
+	Generic 
+	(
+		data_width : integer
+	);
+	Port 
+	(
+		op1_in		: in  unsigned (data_width-1 downto 0);
+		op2_in		: in  unsigned (data_width-1 downto 0);
+		op2_shifted	: in  unsigned (data_width-1 downto 0);
+		ctrl		: in  alu_ctrl_t;
+		result		: out unsigned (data_width-1 downto 0);
+		flags		: out alu_flags_t
+	);
+	END COMPONENT;
+
+--------------------------------------------------------------------------
+	COMPONENT bcu is
+	Generic 
+	(
+		data_width : integer
+	);
+	Port 
+	(
+		op1_in		: in  unsigned (data_width-1 downto 0);
+		op2_in		: in  unsigned (data_width-1 downto 0);
+		flags		: out bcu_flags_t
+	);
+	END COMPONENT;
+	
+--------------------------------------------------------------------------
+	COMPONENT cop is
+	Port 
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		sdu			: in  sdu_t;
+		IR_valid	: in  STD_LOGIC;
+		IR			: in  word_t;
+		events		: in  event_t;
+		ctrl_in		: in  cop_ctrl_in_t;
+		ctrl_out	: out cop_ctrl_out_t;
+		din			: in  word_t;
+		dout		: out word_t
+	);
+	END COMPONENT;
+	
+--------------------------------------------------------------------------
+	COMPONENT muldiv is
+	Port 
+	(
+		rst			: in  std_logic;
+		clk			: in  std_logic;
+		hilo_we		: in  std_logic;
+		din_hi		: in  word_t;
+		din_lo		: in  word_t;
+		mul_divn	: in  std_logic;
+		start		: in  std_logic;
+		s_un		: in  std_logic;
+		hilo_sel	: in  std_logic;
+		busy		: out std_logic;
+		dout		: out word_t
+	);
+	END COMPONENT;
+
+--------------------------------------------------------------------------
+	constant RESET_VECTOR	: word_t := X"BFC00000";
+
+	signal ID_stage			: ID_t;
+	signal EX_stage			: EX_t;
+	signal MEM_stage		: MEM_t;
+	signal WB_stage			: WB_t;
+	signal clk_2, clk_1		: STD_LOGIC;
+	signal hdu				: hdu_t;
+	signal sdu				: sdu_t;
+	signal cpu_rst			: STD_LOGIC;
+	signal reg_a			: word_t;
+	signal reg_b			: word_t;
+	signal ctrl_lines		: ctrl_lines_t;
+	signal cpu_run			: STD_LOGIC;
+	signal branch_ce		: STD_LOGIC;
+	signal run_en			: STD_LOGIC;
+	signal mul_dep			: STD_LOGIC;
+	signal imem_dep			: STD_LOGIC;
+	signal dmem_dep			: STD_LOGIC;
+	signal cop_ctrl			: cop_ctrl_in_t;
+	signal cop_stat			: cop_ctrl_out_t;
+	signal cop_din			: word_t;
+	signal cop_dout			: word_t;
+	signal alu_result		: word_t;
+	signal mul_result		: word_t;
+	signal mul_busy			: STD_LOGIC;
+	signal EX_events_instr	: event_t;
+	signal EX_events_alu	: event_t;
+	signal EX_events_mem	: event_t;
+	signal EX_events		: event_t;
+	signal MEM_events		: event_t;
+	signal bcu_op_a			: word_t;
+	signal bcu_op_b			: word_t;
+	signal bcu_flags		: bcu_flags_t;
+	signal vaddr			: word_t;
+	
+	attribute ram_style : string;
+	
+	attribute ram_style of reg_a: signal is "distributed";
+	attribute ram_style of reg_b: signal is "distributed";
+
+	signal pc : pc_t;
+	
+--------------------------------------------------------------------------
+begin
+	
+	clk_1					<= clk;
+	clk_2					<= not clk;
+	cpu_run					<= run_en;
+	
+	-- Stall Detection Unit ---------------------------------------------------
+	sdu.ID_nop				<= imem_dep or cop_stat.exc_pending or EX_stage.exc or MEM_stage.exc;
+	sdu.EX_nop				<= mul_dep or ID_stage.nop or ID_stage.exc;
+	sdu.MEM_nop				<= EX_stage.nop or EX_stage.exc;
+	sdu.WB_nop				<= dmem_dep or MEM_stage.nop;
+
+	sdu.ID_stall			<= dmem_dep or imem_dep or mul_dep or ID_stage.exc;
+	sdu.EX_stall			<= dmem_dep;
+	sdu.MEM_stall			<= dmem_dep;
+	sdu.WB_stall			<= '0';
+
+	mul_dep					<= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy);
+	imem_dep				<= not imem_rdy;
+	dmem_dep				<= not dmem_rdy and MEM_stage.ctrl.dmem_en;
+	---------------------------------------------------------------------------
+	imem_en 				<= cpu_run and not (mul_dep or dmem_dep or cop_stat.exc_commit);
+	
+--------------------------------------------------------------------------
+-- Muldiv
+--------------------------------------------------------------------------
+inst_muldiv: muldiv
+	PORT MAP
+	(
+		rst			=> cpu_rst,
+		clk			=> clk,
+		hilo_we		=> EX_stage.ctrl.mul_hilo_we,
+		din_hi		=> EX_stage.reg_a,
+		din_lo		=> EX_stage.reg_b,
+		mul_divn	=> EX_stage.ctrl.mul_mul_divn,
+		start		=> EX_stage.ctrl.mul_start,
+		s_un		=> EX_stage.ctrl.mul_s_un,
+		hilo_sel	=> EX_stage.ctrl.mul_hilo_sel,
+		busy		=> mul_busy,
+		dout		=> mul_result
+	);
+
+--------------------------------------------------------------------------
+-- Coprocessor
+--------------------------------------------------------------------------
+inst_cop: cop
+	PORT MAP
+	(
+		rst			=> cpu_rst,
+		clk			=> clk,
+		sdu			=> sdu,
+		events		=> MEM_stage.events,
+		IR_valid	=> ID_stage.ctrl.cop_instr_en,
+		IR			=> ID_stage.IR,
+		ctrl_in		=> cop_ctrl,
+		ctrl_out	=> cop_stat,
+		dout		=> cop_dout,
+		din			=> cop_din
+	);
+
+	cop_ctrl.bd_wb			<= WB_stage.bd;
+	cop_ctrl.epc_mem		<= MEM_stage.pcn;
+	cop_ctrl.epc_wb			<= MEM_stage.epc;
+	cop_ctrl.imem_addr		<= pc.nxt;
+	cop_ctrl.dmem_addr		<= MEM_stage.va;
+
+--------------------------------------------------------------------------
+-- IF stage
+--------------------------------------------------------------------------
+	imem_addr		<= pc.curr;
+
+proc_stage_pc:
+	process(pc, rst, cop_stat)
+	begin
+		if rst = '1' then
+			pc.curr	<= RESET_VECTOR after 2 ns;
+		else
+			if pc.is_branch and cop_stat.exc_pending = '0' then
+				pc.curr	<= pc.pc_branch after 2 ns;
+			else
+				pc.curr	<= pc.nxt after 2 ns;
+			end if;	
+		end if;	
+	end process;
+
+proc_stage_pc_branch:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			if sdu.ID_stall = '0' then
+				pc.pc_branch	<= pc.curr + ID_stage.bimm18;
+			end if;	
+		end if;	
+	end process;
+
+proc_stage_pc_next:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			branch_ce	<= '0';
+			cop_ctrl.exc_left		<= '0';
+			if rst = '1' then
+				pc.nxt	<= RESET_VECTOR;
+				pc.last	<= RESET_VECTOR;
+			elsif cop_stat.exc_commit = '1' then
+				pc.nxt	<= cop_stat.exc_vec;
+			elsif sdu.ID_stall = '0' then
+				cop_ctrl.exc_left		<= cop_stat.exc_exit;
+				branch_ce	<= '1';
+				pc.last	<= pc.curr;
+				if ID_stage.ctrl.jump = '1' then
+					pc.nxt	<= ID_stage.jimm32;
+				elsif ID_stage.ctrl.jump_long = '1' then
+					pc.nxt	<= ID_stage.reg_a;
+				else
+					pc.nxt	<= pc.curr + 4;
+				end if;
+			end if;
+		end if;	
+	end process;
+
+proc_stage_branch:
+	process(clk_2)
+	begin
+		if rising_edge(clk_2) and branch_ce = '1' then
+			pc.is_branch	<= false;
+			if EX_stage.ctrl.branch = '1' then
+
+				case EX_stage.ctrl.bc_src is
+
+				when bc_eq_ne =>
+					if (EX_stage.ctrl.bc_not xor bcu_flags.eq) = '1' then
+						pc.is_branch <= true;
+					end if;
+
+				when bc_lez_gtz =>
+					if (EX_stage.ctrl.bc_not xor (bcu_flags.z or bcu_flags.ltz)) = '1' then
+						pc.is_branch <= true;
+					end if;
+
+				when bc_ltz_gez =>
+					if (EX_stage.ctrl.bc_not xor bcu_flags.ltz) = '1' then
+						pc.is_branch <= true;
+					end if;
+
+				when others => null;
+				end case;
+			end if;	
+		end if;	
+	end process;
+
+	process(rst, clk_1)
+	variable reset_delay : unsigned (5 downto 0);
+	begin
+		if rising_edge(clk_1) then
+			if rst = '1' then
+				reset_delay := (others => '1');
+				cpu_rst <= '1';
+				run_en	<= '0';
+			elsif reset_delay /= (5 downto 0 => '0') then
+				reset_delay := reset_delay - 1;
+			else
+				cpu_rst <= '0';
+			end if;	
+			if reset_delay(reset_delay'left-1) = '0' then
+				run_en	<= '1';
+			end if;	
+		end if;
+	end process;
+
+--------------------------------------------------------------------------
+-- ID stage
+--------------------------------------------------------------------------
+	ID_stage.IR					<= to_01(imem_data);
+	ID_stage.pcn				<= pc.curr;
+	ID_stage.op					<= decode_op(ID_stage.IR);
+	ID_stage.jimm32				<= extract_jimm32(ID_stage.IR, ID_stage.pcn);
+	ID_stage.bimm18				<= extract_bimm18(ID_stage.IR, ID_stage.pcn);
+	ID_stage.shamt				<= extract_shamt(ID_stage.IR);
+	ID_stage.reg_a_rptr			<= extract_rs(ID_stage.IR);
+	ID_stage.reg_b_rptr			<= extract_rt(ID_stage.IR);
+	ID_stage.ctrl				<= ctrl_lines;
+	ID_stage.reg_write			<= ID_stage.ctrl.reg_write or cop_stat.reg_write;
+	ID_stage.epc				<= pc.last;
+	ID_stage.exc				<= event_is_active(ID_stage.events); -- Todo: works
+	ID_stage.nop				<= sdu.ID_nop;
+	
+proc_ID_except:
+	process(ID_stage, cop_stat, pc)
+	begin	
+		ID_stage.events					<= events_clr;
+		ID_stage.events.inst_load_err	<= pc.nxt(1) or pc.nxt(0);
+		ID_stage.events.inst_priv_addr	<= pc.nxt(word_t'left) and cop_stat.user_mode;
+	end process;
+	
+proc_stage_hdu:
+	process(ID_stage, EX_stage, MEM_stage, WB_stage)
+	variable read_a, read_b : boolean;
+	variable raw_a_EX, raw_a_MEM, raw_a_WB : boolean;
+	variable raw_b_EX, raw_b_MEM, raw_b_WB : boolean;
+	variable reg_ptr_a : reg_ptr_t;
+	variable reg_ptr_b : reg_ptr_t;
+	begin
+		
+		reg_ptr_a			:= ID_stage.reg_a_rptr;
+		reg_ptr_b			:= ID_stage.reg_b_rptr;
+		raw_a_EX			:= reg_ptr_a = EX_stage.reg_wptr and EX_stage.wreg_we = '1';
+		raw_a_MEM			:= reg_ptr_a = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1';
+		raw_a_WB			:= reg_ptr_a = WB_stage.reg_wptr and WB_stage.wreg_we = '1';
+		raw_b_EX			:= reg_ptr_b = EX_stage.reg_wptr and EX_stage.wreg_we = '1';
+		raw_b_MEM			:= reg_ptr_b = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1';
+		raw_b_WB			:= reg_ptr_b = WB_stage.reg_wptr and WB_stage.wreg_we = '1';
+
+		hdu.alu_fwd_a_ex	<= raw_a_EX after 1 ns;
+		hdu.alu_fwd_a_mem	<= raw_a_MEM after 1 ns;
+		hdu.alu_fwd_a_wb	<= raw_a_WB after 1 ns;
+		hdu.alu_fwd_b_ex	<= raw_b_EX after 1 ns;
+		hdu.alu_fwd_b_mem	<= raw_b_MEM after 1 ns;
+		hdu.alu_fwd_b_wb	<= raw_b_WB after 1 ns;
+
+	end process;
+	
+proc_stage_fwd_a:
+	process(reg_a, hdu, EX_stage, MEM_stage, WB_stage)
+	variable data : word_t;
+	begin
+		data		:= reg_a;
+		if hdu.alu_fwd_a_ex then
+			data	:= EX_stage.result;
+		elsif hdu.alu_fwd_a_mem then
+			data 	:= MEM_stage.data;
+		elsif hdu.alu_fwd_a_wb then
+			data 	:= WB_stage.data;
+		end if;
+		ID_stage.reg_a	<= to_01(data) after 2 ns;
+	end process;
+
+proc_stage_fwd_b:
+	process(reg_b, hdu, EX_stage, MEM_stage, WB_stage)
+	variable data : word_t;
+	begin
+		data		:= reg_b;
+		if hdu.alu_fwd_b_ex then
+			data	:= EX_stage.result;
+		elsif hdu.alu_fwd_b_mem then
+			data	:= MEM_stage.data;
+		elsif hdu.alu_fwd_b_wb then
+			data	:= WB_stage.data;
+		end if;
+		ID_stage.reg_b	<= to_01(data) after 2 ns;
+	end process;
+	
+proc_imm_mux:
+	process(ID_stage)
+	variable data : word_t;
+	begin
+		data := extract_uimm16(ID_stage.IR);
+
+		case ID_stage.ctrl.imm_src is
+
+		when src_imm32 =>
+			data := extract_simm32(ID_stage.IR);
+
+		when src_imm16 =>
+			data := extract_uimm16(ID_stage.IR);
+
+		when src_imm16_high =>
+			data := ID_stage.IR(word_t'length/2-1 downto 0) & (word_t'length/2-1 downto 0 => '0');
+			
+		when others => null;
+
+		end case;
+
+		ID_stage.imm <= data after 2 ns;
+
+	end process;
+
+--------------------------------------------------------------------------
+inst_idecode_rom: idecode_rom
+	PORT MAP
+	(
+		nop			=> sdu.ID_nop,
+		inst_in		=> ID_stage.IR,
+		ctrl_out	=> ctrl_lines
+	);
+
+inst_reg_dual: reg_dual
+	GENERIC MAP
+	(
+		addr_width	=> reg_ptr_t'length,
+		data_width	=> word_t'length
+	)
+	PORT MAP
+	(
+		clk_w		=> clk_1,
+		we			=> WB_stage.wreg_we,
+		en			=> '1',
+		wptr		=> WB_stage.reg_wptr,
+		din			=> WB_stage.data,
+		rptr_a		=> ID_stage.reg_a_rptr,
+		rptr_b		=> ID_stage.reg_b_rptr,
+		dout_a		=> reg_a,
+		dout_b		=> reg_b
+	);
+
+--------------------------------------------------------------------------
+-- EX stage
+--------------------------------------------------------------------------
+	EX_stage.reg_a_rptr		<= extract_rs(EX_stage.IR);
+	EX_stage.reg_b_rptr		<= extract_rt(EX_stage.IR);
+	EX_stage.result			<= mul_result when EX_stage.ctrl.mul_access = '1' else alu_result;
+	
+proc_stage_ID_EX_1:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			if rst = '1' then
+				EX_stage.op						<= NOP;
+				EX_stage.IR						<= (others => '0');
+				EX_stage.ctrl					<= ctrl_lines_default;
+				EX_stage.reg_write				<= '0';
+				EX_stage.epc					<= (others => '0');
+				EX_stage.pcn					<= (others => '0');
+				EX_stage.events_in				<= events_clr;
+			elsif sdu.EX_stall = '0' then
+				EX_stage.reg_a			<= ID_stage.reg_a;
+				EX_stage.reg_b			<= ID_stage.reg_b;
+				EX_stage.events_in		<= ID_stage.events;
+				EX_stage.op				<= ID_stage.op;
+				EX_stage.ctrl			<= ID_stage.ctrl;
+				EX_stage.reg_write		<= ID_stage.reg_write;
+				EX_stage.nop			<= sdu.EX_nop;
+				EX_stage.IR				<= ID_stage.IR;
+				EX_stage.pcn			<= ID_stage.pcn;
+				if sdu.EX_nop = '1' then
+					EX_stage.op				<= NOP;
+					EX_stage.IR				<= (others => '0');
+					EX_stage.ctrl			<= ctrl_lines_default;
+					EX_stage.reg_write		<= '0';
+				else
+					EX_stage.epc			<= ID_stage.epc;
+				end if;
+			end if;	
+		end if;
+	end process;
+
+proc_stage_EX_instr_except:
+	process(EX_stage)
+	begin
+		EX_events_instr					<= events_clr;
+		EX_events_instr.illegal			<= EX_stage.ctrl.exc_illegal;
+		EX_events_instr.break			<= EX_stage.ctrl.exc_break;
+		EX_events_instr.syscall			<= EX_stage.ctrl.exc_syscall;
+	end process;
+
+proc_stage_EX_alu_except:
+	process(EX_stage)
+	begin
+		EX_events_alu	<= events_clr;
+		if EX_stage.ctrl.alu_exc_en = '1' then
+			if EX_stage.alu_flags.ovf = '1' then
+				EX_events_alu.alu_ovf	<= '1';
+			end if;	
+			if EX_stage.alu_flags.uvf = '1' then
+				EX_events_alu.alu_uvf	<= '1';
+			end if;	
+		end if;	
+	end process;
+
+	vaddr			<= ID_stage.reg_a + extract_simm32(ID_stage.IR);
+	
+proc_stage_EX_mem_except:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			if rst = '1' then
+				dmem_en		<= '0';
+			elsif sdu.EX_stall = '0' then
+				EX_events_mem	<= events_clr;
+				dmem_en		<= '0';
+				if ID_stage.ctrl.dmem_en = '1' then
+					dmem_en		<= '1';
+					if ID_stage.ctrl.except_en = '1' then
+						if ID_stage.ctrl.word2_en = '1' then
+							if vaddr(0) = '1' then
+								EX_events_mem.data_load_err		<= not ID_stage.ctrl.dmem_we;
+								EX_events_mem.data_store_err	<= ID_stage.ctrl.dmem_we;
+								dmem_en							<= '0';
+							end if;
+						elsif vaddr(1 downto 0) /= "00" then
+							EX_events_mem.data_load_err		<= not ID_stage.ctrl.dmem_we;
+							EX_events_mem.data_store_err	<= ID_stage.ctrl.dmem_we;
+							dmem_en							<= '0';
+						end if;	
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+proc_stage_DMEM_ADDR:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			if sdu.EX_stall = '0' then --and ID_stage.ctrl.dmem_en = '1' then
+				EX_stage.va		<= vaddr;
+				if cop_stat.RE = '1' then
+					EX_stage.pa_off	<= not vaddr(1 downto 0);
+				else	
+					EX_stage.pa_off	<= vaddr(1 downto 0);
+				end if;
+			end if;
+		end if;
+	end process;
+	dmem_we		<= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns;
+	dmem_re		<= not EX_stage.ctrl.dmem_we;
+	dmem_dout	<= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
+	dmem_addr	<= EX_stage.va;
+	cop_din		<= EX_stage.reg_b;
+	EX_stage.events			<= EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in;
+	EX_stage.exc			<= event_is_active(EX_stage.events);
+	
+--------------------------------------------------------------------------
+proc_wptr_mux:
+	process(EX_stage)
+	variable opclass : opcode_t;
+	variable reg_wptr : reg_ptr_t;
+	begin
+	
+		opclass := extract_opc(EX_stage.IR);
+		case opclass is
+		when "000000" =>
+			reg_wptr					:= extract_rd(EX_stage.IR);
+		when others =>
+			reg_wptr					:= extract_rt(EX_stage.IR);
+		end case;
+		
+		EX_stage.wreg_we <= EX_stage.reg_write after 1 ns;
+		if reg_wptr = "00000" then
+			EX_stage.wreg_we <= '0' after 1 ns;
+		end if;	
+
+		EX_stage.reg_wptr	<= reg_wptr after 1 ns;
+		case EX_stage.ctrl.wptr_srcsel is
+			when wptr_src_imm =>
+				EX_stage.reg_wptr	<= reg_wptr after 1 ns;
+
+			when wptr_src_const =>
+				EX_stage.reg_wptr	<= to_unsigned(31, reg_ptr_t'length) after 1 ns;
+				EX_stage.wreg_we <= '1' after 1 ns;
+
+			when others => null;
+		end case;
+
+	end process;
+
+--------------------------------------------------------------------------
+proc_stage_bcu_op:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			bcu_op_a		<= ID_stage.reg_a;
+			bcu_op_b		<= ID_stage.reg_b;
+		end if;
+	end process;
+
+alu_op1_mux:
+	process(EX_stage)
+	variable data : word_t;
+	begin
+	
+		data := EX_stage.reg_a;
+
+--		case EX_stage.ctrl.alu.op1_src is
+--
+--		when alu_src_reg =>
+--			data := EX_stage.reg_a;
+--
+--		when alu_src_muldiv =>
+--			data := mul_result;
+--
+--		when others => null;
+--
+--		end case;
+
+		EX_stage.alu_op1 <= data;
+
+	end process;
+
+alu_op2_mux:
+	process(clk_1)
+	variable data : word_t;
+	begin
+
+		if rising_edge(clk_1) and sdu.EX_stall = '0' then
+			data := ID_stage.reg_b;
+
+			case ID_stage.ctrl.alu.op2_src is
+
+			when alu_src_reg =>
+				data := ID_stage.reg_b;
+
+			when alu_src_imm =>
+				data := ID_stage.imm;
+
+			when others => null;
+
+			end case;
+
+			EX_stage.alu_op2 <= data;
+		end if;
+
+	end process;
+
+shifter_sa_mux:
+	process(clk_1)
+	variable data 		: shamt_t;
+	variable data_inv 	: shamt_t;
+
+	begin
+		if rising_edge(clk_1) and sdu.EX_stall = '0' then
+			data 		:= ID_stage.reg_a(4 downto 0);
+			case ID_stage.ctrl.shamt2_srcsel is
+
+				when sa_src_reg =>
+					data := ID_stage.reg_a(4 downto 0);
+
+				when sa_src_imm =>
+					data := ID_stage.shamt;
+
+				when others => null;
+
+			end case;
+			data_inv := not data + 1;
+			if ID_stage.ctrl.alu.shift_right = '0' then
+				EX_stage.shift_ctrl.shamt_rnd	<= data_inv after 2 ns;
+			else	
+				EX_stage.shift_ctrl.shamt_rnd	<= data after 2 ns;
+			end if;
+			EX_stage.shift_ctrl.shamt_nrm	<= data after 1 ns;
+			EX_stage.shift_ctrl.shift_right	<= ID_stage.ctrl.alu.shift_right;
+			EX_stage.shift_ctrl.shift_arith	<= ID_stage.ctrl.alu.shift_arith;
+		end if;
+		
+	end process;
+
+--------------------------------------------------------------------------
+inst_shifter: shifter
+	GENERIC MAP
+	(
+		data_width	=> word_t'length
+	)
+	PORT MAP
+	(
+		shift_ctrl	=> EX_stage.shift_ctrl,
+		din			=> EX_stage.reg_b,
+		dout		=> EX_stage.alu_op2_s
+	);
+
+inst_alu: alu
+	GENERIC MAP
+	(
+		data_width	=> word_t'length
+	)
+	PORT MAP
+	(
+		op1_in			=> EX_stage.alu_op1,
+		op2_in			=> EX_stage.alu_op2,
+		op2_shifted		=> EX_stage.alu_op2_s,
+		ctrl			=> EX_stage.ctrl.alu,
+		result			=> alu_result,
+		flags			=> EX_stage.alu_flags
+	);
+
+inst_bcu: bcu
+	GENERIC MAP
+	(
+		data_width	=> word_t'length
+	)
+	PORT MAP
+	(
+		op1_in		=> bcu_op_a,
+		op2_in		=> bcu_op_b,
+		flags		=> bcu_flags
+	);
+
+--------------------------------------------------------------------------
+-- MEM stage
+--------------------------------------------------------------------------
+proc_stage_MEM_n:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			if rst = '1' then
+				MEM_stage.op		<= NOP;
+				MEM_stage.wreg_we	<= '0';
+				MEM_stage.ctrl		<= ctrl_lines_default;
+				MEM_stage.pa_off	<= (others => '0');
+				MEM_stage.events_in	<= events_clr;
+--				MEM_stage.epc		<= (others => '0');
+--				MEM_stage.pcn		<= (others => '0');
+--				MEM_stage.va		<= (others => '0');
+--				MEM_stage.reg_wptr	<= (others => '0');
+--				MEM_stage.ex_result	<= (others => '0');
+			elsif sdu.MEM_stall = '0' then
+				MEM_stage.events_in		<= EX_stage.events;
+				MEM_stage.op			<= EX_stage.op;
+				MEM_stage.wreg_we		<= EX_stage.wreg_we;
+				MEM_stage.ctrl			<= EX_stage.ctrl;
+				MEM_stage.va			<= EX_stage.va;
+				MEM_stage.pa_off		<= EX_stage.pa_off;
+				MEM_stage.reg_wptr		<= EX_stage.reg_wptr;
+				MEM_stage.nop			<= sdu.MEM_nop;
+				if EX_stage.ctrl.dmem_en = '1' then
+					MEM_stage.ex_result		<= EX_stage.reg_b;
+				else
+					MEM_stage.ex_result		<= EX_stage.result;
+					if cop_stat.cop_read = '1' then
+						MEM_stage.ex_result	<= cop_dout;
+					end if;	
+				end if;	
+				if sdu.MEM_nop = '1' then
+					MEM_stage.op		<= NOP;
+					MEM_stage.wreg_we	<= '0';
+					MEM_stage.ctrl		<= ctrl_lines_default;
+				else
+					MEM_stage.pcn			<= EX_stage.pcn;
+					MEM_stage.epc			<= EX_stage.epc;
+				end if;
+			end if;	
+		end if;
+	end process;
+
+proc_stage_MEM_mux:
+	process(MEM_stage, dmem_din)
+	variable temp1 : word_t;
+	variable temp2 : word_t;
+	variable data : word_t;
+	variable be : unsigned(3 downto 0);
+	begin
+		data	:= MEM_stage.ex_result;
+		be		:= load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp);
+		if MEM_stage.ctrl.reg_link = '1' then
+			data		:= MEM_stage.pcn + 4;
+		elsif MEM_stage.ctrl.dmem_en = '1' then
+			temp1		:= load_shift(dmem_din,  MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp);
+			temp2		:= load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en);
+			if be(0) = '1' then
+				data(7 downto 0)	:= temp2(7 downto 0);
+			end if;	
+			if be(1) = '1' then
+				data(15 downto 8)	:= temp2(15 downto 8);
+			end if;	
+			if be(2) = '1' then
+				data(23 downto 16)	:= temp2(23 downto 16);
+			end if;	
+			if be(3) = '1' then
+				data(31 downto 24)	:= temp2(31 downto 24);
+			end if;	
+		end if;
+		MEM_stage.data				<= data after 1 ns;
+		
+	end process;
+
+proc_stage_MEM_except:
+	process(MEM_stage, int)
+	begin
+		MEM_stage.events				<= MEM_stage.events_in;
+		MEM_stage.events.Int			<= int;
+	end process;
+
+	MEM_stage.exc	<= cop_stat.int or event_is_active(MEM_stage.events_in);
+
+--------------------------------------------------------------------------
+-- WB stage
+--------------------------------------------------------------------------
+proc_stage_WB_p:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			if rst = '1' then
+				WB_stage.op				<= NOP;
+				WB_stage.wreg_we		<= '0';
+--				WB_stage.epc			<= (others => '0');
+--				WB_stage.reg_wptr		<= (others => '0');
+--				WB_stage.data			<= (others => '0');
+			elsif sdu.WB_stall = '0' then
+				WB_stage.op				<= MEM_stage.op;
+				WB_stage.wreg_we		<= MEM_stage.wreg_we;
+				WB_stage.reg_wptr		<= MEM_stage.reg_wptr;
+				WB_stage.data			<= MEM_stage.data;
+				WB_stage.nop			<= sdu.WB_nop;
+				if sdu.WB_nop = '1' then
+					WB_stage.op				<= NOP;
+					WB_stage.wreg_we		<= '0';
+				else
+					WB_stage.epc			<= MEM_stage.epc;
+					WB_stage.bd				<= MEM_stage.ctrl.branch or MEM_stage.ctrl.jump or MEM_stage.ctrl.jump_long; -- Todo: works
+				end if;	
+			end if;	
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end Behavioral;
diff --git a/lib/CPUs/MIPS/src/core/mips_reg.vhd b/lib/CPUs/MIPS/src/core/mips_reg.vhd
new file mode 100644
index 0000000..da76225
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/mips_reg.vhd
@@ -0,0 +1,81 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: On-Chip work registers
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.mips_types.all;
+
+entity reg_dual is
+	Generic
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clk_w		: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		en			: in  STD_LOGIC;
+		wptr		: in  unsigned (addr_width-1 downto 0);
+		din			: in  unsigned (data_width-1 downto 0);
+		rptr_a		: in  unsigned (addr_width-1 downto 0);
+		rptr_b		: in  unsigned (addr_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end reg_dual;
+
+architecture Behavioral of reg_dual is
+
+	constant depth : integer := 2**addr_width;
+	type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+
+	function mem_clear(depth : natural) return mem_t is
+	variable result : mem_t;
+	begin
+		for i in 0 to depth-1 loop
+			result(i) := (others => '0');
+		end loop;
+		return result;
+	end mem_clear;
+	
+	signal reg_mem : mem_t := mem_clear(depth);
+	
+begin
+
+reg_in:
+	process(clk_w)
+	begin
+		if rising_edge(clk_w) then
+			if we = '1' and en = '1' then
+				reg_mem(to_integer(wptr)) <= din;
+			end if;
+		end if;	
+	end process;
+
+	dout_a <= reg_mem(to_integer(rptr_a)) after 2 ns;
+	dout_b <= reg_mem(to_integer(rptr_b)) after 2 ns;
+
+end Behavioral;
+
diff --git a/lib/CPUs/MIPS/src/core/mips_shifter.vhd b/lib/CPUs/MIPS/src/core/mips_shifter.vhd
new file mode 100644
index 0000000..cff2c7d
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/mips_shifter.vhd
@@ -0,0 +1,114 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The shifter unit
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.mips_types.all;
+
+entity shifter is
+	Generic 
+	(
+		data_width : integer := 8
+	);
+	Port
+	(
+		shift_ctrl	: in  shift_ctrl_t;
+		din			: in  unsigned (data_width-1 downto 0);
+		dout		: out unsigned (data_width-1 downto 0)
+	);
+end shifter;
+
+architecture Behavioral of shifter is
+
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to 5) of word_t;
+
+	signal rot_data			: word_array_t;
+	signal sa_rnd			: unsigned (4 downto 0);
+	signal fill	: std_logic;
+	
+--------------------------------------------------------------------------
+function rot_stage(x : unsigned; en : std_logic; stage_num : natural) return unsigned is
+	variable result : unsigned(x'range);
+	constant sa : natural := 2**stage_num;
+	begin
+	if en = '1' then
+		result := x(sa-1 downto 0) & x(x'left downto sa);
+	else
+		result := x;
+	end if;	
+	return result;
+	
+end rot_stage;
+
+function rot_fill(x : unsigned; fill : std_logic; shift_right : std_logic; sa : natural) return unsigned is
+	variable result : unsigned(x'range) := (others => '0');
+	variable j : integer;
+	begin
+		
+	if shift_right = '0' then
+		for i in 0 to x'left loop
+			if i >= sa then
+				result(i) := x(i);
+			else
+				result(i) := fill;
+			end if;	
+		end loop;
+	else	
+		j := x'left;
+		for i in 0 to x'left loop
+			if i < sa then
+				result(j) := fill;
+			else
+				result(j) := x(j);
+			end if;	
+			j := j - 1;
+		end loop;
+	end if;	
+	return result;
+	
+end rot_fill;
+
+--------------------------------------------------------------------------
+begin
+
+	rot_data(0)	<= din;
+
+gen_rotate_right:
+	for stage in 0 to 4 generate
+	begin
+		rot_data(stage+1) <= rot_stage(rot_data(stage), sa_rnd(stage), stage);
+	end generate;
+	
+	sa_rnd	<= shift_ctrl.shamt_rnd;
+	fill	<= shift_ctrl.shift_arith and din(data_width-1);
+	dout	<= rot_fill(rot_data(5), fill, shift_ctrl.shift_right, to_integer(shift_ctrl.shamt_nrm)) after 5 ns;
+--	dout	<= rot_data(5);
+	
+	
+
+--------------------------------------------------------------------------
+end Behavioral;
+
diff --git a/lib/CPUs/MIPS/src/core/mips_top.vhd b/lib/CPUs/MIPS/src/core/mips_top.vhd
new file mode 100644
index 0000000..3d25c3e
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/mips_top.vhd
@@ -0,0 +1,164 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: JIPS top file 
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+
+entity mips_top is
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		int			: in  unsigned (5 downto 0);
+		mem_valid	: in  STD_LOGIC;
+		mem_rdy		: in  STD_LOGIC;
+		mem_en		: out STD_LOGIC;
+		mem_re		: out STD_LOGIC;
+		mem_we		: out unsigned(3 downto 0);
+		mem_din		: in  unsigned (WORD_WIDTH-1 downto 0);
+		mem_dout	: out unsigned (WORD_WIDTH-1 downto 0);
+		mem_addr	: out unsigned (WORD_WIDTH-1 downto 0)
+	);
+	
+end mips_top;
+
+architecture rtl of mips_top is
+
+	COMPONENT pipeline is
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		halt		: in  STD_LOGIC;
+		int			: in  unsigned (5 downto 0);
+		imem_rdy	: in  STD_LOGIC;
+		imem_en		: out STD_LOGIC;
+		imem_addr	: out word_t;
+		imem_data	: in  word_t;
+		dmem_rdy	: in  STD_LOGIC;
+		dmem_en		: out STD_LOGIC;
+		dmem_re		: out STD_LOGIC;
+		dmem_we		: out unsigned(3 downto 0);
+		dmem_addr	: out word_t;
+		dmem_din	: in  word_t;
+		dmem_dout	: out word_t
+	);
+	END COMPONENT;
+	signal halt				: std_logic;
+	signal imem_rdy			: std_logic;
+	signal imem_en			: std_logic;
+	signal imem_addr		: word_t;
+	signal imem_din			: word_t;
+	signal dmem_rdy			: std_logic;
+	signal dmem_en			: std_logic;
+	signal dmem_re			: std_logic;
+	signal dmem_addr		: word_t;
+	signal dmem_dout		: word_t;
+	signal dmem_din			: word_t;
+	signal dmem_we			: unsigned(3 downto 0);
+
+	COMPONENT bui
+	Port
+	(
+		rst				: in  STD_LOGIC;
+		clk				: in  STD_LOGIC;
+		ce				: in  STD_LOGIC;
+		cpu_wait		: out STD_LOGIC;
+		cpu_imem_rdy	: out STD_LOGIC;
+		cpu_imem_en		: in  STD_LOGIC;
+		cpu_imem_addr	: in  word_t;
+		cpu_imem_din	: out word_t;
+		cpu_dmem_rdy	: out STD_LOGIC;
+		cpu_dmem_en		: in  STD_LOGIC;
+		cpu_dmem_re		: in  STD_LOGIC;
+		cpu_dmem_we		: in  unsigned(3 downto 0);
+		cpu_dmem_addr	: in  word_t;
+		cpu_dmem_din	: out word_t;
+		cpu_dmem_dout	: in  word_t;
+		mem_valid		: in  STD_LOGIC;
+		mem_rdy			: in  STD_LOGIC;
+		mem_addr		: out word_t;
+		mem_din			: in  word_t;
+		mem_dout		: out word_t;
+		mem_re			: out STD_LOGIC;
+		mem_we			: out unsigned(3 downto 0);
+		mem_ce			: out STD_LOGIC
+	);
+	END COMPONENT;
+
+begin
+
+-------------------------------------------------------------------
+	
+inst_pipeline: pipeline
+	PORT MAP
+	(
+		rst			=> rst,
+		clk			=> clk,
+		halt		=> halt,
+		int			=> int,
+		imem_rdy	=> imem_rdy,
+		imem_en		=> imem_en,
+		imem_addr	=> imem_addr,
+		imem_data	=> imem_din,
+		dmem_rdy	=> dmem_rdy,
+		dmem_en		=> dmem_en,
+		dmem_re		=> dmem_re,
+		dmem_we		=> dmem_we,
+		dmem_addr	=> dmem_addr,
+		dmem_din	=> dmem_din,
+		dmem_dout	=> dmem_dout
+	);
+
+inst_bui: bui
+	PORT MAP
+	(
+		rst				=> rst,
+		clk				=> clk,
+		ce				=> '1',
+		cpu_wait		=> halt,
+		cpu_imem_rdy	=> imem_rdy,
+		cpu_imem_en		=> imem_en,
+		cpu_imem_addr	=> imem_addr,
+		cpu_imem_din	=> imem_din,
+		cpu_dmem_rdy	=> dmem_rdy,
+		cpu_dmem_en		=> dmem_en,
+		cpu_dmem_re		=> dmem_re,
+		cpu_dmem_we		=> dmem_we,
+		cpu_dmem_addr	=> dmem_addr,
+		cpu_dmem_din	=> dmem_din,
+		cpu_dmem_dout	=> dmem_dout,
+		mem_valid		=> mem_valid,
+		mem_rdy			=> mem_rdy,
+		mem_addr		=> mem_addr,
+		mem_din			=> mem_din,
+		mem_dout		=> mem_dout,
+		mem_re			=> mem_re,
+		mem_we			=> mem_we,
+		mem_ce			=> mem_en
+	);
+
+end rtl;
diff --git a/lib/CPUs/MIPS/src/core/mips_types.vhd b/lib/CPUs/MIPS/src/core/mips_types.vhd
new file mode 100644
index 0000000..0dec8a1
--- /dev/null
+++ b/lib/CPUs/MIPS/src/core/mips_types.vhd
@@ -0,0 +1,620 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: Types, constants and functions for JIPS
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+
+--------------------------------------------------------------------------
+package mips_types is
+
+	-- Revision of the CPU
+	constant REVISION : integer := 1;
+	constant WORD_WIDTH : integer := 32;
+	
+	--Types
+	subtype instr_name_t is string(1 to 12);
+	type instr_name_array_t is array (0 to 63) of instr_name_t;
+	subtype opcode_t is unsigned (5 downto 0);
+	subtype word_t is unsigned (WORD_WIDTH-1 downto 0);
+	subtype reg_ptr_t is unsigned (4 downto 0);
+	subtype shamt_t is unsigned(4 downto 0);
+	subtype sa_t is natural range 0 to 63;
+	subtype func_t is unsigned(5 downto 0);
+
+	type opclass_t is (special, regimm, opcode);
+	
+	type op_t is
+	(
+		nop,
+		op_sll,
+		op_srl,
+		op_sra,
+		op_sllv,
+		op_srlv,
+		op_srav,
+		op_jr,
+		op_jalr,
+		op_syscall,
+		op_break,
+		op_mfhi,
+		op_mthi,
+		op_mflo,
+		op_mtlo,
+		op_mult,
+		op_multu,
+		op_div,
+		op_divu,
+		op_add,
+		op_addu,
+		op_sub,
+		op_subu,
+		op_and,
+		op_or,
+		op_xor,
+		op_nor,
+		op_slt,
+		op_sltu,
+		op_bltz,
+		op_bgez,
+		op_bltzal,
+		op_bgezal,
+		op_j,
+		op_jal,
+		op_beq,
+		op_bne,
+		op_blez,
+		op_bgtz,
+		op_addi,
+		op_addiu,
+		op_slti,
+		op_sltiu,
+		op_andi,
+		op_ori,
+		op_xori,
+		op_lui,
+		op_lb,
+		op_lh,
+		op_lwl,
+		op_lw,
+		op_lbu,
+		op_lhu,
+		op_lwr,
+		op_sb,
+		op_sh,
+		op_swl,
+		op_sw,
+		op_swr,
+		op_cop0,
+		op_cop1,
+		op_cop2,
+		op_cop3,
+		op_lwc1,
+		op_lwc2,
+		op_lwc3,
+		op_swc1,
+		op_swc2,
+		op_swc3
+	);
+	
+	attribute ENUM_ENCODING : string;
+	
+	type imm_src_t is (src_imm32, src_imm16, src_imm16_high);
+	type sa_src_t is (sa_src_reg, sa_src_imm);
+	type alu_src1_t is (alu_src_reg);
+	type alu_src2_t is (alu_src_reg, alu_src_imm);
+	type bc_src_t is (bc_eq_ne, bc_lez_gtz, bc_ltz_gez);
+	type shift_opsel_t is (shift_sll, shift_srl, shift_sra);
+	type wptr_src_t is (wptr_src_imm, wptr_src_const);
+	
+--	attribute ENUM_ENCODING of itype_t: type is "ONE-HOT";
+
+	type pc_t is record	
+		curr			: word_t;
+		last			: word_t;
+		nxt				: word_t;
+		pc_branch		: word_t;
+		is_branch		: boolean;
+	end record;
+	
+	type alu_outsel_t is
+	(
+		alu_adder,
+		alu_shift2,
+		alu_and,
+		alu_or,
+		alu_xor,
+		alu_nor,
+		alu_ltu,
+		alu_lts
+	);
+
+	type alu_flags_t is record
+		c				: STD_LOGIC;
+		uvf				: STD_LOGIC;
+		ovf				: STD_LOGIC;
+		ltu				: STD_LOGIC;
+		lts				: STD_LOGIC;
+	end record;
+		
+	type bcu_flags_t is record
+		z				: STD_LOGIC;
+		eq				: STD_LOGIC;
+		ltz				: STD_LOGIC;
+	end record;
+
+	type event_t is record
+		Int				: unsigned(5 downto 0);
+		data_load_err	: STD_LOGIC;
+		data_store_err	: STD_LOGIC;
+		inst_load_err	: STD_LOGIC;
+		inst_priv_addr	: STD_LOGIC;
+		alu_ovf			: STD_LOGIC;
+		alu_uvf			: STD_LOGIC;
+		syscall			: STD_LOGIC;
+		break			: STD_LOGIC;
+		illegal			: STD_LOGIC;
+	end record;
+	
+	type exc_flags_t is record
+		Int				: STD_LOGIC;
+		DAdEL			: STD_LOGIC;
+		DAdES			: STD_LOGIC;
+		IAdEL			: STD_LOGIC;
+		IAdEK			: STD_LOGIC;
+		Ov				: STD_LOGIC;
+		Sys				: STD_LOGIC;
+		Bp				: STD_LOGIC;
+		RI				: STD_LOGIC;
+		IBE				: STD_LOGIC;
+		DBE				: STD_LOGIC;
+	end record;
+
+	type except_t is record
+		act				: STD_LOGIC;
+		epc				: word_t;
+		cause			: word_t;
+	end record;
+	
+	type cop_ctrl_in_t is record
+		bd_wb			: STD_LOGIC;
+		epc_mem			: word_t;
+		epc_wb			: word_t;
+		imem_addr		: word_t;
+		dmem_addr		: word_t;
+		exc_left		: STD_LOGIC;
+	end record;
+
+	type cop_ctrl_out_t is record
+		RE				: STD_LOGIC;
+		ee				: STD_LOGIC;
+		ec				: STD_LOGIC;
+		exc_commit		: STD_LOGIC;
+		exc_pending		: STD_LOGIC;
+		exc_exit		: STD_LOGIC;
+		reg_write		: STD_LOGIC;
+		cop_read		: STD_LOGIC;
+		user_mode		: STD_LOGIC;
+		int				: STD_LOGIC;
+		exc_vec			: word_t;
+	end record;
+	
+	type sdu_t is record
+		ID_nop			: STD_LOGIC;
+		EX_nop			: STD_LOGIC;
+		MEM_nop			: STD_LOGIC;
+		WB_nop			: STD_LOGIC;
+		ID_stall		: STD_LOGIC;
+		EX_stall		: STD_LOGIC;
+		MEM_stall		: STD_LOGIC;
+		WB_stall		: STD_LOGIC;
+	end record;
+
+	type hdu_t is record
+		alu_fwd_a_ex	: boolean;
+		alu_fwd_a_mem	: boolean;
+		alu_fwd_a_wb	: boolean;
+		alu_fwd_b_ex	: boolean;
+		alu_fwd_b_mem	: boolean;
+		alu_fwd_b_wb	: boolean;
+	end record;
+
+	type alu_ctrl_t is record
+		outsel			: alu_outsel_t;
+		add				: STD_LOGIC;
+		shift_right		: STD_LOGIC;
+		shift_arith		: STD_LOGIC;
+		op1_src			: alu_src1_t;
+		op2_src			: alu_src2_t;
+	end record;
+	
+	type shift_ctrl_t is record
+		shamt_nrm		: shamt_t;
+		shamt_rnd		: shamt_t;
+		shift_right		: STD_LOGIC;
+		shift_arith		: STD_LOGIC;
+	end record;
+
+	type ctrl_lines_t is record
+		branch			: STD_LOGIC;
+		jump_long		: STD_LOGIC;
+		jump			: STD_LOGIC;
+		bc_not			: STD_LOGIC;
+		bc_src			: bc_src_t;
+		imm_src			: imm_src_t;
+		alu				: alu_ctrl_t;
+		reg_write		: STD_LOGIC;
+		reg_link		: STD_LOGIC;
+		dmem_we			: STD_LOGIC;
+		dmem_en			: STD_LOGIC;
+		shamt2_srcsel	: sa_src_t;
+		wptr_srcsel		: wptr_src_t;
+		cop_instr_en	: STD_LOGIC;
+		shift_offset	: unsigned(1 downto 0);
+		shift_byp		: STD_LOGIC;
+		byte_en_byp		: STD_LOGIC;
+		sign_ext_byp	: STD_LOGIC;
+		word4_en		: STD_LOGIC;
+		word2_en		: STD_LOGIC;
+		align_left		: STD_LOGIC;
+		load_signed		: STD_LOGIC;
+		mul_access		: STD_LOGIC;
+		mul_hilo_we		: STD_LOGIC;
+		mul_mul_divn	: STD_LOGIC;
+		mul_start		: STD_LOGIC;
+		mul_s_un		: STD_LOGIC;
+		mul_hilo_sel	: STD_LOGIC;
+		exc_break		: STD_LOGIC;
+		exc_syscall		: STD_LOGIC;
+		exc_illegal		: STD_LOGIC;
+		except_en		: STD_LOGIC;
+		alu_exc_en		: STD_LOGIC;
+	end record;
+
+	type ID_t is record
+		nop			: STD_LOGIC;
+		exc			: std_logic;
+		IR			: word_t;
+		op			: op_t;
+		pcn			: word_t;
+		epc			: word_t;
+		jimm32		: word_t;
+		bimm18		: word_t;
+		imm			: word_t;
+		shamt		: shamt_t;
+		ctrl		: ctrl_lines_t;
+		reg_write	: STD_LOGIC;
+		reg_a_rptr	: reg_ptr_t;
+		reg_b_rptr	: reg_ptr_t;
+		reg_a		: word_t;
+		reg_b		: word_t;
+		events		: event_t;
+	end record;
+	
+	type EX_t is record
+		nop			: STD_LOGIC;
+		exc			: std_logic;
+		IR			: word_t;
+		op			: op_t;
+		pcn			: word_t;
+		epc			: word_t;
+		reg_a		: word_t;
+		reg_b		: word_t;
+		ctrl		: ctrl_lines_t;
+		shift_ctrl	: shift_ctrl_t;
+		alu_op1		: word_t;
+		alu_op2		: word_t;
+		alu_op2_s	: word_t;
+		alu_flags	: alu_flags_t;
+		result		: word_t;
+		reg_write	: STD_LOGIC;
+		wreg_we		: STD_LOGIC;
+		reg_wptr	: reg_ptr_t;
+		reg_a_rptr	: reg_ptr_t;
+		reg_b_rptr	: reg_ptr_t;
+		va			: word_t;
+		pa_off		: unsigned(1 downto 0);
+		events_in	: event_t;
+		events		: event_t;
+	end record;
+	
+	type MEM_t is record
+		nop			: STD_LOGIC;
+		exc			: std_logic;
+		op			: op_t;
+		pcn			: word_t;
+		epc			: word_t;
+		ctrl		: ctrl_lines_t;
+		ex_result	: word_t;
+		reg_wptr	: reg_ptr_t;
+		wreg_we		: STD_LOGIC;
+		data		: word_t;
+		va			: word_t;
+		pa_off		: unsigned(1 downto 0);
+		events_in	: event_t;
+		events		: event_t;
+	end record;
+	
+	type WB_t is record
+		nop			: STD_LOGIC;
+		op			: op_t;
+		epc			: word_t;
+		reg_wptr	: reg_ptr_t;
+		wreg_we		: STD_LOGIC;
+		data		: word_t;
+		bd			: STD_LOGIC;
+	end record;
+
+	
+	type rom_special_t is array (0 to 2**func_t'length-1) of ctrl_lines_t;
+	type rom_regimm_t is array (0 to 2**reg_ptr_t'length-1) of ctrl_lines_t;
+	type rom_opcode_t is array (0 to 2**opcode_t'length-1) of ctrl_lines_t;
+
+	function store_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t;
+	function store_be(va : unsigned(1 downto 0); be_src, word2_en, word4_en, align_left, bypass : std_logic) return unsigned;
+	function load_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t;
+	function load_be(va : unsigned(1 downto 0); align_left, bypass : std_logic) return unsigned;
+	function load_sign_ext(x : word_t; bypass, signed, word2_en, word4_en : std_logic) return word_t;
+	function events_clr return event_t;
+	function event_is_active(e : event_t) return std_logic;
+	function "or" (a, b : event_t) return event_t;
+
+end mips_types;
+
+--------------------------------------------------------------------------
+package body mips_types is
+
+	function store_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t is
+	variable stage1 : word_t;
+	variable result : word_t;
+	variable sa : unsigned(1 downto 0);
+	begin
+		
+		if bypass = '1'	then
+			sa := "00";
+		else
+			sa := va + shift_off;
+		end if;
+		
+		stage1 := x;
+		if sa(0) = '1' then
+			stage1 := x(23 downto 0) & x(31 downto 24);
+		end if;
+		result := stage1;
+		if sa(1) = '1' then
+			result := stage1(15 downto 0) & stage1(31 downto 16);
+		end if;
+		
+		return result;
+	end store_shift;
+	
+--------------------------------------------------------------------------
+	function store_be(va : unsigned(1 downto 0); be_src, word2_en, word4_en, align_left, bypass : std_logic) return unsigned is
+	variable result : unsigned(3 downto 0);
+	begin
+		if bypass = '1' then
+			result := (3 downto 0 => be_src);
+		elsif word2_en = '1' then
+			case va is
+				when "00" | "01" =>
+					result := "00" & be_src & be_src;
+				when "10" | "11" =>
+					result := be_src & be_src & "00";
+				when others =>
+					result := "0000";
+			end case;
+		elsif word4_en = '1' then
+			case va is
+				when "00" =>
+					result := "000" & be_src;
+				when "01" =>
+					result := "00" & be_src & '0';
+				when "10" =>
+					result := '0' & be_src & "00";
+				when "11" =>
+					result := be_src & "000";
+				when others =>
+					result := "0000";
+			end case;
+		elsif align_left = '1' then
+			case va is
+				when "00" =>
+					result := be_src & be_src & be_src & be_src;
+				when "01" =>
+					result := be_src & be_src & be_src & '0';
+				when "10" =>
+					result := be_src & be_src & "00";
+				when "11" =>
+					result := be_src & "000";
+				when others =>
+					result := "0000";
+			end case;
+		else
+			case va is
+				when "00" =>
+					result := "000" & be_src;
+				when "01" =>
+					result := "00" & be_src & be_src;
+				when "10" =>
+					result := '0' & be_src & be_src & be_src;
+				when "11" =>
+					result := be_src & be_src & be_src & be_src;
+				when others =>
+					result := "0000";
+			end case;
+		end if;
+		
+		return result;
+	
+	end store_be;
+	
+--------------------------------------------------------------------------
+	function load_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t is
+	variable stage1 : word_t;
+	variable result : word_t;
+	variable sa : unsigned(1 downto 0);
+	
+	begin
+		if bypass = '1' then
+			sa 		:= "00";
+		else
+			sa		:= va + shift_off;
+		end if;
+		
+		stage1 := x;
+		if sa(0) = '1' then
+			stage1 :=  x(7 downto 0) & x(31 downto 8);
+		end if;
+		result := stage1;
+		if sa(1) = '1' then
+			result := stage1(15 downto 0) & stage1(31 downto 16);
+		end if;
+		
+		return result;
+	end load_shift;
+	
+--------------------------------------------------------------------------
+	function load_be(va : unsigned(1 downto 0); align_left, bypass : std_logic) return unsigned is
+	variable result : unsigned(3 downto 0);
+	begin
+		if bypass = '1' then
+			result := (3 downto 0 => '1');
+		elsif align_left = '1' then
+			case va is
+				when "00" =>
+					result := "1000";
+				when "01" =>
+					result := "1100";
+				when "10" =>
+					result := "1110";
+				when "11" =>
+					result := "1111";
+				when others =>
+					result := "0000";
+			end case;
+		else
+			case va is
+				when "00" =>
+					result := "1111";
+				when "01" =>
+					result := "0111";
+				when "10" =>
+					result := "0011";
+				when "11" =>
+					result := "0001";
+				when others =>
+					result := "0000";
+			end case;
+		end if;
+		
+		return result;
+	
+	end load_be;
+	
+--------------------------------------------------------------------------
+	function load_sign_ext(x : word_t; bypass, signed, word2_en, word4_en : std_logic) return word_t is
+	variable result : word_t;
+	variable sign : std_logic;
+	
+	begin
+		if bypass = '1' then
+			result := x;
+		elsif word2_en = '1' then
+			sign	:= signed and x(15);
+			result := (31 downto 16 => sign) & x(15 downto 0);
+		else
+			sign	:= signed and x(7);
+			result := (31 downto 8 => sign) & x(7 downto 0);
+		end if;
+		
+		return result;
+	end load_sign_ext;
+	
+--------------------------------------------------------------------------
+	function events_clr return event_t is
+	variable result : event_t;
+	begin
+		result.Int				:= (others => '0');
+		result.data_load_err	:= '0';
+		result.data_store_err	:= '0';
+		result.inst_load_err	:= '0';
+		result.inst_priv_addr	:= '0';
+		result.alu_ovf			:= '0';
+		result.alu_uvf			:= '0';
+		result.syscall			:= '0';
+		result.break			:= '0';
+		result.illegal			:= '0';
+		
+		return result;
+		
+	end events_clr;
+
+	function event_is_active(e : event_t) return std_logic is
+	variable result : std_logic;
+	begin
+		result := '0';
+		
+		for i in e.Int'range loop
+			result := result or e.Int(i);
+		end loop;
+
+		result	:= result or e.data_load_err;
+		result	:= result or e.data_store_err;
+		result	:= result or e.inst_load_err;
+		result	:= result or e.inst_priv_addr;
+		result	:= result or e.alu_ovf;
+		result	:= result or e.alu_uvf;
+		result	:= result or e.syscall;
+		result	:= result or e.break;
+		result	:= result or e.illegal;
+
+		return result;
+		
+	end event_is_active;
+
+	function "or" (a, b : event_t) return event_t is
+	variable result : event_t;
+	begin
+		for i in a.Int'range loop
+			result.Int(i) := a.Int(i) or b.Int(i);
+		end loop;
+		result.data_load_err	:= a.data_load_err or b.data_load_err;
+		result.data_store_err	:= a.data_store_err or b.data_store_err;
+		result.inst_load_err	:= a.inst_load_err or b.inst_load_err;
+		result.inst_priv_addr	:= a.inst_priv_addr or b.inst_priv_addr;
+		result.alu_ovf			:= a.alu_ovf or b.alu_ovf;
+		result.alu_uvf			:= a.alu_uvf or b.alu_uvf;
+		result.syscall			:= a.syscall or b.syscall;
+		result.break			:= a.break or b.break;
+		result.illegal			:= a.illegal or b.illegal;
+		
+		return result;
+		
+	end "or";
+
+--------------------------------------------------------------------------
+end mips_types;
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
diff --git a/lib/CPUs/MIPS/src/fibonacci.ROM_ld.vhd b/lib/CPUs/MIPS/src/fibonacci.ROM_ld.vhd
new file mode 100644
index 0000000..759ad2a
--- /dev/null
+++ b/lib/CPUs/MIPS/src/fibonacci.ROM_ld.vhd
@@ -0,0 +1,2174 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+ENTITY rom IS
+	Port
+	(
+		clk		: in  STD_LOGIC;
+		ce		: in  STD_LOGIC;
+		addr		: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+END rom;
+
+ARCHITECTURE data OF rom IS
+
+	subtype word_t is unsigned(31 downto 0);
+	type word_array_t is array (0 to 2047) of word_t;
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: unsigned (15 downto 0);
+	signal jtag_ld_dout		: unsigned (31 downto 0);
+	signal jtag_ld_din		: unsigned (31 downto 0);
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (47 downto 0);
+
+	signal word_array : word_array_t :=
+	(
+
+		X"401A6000", -- 00000000
+		X"3C1B0040", -- 00000004
+		X"035BD024", -- 00000008
+		X"375A000C", -- 0000000C
+		X"409A6000", -- 00000010
+		X"401A7800", -- 00000014
+		X"00000000", -- 00000018
+		X"409AF800", -- 0000001C
+		X"3C1D7FFF", -- 00000020
+		X"37BDEFFC", -- 00000024
+		X"3C1A0040", -- 00000028
+		X"275A02E4", -- 0000002C
+		X"0340F809", -- 00000030
+		X"42000010", -- 00000034
+		X"00000000", -- 00000038
+		X"00000000", -- 0000003C
+		X"00000000", -- 00000040
+		X"00000000", -- 00000044
+		X"00000000", -- 00000048
+		X"00000000", -- 0000004C
+		X"00000000", -- 00000050
+		X"00000000", -- 00000054
+		X"00000000", -- 00000058
+		X"00000000", -- 0000005C
+		X"00000000", -- 00000060
+		X"00000000", -- 00000064
+		X"00000000", -- 00000068
+		X"00000000", -- 0000006C
+		X"00000000", -- 00000070
+		X"00000000", -- 00000074
+		X"00000000", -- 00000078
+		X"00000000", -- 0000007C
+		X"00000000", -- 00000080
+		X"00000000", -- 00000084
+		X"00000000", -- 00000088
+		X"00000000", -- 0000008C
+		X"00000000", -- 00000090
+		X"00000000", -- 00000094
+		X"00000000", -- 00000098
+		X"00000000", -- 0000009C
+		X"00000000", -- 000000A0
+		X"00000000", -- 000000A4
+		X"00000000", -- 000000A8
+		X"00000000", -- 000000AC
+		X"00000000", -- 000000B0
+		X"00000000", -- 000000B4
+		X"00000000", -- 000000B8
+		X"00000000", -- 000000BC
+		X"00000000", -- 000000C0
+		X"00000000", -- 000000C4
+		X"00000000", -- 000000C8
+		X"00000000", -- 000000CC
+		X"00000000", -- 000000D0
+		X"00000000", -- 000000D4
+		X"00000000", -- 000000D8
+		X"00000000", -- 000000DC
+		X"00000000", -- 000000E0
+		X"00000000", -- 000000E4
+		X"00000000", -- 000000E8
+		X"00000000", -- 000000EC
+		X"00000000", -- 000000F0
+		X"00000000", -- 000000F4
+		X"00000000", -- 000000F8
+		X"00000000", -- 000000FC
+		X"00000000", -- 00000100
+		X"00000000", -- 00000104
+		X"00000000", -- 00000108
+		X"00000000", -- 0000010C
+		X"00000000", -- 00000110
+		X"00000000", -- 00000114
+		X"00000000", -- 00000118
+		X"00000000", -- 0000011C
+		X"00000000", -- 00000120
+		X"00000000", -- 00000124
+		X"00000000", -- 00000128
+		X"00000000", -- 0000012C
+		X"00000000", -- 00000130
+		X"00000000", -- 00000134
+		X"00000000", -- 00000138
+		X"00000000", -- 0000013C
+		X"00000000", -- 00000140
+		X"00000000", -- 00000144
+		X"00000000", -- 00000148
+		X"00000000", -- 0000014C
+		X"00000000", -- 00000150
+		X"00000000", -- 00000154
+		X"00000000", -- 00000158
+		X"00000000", -- 0000015C
+		X"00000000", -- 00000160
+		X"00000000", -- 00000164
+		X"00000000", -- 00000168
+		X"00000000", -- 0000016C
+		X"00000000", -- 00000170
+		X"00000000", -- 00000174
+		X"00000000", -- 00000178
+		X"00000000", -- 0000017C
+		X"401A6800", -- 00000180
+		X"3C1B8000", -- 00000184
+		X"001AD082", -- 00000188
+		X"335A000F", -- 0000018C
+		X"035BD025", -- 00000190
+		X"AF7A0000", -- 00000194
+		X"401A7000", -- 00000198
+		X"00000000", -- 0000019C
+		X"03400008", -- 000001A0
+		X"42000010", -- 000001A4
+		X"24080002", -- 000001A8
+		X"0107102A", -- 000001AC
+		X"ACC40000", -- 000001B0
+		X"1040000B", -- 000001B4
+		X"ACC50004", -- 000001B8
+		X"24C60008", -- 000001BC
+		X"24E8FFFE", -- 000001C0
+		X"8CC2FFF8", -- 000001C4
+		X"8CC3FFFC", -- 000001C8
+		X"2508FFFF", -- 000001CC
+		X"00431021", -- 000001D0
+		X"ACC20000", -- 000001D4
+		X"1500FFFA", -- 000001D8
+		X"24C60004", -- 000001DC
+		X"00E04021", -- 000001E0
+		X"03E00008", -- 000001E4
+		X"01001021", -- 000001E8
+		X"94820002", -- 000001EC
+		X"A0800000", -- 000001F0
+		X"2442FFFF", -- 000001F4
+		X"00021C00", -- 000001F8
+		X"A4820002", -- 000001FC
+		X"00031C03", -- 00000200
+		X"2402FFFF", -- 00000204
+		X"8C850004", -- 00000208
+		X"1062000F", -- 0000020C
+		X"00000000", -- 00000210
+		X"2406FFFF", -- 00000214
+		X"90A30000", -- 00000218
+		X"90820000", -- 0000021C
+		X"00000000", -- 00000220
+		X"00431021", -- 00000224
+		X"A0820000", -- 00000228
+		X"A0A20000", -- 0000022C
+		X"94830002", -- 00000230
+		X"24A50001", -- 00000234
+		X"2463FFFF", -- 00000238
+		X"00031400", -- 0000023C
+		X"00021403", -- 00000240
+		X"1446FFF4", -- 00000244
+		X"A4830002", -- 00000248
+		X"80820002", -- 0000024C
+		X"03E00008", -- 00000250
+		X"00000000", -- 00000254
+		X"3C028000", -- 00000258
+		X"00042600", -- 0000025C
+		X"00042603", -- 00000260
+		X"34450004", -- 00000264
+		X"34430008", -- 00000268
+		X"90620000", -- 0000026C
+		X"00000000", -- 00000270
+		X"00021042", -- 00000274
+		X"30420001", -- 00000278
+		X"1440FFFB", -- 0000027C
+		X"00000000", -- 00000280
+		X"03E00008", -- 00000284
+		X"A0A40000", -- 00000288
+		X"27BDFFE0", -- 0000028C
+		X"AFB10014", -- 00000290
+		X"AFB00010", -- 00000294
+		X"AFBF0018", -- 00000298
+		X"80820000", -- 0000029C
+		X"00808821", -- 000002A0
+		X"1040000A", -- 000002A4
+		X"00008021", -- 000002A8
+		X"00801821", -- 000002AC
+		X"80640000", -- 000002B0
+		X"0C100096", -- 000002B4
+		X"26100001", -- 000002B8
+		X"02301821", -- 000002BC
+		X"80620000", -- 000002C0
+		X"00000000", -- 000002C4
+		X"1440FFF9", -- 000002C8
+		X"00000000", -- 000002CC
+		X"8FBF0018", -- 000002D0
+		X"8FB10014", -- 000002D4
+		X"8FB00010", -- 000002D8
+		X"03E00008", -- 000002DC
+		X"27BD0020", -- 000002E0
+		X"27BDF020", -- 000002E4
+		X"3C02AAAA", -- 000002E8
+		X"24040041", -- 000002EC
+		X"AFBF0FDC", -- 000002F0
+		X"AFBE0FD8", -- 000002F4
+		X"AFB70FD4", -- 000002F8
+		X"AFB60FD0", -- 000002FC
+		X"AFB50FCC", -- 00000300
+		X"AFB40FC8", -- 00000304
+		X"AFB30FC4", -- 00000308
+		X"AFB00FB8", -- 0000030C
+		X"AFB20FC0", -- 00000310
+		X"3450AAAA", -- 00000314
+		X"0C100096", -- 00000318
+		X"AFB10FBC", -- 0000031C
+		X"0C100096", -- 00000320
+		X"24040020", -- 00000324
+		X"0C100096", -- 00000328
+		X"24040041", -- 0000032C
+		X"0C100096", -- 00000330
+		X"24040020", -- 00000334
+		X"0C100096", -- 00000338
+		X"24040041", -- 0000033C
+		X"0C100096", -- 00000340
+		X"24040020", -- 00000344
+		X"0C100096", -- 00000348
+		X"24040041", -- 0000034C
+		X"0C100096", -- 00000350
+		X"24040020", -- 00000354
+		X"0C100096", -- 00000358
+		X"24040030", -- 0000035C
+		X"0C100096", -- 00000360
+		X"24040031", -- 00000364
+		X"0C100096", -- 00000368
+		X"24040032", -- 0000036C
+		X"0C100096", -- 00000370
+		X"24040033", -- 00000374
+		X"0C100096", -- 00000378
+		X"24040034", -- 0000037C
+		X"0C100096", -- 00000380
+		X"24040035", -- 00000384
+		X"0C100096", -- 00000388
+		X"24040036", -- 0000038C
+		X"0C100096", -- 00000390
+		X"24040037", -- 00000394
+		X"0C100096", -- 00000398
+		X"24040038", -- 0000039C
+		X"0C100096", -- 000003A0
+		X"24040039", -- 000003A4
+		X"0C100096", -- 000003A8
+		X"24040041", -- 000003AC
+		X"0C100096", -- 000003B0
+		X"24040042", -- 000003B4
+		X"0C100096", -- 000003B8
+		X"24040043", -- 000003BC
+		X"0C100096", -- 000003C0
+		X"24040044", -- 000003C4
+		X"0C100096", -- 000003C8
+		X"24040045", -- 000003CC
+		X"0C100096", -- 000003D0
+		X"24040046", -- 000003D4
+		X"0C100096", -- 000003D8
+		X"2404000D", -- 000003DC
+		X"0C100096", -- 000003E0
+		X"2404000A", -- 000003E4
+		X"3C148000", -- 000003E8
+		X"00009821", -- 000003EC
+		X"27BE0010", -- 000003F0
+		X"27B70FB0", -- 000003F4
+		X"241503E8", -- 000003F8
+		X"3C164000", -- 000003FC
+		X"00008821", -- 00000400
+		X"00002021", -- 00000404
+		X"03C01021", -- 00000408
+		X"240603E7", -- 0000040C
+		X"24C6FFFF", -- 00000410
+		X"AC500000", -- 00000414
+		X"04C1FFFD", -- 00000418
+		X"24420004", -- 0000041C
+		X"02041026", -- 00000420
+		X"24920001", -- 00000424
+		X"24420001", -- 00000428
+		X"02402821", -- 0000042C
+		X"27A60010", -- 00000430
+		X"240703E8", -- 00000434
+		X"0C10006A", -- 00000438
+		X"00028040", -- 0000043C
+		X"24070002", -- 00000440
+		X"27C50008", -- 00000444
+		X"08100116", -- 00000448
+		X"240603E5", -- 0000044C
+		X"04C0000A", -- 00000450
+		X"00000000", -- 00000454
+		X"8CA20000", -- 00000458
+		X"8CA3FFFC", -- 0000045C
+		X"8CA4FFF8", -- 00000460
+		X"00431023", -- 00000464
+		X"24C6FFFF", -- 00000468
+		X"1482FFF8", -- 0000046C
+		X"24A50004", -- 00000470
+		X"04C1FFF8", -- 00000474
+		X"24E70001", -- 00000478
+		X"10F50013", -- 0000047C
+		X"00000000", -- 00000480
+		X"2A4203E8", -- 00000484
+		X"1440FFDF", -- 00000488
+		X"02402021", -- 0000048C
+		X"12350010", -- 00000490
+		X"00000000", -- 00000494
+		X"02761025", -- 00000498
+		X"AE820000", -- 0000049C
+		X"02E02021", -- 000004A0
+		X"24020FA0", -- 000004A4
+		X"A7A20FB2", -- 000004A8
+		X"A3A00FB0", -- 000004AC
+		X"0C10007B", -- 000004B0
+		X"AFBE0FB4", -- 000004B4
+		X"02028026", -- 000004B8
+		X"26730001", -- 000004BC
+		X"00008821", -- 000004C0
+		X"08100102", -- 000004C4
+		X"00002021", -- 000004C8
+		X"08100121", -- 000004CC
+		X"26310001", -- 000004D0
+		X"08100128", -- 000004D4
+		X"AE930000", -- 000004D8
+		X"00000000", -- 000004DC
+		X"00000000", -- 000004E0
+		X"00000000", -- 000004E4
+		X"00000000", -- 000004E8
+		X"00000000", -- 000004EC
+		X"00000000", -- 000004F0
+		X"00000000", -- 000004F4
+		X"00000000", -- 000004F8
+		X"00000000", -- 000004FC
+		X"00000000", -- 00000500
+		X"00000000", -- 00000504
+		X"00000000", -- 00000508
+		X"00000000", -- 0000050C
+		X"00000000", -- 00000510
+		X"00000000", -- 00000514
+		X"00000000", -- 00000518
+		X"00000000", -- 0000051C
+		X"00000000", -- 00000520
+		X"00000000", -- 00000524
+		X"00000000", -- 00000528
+		X"00000000", -- 0000052C
+		X"00000000", -- 00000530
+		X"00000000", -- 00000534
+		X"00000000", -- 00000538
+		X"00000000", -- 0000053C
+		X"00000000", -- 00000540
+		X"00000000", -- 00000544
+		X"00000000", -- 00000548
+		X"00000000", -- 0000054C
+		X"00000000", -- 00000550
+		X"00000000", -- 00000554
+		X"00000000", -- 00000558
+		X"00000000", -- 0000055C
+		X"00000000", -- 00000560
+		X"00000000", -- 00000564
+		X"00000000", -- 00000568
+		X"00000000", -- 0000056C
+		X"00000000", -- 00000570
+		X"00000000", -- 00000574
+		X"00000000", -- 00000578
+		X"00000000", -- 0000057C
+		X"00000000", -- 00000580
+		X"00000000", -- 00000584
+		X"00000000", -- 00000588
+		X"00000000", -- 0000058C
+		X"00000000", -- 00000590
+		X"00000000", -- 00000594
+		X"00000000", -- 00000598
+		X"00000000", -- 0000059C
+		X"00000000", -- 000005A0
+		X"00000000", -- 000005A4
+		X"00000000", -- 000005A8
+		X"00000000", -- 000005AC
+		X"00000000", -- 000005B0
+		X"00000000", -- 000005B4
+		X"00000000", -- 000005B8
+		X"00000000", -- 000005BC
+		X"00000000", -- 000005C0
+		X"00000000", -- 000005C4
+		X"00000000", -- 000005C8
+		X"00000000", -- 000005CC
+		X"00000000", -- 000005D0
+		X"00000000", -- 000005D4
+		X"00000000", -- 000005D8
+		X"00000000", -- 000005DC
+		X"00000000", -- 000005E0
+		X"00000000", -- 000005E4
+		X"00000000", -- 000005E8
+		X"00000000", -- 000005EC
+		X"00000000", -- 000005F0
+		X"00000000", -- 000005F4
+		X"00000000", -- 000005F8
+		X"00000000", -- 000005FC
+		X"00000000", -- 00000600
+		X"00000000", -- 00000604
+		X"00000000", -- 00000608
+		X"00000000", -- 0000060C
+		X"00000000", -- 00000610
+		X"00000000", -- 00000614
+		X"00000000", -- 00000618
+		X"00000000", -- 0000061C
+		X"00000000", -- 00000620
+		X"00000000", -- 00000624
+		X"00000000", -- 00000628
+		X"00000000", -- 0000062C
+		X"00000000", -- 00000630
+		X"00000000", -- 00000634
+		X"00000000", -- 00000638
+		X"00000000", -- 0000063C
+		X"00000000", -- 00000640
+		X"00000000", -- 00000644
+		X"00000000", -- 00000648
+		X"00000000", -- 0000064C
+		X"00000000", -- 00000650
+		X"00000000", -- 00000654
+		X"00000000", -- 00000658
+		X"00000000", -- 0000065C
+		X"00000000", -- 00000660
+		X"00000000", -- 00000664
+		X"00000000", -- 00000668
+		X"00000000", -- 0000066C
+		X"00000000", -- 00000670
+		X"00000000", -- 00000674
+		X"00000000", -- 00000678
+		X"00000000", -- 0000067C
+		X"00000000", -- 00000680
+		X"00000000", -- 00000684
+		X"00000000", -- 00000688
+		X"00000000", -- 0000068C
+		X"00000000", -- 00000690
+		X"00000000", -- 00000694
+		X"00000000", -- 00000698
+		X"00000000", -- 0000069C
+		X"00000000", -- 000006A0
+		X"00000000", -- 000006A4
+		X"00000000", -- 000006A8
+		X"00000000", -- 000006AC
+		X"00000000", -- 000006B0
+		X"00000000", -- 000006B4
+		X"00000000", -- 000006B8
+		X"00000000", -- 000006BC
+		X"00000000", -- 000006C0
+		X"00000000", -- 000006C4
+		X"00000000", -- 000006C8
+		X"00000000", -- 000006CC
+		X"00000000", -- 000006D0
+		X"00000000", -- 000006D4
+		X"00000000", -- 000006D8
+		X"00000000", -- 000006DC
+		X"00000000", -- 000006E0
+		X"00000000", -- 000006E4
+		X"00000000", -- 000006E8
+		X"00000000", -- 000006EC
+		X"00000000", -- 000006F0
+		X"00000000", -- 000006F4
+		X"00000000", -- 000006F8
+		X"00000000", -- 000006FC
+		X"00000000", -- 00000700
+		X"00000000", -- 00000704
+		X"00000000", -- 00000708
+		X"00000000", -- 0000070C
+		X"00000000", -- 00000710
+		X"00000000", -- 00000714
+		X"00000000", -- 00000718
+		X"00000000", -- 0000071C
+		X"00000000", -- 00000720
+		X"00000000", -- 00000724
+		X"00000000", -- 00000728
+		X"00000000", -- 0000072C
+		X"00000000", -- 00000730
+		X"00000000", -- 00000734
+		X"00000000", -- 00000738
+		X"00000000", -- 0000073C
+		X"00000000", -- 00000740
+		X"00000000", -- 00000744
+		X"00000000", -- 00000748
+		X"00000000", -- 0000074C
+		X"00000000", -- 00000750
+		X"00000000", -- 00000754
+		X"00000000", -- 00000758
+		X"00000000", -- 0000075C
+		X"00000000", -- 00000760
+		X"00000000", -- 00000764
+		X"00000000", -- 00000768
+		X"00000000", -- 0000076C
+		X"00000000", -- 00000770
+		X"00000000", -- 00000774
+		X"00000000", -- 00000778
+		X"00000000", -- 0000077C
+		X"00000000", -- 00000780
+		X"00000000", -- 00000784
+		X"00000000", -- 00000788
+		X"00000000", -- 0000078C
+		X"00000000", -- 00000790
+		X"00000000", -- 00000794
+		X"00000000", -- 00000798
+		X"00000000", -- 0000079C
+		X"00000000", -- 000007A0
+		X"00000000", -- 000007A4
+		X"00000000", -- 000007A8
+		X"00000000", -- 000007AC
+		X"00000000", -- 000007B0
+		X"00000000", -- 000007B4
+		X"00000000", -- 000007B8
+		X"00000000", -- 000007BC
+		X"00000000", -- 000007C0
+		X"00000000", -- 000007C4
+		X"00000000", -- 000007C8
+		X"00000000", -- 000007CC
+		X"00000000", -- 000007D0
+		X"00000000", -- 000007D4
+		X"00000000", -- 000007D8
+		X"00000000", -- 000007DC
+		X"00000000", -- 000007E0
+		X"00000000", -- 000007E4
+		X"00000000", -- 000007E8
+		X"00000000", -- 000007EC
+		X"00000000", -- 000007F0
+		X"00000000", -- 000007F4
+		X"00000000", -- 000007F8
+		X"00000000", -- 000007FC
+		X"00000000", -- 00000800
+		X"00000000", -- 00000804
+		X"00000000", -- 00000808
+		X"00000000", -- 0000080C
+		X"00000000", -- 00000810
+		X"00000000", -- 00000814
+		X"00000000", -- 00000818
+		X"00000000", -- 0000081C
+		X"00000000", -- 00000820
+		X"00000000", -- 00000824
+		X"00000000", -- 00000828
+		X"00000000", -- 0000082C
+		X"00000000", -- 00000830
+		X"00000000", -- 00000834
+		X"00000000", -- 00000838
+		X"00000000", -- 0000083C
+		X"00000000", -- 00000840
+		X"00000000", -- 00000844
+		X"00000000", -- 00000848
+		X"00000000", -- 0000084C
+		X"00000000", -- 00000850
+		X"00000000", -- 00000854
+		X"00000000", -- 00000858
+		X"00000000", -- 0000085C
+		X"00000000", -- 00000860
+		X"00000000", -- 00000864
+		X"00000000", -- 00000868
+		X"00000000", -- 0000086C
+		X"00000000", -- 00000870
+		X"00000000", -- 00000874
+		X"00000000", -- 00000878
+		X"00000000", -- 0000087C
+		X"00000000", -- 00000880
+		X"00000000", -- 00000884
+		X"00000000", -- 00000888
+		X"00000000", -- 0000088C
+		X"00000000", -- 00000890
+		X"00000000", -- 00000894
+		X"00000000", -- 00000898
+		X"00000000", -- 0000089C
+		X"00000000", -- 000008A0
+		X"00000000", -- 000008A4
+		X"00000000", -- 000008A8
+		X"00000000", -- 000008AC
+		X"00000000", -- 000008B0
+		X"00000000", -- 000008B4
+		X"00000000", -- 000008B8
+		X"00000000", -- 000008BC
+		X"00000000", -- 000008C0
+		X"00000000", -- 000008C4
+		X"00000000", -- 000008C8
+		X"00000000", -- 000008CC
+		X"00000000", -- 000008D0
+		X"00000000", -- 000008D4
+		X"00000000", -- 000008D8
+		X"00000000", -- 000008DC
+		X"00000000", -- 000008E0
+		X"00000000", -- 000008E4
+		X"00000000", -- 000008E8
+		X"00000000", -- 000008EC
+		X"00000000", -- 000008F0
+		X"00000000", -- 000008F4
+		X"00000000", -- 000008F8
+		X"00000000", -- 000008FC
+		X"00000000", -- 00000900
+		X"00000000", -- 00000904
+		X"00000000", -- 00000908
+		X"00000000", -- 0000090C
+		X"00000000", -- 00000910
+		X"00000000", -- 00000914
+		X"00000000", -- 00000918
+		X"00000000", -- 0000091C
+		X"00000000", -- 00000920
+		X"00000000", -- 00000924
+		X"00000000", -- 00000928
+		X"00000000", -- 0000092C
+		X"00000000", -- 00000930
+		X"00000000", -- 00000934
+		X"00000000", -- 00000938
+		X"00000000", -- 0000093C
+		X"00000000", -- 00000940
+		X"00000000", -- 00000944
+		X"00000000", -- 00000948
+		X"00000000", -- 0000094C
+		X"00000000", -- 00000950
+		X"00000000", -- 00000954
+		X"00000000", -- 00000958
+		X"00000000", -- 0000095C
+		X"00000000", -- 00000960
+		X"00000000", -- 00000964
+		X"00000000", -- 00000968
+		X"00000000", -- 0000096C
+		X"00000000", -- 00000970
+		X"00000000", -- 00000974
+		X"00000000", -- 00000978
+		X"00000000", -- 0000097C
+		X"00000000", -- 00000980
+		X"00000000", -- 00000984
+		X"00000000", -- 00000988
+		X"00000000", -- 0000098C
+		X"00000000", -- 00000990
+		X"00000000", -- 00000994
+		X"00000000", -- 00000998
+		X"00000000", -- 0000099C
+		X"00000000", -- 000009A0
+		X"00000000", -- 000009A4
+		X"00000000", -- 000009A8
+		X"00000000", -- 000009AC
+		X"00000000", -- 000009B0
+		X"00000000", -- 000009B4
+		X"00000000", -- 000009B8
+		X"00000000", -- 000009BC
+		X"00000000", -- 000009C0
+		X"00000000", -- 000009C4
+		X"00000000", -- 000009C8
+		X"00000000", -- 000009CC
+		X"00000000", -- 000009D0
+		X"00000000", -- 000009D4
+		X"00000000", -- 000009D8
+		X"00000000", -- 000009DC
+		X"00000000", -- 000009E0
+		X"00000000", -- 000009E4
+		X"00000000", -- 000009E8
+		X"00000000", -- 000009EC
+		X"00000000", -- 000009F0
+		X"00000000", -- 000009F4
+		X"00000000", -- 000009F8
+		X"00000000", -- 000009FC
+		X"00000000", -- 00000A00
+		X"00000000", -- 00000A04
+		X"00000000", -- 00000A08
+		X"00000000", -- 00000A0C
+		X"00000000", -- 00000A10
+		X"00000000", -- 00000A14
+		X"00000000", -- 00000A18
+		X"00000000", -- 00000A1C
+		X"00000000", -- 00000A20
+		X"00000000", -- 00000A24
+		X"00000000", -- 00000A28
+		X"00000000", -- 00000A2C
+		X"00000000", -- 00000A30
+		X"00000000", -- 00000A34
+		X"00000000", -- 00000A38
+		X"00000000", -- 00000A3C
+		X"00000000", -- 00000A40
+		X"00000000", -- 00000A44
+		X"00000000", -- 00000A48
+		X"00000000", -- 00000A4C
+		X"00000000", -- 00000A50
+		X"00000000", -- 00000A54
+		X"00000000", -- 00000A58
+		X"00000000", -- 00000A5C
+		X"00000000", -- 00000A60
+		X"00000000", -- 00000A64
+		X"00000000", -- 00000A68
+		X"00000000", -- 00000A6C
+		X"00000000", -- 00000A70
+		X"00000000", -- 00000A74
+		X"00000000", -- 00000A78
+		X"00000000", -- 00000A7C
+		X"00000000", -- 00000A80
+		X"00000000", -- 00000A84
+		X"00000000", -- 00000A88
+		X"00000000", -- 00000A8C
+		X"00000000", -- 00000A90
+		X"00000000", -- 00000A94
+		X"00000000", -- 00000A98
+		X"00000000", -- 00000A9C
+		X"00000000", -- 00000AA0
+		X"00000000", -- 00000AA4
+		X"00000000", -- 00000AA8
+		X"00000000", -- 00000AAC
+		X"00000000", -- 00000AB0
+		X"00000000", -- 00000AB4
+		X"00000000", -- 00000AB8
+		X"00000000", -- 00000ABC
+		X"00000000", -- 00000AC0
+		X"00000000", -- 00000AC4
+		X"00000000", -- 00000AC8
+		X"00000000", -- 00000ACC
+		X"00000000", -- 00000AD0
+		X"00000000", -- 00000AD4
+		X"00000000", -- 00000AD8
+		X"00000000", -- 00000ADC
+		X"00000000", -- 00000AE0
+		X"00000000", -- 00000AE4
+		X"00000000", -- 00000AE8
+		X"00000000", -- 00000AEC
+		X"00000000", -- 00000AF0
+		X"00000000", -- 00000AF4
+		X"00000000", -- 00000AF8
+		X"00000000", -- 00000AFC
+		X"00000000", -- 00000B00
+		X"00000000", -- 00000B04
+		X"00000000", -- 00000B08
+		X"00000000", -- 00000B0C
+		X"00000000", -- 00000B10
+		X"00000000", -- 00000B14
+		X"00000000", -- 00000B18
+		X"00000000", -- 00000B1C
+		X"00000000", -- 00000B20
+		X"00000000", -- 00000B24
+		X"00000000", -- 00000B28
+		X"00000000", -- 00000B2C
+		X"00000000", -- 00000B30
+		X"00000000", -- 00000B34
+		X"00000000", -- 00000B38
+		X"00000000", -- 00000B3C
+		X"00000000", -- 00000B40
+		X"00000000", -- 00000B44
+		X"00000000", -- 00000B48
+		X"00000000", -- 00000B4C
+		X"00000000", -- 00000B50
+		X"00000000", -- 00000B54
+		X"00000000", -- 00000B58
+		X"00000000", -- 00000B5C
+		X"00000000", -- 00000B60
+		X"00000000", -- 00000B64
+		X"00000000", -- 00000B68
+		X"00000000", -- 00000B6C
+		X"00000000", -- 00000B70
+		X"00000000", -- 00000B74
+		X"00000000", -- 00000B78
+		X"00000000", -- 00000B7C
+		X"00000000", -- 00000B80
+		X"00000000", -- 00000B84
+		X"00000000", -- 00000B88
+		X"00000000", -- 00000B8C
+		X"00000000", -- 00000B90
+		X"00000000", -- 00000B94
+		X"00000000", -- 00000B98
+		X"00000000", -- 00000B9C
+		X"00000000", -- 00000BA0
+		X"00000000", -- 00000BA4
+		X"00000000", -- 00000BA8
+		X"00000000", -- 00000BAC
+		X"00000000", -- 00000BB0
+		X"00000000", -- 00000BB4
+		X"00000000", -- 00000BB8
+		X"00000000", -- 00000BBC
+		X"00000000", -- 00000BC0
+		X"00000000", -- 00000BC4
+		X"00000000", -- 00000BC8
+		X"00000000", -- 00000BCC
+		X"00000000", -- 00000BD0
+		X"00000000", -- 00000BD4
+		X"00000000", -- 00000BD8
+		X"00000000", -- 00000BDC
+		X"00000000", -- 00000BE0
+		X"00000000", -- 00000BE4
+		X"00000000", -- 00000BE8
+		X"00000000", -- 00000BEC
+		X"00000000", -- 00000BF0
+		X"00000000", -- 00000BF4
+		X"00000000", -- 00000BF8
+		X"00000000", -- 00000BFC
+		X"00000000", -- 00000C00
+		X"00000000", -- 00000C04
+		X"00000000", -- 00000C08
+		X"00000000", -- 00000C0C
+		X"00000000", -- 00000C10
+		X"00000000", -- 00000C14
+		X"00000000", -- 00000C18
+		X"00000000", -- 00000C1C
+		X"00000000", -- 00000C20
+		X"00000000", -- 00000C24
+		X"00000000", -- 00000C28
+		X"00000000", -- 00000C2C
+		X"00000000", -- 00000C30
+		X"00000000", -- 00000C34
+		X"00000000", -- 00000C38
+		X"00000000", -- 00000C3C
+		X"00000000", -- 00000C40
+		X"00000000", -- 00000C44
+		X"00000000", -- 00000C48
+		X"00000000", -- 00000C4C
+		X"00000000", -- 00000C50
+		X"00000000", -- 00000C54
+		X"00000000", -- 00000C58
+		X"00000000", -- 00000C5C
+		X"00000000", -- 00000C60
+		X"00000000", -- 00000C64
+		X"00000000", -- 00000C68
+		X"00000000", -- 00000C6C
+		X"00000000", -- 00000C70
+		X"00000000", -- 00000C74
+		X"00000000", -- 00000C78
+		X"00000000", -- 00000C7C
+		X"00000000", -- 00000C80
+		X"00000000", -- 00000C84
+		X"00000000", -- 00000C88
+		X"00000000", -- 00000C8C
+		X"00000000", -- 00000C90
+		X"00000000", -- 00000C94
+		X"00000000", -- 00000C98
+		X"00000000", -- 00000C9C
+		X"00000000", -- 00000CA0
+		X"00000000", -- 00000CA4
+		X"00000000", -- 00000CA8
+		X"00000000", -- 00000CAC
+		X"00000000", -- 00000CB0
+		X"00000000", -- 00000CB4
+		X"00000000", -- 00000CB8
+		X"00000000", -- 00000CBC
+		X"00000000", -- 00000CC0
+		X"00000000", -- 00000CC4
+		X"00000000", -- 00000CC8
+		X"00000000", -- 00000CCC
+		X"00000000", -- 00000CD0
+		X"00000000", -- 00000CD4
+		X"00000000", -- 00000CD8
+		X"00000000", -- 00000CDC
+		X"00000000", -- 00000CE0
+		X"00000000", -- 00000CE4
+		X"00000000", -- 00000CE8
+		X"00000000", -- 00000CEC
+		X"00000000", -- 00000CF0
+		X"00000000", -- 00000CF4
+		X"00000000", -- 00000CF8
+		X"00000000", -- 00000CFC
+		X"00000000", -- 00000D00
+		X"00000000", -- 00000D04
+		X"00000000", -- 00000D08
+		X"00000000", -- 00000D0C
+		X"00000000", -- 00000D10
+		X"00000000", -- 00000D14
+		X"00000000", -- 00000D18
+		X"00000000", -- 00000D1C
+		X"00000000", -- 00000D20
+		X"00000000", -- 00000D24
+		X"00000000", -- 00000D28
+		X"00000000", -- 00000D2C
+		X"00000000", -- 00000D30
+		X"00000000", -- 00000D34
+		X"00000000", -- 00000D38
+		X"00000000", -- 00000D3C
+		X"00000000", -- 00000D40
+		X"00000000", -- 00000D44
+		X"00000000", -- 00000D48
+		X"00000000", -- 00000D4C
+		X"00000000", -- 00000D50
+		X"00000000", -- 00000D54
+		X"00000000", -- 00000D58
+		X"00000000", -- 00000D5C
+		X"00000000", -- 00000D60
+		X"00000000", -- 00000D64
+		X"00000000", -- 00000D68
+		X"00000000", -- 00000D6C
+		X"00000000", -- 00000D70
+		X"00000000", -- 00000D74
+		X"00000000", -- 00000D78
+		X"00000000", -- 00000D7C
+		X"00000000", -- 00000D80
+		X"00000000", -- 00000D84
+		X"00000000", -- 00000D88
+		X"00000000", -- 00000D8C
+		X"00000000", -- 00000D90
+		X"00000000", -- 00000D94
+		X"00000000", -- 00000D98
+		X"00000000", -- 00000D9C
+		X"00000000", -- 00000DA0
+		X"00000000", -- 00000DA4
+		X"00000000", -- 00000DA8
+		X"00000000", -- 00000DAC
+		X"00000000", -- 00000DB0
+		X"00000000", -- 00000DB4
+		X"00000000", -- 00000DB8
+		X"00000000", -- 00000DBC
+		X"00000000", -- 00000DC0
+		X"00000000", -- 00000DC4
+		X"00000000", -- 00000DC8
+		X"00000000", -- 00000DCC
+		X"00000000", -- 00000DD0
+		X"00000000", -- 00000DD4
+		X"00000000", -- 00000DD8
+		X"00000000", -- 00000DDC
+		X"00000000", -- 00000DE0
+		X"00000000", -- 00000DE4
+		X"00000000", -- 00000DE8
+		X"00000000", -- 00000DEC
+		X"00000000", -- 00000DF0
+		X"00000000", -- 00000DF4
+		X"00000000", -- 00000DF8
+		X"00000000", -- 00000DFC
+		X"00000000", -- 00000E00
+		X"00000000", -- 00000E04
+		X"00000000", -- 00000E08
+		X"00000000", -- 00000E0C
+		X"00000000", -- 00000E10
+		X"00000000", -- 00000E14
+		X"00000000", -- 00000E18
+		X"00000000", -- 00000E1C
+		X"00000000", -- 00000E20
+		X"00000000", -- 00000E24
+		X"00000000", -- 00000E28
+		X"00000000", -- 00000E2C
+		X"00000000", -- 00000E30
+		X"00000000", -- 00000E34
+		X"00000000", -- 00000E38
+		X"00000000", -- 00000E3C
+		X"00000000", -- 00000E40
+		X"00000000", -- 00000E44
+		X"00000000", -- 00000E48
+		X"00000000", -- 00000E4C
+		X"00000000", -- 00000E50
+		X"00000000", -- 00000E54
+		X"00000000", -- 00000E58
+		X"00000000", -- 00000E5C
+		X"00000000", -- 00000E60
+		X"00000000", -- 00000E64
+		X"00000000", -- 00000E68
+		X"00000000", -- 00000E6C
+		X"00000000", -- 00000E70
+		X"00000000", -- 00000E74
+		X"00000000", -- 00000E78
+		X"00000000", -- 00000E7C
+		X"00000000", -- 00000E80
+		X"00000000", -- 00000E84
+		X"00000000", -- 00000E88
+		X"00000000", -- 00000E8C
+		X"00000000", -- 00000E90
+		X"00000000", -- 00000E94
+		X"00000000", -- 00000E98
+		X"00000000", -- 00000E9C
+		X"00000000", -- 00000EA0
+		X"00000000", -- 00000EA4
+		X"00000000", -- 00000EA8
+		X"00000000", -- 00000EAC
+		X"00000000", -- 00000EB0
+		X"00000000", -- 00000EB4
+		X"00000000", -- 00000EB8
+		X"00000000", -- 00000EBC
+		X"00000000", -- 00000EC0
+		X"00000000", -- 00000EC4
+		X"00000000", -- 00000EC8
+		X"00000000", -- 00000ECC
+		X"00000000", -- 00000ED0
+		X"00000000", -- 00000ED4
+		X"00000000", -- 00000ED8
+		X"00000000", -- 00000EDC
+		X"00000000", -- 00000EE0
+		X"00000000", -- 00000EE4
+		X"00000000", -- 00000EE8
+		X"00000000", -- 00000EEC
+		X"00000000", -- 00000EF0
+		X"00000000", -- 00000EF4
+		X"00000000", -- 00000EF8
+		X"00000000", -- 00000EFC
+		X"00000000", -- 00000F00
+		X"00000000", -- 00000F04
+		X"00000000", -- 00000F08
+		X"00000000", -- 00000F0C
+		X"00000000", -- 00000F10
+		X"00000000", -- 00000F14
+		X"00000000", -- 00000F18
+		X"00000000", -- 00000F1C
+		X"00000000", -- 00000F20
+		X"00000000", -- 00000F24
+		X"00000000", -- 00000F28
+		X"00000000", -- 00000F2C
+		X"00000000", -- 00000F30
+		X"00000000", -- 00000F34
+		X"00000000", -- 00000F38
+		X"00000000", -- 00000F3C
+		X"00000000", -- 00000F40
+		X"00000000", -- 00000F44
+		X"00000000", -- 00000F48
+		X"00000000", -- 00000F4C
+		X"00000000", -- 00000F50
+		X"00000000", -- 00000F54
+		X"00000000", -- 00000F58
+		X"00000000", -- 00000F5C
+		X"00000000", -- 00000F60
+		X"00000000", -- 00000F64
+		X"00000000", -- 00000F68
+		X"00000000", -- 00000F6C
+		X"00000000", -- 00000F70
+		X"00000000", -- 00000F74
+		X"00000000", -- 00000F78
+		X"00000000", -- 00000F7C
+		X"00000000", -- 00000F80
+		X"00000000", -- 00000F84
+		X"00000000", -- 00000F88
+		X"00000000", -- 00000F8C
+		X"00000000", -- 00000F90
+		X"00000000", -- 00000F94
+		X"00000000", -- 00000F98
+		X"00000000", -- 00000F9C
+		X"00000000", -- 00000FA0
+		X"00000000", -- 00000FA4
+		X"00000000", -- 00000FA8
+		X"00000000", -- 00000FAC
+		X"00000000", -- 00000FB0
+		X"00000000", -- 00000FB4
+		X"00000000", -- 00000FB8
+		X"00000000", -- 00000FBC
+		X"00000000", -- 00000FC0
+		X"00000000", -- 00000FC4
+		X"00000000", -- 00000FC8
+		X"00000000", -- 00000FCC
+		X"00000000", -- 00000FD0
+		X"00000000", -- 00000FD4
+		X"00000000", -- 00000FD8
+		X"00000000", -- 00000FDC
+		X"00000000", -- 00000FE0
+		X"00000000", -- 00000FE4
+		X"00000000", -- 00000FE8
+		X"00000000", -- 00000FEC
+		X"00000000", -- 00000FF0
+		X"00000000", -- 00000FF4
+		X"00000000", -- 00000FF8
+		X"00000000", -- 00000FFC
+		X"00000000", -- 00001000
+		X"00000000", -- 00001004
+		X"00000000", -- 00001008
+		X"00000000", -- 0000100C
+		X"00000000", -- 00001010
+		X"00000000", -- 00001014
+		X"00000000", -- 00001018
+		X"00000000", -- 0000101C
+		X"00000000", -- 00001020
+		X"00000000", -- 00001024
+		X"00000000", -- 00001028
+		X"00000000", -- 0000102C
+		X"00000000", -- 00001030
+		X"00000000", -- 00001034
+		X"00000000", -- 00001038
+		X"00000000", -- 0000103C
+		X"00000000", -- 00001040
+		X"00000000", -- 00001044
+		X"00000000", -- 00001048
+		X"00000000", -- 0000104C
+		X"00000000", -- 00001050
+		X"00000000", -- 00001054
+		X"00000000", -- 00001058
+		X"00000000", -- 0000105C
+		X"00000000", -- 00001060
+		X"00000000", -- 00001064
+		X"00000000", -- 00001068
+		X"00000000", -- 0000106C
+		X"00000000", -- 00001070
+		X"00000000", -- 00001074
+		X"00000000", -- 00001078
+		X"00000000", -- 0000107C
+		X"00000000", -- 00001080
+		X"00000000", -- 00001084
+		X"00000000", -- 00001088
+		X"00000000", -- 0000108C
+		X"00000000", -- 00001090
+		X"00000000", -- 00001094
+		X"00000000", -- 00001098
+		X"00000000", -- 0000109C
+		X"00000000", -- 000010A0
+		X"00000000", -- 000010A4
+		X"00000000", -- 000010A8
+		X"00000000", -- 000010AC
+		X"00000000", -- 000010B0
+		X"00000000", -- 000010B4
+		X"00000000", -- 000010B8
+		X"00000000", -- 000010BC
+		X"00000000", -- 000010C0
+		X"00000000", -- 000010C4
+		X"00000000", -- 000010C8
+		X"00000000", -- 000010CC
+		X"00000000", -- 000010D0
+		X"00000000", -- 000010D4
+		X"00000000", -- 000010D8
+		X"00000000", -- 000010DC
+		X"00000000", -- 000010E0
+		X"00000000", -- 000010E4
+		X"00000000", -- 000010E8
+		X"00000000", -- 000010EC
+		X"00000000", -- 000010F0
+		X"00000000", -- 000010F4
+		X"00000000", -- 000010F8
+		X"00000000", -- 000010FC
+		X"00000000", -- 00001100
+		X"00000000", -- 00001104
+		X"00000000", -- 00001108
+		X"00000000", -- 0000110C
+		X"00000000", -- 00001110
+		X"00000000", -- 00001114
+		X"00000000", -- 00001118
+		X"00000000", -- 0000111C
+		X"00000000", -- 00001120
+		X"00000000", -- 00001124
+		X"00000000", -- 00001128
+		X"00000000", -- 0000112C
+		X"00000000", -- 00001130
+		X"00000000", -- 00001134
+		X"00000000", -- 00001138
+		X"00000000", -- 0000113C
+		X"00000000", -- 00001140
+		X"00000000", -- 00001144
+		X"00000000", -- 00001148
+		X"00000000", -- 0000114C
+		X"00000000", -- 00001150
+		X"00000000", -- 00001154
+		X"00000000", -- 00001158
+		X"00000000", -- 0000115C
+		X"00000000", -- 00001160
+		X"00000000", -- 00001164
+		X"00000000", -- 00001168
+		X"00000000", -- 0000116C
+		X"00000000", -- 00001170
+		X"00000000", -- 00001174
+		X"00000000", -- 00001178
+		X"00000000", -- 0000117C
+		X"00000000", -- 00001180
+		X"00000000", -- 00001184
+		X"00000000", -- 00001188
+		X"00000000", -- 0000118C
+		X"00000000", -- 00001190
+		X"00000000", -- 00001194
+		X"00000000", -- 00001198
+		X"00000000", -- 0000119C
+		X"00000000", -- 000011A0
+		X"00000000", -- 000011A4
+		X"00000000", -- 000011A8
+		X"00000000", -- 000011AC
+		X"00000000", -- 000011B0
+		X"00000000", -- 000011B4
+		X"00000000", -- 000011B8
+		X"00000000", -- 000011BC
+		X"00000000", -- 000011C0
+		X"00000000", -- 000011C4
+		X"00000000", -- 000011C8
+		X"00000000", -- 000011CC
+		X"00000000", -- 000011D0
+		X"00000000", -- 000011D4
+		X"00000000", -- 000011D8
+		X"00000000", -- 000011DC
+		X"00000000", -- 000011E0
+		X"00000000", -- 000011E4
+		X"00000000", -- 000011E8
+		X"00000000", -- 000011EC
+		X"00000000", -- 000011F0
+		X"00000000", -- 000011F4
+		X"00000000", -- 000011F8
+		X"00000000", -- 000011FC
+		X"00000000", -- 00001200
+		X"00000000", -- 00001204
+		X"00000000", -- 00001208
+		X"00000000", -- 0000120C
+		X"00000000", -- 00001210
+		X"00000000", -- 00001214
+		X"00000000", -- 00001218
+		X"00000000", -- 0000121C
+		X"00000000", -- 00001220
+		X"00000000", -- 00001224
+		X"00000000", -- 00001228
+		X"00000000", -- 0000122C
+		X"00000000", -- 00001230
+		X"00000000", -- 00001234
+		X"00000000", -- 00001238
+		X"00000000", -- 0000123C
+		X"00000000", -- 00001240
+		X"00000000", -- 00001244
+		X"00000000", -- 00001248
+		X"00000000", -- 0000124C
+		X"00000000", -- 00001250
+		X"00000000", -- 00001254
+		X"00000000", -- 00001258
+		X"00000000", -- 0000125C
+		X"00000000", -- 00001260
+		X"00000000", -- 00001264
+		X"00000000", -- 00001268
+		X"00000000", -- 0000126C
+		X"00000000", -- 00001270
+		X"00000000", -- 00001274
+		X"00000000", -- 00001278
+		X"00000000", -- 0000127C
+		X"00000000", -- 00001280
+		X"00000000", -- 00001284
+		X"00000000", -- 00001288
+		X"00000000", -- 0000128C
+		X"00000000", -- 00001290
+		X"00000000", -- 00001294
+		X"00000000", -- 00001298
+		X"00000000", -- 0000129C
+		X"00000000", -- 000012A0
+		X"00000000", -- 000012A4
+		X"00000000", -- 000012A8
+		X"00000000", -- 000012AC
+		X"00000000", -- 000012B0
+		X"00000000", -- 000012B4
+		X"00000000", -- 000012B8
+		X"00000000", -- 000012BC
+		X"00000000", -- 000012C0
+		X"00000000", -- 000012C4
+		X"00000000", -- 000012C8
+		X"00000000", -- 000012CC
+		X"00000000", -- 000012D0
+		X"00000000", -- 000012D4
+		X"00000000", -- 000012D8
+		X"00000000", -- 000012DC
+		X"00000000", -- 000012E0
+		X"00000000", -- 000012E4
+		X"00000000", -- 000012E8
+		X"00000000", -- 000012EC
+		X"00000000", -- 000012F0
+		X"00000000", -- 000012F4
+		X"00000000", -- 000012F8
+		X"00000000", -- 000012FC
+		X"00000000", -- 00001300
+		X"00000000", -- 00001304
+		X"00000000", -- 00001308
+		X"00000000", -- 0000130C
+		X"00000000", -- 00001310
+		X"00000000", -- 00001314
+		X"00000000", -- 00001318
+		X"00000000", -- 0000131C
+		X"00000000", -- 00001320
+		X"00000000", -- 00001324
+		X"00000000", -- 00001328
+		X"00000000", -- 0000132C
+		X"00000000", -- 00001330
+		X"00000000", -- 00001334
+		X"00000000", -- 00001338
+		X"00000000", -- 0000133C
+		X"00000000", -- 00001340
+		X"00000000", -- 00001344
+		X"00000000", -- 00001348
+		X"00000000", -- 0000134C
+		X"00000000", -- 00001350
+		X"00000000", -- 00001354
+		X"00000000", -- 00001358
+		X"00000000", -- 0000135C
+		X"00000000", -- 00001360
+		X"00000000", -- 00001364
+		X"00000000", -- 00001368
+		X"00000000", -- 0000136C
+		X"00000000", -- 00001370
+		X"00000000", -- 00001374
+		X"00000000", -- 00001378
+		X"00000000", -- 0000137C
+		X"00000000", -- 00001380
+		X"00000000", -- 00001384
+		X"00000000", -- 00001388
+		X"00000000", -- 0000138C
+		X"00000000", -- 00001390
+		X"00000000", -- 00001394
+		X"00000000", -- 00001398
+		X"00000000", -- 0000139C
+		X"00000000", -- 000013A0
+		X"00000000", -- 000013A4
+		X"00000000", -- 000013A8
+		X"00000000", -- 000013AC
+		X"00000000", -- 000013B0
+		X"00000000", -- 000013B4
+		X"00000000", -- 000013B8
+		X"00000000", -- 000013BC
+		X"00000000", -- 000013C0
+		X"00000000", -- 000013C4
+		X"00000000", -- 000013C8
+		X"00000000", -- 000013CC
+		X"00000000", -- 000013D0
+		X"00000000", -- 000013D4
+		X"00000000", -- 000013D8
+		X"00000000", -- 000013DC
+		X"00000000", -- 000013E0
+		X"00000000", -- 000013E4
+		X"00000000", -- 000013E8
+		X"00000000", -- 000013EC
+		X"00000000", -- 000013F0
+		X"00000000", -- 000013F4
+		X"00000000", -- 000013F8
+		X"00000000", -- 000013FC
+		X"00000000", -- 00001400
+		X"00000000", -- 00001404
+		X"00000000", -- 00001408
+		X"00000000", -- 0000140C
+		X"00000000", -- 00001410
+		X"00000000", -- 00001414
+		X"00000000", -- 00001418
+		X"00000000", -- 0000141C
+		X"00000000", -- 00001420
+		X"00000000", -- 00001424
+		X"00000000", -- 00001428
+		X"00000000", -- 0000142C
+		X"00000000", -- 00001430
+		X"00000000", -- 00001434
+		X"00000000", -- 00001438
+		X"00000000", -- 0000143C
+		X"00000000", -- 00001440
+		X"00000000", -- 00001444
+		X"00000000", -- 00001448
+		X"00000000", -- 0000144C
+		X"00000000", -- 00001450
+		X"00000000", -- 00001454
+		X"00000000", -- 00001458
+		X"00000000", -- 0000145C
+		X"00000000", -- 00001460
+		X"00000000", -- 00001464
+		X"00000000", -- 00001468
+		X"00000000", -- 0000146C
+		X"00000000", -- 00001470
+		X"00000000", -- 00001474
+		X"00000000", -- 00001478
+		X"00000000", -- 0000147C
+		X"00000000", -- 00001480
+		X"00000000", -- 00001484
+		X"00000000", -- 00001488
+		X"00000000", -- 0000148C
+		X"00000000", -- 00001490
+		X"00000000", -- 00001494
+		X"00000000", -- 00001498
+		X"00000000", -- 0000149C
+		X"00000000", -- 000014A0
+		X"00000000", -- 000014A4
+		X"00000000", -- 000014A8
+		X"00000000", -- 000014AC
+		X"00000000", -- 000014B0
+		X"00000000", -- 000014B4
+		X"00000000", -- 000014B8
+		X"00000000", -- 000014BC
+		X"00000000", -- 000014C0
+		X"00000000", -- 000014C4
+		X"00000000", -- 000014C8
+		X"00000000", -- 000014CC
+		X"00000000", -- 000014D0
+		X"00000000", -- 000014D4
+		X"00000000", -- 000014D8
+		X"00000000", -- 000014DC
+		X"00000000", -- 000014E0
+		X"00000000", -- 000014E4
+		X"00000000", -- 000014E8
+		X"00000000", -- 000014EC
+		X"00000000", -- 000014F0
+		X"00000000", -- 000014F4
+		X"00000000", -- 000014F8
+		X"00000000", -- 000014FC
+		X"00000000", -- 00001500
+		X"00000000", -- 00001504
+		X"00000000", -- 00001508
+		X"00000000", -- 0000150C
+		X"00000000", -- 00001510
+		X"00000000", -- 00001514
+		X"00000000", -- 00001518
+		X"00000000", -- 0000151C
+		X"00000000", -- 00001520
+		X"00000000", -- 00001524
+		X"00000000", -- 00001528
+		X"00000000", -- 0000152C
+		X"00000000", -- 00001530
+		X"00000000", -- 00001534
+		X"00000000", -- 00001538
+		X"00000000", -- 0000153C
+		X"00000000", -- 00001540
+		X"00000000", -- 00001544
+		X"00000000", -- 00001548
+		X"00000000", -- 0000154C
+		X"00000000", -- 00001550
+		X"00000000", -- 00001554
+		X"00000000", -- 00001558
+		X"00000000", -- 0000155C
+		X"00000000", -- 00001560
+		X"00000000", -- 00001564
+		X"00000000", -- 00001568
+		X"00000000", -- 0000156C
+		X"00000000", -- 00001570
+		X"00000000", -- 00001574
+		X"00000000", -- 00001578
+		X"00000000", -- 0000157C
+		X"00000000", -- 00001580
+		X"00000000", -- 00001584
+		X"00000000", -- 00001588
+		X"00000000", -- 0000158C
+		X"00000000", -- 00001590
+		X"00000000", -- 00001594
+		X"00000000", -- 00001598
+		X"00000000", -- 0000159C
+		X"00000000", -- 000015A0
+		X"00000000", -- 000015A4
+		X"00000000", -- 000015A8
+		X"00000000", -- 000015AC
+		X"00000000", -- 000015B0
+		X"00000000", -- 000015B4
+		X"00000000", -- 000015B8
+		X"00000000", -- 000015BC
+		X"00000000", -- 000015C0
+		X"00000000", -- 000015C4
+		X"00000000", -- 000015C8
+		X"00000000", -- 000015CC
+		X"00000000", -- 000015D0
+		X"00000000", -- 000015D4
+		X"00000000", -- 000015D8
+		X"00000000", -- 000015DC
+		X"00000000", -- 000015E0
+		X"00000000", -- 000015E4
+		X"00000000", -- 000015E8
+		X"00000000", -- 000015EC
+		X"00000000", -- 000015F0
+		X"00000000", -- 000015F4
+		X"00000000", -- 000015F8
+		X"00000000", -- 000015FC
+		X"00000000", -- 00001600
+		X"00000000", -- 00001604
+		X"00000000", -- 00001608
+		X"00000000", -- 0000160C
+		X"00000000", -- 00001610
+		X"00000000", -- 00001614
+		X"00000000", -- 00001618
+		X"00000000", -- 0000161C
+		X"00000000", -- 00001620
+		X"00000000", -- 00001624
+		X"00000000", -- 00001628
+		X"00000000", -- 0000162C
+		X"00000000", -- 00001630
+		X"00000000", -- 00001634
+		X"00000000", -- 00001638
+		X"00000000", -- 0000163C
+		X"00000000", -- 00001640
+		X"00000000", -- 00001644
+		X"00000000", -- 00001648
+		X"00000000", -- 0000164C
+		X"00000000", -- 00001650
+		X"00000000", -- 00001654
+		X"00000000", -- 00001658
+		X"00000000", -- 0000165C
+		X"00000000", -- 00001660
+		X"00000000", -- 00001664
+		X"00000000", -- 00001668
+		X"00000000", -- 0000166C
+		X"00000000", -- 00001670
+		X"00000000", -- 00001674
+		X"00000000", -- 00001678
+		X"00000000", -- 0000167C
+		X"00000000", -- 00001680
+		X"00000000", -- 00001684
+		X"00000000", -- 00001688
+		X"00000000", -- 0000168C
+		X"00000000", -- 00001690
+		X"00000000", -- 00001694
+		X"00000000", -- 00001698
+		X"00000000", -- 0000169C
+		X"00000000", -- 000016A0
+		X"00000000", -- 000016A4
+		X"00000000", -- 000016A8
+		X"00000000", -- 000016AC
+		X"00000000", -- 000016B0
+		X"00000000", -- 000016B4
+		X"00000000", -- 000016B8
+		X"00000000", -- 000016BC
+		X"00000000", -- 000016C0
+		X"00000000", -- 000016C4
+		X"00000000", -- 000016C8
+		X"00000000", -- 000016CC
+		X"00000000", -- 000016D0
+		X"00000000", -- 000016D4
+		X"00000000", -- 000016D8
+		X"00000000", -- 000016DC
+		X"00000000", -- 000016E0
+		X"00000000", -- 000016E4
+		X"00000000", -- 000016E8
+		X"00000000", -- 000016EC
+		X"00000000", -- 000016F0
+		X"00000000", -- 000016F4
+		X"00000000", -- 000016F8
+		X"00000000", -- 000016FC
+		X"00000000", -- 00001700
+		X"00000000", -- 00001704
+		X"00000000", -- 00001708
+		X"00000000", -- 0000170C
+		X"00000000", -- 00001710
+		X"00000000", -- 00001714
+		X"00000000", -- 00001718
+		X"00000000", -- 0000171C
+		X"00000000", -- 00001720
+		X"00000000", -- 00001724
+		X"00000000", -- 00001728
+		X"00000000", -- 0000172C
+		X"00000000", -- 00001730
+		X"00000000", -- 00001734
+		X"00000000", -- 00001738
+		X"00000000", -- 0000173C
+		X"00000000", -- 00001740
+		X"00000000", -- 00001744
+		X"00000000", -- 00001748
+		X"00000000", -- 0000174C
+		X"00000000", -- 00001750
+		X"00000000", -- 00001754
+		X"00000000", -- 00001758
+		X"00000000", -- 0000175C
+		X"00000000", -- 00001760
+		X"00000000", -- 00001764
+		X"00000000", -- 00001768
+		X"00000000", -- 0000176C
+		X"00000000", -- 00001770
+		X"00000000", -- 00001774
+		X"00000000", -- 00001778
+		X"00000000", -- 0000177C
+		X"00000000", -- 00001780
+		X"00000000", -- 00001784
+		X"00000000", -- 00001788
+		X"00000000", -- 0000178C
+		X"00000000", -- 00001790
+		X"00000000", -- 00001794
+		X"00000000", -- 00001798
+		X"00000000", -- 0000179C
+		X"00000000", -- 000017A0
+		X"00000000", -- 000017A4
+		X"00000000", -- 000017A8
+		X"00000000", -- 000017AC
+		X"00000000", -- 000017B0
+		X"00000000", -- 000017B4
+		X"00000000", -- 000017B8
+		X"00000000", -- 000017BC
+		X"00000000", -- 000017C0
+		X"00000000", -- 000017C4
+		X"00000000", -- 000017C8
+		X"00000000", -- 000017CC
+		X"00000000", -- 000017D0
+		X"00000000", -- 000017D4
+		X"00000000", -- 000017D8
+		X"00000000", -- 000017DC
+		X"00000000", -- 000017E0
+		X"00000000", -- 000017E4
+		X"00000000", -- 000017E8
+		X"00000000", -- 000017EC
+		X"00000000", -- 000017F0
+		X"00000000", -- 000017F4
+		X"00000000", -- 000017F8
+		X"00000000", -- 000017FC
+		X"00000000", -- 00001800
+		X"00000000", -- 00001804
+		X"00000000", -- 00001808
+		X"00000000", -- 0000180C
+		X"00000000", -- 00001810
+		X"00000000", -- 00001814
+		X"00000000", -- 00001818
+		X"00000000", -- 0000181C
+		X"00000000", -- 00001820
+		X"00000000", -- 00001824
+		X"00000000", -- 00001828
+		X"00000000", -- 0000182C
+		X"00000000", -- 00001830
+		X"00000000", -- 00001834
+		X"00000000", -- 00001838
+		X"00000000", -- 0000183C
+		X"00000000", -- 00001840
+		X"00000000", -- 00001844
+		X"00000000", -- 00001848
+		X"00000000", -- 0000184C
+		X"00000000", -- 00001850
+		X"00000000", -- 00001854
+		X"00000000", -- 00001858
+		X"00000000", -- 0000185C
+		X"00000000", -- 00001860
+		X"00000000", -- 00001864
+		X"00000000", -- 00001868
+		X"00000000", -- 0000186C
+		X"00000000", -- 00001870
+		X"00000000", -- 00001874
+		X"00000000", -- 00001878
+		X"00000000", -- 0000187C
+		X"00000000", -- 00001880
+		X"00000000", -- 00001884
+		X"00000000", -- 00001888
+		X"00000000", -- 0000188C
+		X"00000000", -- 00001890
+		X"00000000", -- 00001894
+		X"00000000", -- 00001898
+		X"00000000", -- 0000189C
+		X"00000000", -- 000018A0
+		X"00000000", -- 000018A4
+		X"00000000", -- 000018A8
+		X"00000000", -- 000018AC
+		X"00000000", -- 000018B0
+		X"00000000", -- 000018B4
+		X"00000000", -- 000018B8
+		X"00000000", -- 000018BC
+		X"00000000", -- 000018C0
+		X"00000000", -- 000018C4
+		X"00000000", -- 000018C8
+		X"00000000", -- 000018CC
+		X"00000000", -- 000018D0
+		X"00000000", -- 000018D4
+		X"00000000", -- 000018D8
+		X"00000000", -- 000018DC
+		X"00000000", -- 000018E0
+		X"00000000", -- 000018E4
+		X"00000000", -- 000018E8
+		X"00000000", -- 000018EC
+		X"00000000", -- 000018F0
+		X"00000000", -- 000018F4
+		X"00000000", -- 000018F8
+		X"00000000", -- 000018FC
+		X"00000000", -- 00001900
+		X"00000000", -- 00001904
+		X"00000000", -- 00001908
+		X"00000000", -- 0000190C
+		X"00000000", -- 00001910
+		X"00000000", -- 00001914
+		X"00000000", -- 00001918
+		X"00000000", -- 0000191C
+		X"00000000", -- 00001920
+		X"00000000", -- 00001924
+		X"00000000", -- 00001928
+		X"00000000", -- 0000192C
+		X"00000000", -- 00001930
+		X"00000000", -- 00001934
+		X"00000000", -- 00001938
+		X"00000000", -- 0000193C
+		X"00000000", -- 00001940
+		X"00000000", -- 00001944
+		X"00000000", -- 00001948
+		X"00000000", -- 0000194C
+		X"00000000", -- 00001950
+		X"00000000", -- 00001954
+		X"00000000", -- 00001958
+		X"00000000", -- 0000195C
+		X"00000000", -- 00001960
+		X"00000000", -- 00001964
+		X"00000000", -- 00001968
+		X"00000000", -- 0000196C
+		X"00000000", -- 00001970
+		X"00000000", -- 00001974
+		X"00000000", -- 00001978
+		X"00000000", -- 0000197C
+		X"00000000", -- 00001980
+		X"00000000", -- 00001984
+		X"00000000", -- 00001988
+		X"00000000", -- 0000198C
+		X"00000000", -- 00001990
+		X"00000000", -- 00001994
+		X"00000000", -- 00001998
+		X"00000000", -- 0000199C
+		X"00000000", -- 000019A0
+		X"00000000", -- 000019A4
+		X"00000000", -- 000019A8
+		X"00000000", -- 000019AC
+		X"00000000", -- 000019B0
+		X"00000000", -- 000019B4
+		X"00000000", -- 000019B8
+		X"00000000", -- 000019BC
+		X"00000000", -- 000019C0
+		X"00000000", -- 000019C4
+		X"00000000", -- 000019C8
+		X"00000000", -- 000019CC
+		X"00000000", -- 000019D0
+		X"00000000", -- 000019D4
+		X"00000000", -- 000019D8
+		X"00000000", -- 000019DC
+		X"00000000", -- 000019E0
+		X"00000000", -- 000019E4
+		X"00000000", -- 000019E8
+		X"00000000", -- 000019EC
+		X"00000000", -- 000019F0
+		X"00000000", -- 000019F4
+		X"00000000", -- 000019F8
+		X"00000000", -- 000019FC
+		X"00000000", -- 00001A00
+		X"00000000", -- 00001A04
+		X"00000000", -- 00001A08
+		X"00000000", -- 00001A0C
+		X"00000000", -- 00001A10
+		X"00000000", -- 00001A14
+		X"00000000", -- 00001A18
+		X"00000000", -- 00001A1C
+		X"00000000", -- 00001A20
+		X"00000000", -- 00001A24
+		X"00000000", -- 00001A28
+		X"00000000", -- 00001A2C
+		X"00000000", -- 00001A30
+		X"00000000", -- 00001A34
+		X"00000000", -- 00001A38
+		X"00000000", -- 00001A3C
+		X"00000000", -- 00001A40
+		X"00000000", -- 00001A44
+		X"00000000", -- 00001A48
+		X"00000000", -- 00001A4C
+		X"00000000", -- 00001A50
+		X"00000000", -- 00001A54
+		X"00000000", -- 00001A58
+		X"00000000", -- 00001A5C
+		X"00000000", -- 00001A60
+		X"00000000", -- 00001A64
+		X"00000000", -- 00001A68
+		X"00000000", -- 00001A6C
+		X"00000000", -- 00001A70
+		X"00000000", -- 00001A74
+		X"00000000", -- 00001A78
+		X"00000000", -- 00001A7C
+		X"00000000", -- 00001A80
+		X"00000000", -- 00001A84
+		X"00000000", -- 00001A88
+		X"00000000", -- 00001A8C
+		X"00000000", -- 00001A90
+		X"00000000", -- 00001A94
+		X"00000000", -- 00001A98
+		X"00000000", -- 00001A9C
+		X"00000000", -- 00001AA0
+		X"00000000", -- 00001AA4
+		X"00000000", -- 00001AA8
+		X"00000000", -- 00001AAC
+		X"00000000", -- 00001AB0
+		X"00000000", -- 00001AB4
+		X"00000000", -- 00001AB8
+		X"00000000", -- 00001ABC
+		X"00000000", -- 00001AC0
+		X"00000000", -- 00001AC4
+		X"00000000", -- 00001AC8
+		X"00000000", -- 00001ACC
+		X"00000000", -- 00001AD0
+		X"00000000", -- 00001AD4
+		X"00000000", -- 00001AD8
+		X"00000000", -- 00001ADC
+		X"00000000", -- 00001AE0
+		X"00000000", -- 00001AE4
+		X"00000000", -- 00001AE8
+		X"00000000", -- 00001AEC
+		X"00000000", -- 00001AF0
+		X"00000000", -- 00001AF4
+		X"00000000", -- 00001AF8
+		X"00000000", -- 00001AFC
+		X"00000000", -- 00001B00
+		X"00000000", -- 00001B04
+		X"00000000", -- 00001B08
+		X"00000000", -- 00001B0C
+		X"00000000", -- 00001B10
+		X"00000000", -- 00001B14
+		X"00000000", -- 00001B18
+		X"00000000", -- 00001B1C
+		X"00000000", -- 00001B20
+		X"00000000", -- 00001B24
+		X"00000000", -- 00001B28
+		X"00000000", -- 00001B2C
+		X"00000000", -- 00001B30
+		X"00000000", -- 00001B34
+		X"00000000", -- 00001B38
+		X"00000000", -- 00001B3C
+		X"00000000", -- 00001B40
+		X"00000000", -- 00001B44
+		X"00000000", -- 00001B48
+		X"00000000", -- 00001B4C
+		X"00000000", -- 00001B50
+		X"00000000", -- 00001B54
+		X"00000000", -- 00001B58
+		X"00000000", -- 00001B5C
+		X"00000000", -- 00001B60
+		X"00000000", -- 00001B64
+		X"00000000", -- 00001B68
+		X"00000000", -- 00001B6C
+		X"00000000", -- 00001B70
+		X"00000000", -- 00001B74
+		X"00000000", -- 00001B78
+		X"00000000", -- 00001B7C
+		X"00000000", -- 00001B80
+		X"00000000", -- 00001B84
+		X"00000000", -- 00001B88
+		X"00000000", -- 00001B8C
+		X"00000000", -- 00001B90
+		X"00000000", -- 00001B94
+		X"00000000", -- 00001B98
+		X"00000000", -- 00001B9C
+		X"00000000", -- 00001BA0
+		X"00000000", -- 00001BA4
+		X"00000000", -- 00001BA8
+		X"00000000", -- 00001BAC
+		X"00000000", -- 00001BB0
+		X"00000000", -- 00001BB4
+		X"00000000", -- 00001BB8
+		X"00000000", -- 00001BBC
+		X"00000000", -- 00001BC0
+		X"00000000", -- 00001BC4
+		X"00000000", -- 00001BC8
+		X"00000000", -- 00001BCC
+		X"00000000", -- 00001BD0
+		X"00000000", -- 00001BD4
+		X"00000000", -- 00001BD8
+		X"00000000", -- 00001BDC
+		X"00000000", -- 00001BE0
+		X"00000000", -- 00001BE4
+		X"00000000", -- 00001BE8
+		X"00000000", -- 00001BEC
+		X"00000000", -- 00001BF0
+		X"00000000", -- 00001BF4
+		X"00000000", -- 00001BF8
+		X"00000000", -- 00001BFC
+		X"00000000", -- 00001C00
+		X"00000000", -- 00001C04
+		X"00000000", -- 00001C08
+		X"00000000", -- 00001C0C
+		X"00000000", -- 00001C10
+		X"00000000", -- 00001C14
+		X"00000000", -- 00001C18
+		X"00000000", -- 00001C1C
+		X"00000000", -- 00001C20
+		X"00000000", -- 00001C24
+		X"00000000", -- 00001C28
+		X"00000000", -- 00001C2C
+		X"00000000", -- 00001C30
+		X"00000000", -- 00001C34
+		X"00000000", -- 00001C38
+		X"00000000", -- 00001C3C
+		X"00000000", -- 00001C40
+		X"00000000", -- 00001C44
+		X"00000000", -- 00001C48
+		X"00000000", -- 00001C4C
+		X"00000000", -- 00001C50
+		X"00000000", -- 00001C54
+		X"00000000", -- 00001C58
+		X"00000000", -- 00001C5C
+		X"00000000", -- 00001C60
+		X"00000000", -- 00001C64
+		X"00000000", -- 00001C68
+		X"00000000", -- 00001C6C
+		X"00000000", -- 00001C70
+		X"00000000", -- 00001C74
+		X"00000000", -- 00001C78
+		X"00000000", -- 00001C7C
+		X"00000000", -- 00001C80
+		X"00000000", -- 00001C84
+		X"00000000", -- 00001C88
+		X"00000000", -- 00001C8C
+		X"00000000", -- 00001C90
+		X"00000000", -- 00001C94
+		X"00000000", -- 00001C98
+		X"00000000", -- 00001C9C
+		X"00000000", -- 00001CA0
+		X"00000000", -- 00001CA4
+		X"00000000", -- 00001CA8
+		X"00000000", -- 00001CAC
+		X"00000000", -- 00001CB0
+		X"00000000", -- 00001CB4
+		X"00000000", -- 00001CB8
+		X"00000000", -- 00001CBC
+		X"00000000", -- 00001CC0
+		X"00000000", -- 00001CC4
+		X"00000000", -- 00001CC8
+		X"00000000", -- 00001CCC
+		X"00000000", -- 00001CD0
+		X"00000000", -- 00001CD4
+		X"00000000", -- 00001CD8
+		X"00000000", -- 00001CDC
+		X"00000000", -- 00001CE0
+		X"00000000", -- 00001CE4
+		X"00000000", -- 00001CE8
+		X"00000000", -- 00001CEC
+		X"00000000", -- 00001CF0
+		X"00000000", -- 00001CF4
+		X"00000000", -- 00001CF8
+		X"00000000", -- 00001CFC
+		X"00000000", -- 00001D00
+		X"00000000", -- 00001D04
+		X"00000000", -- 00001D08
+		X"00000000", -- 00001D0C
+		X"00000000", -- 00001D10
+		X"00000000", -- 00001D14
+		X"00000000", -- 00001D18
+		X"00000000", -- 00001D1C
+		X"00000000", -- 00001D20
+		X"00000000", -- 00001D24
+		X"00000000", -- 00001D28
+		X"00000000", -- 00001D2C
+		X"00000000", -- 00001D30
+		X"00000000", -- 00001D34
+		X"00000000", -- 00001D38
+		X"00000000", -- 00001D3C
+		X"00000000", -- 00001D40
+		X"00000000", -- 00001D44
+		X"00000000", -- 00001D48
+		X"00000000", -- 00001D4C
+		X"00000000", -- 00001D50
+		X"00000000", -- 00001D54
+		X"00000000", -- 00001D58
+		X"00000000", -- 00001D5C
+		X"00000000", -- 00001D60
+		X"00000000", -- 00001D64
+		X"00000000", -- 00001D68
+		X"00000000", -- 00001D6C
+		X"00000000", -- 00001D70
+		X"00000000", -- 00001D74
+		X"00000000", -- 00001D78
+		X"00000000", -- 00001D7C
+		X"00000000", -- 00001D80
+		X"00000000", -- 00001D84
+		X"00000000", -- 00001D88
+		X"00000000", -- 00001D8C
+		X"00000000", -- 00001D90
+		X"00000000", -- 00001D94
+		X"00000000", -- 00001D98
+		X"00000000", -- 00001D9C
+		X"00000000", -- 00001DA0
+		X"00000000", -- 00001DA4
+		X"00000000", -- 00001DA8
+		X"00000000", -- 00001DAC
+		X"00000000", -- 00001DB0
+		X"00000000", -- 00001DB4
+		X"00000000", -- 00001DB8
+		X"00000000", -- 00001DBC
+		X"00000000", -- 00001DC0
+		X"00000000", -- 00001DC4
+		X"00000000", -- 00001DC8
+		X"00000000", -- 00001DCC
+		X"00000000", -- 00001DD0
+		X"00000000", -- 00001DD4
+		X"00000000", -- 00001DD8
+		X"00000000", -- 00001DDC
+		X"00000000", -- 00001DE0
+		X"00000000", -- 00001DE4
+		X"00000000", -- 00001DE8
+		X"00000000", -- 00001DEC
+		X"00000000", -- 00001DF0
+		X"00000000", -- 00001DF4
+		X"00000000", -- 00001DF8
+		X"00000000", -- 00001DFC
+		X"00000000", -- 00001E00
+		X"00000000", -- 00001E04
+		X"00000000", -- 00001E08
+		X"00000000", -- 00001E0C
+		X"00000000", -- 00001E10
+		X"00000000", -- 00001E14
+		X"00000000", -- 00001E18
+		X"00000000", -- 00001E1C
+		X"00000000", -- 00001E20
+		X"00000000", -- 00001E24
+		X"00000000", -- 00001E28
+		X"00000000", -- 00001E2C
+		X"00000000", -- 00001E30
+		X"00000000", -- 00001E34
+		X"00000000", -- 00001E38
+		X"00000000", -- 00001E3C
+		X"00000000", -- 00001E40
+		X"00000000", -- 00001E44
+		X"00000000", -- 00001E48
+		X"00000000", -- 00001E4C
+		X"00000000", -- 00001E50
+		X"00000000", -- 00001E54
+		X"00000000", -- 00001E58
+		X"00000000", -- 00001E5C
+		X"00000000", -- 00001E60
+		X"00000000", -- 00001E64
+		X"00000000", -- 00001E68
+		X"00000000", -- 00001E6C
+		X"00000000", -- 00001E70
+		X"00000000", -- 00001E74
+		X"00000000", -- 00001E78
+		X"00000000", -- 00001E7C
+		X"00000000", -- 00001E80
+		X"00000000", -- 00001E84
+		X"00000000", -- 00001E88
+		X"00000000", -- 00001E8C
+		X"00000000", -- 00001E90
+		X"00000000", -- 00001E94
+		X"00000000", -- 00001E98
+		X"00000000", -- 00001E9C
+		X"00000000", -- 00001EA0
+		X"00000000", -- 00001EA4
+		X"00000000", -- 00001EA8
+		X"00000000", -- 00001EAC
+		X"00000000", -- 00001EB0
+		X"00000000", -- 00001EB4
+		X"00000000", -- 00001EB8
+		X"00000000", -- 00001EBC
+		X"00000000", -- 00001EC0
+		X"00000000", -- 00001EC4
+		X"00000000", -- 00001EC8
+		X"00000000", -- 00001ECC
+		X"00000000", -- 00001ED0
+		X"00000000", -- 00001ED4
+		X"00000000", -- 00001ED8
+		X"00000000", -- 00001EDC
+		X"00000000", -- 00001EE0
+		X"00000000", -- 00001EE4
+		X"00000000", -- 00001EE8
+		X"00000000", -- 00001EEC
+		X"00000000", -- 00001EF0
+		X"00000000", -- 00001EF4
+		X"00000000", -- 00001EF8
+		X"00000000", -- 00001EFC
+		X"00000000", -- 00001F00
+		X"00000000", -- 00001F04
+		X"00000000", -- 00001F08
+		X"00000000", -- 00001F0C
+		X"00000000", -- 00001F10
+		X"00000000", -- 00001F14
+		X"00000000", -- 00001F18
+		X"00000000", -- 00001F1C
+		X"00000000", -- 00001F20
+		X"00000000", -- 00001F24
+		X"00000000", -- 00001F28
+		X"00000000", -- 00001F2C
+		X"00000000", -- 00001F30
+		X"00000000", -- 00001F34
+		X"00000000", -- 00001F38
+		X"00000000", -- 00001F3C
+		X"00000000", -- 00001F40
+		X"00000000", -- 00001F44
+		X"00000000", -- 00001F48
+		X"00000000", -- 00001F4C
+		X"00000000", -- 00001F50
+		X"00000000", -- 00001F54
+		X"00000000", -- 00001F58
+		X"00000000", -- 00001F5C
+		X"00000000", -- 00001F60
+		X"00000000", -- 00001F64
+		X"00000000", -- 00001F68
+		X"00000000", -- 00001F6C
+		X"00000000", -- 00001F70
+		X"00000000", -- 00001F74
+		X"00000000", -- 00001F78
+		X"00000000", -- 00001F7C
+		X"00000000", -- 00001F80
+		X"00000000", -- 00001F84
+		X"00000000", -- 00001F88
+		X"00000000", -- 00001F8C
+		X"00000000", -- 00001F90
+		X"00000000", -- 00001F94
+		X"00000000", -- 00001F98
+		X"00000000", -- 00001F9C
+		X"00000000", -- 00001FA0
+		X"00000000", -- 00001FA4
+		X"00000000", -- 00001FA8
+		X"00000000", -- 00001FAC
+		X"00000000", -- 00001FB0
+		X"00000000", -- 00001FB4
+		X"00000000", -- 00001FB8
+		X"00000000", -- 00001FBC
+		X"00000000", -- 00001FC0
+		X"00000000", -- 00001FC4
+		X"00000000", -- 00001FC8
+		X"00000000", -- 00001FCC
+		X"00000000", -- 00001FD0
+		X"00000000", -- 00001FD4
+		X"00000000", -- 00001FD8
+		X"00000000", -- 00001FDC
+		X"00000000", -- 00001FE0
+		X"00000000", -- 00001FE4
+		X"00000000", -- 00001FE8
+		X"00000000", -- 00001FEC
+		X"00000000", -- 00001FF0
+		X"00000000", -- 00001FF4
+		X"00000000", -- 00001FF8
+		X"00000000"  -- 00001FFC
+	);
+
+begin
+
+PROM_READ:
+	process(clk)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= word_array(to_integer(addr(12 downto 2)));
+		end if;
+	end process;
+
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
+	jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;	
+	
+			end if;
+		end if;
+	end process;
+
+PROM_WRITE:
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				word_array(to_integer(jtag_ld_addr(10 downto 0))) <= jtag_ld_din;
+			else
+				jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(10 downto 0)));
+			end if;
+		end if;
+	end process;
+
+end data;
diff --git a/lib/CPUs/MIPS/src/irom_hello.vhd b/lib/CPUs/MIPS/src/irom_hello.vhd
new file mode 100644
index 0000000..21ee2eb
--- /dev/null
+++ b/lib/CPUs/MIPS/src/irom_hello.vhd
@@ -0,0 +1,320 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY rom IS
+	Generic 
+	(
+		addr_width 	: integer := 2;
+		data_width 	: integer := 32
+	);
+	Port 
+	(
+		clk			: in  STD_LOGIC;
+		addr		: in  unsigned(addr_width-1 downto 0);
+		dout		: out unsigned(data_width-1 downto 0)
+	);
+END rom;
+
+ARCHITECTURE itest OF rom IS 
+	
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to 2**addr_width-1) of word_t;
+
+	-- Assembled from itest.jsm
+	constant word_array : word_array_t :=
+	(
+		X"3C1D7FFF", -- 00000000
+		X"0C100014", -- 00000004
+		X"37BDEFFC", -- 00000008
+		X"24080002", -- 0000000C
+		X"0107102A", -- 00000010
+		X"ACC40000", -- 00000014
+		X"1040000B", -- 00000018
+		X"ACC50004", -- 0000001C
+		X"24C60008", -- 00000020
+		X"24E8FFFE", -- 00000024
+		X"8CC2FFF8", -- 00000028
+		X"8CC3FFFC", -- 0000002C
+		X"2508FFFF", -- 00000030
+		X"00431021", -- 00000034
+		X"ACC20000", -- 00000038
+		X"1500FFFA", -- 0000003C
+		X"24C60004", -- 00000040
+		X"00E04021", -- 00000044
+		X"03E00008", -- 00000048
+		X"01001021", -- 0000004C
+		X"27BDFF78", -- 00000050
+		X"3C021003", -- 00000054
+		X"3C030001", -- 00000058
+		X"AFB60078", -- 0000005C
+		X"3456FFFC", -- 00000060
+		X"3C02AAAA", -- 00000064
+		X"AFB7007C", -- 00000068
+		X"AFB50074", -- 0000006C
+		X"AFB40070", -- 00000070
+		X"AFB20068", -- 00000074
+		X"AFB00060", -- 00000078
+		X"AFBF0080", -- 0000007C
+		X"AFB3006C", -- 00000080
+		X"AFB10064", -- 00000084
+		X"AEC00000", -- 00000088
+		X"3450AAAA", -- 0000008C
+		X"347786A0", -- 00000090
+		X"27B20010", -- 00000094
+		X"24150014", -- 00000098
+		X"3474869F", -- 0000009C
+		X"00009821", -- 000000A0
+		X"00002021", -- 000000A4
+		X"02401021", -- 000000A8
+		X"24060013", -- 000000AC
+		X"24C6FFFF", -- 000000B0
+		X"AC500000", -- 000000B4
+		X"04C1FFFD", -- 000000B8
+		X"24420004", -- 000000BC
+		X"02041026", -- 000000C0
+		X"24910001", -- 000000C4
+		X"24420001", -- 000000C8
+		X"02202821", -- 000000CC
+		X"27A60010", -- 000000D0
+		X"24070014", -- 000000D4
+		X"0C100003", -- 000000D8
+		X"00028040", -- 000000DC
+		X"24070002", -- 000000E0
+		X"26450008", -- 000000E4
+		X"0810003E", -- 000000E8
+		X"24060011", -- 000000EC
+		X"04C0000A", -- 000000F0
+		X"00000000", -- 000000F4
+		X"8CA20000", -- 000000F8
+		X"8CA3FFFC", -- 000000FC
+		X"8CA4FFF8", -- 00000100
+		X"00431023", -- 00000104
+		X"24C6FFFF", -- 00000108
+		X"1482FFF8", -- 0000010C
+		X"24A50004", -- 00000110
+		X"04C1FFF8", -- 00000114
+		X"24E70001", -- 00000118
+		X"10F5000C", -- 0000011C
+		X"00000000", -- 00000120
+		X"0291102A", -- 00000124
+		X"1040FFDF", -- 00000128
+		X"02202021", -- 0000012C
+		X"1677FFDB", -- 00000130
+		X"00009821", -- 00000134
+		X"8EC20000", -- 00000138
+		X"00000000", -- 0000013C
+		X"24420001", -- 00000140
+		X"AEC20000", -- 00000144
+		X"0810002A", -- 00000148
+		X"00002021", -- 0000014C
+		X"08100049", -- 00000150
+		X"26730001", -- 00000154
+		X"00000000", -- 00000158
+		X"00000000", -- 0000015C
+		X"00000000", -- 00000160
+		X"00000000", -- 00000164
+		X"00000000", -- 00000168
+		X"00000000", -- 0000016C
+		X"00000000", -- 00000170
+		X"00000000", -- 00000174
+		X"00000000", -- 00000178
+		X"00000000", -- 0000017C
+		X"00000000", -- 00000180
+		X"00000000", -- 00000184
+		X"00000000", -- 00000188
+		X"00000000", -- 0000018C
+		X"00000000", -- 00000190
+		X"00000000", -- 00000194
+		X"00000000", -- 00000198
+		X"00000000", -- 0000019C
+		X"00000000", -- 000001A0
+		X"00000000", -- 000001A4
+		X"00000000", -- 000001A8
+		X"00000000", -- 000001AC
+		X"00000000", -- 000001B0
+		X"00000000", -- 000001B4
+		X"00000000", -- 000001B8
+		X"00000000", -- 000001BC
+		X"00000000", -- 000001C0
+		X"00000000", -- 000001C4
+		X"00000000", -- 000001C8
+		X"00000000", -- 000001CC
+		X"00000000", -- 000001D0
+		X"00000000", -- 000001D4
+		X"00000000", -- 000001D8
+		X"00000000", -- 000001DC
+		X"00000000", -- 000001E0
+		X"00000000", -- 000001E4
+		X"00000000", -- 000001E8
+		X"00000000", -- 000001EC
+		X"00000000", -- 000001F0
+		X"00000000", -- 000001F4
+		X"00000000", -- 000001F8
+		X"00000000", -- 000001FC
+		X"00000000", -- 00000200
+		X"00000000", -- 00000204
+		X"00000000", -- 00000208
+		X"00000000", -- 0000020C
+		X"00000000", -- 00000210
+		X"00000000", -- 00000214
+		X"00000000", -- 00000218
+		X"00000000", -- 0000021C
+		X"00000000", -- 00000220
+		X"00000000", -- 00000224
+		X"00000000", -- 00000228
+		X"00000000", -- 0000022C
+		X"00000000", -- 00000230
+		X"00000000", -- 00000234
+		X"00000000", -- 00000238
+		X"00000000", -- 0000023C
+		X"00000000", -- 00000240
+		X"00000000", -- 00000244
+		X"00000000", -- 00000248
+		X"00000000", -- 0000024C
+		X"00000000", -- 00000250
+		X"00000000", -- 00000254
+		X"00000000", -- 00000258
+		X"00000000", -- 0000025C
+		X"00000000", -- 00000260
+		X"00000000", -- 00000264
+		X"00000000", -- 00000268
+		X"00000000", -- 0000026C
+		X"00000000", -- 00000270
+		X"00000000", -- 00000274
+		X"00000000", -- 00000278
+		X"00000000", -- 0000027C
+		X"00000000", -- 00000280
+		X"00000000", -- 00000284
+		X"00000000", -- 00000288
+		X"00000000", -- 0000028C
+		X"00000000", -- 00000290
+		X"00000000", -- 00000294
+		X"00000000", -- 00000298
+		X"00000000", -- 0000029C
+		X"00000000", -- 000002A0
+		X"00000000", -- 000002A4
+		X"00000000", -- 000002A8
+		X"00000000", -- 000002AC
+		X"00000000", -- 000002B0
+		X"00000000", -- 000002B4
+		X"00000000", -- 000002B8
+		X"00000000", -- 000002BC
+		X"00000000", -- 000002C0
+		X"00000000", -- 000002C4
+		X"00000000", -- 000002C8
+		X"00000000", -- 000002CC
+		X"00000000", -- 000002D0
+		X"00000000", -- 000002D4
+		X"00000000", -- 000002D8
+		X"00000000", -- 000002DC
+		X"00000000", -- 000002E0
+		X"00000000", -- 000002E4
+		X"00000000", -- 000002E8
+		X"00000000", -- 000002EC
+		X"00000000", -- 000002F0
+		X"00000000", -- 000002F4
+		X"00000000", -- 000002F8
+		X"00000000", -- 000002FC
+		X"00000000", -- 00000300
+		X"00000000", -- 00000304
+		X"00000000", -- 00000308
+		X"00000000", -- 0000030C
+		X"00000000", -- 00000310
+		X"00000000", -- 00000314
+		X"00000000", -- 00000318
+		X"00000000", -- 0000031C
+		X"00000000", -- 00000320
+		X"00000000", -- 00000324
+		X"00000000", -- 00000328
+		X"00000000", -- 0000032C
+		X"00000000", -- 00000330
+		X"00000000", -- 00000334
+		X"00000000", -- 00000338
+		X"00000000", -- 0000033C
+		X"00000000", -- 00000340
+		X"00000000", -- 00000344
+		X"00000000", -- 00000348
+		X"00000000", -- 0000034C
+		X"00000000", -- 00000350
+		X"00000000", -- 00000354
+		X"00000000", -- 00000358
+		X"00000000", -- 0000035C
+		X"00000000", -- 00000360
+		X"00000000", -- 00000364
+		X"00000000", -- 00000368
+		X"00000000", -- 0000036C
+		X"00000000", -- 00000370
+		X"00000000", -- 00000374
+		X"00000000", -- 00000378
+		X"00000000", -- 0000037C
+		X"00000000", -- 00000380
+		X"00000000", -- 00000384
+		X"00000000", -- 00000388
+		X"00000000", -- 0000038C
+		X"00000000", -- 00000390
+		X"00000000", -- 00000394
+		X"00000000", -- 00000398
+		X"00000000", -- 0000039C
+		X"00000000", -- 000003A0
+		X"00000000", -- 000003A4
+		X"00000000", -- 000003A8
+		X"00000000", -- 000003AC
+		X"00000000", -- 000003B0
+		X"00000000", -- 000003B4
+		X"00000000", -- 000003B8
+		X"00000000", -- 000003BC
+		X"00000000", -- 000003C0
+		X"00000000", -- 000003C4
+		X"00000000", -- 000003C8
+		X"00000000", -- 000003CC
+		X"00000000", -- 000003D0
+		X"00000000", -- 000003D4
+		X"00000000", -- 000003D8
+		X"00000000", -- 000003DC
+		X"00000000", -- 000003E0
+		X"00000000", -- 000003E4
+		X"00000000", -- 000003E8
+		X"00000000", -- 000003EC
+		X"00000000", -- 000003F0
+		X"00000000", -- 000003F4
+		X"00000000", -- 000003F8
+		X"00000000"  -- 000003FC
+	);
+
+begin
+
+PROM_READ:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			dout <= word_array(to_integer(addr));
+		end if;
+	end process;
+
+
+end itest;
diff --git a/lib/CPUs/MIPS/src/irom_test1.vhd b/lib/CPUs/MIPS/src/irom_test1.vhd
new file mode 100644
index 0000000..24007c4
--- /dev/null
+++ b/lib/CPUs/MIPS/src/irom_test1.vhd
@@ -0,0 +1,121 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY rom IS
+	Generic 
+	(
+		addr_width 	: integer := 2;
+		data_width 	: integer := 32
+	);
+	Port 
+	(
+		addr		: in  unsigned(addr_width-1 downto 0);
+		dout		: out unsigned(data_width-1 downto 0)
+	);
+END rom;
+
+ARCHITECTURE itest OF rom IS 
+	
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to 2**addr_width-1) of word_t;
+
+	-- Assembled from itest.jsm
+	constant word_array : word_array_t :=
+	(
+		X"08100001", --	[0x00400000]	j 0x00400004 [main]              
+		X"3c011234", --	[0x00400004]	lui $1, 4660                    
+		X"34215678", --	[0x00400008]	ori $1, $1, 22136                
+		X"3021f00f", --	[0x0040000c]	andi $1, $1, -4081              
+		X"2021affc", --	[0x00400010]	addi $1, $1, -20484              
+		X"2021ffff", --	[0x00400014]	addi $1, $1, -1                 
+		X"1c20fffe", --	[0x00400018]	bgtz $1 -8 [loop-0x00400018]     
+		X"3c020000", --	[0x0040001c]	lui $2, 0                       
+		X"34420001", --	[0x00400020]	ori $2, $2, 1                    
+		X"3c010000", --	[0x00400024]	lui $1, 0                        
+		X"34210004", --	[0x00400028]	ori $1, $1, 4                    
+		X"00220822", --	[0x0040002c]	sub $1, $1, $2                   
+		X"1c20fffe", --	[0x00400030]	bgtz $1 -8 [loop2-0x00400030]    
+		X"3c1f0040", --	[0x00400034]	lui $31, 64                      
+		X"03e00008", --	[0x00400038]	jr $31                           
+		X"00000000", --	[0x0040003c]	nop                              
+		X"00000000", --	[0x00400040]	nop
+		X"00000000", --	[0x00400044]	nop   
+		X"00000000", --	[0x00400048]	nop  
+		X"00000000", --	[0x0040004c]	nop   
+		X"00000000", --	[0x00400050]	nop   
+		X"00000000", --	[0x00400054]	nop   
+		X"00000000", --	[0x00400058]	nop   
+		X"00000000", --	[0x0040005c]	nop  
+		X"00000000", --	[0x00400060]	nop  
+		X"00000000", --	[0x00400064]	nop  
+		X"00000000", --	[0x00400068]	nop  
+		X"00000000", --	[0x0040006c]	nop    
+		X"00000000", --	[0x00400070]	nop    
+		X"00000000", --	[0x00400074]	nop    
+		X"00000000", --	[0x00400078]	nop    
+		X"00000000", --	[0x0040007c]	nop    
+		X"00000000", --	[0x00400080]	nop    
+		X"00000000", --	[0x00400084]	nop    
+		X"00000000", --	[0x00400088]	nop    
+		X"00000000", --	[0x0040008c]	nop    
+		X"00000000", --	[0x00400090]	nop    
+		X"00000000", --	[0x00400094]	nop    
+		X"00000000", --	[0x00400098]	nop    
+		X"00000000", --	[0x0040009c]	nop    
+		X"00000000", --	[0x004000a0]	nop    
+		X"00000000", --	[0x004000a4]	nop    
+		X"00000000", --	[0x004000a8]	nop    
+		X"00000000", --	[0x004000ac]	nop
+		X"00000000", --	[0x004000b0]	nop
+		X"00000000", --	[0x004000b4]	nop
+		X"00000000", --	[0x004000b8]	nop
+		X"00000000", --	[0x004000bc]	nop
+		X"00000000", --	[0x004000c0]	nop
+		X"00000000", --	[0x004000c4]	nop
+		X"00000000", --	[0x004000c8]	nop
+		X"00000000", --	[0x004000cc]	nop
+		X"00000000", --	[0x004000d0]	nop
+		X"00000000", --	[0x004000d4]	nop
+		X"00000000", --	[0x004000d8]	nop
+		X"00000000", --	[0x004000dc]	nop
+		X"00000000", --	[0x004000e0]	nop
+		X"00000000", --	[0x004000e4]	nop
+		X"00000000", --	[0x004000e8]	nop
+		X"00000000", --	[0x004000ec]	nop
+		X"00000000", --	[0x004000f0]	nop
+		X"00000000", --	[0x004000f4]	nop
+		X"00000000", --	[0x004000f8]	nop
+		X"00000000"  --	[0x004000fc]	nop
+	);
+
+begin
+
+PROM_READ:
+	dout <= word_array(to_integer(addr));
+
+end itest;
diff --git a/lib/CPUs/MIPS/src/irom_test2.vhd b/lib/CPUs/MIPS/src/irom_test2.vhd
new file mode 100644
index 0000000..289c9f9
--- /dev/null
+++ b/lib/CPUs/MIPS/src/irom_test2.vhd
@@ -0,0 +1,73 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY rom IS
+	Generic 
+	(
+		addr_width 	: integer := 2;
+		data_width 	: integer := 32
+	);
+	Port 
+	(
+		addr		: in  unsigned(addr_width-1 downto 0);
+		dout		: out unsigned(data_width-1 downto 0)
+	);
+END rom;
+
+ARCHITECTURE itest OF rom IS 
+	
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to 2**addr_width-1) of word_t;
+
+	-- Assembled from itest.jsm
+	constant word_array : word_array_t :=
+	(
+		X"08100001", -- j 0x00400004 [main]             ; 5: j main
+		X"3c011234", --	lui $1, 4660                    ; 7: lui $1, 0x1234
+		X"34215678", --	ori $1, $1, 22136               ; 8: ori $1, $1, 0x5678
+		X"3c035555", --	lui $3, 21845                   ; 9: lui $3, 0x5555
+		X"3463aaaa", --	ori $3, $3, -21846              ; 10: ori $3, $3, 0xAAAA
+		X"3c021000", --	lui $2, 4096                    ; 11: lui $2, 0x1000
+		X"ac410000", --	sw $1, 0($2)                    ; 12: sw	$1, 0($2)
+		X"ac430004", --	sw $3, 4($2)                    ; 13: sw	$3, 4($2)
+		X"00000000", --	nop                             ; 14: sll $0, $0, 0
+		X"ac400000", --	sw $0, 0($2)                    ; 15: sw	$0, 0($2)
+		X"ac400004", --	sw $0, 4($2)                    ; 16: sw	$0, 4($2)
+		X"8c410000", --	lw $1, 0($2)                    ; 17: lw  $1, 0($2)
+		X"8c430004", --	lw $3, 4($2)                    ; 18: lw  $3, 4($2)
+		X"00000000", --	nop                             ; 19: sll $0, $0, 0
+		X"00000000", --	nop                             ; 20: sll $0, $0, 0
+		X"08100001"	 --	j 0x00400004 [main]             ; 21: j   main
+	);
+
+begin
+
+PROM_READ:
+	dout <= word_array(to_integer(addr));
+
+end itest;
diff --git a/lib/CPUs/MIPS/src/irom_test3.vhd b/lib/CPUs/MIPS/src/irom_test3.vhd
new file mode 100644
index 0000000..7d53d2a
--- /dev/null
+++ b/lib/CPUs/MIPS/src/irom_test3.vhd
@@ -0,0 +1,122 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY rom IS
+	Generic 
+	(
+		addr_width 	: integer := 2;
+		data_width 	: integer := 32
+	);
+	Port 
+	(
+		addr		: in  unsigned(addr_width-1 downto 0);
+		dout		: out unsigned(data_width-1 downto 0)
+	);
+END rom;
+
+ARCHITECTURE itest OF rom IS 
+	
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to 2**addr_width-1) of word_t;
+
+	-- Assembled from itest.jsm
+	constant word_array : word_array_t :=
+	(
+
+		X"08100001", --	[0x00400000]	j 0x00400004 [main]               
+		X"3c011234", --	[0x00400004]	lui $1, 4660       
+		X"34215a5a", --	[0x00400008]	ori $1, $1, 23130                 
+		X"00010840", --	[0x0040000c]	sll $1, $1, 1      
+		X"00010900", --	[0x00400010]	sll $1, $1, 4                     
+		X"00010880", --	[0x00400014]	sll $1, $1, 2      
+		X"00010840", --	[0x00400018]	sll $1, $1, 1                     
+		X"00010a00", --	[0x0040001c]	sll $1, $1, 8      
+		X"00010882", --	[0x00400020]	srl $1, $1, 2                  
+		X"00010942", --	[0x00400024]	srl $1, $1, 5                  
+		X"00010842", --	[0x00400028]	srl $1, $1, 1                  
+		X"00010a02", --	[0x0040002c]	srl $1, $1, 8                  
+		X"3821ffff", --	[0x00400030]	xori $1, $1, -1                
+		X"3c1f0040", --	[0x00400034]	lui $31, 64                    
+		X"03e00008", --	[0x00400038]	jr $31                         
+		X"003f0826", --	[0x0040003c]	xor $1, $1, $31                
+		X"00000000", --	[0x00400040]	nop             
+		X"00000000", --	[0x00400044]	nop             
+		X"00000000", --	[0x00400048]	nop             
+		X"00000000", --	[0x0040004c]	nop             
+		X"00000000", --	[0x00400050]	nop             
+		X"00000000", --	[0x00400054]	nop             
+		X"00000000", --	[0x00400058]	nop             
+		X"00000000", --	[0x0040005c]	nop             
+		X"00000000", --	[0x00400060]	nop             
+		X"00000000", --	[0x00400064]	nop             
+		X"00000000", --	[0x00400068]	nop             
+		X"00000000", --	[0x0040006c]	nop             
+		X"00000000", --	[0x00400070]	nop             
+		X"00000000", --	[0x00400074]	nop             
+		X"00000000", --	[0x00400078]	nop             
+		X"00000000", --	[0x0040007c]	nop             
+		X"00000000", --	[0x00400080]	nop              
+		X"00000000", --	[0x00400084]	nop              
+		X"00000000", --	[0x00400088]	nop              
+		X"00000000", --	[0x0040008c]	nop              
+		X"00000000", --	[0x00400090]	nop              
+		X"00000000", --	[0x00400094]	nop              
+		X"00000000", --	[0x00400098]	nop
+		X"00000000", --	[0x0040009c]	nop
+		X"00000000", --	[0x004000a0]	nop               
+		X"00000000", --	[0x004000a4]	nop              
+		X"00000000", --	[0x004000a8]	nop              
+		X"00000000", --	[0x004000ac]	nop                              
+		X"00000000", --	[0x004000b0]	nop              
+		X"00000000", --	[0x004000b4]	nop                              
+		X"00000000", --	[0x004000b8]
+		X"00000000", --	[0x004000bc]
+		X"00000000", --	[0x004000c0]
+		X"00000000", --	[0x004000c4]
+		X"00000000", --	[0x004000c8]
+		X"00000000", --	[0x004000cc]
+		X"00000000", --	[0x004000d0]
+		X"00000000", --	[0x004000d4]
+		X"00000000", --	[0x004000d8]
+		X"00000000", --	[0x004000dc]
+		X"00000000", --	[0x004000e0]
+		X"00000000", --	[0x004000e4]
+		X"00000000", --	[0x004000e8]
+		X"00000000", --	[0x004000ec]
+		X"00000000", --	[0x004000f0]
+		X"00000000", --	[0x004000f4]
+		X"00000000", --	[0x004000f8]
+		X"00000000"  --	[0x004000fc]
+	);
+
+begin
+
+PROM_READ:
+	dout <= word_array(to_integer(addr));
+
+end itest;
diff --git a/lib/CPUs/MIPS/src/irom_test4.vhd b/lib/CPUs/MIPS/src/irom_test4.vhd
new file mode 100644
index 0000000..bbce904
--- /dev/null
+++ b/lib/CPUs/MIPS/src/irom_test4.vhd
@@ -0,0 +1,122 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY rom IS
+	Generic 
+	(
+		addr_width 	: integer := 2;
+		data_width 	: integer := 32
+	);
+	Port 
+	(
+		addr		: in  unsigned(addr_width-1 downto 0);
+		dout		: out unsigned(data_width-1 downto 0)
+	);
+END rom;
+
+ARCHITECTURE itest OF rom IS 
+	
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to 2**addr_width-1) of word_t;
+
+	-- Assembled from itest.jsm
+	constant word_array : word_array_t :=
+	(
+		
+		X"08100001", --	[0x00400000]	j 0x00400004 [main]             ; 5: j main
+		X"00000000", --	[0x00400004]	nop                             ; 7: sll $0, $0, 0
+		X"3c011000", --	[0x00400008]	lui $1, 4096                    ; 8: lui $1, 0x1000
+		X"20220000", --	[0x0040000c]	addi $2, $1, 0                  ; 9: addi $2, $1, 0
+		X"3c071234", --	[0x00400010]	lui $7, 4660                    ; 10: lui $7, 0x1234
+		X"3c050001", --	[0x00400014]	lui $5, 1                       ; 11: lui $5, 0x0001
+		X"ac270000", --	[0x00400018]	sw $7, 0($1)                    ; 12: sw	$7, 0($1)
+		X"8c430000", --	[0x0040001c]	lw $3, 0($2)                    ; 13: lw  $3, 0($2)
+		X"00654020", --	[0x00400020]	add $8, $3, $5                  ; 14: add $8, $3, $5
+		X"00654820", --	[0x00400024]	add $9, $3, $5                  ; 15: add $9, $3, $5
+		X"00655020", --	[0x00400028]	add $10, $3, $5                 ; 16: add $10, $3, $5
+		X"00655820", --	[0x0040002c]	add $11, $3, $5                 ; 17: add $11, $3, $5
+		X"00000000", --	[0x00400030]	nop                             ; 18: sll $0, $0, 0
+		X"00000000", --	[0x00400034]	nop                             ; 19: sll $0, $0, 0
+		X"08100001", --	[0x00400038]	j 0x00400004 [main]             ; 20: j   main
+		X"00000000", --	[0x0040003c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400040]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400044]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400048]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x0040004c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400050]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400054]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400058]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x0040005c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400060]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400064]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400068]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x0040006c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400070]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400074]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400078]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x0040007c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400080]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400084]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400088]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x0040008c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400090]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400094]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400098]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x0040009c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000a0]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000a4]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000a8]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000ac]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000b0]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000b4]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000b8]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000bc]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000c0]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000c4]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000c8]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000cc]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000d0]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000d4]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000d8]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000dc]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000e0]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000e4]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000e8]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000ec]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000f0]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000f4]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000f8]	nop                             ; 21: sll $0, $0, 0
+		X"00000000"  --	[0x004000fc]	nop                             ; 21: sll $0, $0, 0
+	);
+
+begin
+
+PROM_READ:
+	dout <= word_array(to_integer(addr));
+
+end itest;
diff --git a/lib/CPUs/MIPS/src/irom_test5.vhd b/lib/CPUs/MIPS/src/irom_test5.vhd
new file mode 100644
index 0000000..490bdd9
--- /dev/null
+++ b/lib/CPUs/MIPS/src/irom_test5.vhd
@@ -0,0 +1,122 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY rom IS
+	Generic 
+	(
+		addr_width 	: integer := 2;
+		data_width 	: integer := 32
+	);
+	Port 
+	(
+		addr		: in  unsigned(addr_width-1 downto 0);
+		dout		: out unsigned(data_width-1 downto 0)
+	);
+END rom;
+
+ARCHITECTURE itest OF rom IS 
+	
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to 2**addr_width-1) of word_t;
+
+	-- Assembled from itest.jsm
+	constant word_array : word_array_t :=
+	(
+
+		X"08100001", --	[0x00400000]	j 0x00400004 [main]               
+		X"3c018000", --	[0x00400004]	lui $1, -32768                   
+		X"3c020000", --	[0x00400008]	lui $2, 0                         
+		X"3c030000", --	[0x0040000c]	lui $3, 0                        
+		X"34420001", --	[0x00400010]	ori $2, $2, 1                     
+		X"34630003", --	[0x00400014]	ori $3, $3, 3                    
+		X"00010842", --	[0x00400018]	srl $1, $1, 1                     
+		X"00010840", --	[0x0040001c]	sll $1, $1, 1                    
+		X"00010843", --	[0x00400020]	sra $1, $1, 1                     
+		X"000108c3", --	[0x00400024]	sra $1, $1, 3                     
+		X"00612004", --	[0x00400028]	sllv $4, $1, $3                   
+		X"00412807", --	[0x0040002c]	srav $5, $1, $2                   
+		X"00613007", --	[0x00400030]	srav $6, $1, $3                   
+		X"3c1f0040", --	[0x00400034]	lui $31, 64                       
+		X"03e00008", --	[0x00400038]	jr $31                            
+		X"00000000", --	[0x0040003c]	nop                               
+		X"00000000", --	[0x00400040]	nop
+		X"00000000", --	[0x00400044]	nop   
+		X"00000000", --	[0x00400048]	nop  
+		X"00000000", --	[0x0040004c]	nop   
+		X"00000000", --	[0x00400050]	nop   
+		X"00000000", --	[0x00400054]	nop   
+		X"00000000", --	[0x00400058]	nop   
+		X"00000000", --	[0x0040005c]	nop  
+		X"00000000", --	[0x00400060]	nop  
+		X"00000000", --	[0x00400064]	nop  
+		X"00000000", --	[0x00400068]	nop  
+		X"00000000", --	[0x0040006c]	nop    
+		X"00000000", --	[0x00400070]	nop    
+		X"00000000", --	[0x00400074]	nop    
+		X"00000000", --	[0x00400078]	nop    
+		X"00000000", --	[0x0040007c]	nop    
+		X"00000000", --	[0x00400080]	nop    
+		X"00000000", --	[0x00400084]	nop    
+		X"00000000", --	[0x00400088]	nop    
+		X"00000000", --	[0x0040008c]	nop    
+		X"00000000", --	[0x00400090]	nop    
+		X"00000000", --	[0x00400094]	nop    
+		X"00000000", --	[0x00400098]	nop    
+		X"00000000", --	[0x0040009c]	nop    
+		X"00000000", --	[0x004000a0]	nop    
+		X"00000000", --	[0x004000a4]	nop    
+		X"00000000", --	[0x004000a8]	nop    
+		X"00000000", --	[0x004000ac]	nop
+		X"00000000", --	[0x004000b0]	nop
+		X"00000000", --	[0x004000b4]	nop
+		X"00000000", --	[0x004000b8]	nop
+		X"00000000", --	[0x004000bc]	nop
+		X"00000000", --	[0x004000c0]	nop
+		X"00000000", --	[0x004000c4]	nop
+		X"00000000", --	[0x004000c8]	nop
+		X"00000000", --	[0x004000cc]	nop
+		X"00000000", --	[0x004000d0]	nop
+		X"00000000", --	[0x004000d4]	nop
+		X"00000000", --	[0x004000d8]	nop
+		X"00000000", --	[0x004000dc]	nop
+		X"00000000", --	[0x004000e0]	nop
+		X"00000000", --	[0x004000e4]	nop
+		X"00000000", --	[0x004000e8]	nop
+		X"00000000", --	[0x004000ec]	nop
+		X"00000000", --	[0x004000f0]	nop
+		X"00000000", --	[0x004000f4]	nop
+		X"00000000", --	[0x004000f8]	nop
+		X"00000000"  --	[0x004000fc]	nop
+	);
+
+begin
+
+PROM_READ:
+	dout <= word_array(to_integer(addr));
+
+end itest;
diff --git a/lib/CPUs/MIPS/src/irom_test6.vhd b/lib/CPUs/MIPS/src/irom_test6.vhd
new file mode 100644
index 0000000..5231af8
--- /dev/null
+++ b/lib/CPUs/MIPS/src/irom_test6.vhd
@@ -0,0 +1,121 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY rom IS
+	Generic 
+	(
+		addr_width 	: integer := 2;
+		data_width 	: integer := 32
+	);
+	Port 
+	(
+		addr		: in  unsigned(addr_width-1 downto 0);
+		dout		: out unsigned(data_width-1 downto 0)
+	);
+END rom;
+
+ARCHITECTURE itest OF rom IS 
+	
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to 2**addr_width-1) of word_t;
+
+	-- Assembled from itest.jsm
+	constant word_array : word_array_t :=
+	(
+		X"08100001", --	[0x00400000]	j 0x00400004 [main]             ; 5: j main
+		X"3c080000", --	[0x00400004]	lui $8, 0                       ; 7: lui $8, 0
+		X"00000000", --	[0x00400008]	nop                             ; 8: sll $0, $0, 0	
+		X"0c100009", --	[0x0040000c]	jal 0x00400024 [subr1]          ; 9: jal subr1
+		X"3c010040", --	[0x00400010]	lui $1, 64 [subr2]              ; 10: la $2, subr2
+		X"34220030", --	[0x00400014]	ori $2, $1, 48 [subr2]
+		X"00407809", --	[0x00400018]	jalr $15, $2                    ; 11: jalr $15, $2
+		X"00000000", --	[0x0040001c]	nop                             ; 12: sll $0, $0, 0
+		X"08100002", --	[0x00400020]	j 0x00400008 [loop]             ; 13: j	loop
+		X"21080001", --	[0x00400024]	addi $8, $8, 1                  ; 15: addi $8, 1
+		X"00000000", --	[0x00400028]	nop                             ; 16: sll $0, $0, 0
+		X"03e00008", --	[0x0040002c]	jr $31                          ; 17: jr   $31
+		X"21080010", --	[0x00400030]	addi $8, $8, 16                 ; 18: addi $8, 16
+		X"00000000", --	[0x00400034]	nop                             ; 19: sll $0, $0, 0
+		X"01e00008", --	[0x00400038]	jr $15                          ; 20: jr   $15
+		X"00000000", --	[0x0040003c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400040]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400044]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400048]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x0040004c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400050]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400054]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400058]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x0040005c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400060]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400064]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400068]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x0040006c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400070]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400074]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400078]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x0040007c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400080]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400084]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400088]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x0040008c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400090]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400094]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x00400098]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x0040009c]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000a0]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000a4]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000a8]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000ac]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000b0]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000b4]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000b8]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000bc]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000c0]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000c4]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000c8]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000cc]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000d0]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000d4]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000d8]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000dc]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000e0]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000e4]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000e8]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000ec]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000f0]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000f4]	nop                             ; 21: sll $0, $0, 0
+		X"00000000", --	[0x004000f8]	nop                             ; 21: sll $0, $0, 0
+		X"00000000"  --	[0x004000fc]	nop                             ; 21: sll $0, $0, 0
+	);
+
+begin
+
+PROM_READ:
+	dout <= word_array(to_integer(addr));
+
+end itest;
diff --git a/lib/CPUs/MIPS/src/irom_test_addsub.vhd b/lib/CPUs/MIPS/src/irom_test_addsub.vhd
new file mode 100644
index 0000000..bbe764f
--- /dev/null
+++ b/lib/CPUs/MIPS/src/irom_test_addsub.vhd
@@ -0,0 +1,121 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY rom IS
+	Generic 
+	(
+		addr_width 	: integer := 2;
+		data_width 	: integer := 32
+	);
+	Port 
+	(
+		addr		: in  unsigned(addr_width-1 downto 0);
+		dout		: out unsigned(data_width-1 downto 0)
+	);
+END rom;
+
+ARCHITECTURE itest OF rom IS 
+	
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to 2**addr_width-1) of word_t;
+
+	-- Assembled from itest.jsm
+	constant word_array : word_array_t :=
+	(
+		X"3c011234", --	[0x00400000]	lui $1, 4660       
+		X"34225678", --	[0x00400004]	ori $2, $1, 22136
+		X"3c012345", --	[0x00400008]	lui $1, 9029       
+		X"34236789", --	[0x0040000c]	ori $3, $1, 26505
+		X"3c018765", --	[0x00400010]	lui $1, -30875     
+		X"34244321", --	[0x00400014]	ori $4, $1, 17185
+		X"3c019876", --	[0x00400018]	lui $1, -26506     
+		X"34255432", --	[0x0040001c]	ori $5, $1, 21554
+		X"00000000", --	[0x00400020]	nop                
+		X"00427823", --	[0x00400024]	subu $15, $2, $2   
+		X"00437823", --	[0x00400028]	subu $15, $2, $3   
+		X"00447823", --	[0x0040002c]	subu $15, $2, $4   
+		X"00457823", --	[0x00400030]	subu $15, $2, $5   
+		X"00627823", --	[0x00400034]	subu $15, $3, $2   
+		X"00637823", --	[0x00400038]	subu $15, $3, $3   
+		X"00647823", --	[0x0040003c]	subu $15, $3, $4   
+		X"00657823", --	[0x00400040]	subu $15, $3, $5   
+		X"00827823", --	[0x00400044]	subu $15, $4, $2   
+		X"00837823", --	[0x00400048]	subu $15, $4, $3   
+		X"00847823", --	[0x0040004c]	subu $15, $4, $4   
+		X"00857823", --	[0x00400050]	subu $15, $4, $5   
+		X"00a27823", --	[0x00400054]	subu $15, $5, $2   
+		X"00a37823", --	[0x00400058]	subu $15, $5, $3   
+		X"00a47823", --	[0x0040005c]	subu $15, $5, $4   
+		X"00a57823", --	[0x00400060]	subu $15, $5, $5   
+		X"00000000", --	[0x00400064]	nop                
+		X"00427822", --	[0x00400068]	sub $15, $2, $2    
+		X"00437822", --	[0x0040006c]	sub $15, $2, $3    
+		X"00447822", --	[0x00400070]	sub $15, $2, $4    
+		X"00457822", --	[0x00400074]	sub $15, $2, $5    
+		X"00627822", --	[0x00400078]	sub $15, $3, $2    
+		X"00637822", --	[0x0040007c]	sub $15, $3, $3    
+		X"00647822", --	[0x00400080]	sub $15, $3, $4    
+		X"00657822", --	[0x00400084]	sub $15, $3, $5    
+		X"00827822", --	[0x00400088]	sub $15, $4, $2    
+		X"00837822", --	[0x0040008c]	sub $15, $4, $3    
+		X"00847822", --	[0x00400090]	sub $15, $4, $4    
+		X"00857822", --	[0x00400094]	sub $15, $4, $5    
+		X"00a27822", --	[0x00400098]	sub $15, $5, $2    
+		X"00a37822", --	[0x0040009c]	sub $15, $5, $3    
+		X"00a47822", --	[0x004000a0]	sub $15, $5, $4    
+		X"00a57822", --	[0x004000a4]	sub $15, $5, $5    
+		X"00000000", --	[0x004000a8]	nop                
+		X"08104000", --	[0x004000ac]	j 0x00410000 [main]
+		X"00000000", --	[0x004000b0]	nop                
+		X"00000000", --	[0x004000b4]
+		X"00000000", --	[0x004000b8]
+		X"00000000", --	[0x004000bc]
+		X"00000000", --	[0x004000c0]
+		X"00000000", --	[0x004000c4]
+		X"00000000", --	[0x004000c8]
+		X"00000000", --	[0x004000cc]
+		X"00000000", --	[0x004000d0]
+		X"00000000", --	[0x004000d4]
+		X"00000000", --	[0x004000d8]
+		X"00000000", --	[0x004000dc]
+		X"00000000", --	[0x004000e0]
+		X"00000000", --	[0x004000e4]
+		X"00000000", --	[0x004000e8]
+		X"00000000", --	[0x004000ec]
+		X"00000000", --	[0x004000f0]
+		X"00000000", --	[0x004000f4]
+		X"00000000", --	[0x004000f8]
+		X"00000000"  --	[0x004000fc]
+	);
+
+begin
+
+PROM_READ:
+	dout <= word_array(to_integer(addr));
+
+end itest;
diff --git a/lib/CPUs/MIPS/src/irom_test_slt.vhd b/lib/CPUs/MIPS/src/irom_test_slt.vhd
new file mode 100644
index 0000000..5fcf2fe
--- /dev/null
+++ b/lib/CPUs/MIPS/src/irom_test_slt.vhd
@@ -0,0 +1,121 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY rom IS
+	Generic 
+	(
+		addr_width 	: integer := 2;
+		data_width 	: integer := 32
+	);
+	Port 
+	(
+		addr		: in  unsigned(addr_width-1 downto 0);
+		dout		: out unsigned(data_width-1 downto 0)
+	);
+END rom;
+
+ARCHITECTURE itest OF rom IS 
+	
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to 2**addr_width-1) of word_t;
+
+	-- Assembled from itest.jsm
+	constant word_array : word_array_t :=
+	(
+		X"3c011234", --	[0x00400000]	lui $1, 4660                    
+		X"34225678", --	[0x00400004]	ori $2, $1, 22136
+		X"3c012345", --	[0x00400008]	lui $1, 9029                    
+		X"34236789", --	[0x0040000c]	ori $3, $1, 26505
+		X"3c018765", --	[0x00400010]	lui $1, -30875                  
+		X"34244321", --	[0x00400014]	ori $4, $1, 17185
+		X"3c019876", --	[0x00400018]	lui $1, -26506                  
+		X"34255432", --	[0x0040001c]	ori $5, $1, 21554
+		X"3c081000", --	[0x00400020]	lui $8, 4096                    
+		X"00000000", --	[0x00400024]	nop                             
+		X"0042782b", --	[0x00400028]	sltu $15, $2, $2                
+		X"0043782b", --	[0x0040002c]	sltu $15, $2, $3                
+		X"0044782b", --	[0x00400030]	sltu $15, $2, $4                
+		X"0045782b", --	[0x00400034]	sltu $15, $2, $5                
+		X"0062782b", --	[0x00400038]	sltu $15, $3, $2                
+		X"0063782b", --	[0x0040003c]	sltu $15, $3, $3                
+		X"0064782b", --	[0x00400040]	sltu $15, $3, $4                
+		X"0065782b", --	[0x00400044]	sltu $15, $3, $5                
+		X"0082782b", --	[0x00400048]	sltu $15, $4, $2                
+		X"0083782b", --	[0x0040004c]	sltu $15, $4, $3                
+		X"0084782b", --	[0x00400050]	sltu $15, $4, $4                
+		X"0085782b", --	[0x00400054]	sltu $15, $4, $5                
+		X"00a2782b", --	[0x00400058]	sltu $15, $5, $2                
+		X"00a3782b", --	[0x0040005c]	sltu $15, $5, $3                
+		X"00a4782b", --	[0x00400060]	sltu $15, $5, $4                
+		X"00a5782b", --	[0x00400064]	sltu $15, $5, $5                
+		X"00000000", --	[0x00400068]	nop                             
+		X"0042782a", --	[0x0040006c]	slt $15, $2, $2                 
+		X"0043782a", --	[0x00400070]	slt $15, $2, $3                 
+		X"0044782a", --	[0x00400074]	slt $15, $2, $4                 
+		X"0045782a", --	[0x00400078]	slt $15, $2, $5                 
+		X"0062782a", --	[0x0040007c]	slt $15, $3, $2                 
+		X"0063782a", --	[0x00400080]	slt $15, $3, $3                 
+		X"0064782a", --	[0x00400084]	slt $15, $3, $4                 
+		X"0065782a", --	[0x00400088]	slt $15, $3, $5                 
+		X"0082782a", --	[0x0040008c]	slt $15, $4, $2                 
+		X"0083782a", --	[0x00400090]	slt $15, $4, $3                 
+		X"0084782a", --	[0x00400094]	slt $15, $4, $4                 
+		X"0085782a", --	[0x00400098]	slt $15, $4, $5                 
+		X"00a2782a", --	[0x0040009c]	slt $15, $5, $2                 
+		X"00a3782a", --	[0x004000a0]	slt $15, $5, $3                 
+		X"00a4782a", --	[0x004000a4]	slt $15, $5, $4                 
+		X"00a5782a", --	[0x004000a8]	slt $15, $5, $5                 
+		X"00000000", --	[0x004000ac]	nop                             
+		X"08104000", --	[0x004000b0]	j 0x00410000 [main]             
+		X"00000000", --	[0x004000b4]	nop                             
+		X"00000000", --	[0x004000b8]
+		X"00000000", --	[0x004000bc]
+		X"00000000", --	[0x004000c0]
+		X"00000000", --	[0x004000c4]
+		X"00000000", --	[0x004000c8]
+		X"00000000", --	[0x004000cc]
+		X"00000000", --	[0x004000d0]
+		X"00000000", --	[0x004000d4]
+		X"00000000", --	[0x004000d8]
+		X"00000000", --	[0x004000dc]
+		X"00000000", --	[0x004000e0]
+		X"00000000", --	[0x004000e4]
+		X"00000000", --	[0x004000e8]
+		X"00000000", --	[0x004000ec]
+		X"00000000", --	[0x004000f0]
+		X"00000000", --	[0x004000f4]
+		X"00000000", --	[0x004000f8]
+		X"00000000"  --	[0x004000fc]
+	);
+
+begin
+
+PROM_READ:
+	dout <= word_array(to_integer(addr));
+
+end itest;
diff --git a/lib/CPUs/MIPS/src/irom_test_slti.vhd b/lib/CPUs/MIPS/src/irom_test_slti.vhd
new file mode 100644
index 0000000..b87fd8a
--- /dev/null
+++ b/lib/CPUs/MIPS/src/irom_test_slti.vhd
@@ -0,0 +1,121 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY rom IS
+	Generic 
+	(
+		addr_width 	: integer := 2;
+		data_width 	: integer := 32
+	);
+	Port 
+	(
+		addr		: in  unsigned(addr_width-1 downto 0);
+		dout		: out unsigned(data_width-1 downto 0)
+	);
+END rom;
+
+ARCHITECTURE itest OF rom IS 
+	
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to 2**addr_width-1) of word_t;
+
+	-- Assembled from itest.jsm
+	constant word_array : word_array_t :=
+	(
+		X"3c011234", --	[0x00400000]	lui $1, 4660                     
+		X"34225678", --	[0x00400004]	ori $2, $1, 22136
+		X"3c012345", --	[0x00400008]	lui $1, 9029                     
+		X"34236789", --	[0x0040000c]	ori $3, $1, 26505
+		X"3c018765", --	[0x00400010]	lui $1, -30875                   
+		X"34244321", --	[0x00400014]	ori $4, $1, 17185
+		X"3c019876", --	[0x00400018]	lui $1, -26506                   
+		X"34255432", --	[0x0040001c]	ori $5, $1, 21554
+		X"3c081000", --	[0x00400020]	lui $8, 4096                     
+		X"00000000", --	[0x00400024]	nop                              
+		X"2c4f1234", --	[0x00400028]	sltiu $15, $2, 4660              
+		X"2c4f2345", --	[0x0040002c]	sltiu $15, $2, 9029              
+		X"2c4fedcc", --	[0x00400030]	sltiu $15, $2, -4660             
+		X"2c4fdcbb", --	[0x00400034]	sltiu $15, $2, -9029             
+		X"2c6f1234", --	[0x00400038]	sltiu $15, $3, 4660              
+		X"2c6f2345", --	[0x0040003c]	sltiu $15, $3, 9029              
+		X"2c6fedcc", --	[0x00400040]	sltiu $15, $3, -4660             
+		X"2c6fdcbb", --	[0x00400044]	sltiu $15, $3, -9029             
+		X"2c8f1234", --	[0x00400048]	sltiu $15, $4, 4660              
+		X"2c8f2345", --	[0x0040004c]	sltiu $15, $4, 9029              
+		X"2c8fedcc", --	[0x00400050]	sltiu $15, $4, -4660             
+		X"2c8fdcbb", --	[0x00400054]	sltiu $15, $4, -9029             
+		X"2caf1234", --	[0x00400058]	sltiu $15, $5, 4660              
+		X"2caf2345", --	[0x0040005c]	sltiu $15, $5, 9029              
+		X"2cafedcc", --	[0x00400060]	sltiu $15, $5, -4660             
+		X"2cafdcbb", --	[0x00400064]	sltiu $15, $5, -9029             
+		X"00000000", --	[0x00400068]	nop                              
+		X"284f1234", --	[0x0040006c]	slti $15, $2, 4660               
+		X"284f2345", --	[0x00400070]	slti $15, $2, 9029               
+		X"284fedcc", --	[0x00400074]	slti $15, $2, -4660              
+		X"284fdcbb", --	[0x00400078]	slti $15, $2, -9029              
+		X"286f1234", --	[0x0040007c]	slti $15, $3, 4660               
+		X"286f2345", --	[0x00400080]	slti $15, $3, 9029               
+		X"286fedcc", --	[0x00400084]	slti $15, $3, -4660              
+		X"286fdcbb", --	[0x00400088]	slti $15, $3, -9029              
+		X"288f1234", --	[0x0040008c]	slti $15, $4, 4660               
+		X"288f2345", --	[0x00400090]	slti $15, $4, 9029               
+		X"288fedcc", --	[0x00400094]	slti $15, $4, -4660              
+		X"288fdcbb", --	[0x00400098]	slti $15, $4, -9029              
+		X"28af1234", --	[0x0040009c]	slti $15, $5, 4660               
+		X"28af2345", --	[0x004000a0]	slti $15, $5, 9029               
+		X"28afedcc", --	[0x004000a4]	slti $15, $5, -4660              
+		X"28afdcbb", --	[0x004000a8]	slti $15, $5, -9029              
+		X"00000000", --	[0x004000ac]	nop                              
+		X"08104000", --	[0x004000b0]	j 0x00410000 [main]              
+		X"00000000", --	[0x004000b4]	nop                              
+		X"00000000", --	[0x004000b8]
+		X"00000000", --	[0x004000bc]
+		X"00000000", --	[0x004000c0]
+		X"00000000", --	[0x004000c4]
+		X"00000000", --	[0x004000c8]
+		X"00000000", --	[0x004000cc]
+		X"00000000", --	[0x004000d0]
+		X"00000000", --	[0x004000d4]
+		X"00000000", --	[0x004000d8]
+		X"00000000", --	[0x004000dc]
+		X"00000000", --	[0x004000e0]
+		X"00000000", --	[0x004000e4]
+		X"00000000", --	[0x004000e8]
+		X"00000000", --	[0x004000ec]
+		X"00000000", --	[0x004000f0]
+		X"00000000", --	[0x004000f4]
+		X"00000000", --	[0x004000f8]
+		X"00000000"  --	[0x004000fc]
+	);
+
+begin
+
+PROM_READ:
+	dout <= word_array(to_integer(addr));
+
+end itest;
diff --git a/lib/CPUs/MIPS/src/irom_test_sub.vhd b/lib/CPUs/MIPS/src/irom_test_sub.vhd
new file mode 100644
index 0000000..bbe764f
--- /dev/null
+++ b/lib/CPUs/MIPS/src/irom_test_sub.vhd
@@ -0,0 +1,121 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY rom IS
+	Generic 
+	(
+		addr_width 	: integer := 2;
+		data_width 	: integer := 32
+	);
+	Port 
+	(
+		addr		: in  unsigned(addr_width-1 downto 0);
+		dout		: out unsigned(data_width-1 downto 0)
+	);
+END rom;
+
+ARCHITECTURE itest OF rom IS 
+	
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to 2**addr_width-1) of word_t;
+
+	-- Assembled from itest.jsm
+	constant word_array : word_array_t :=
+	(
+		X"3c011234", --	[0x00400000]	lui $1, 4660       
+		X"34225678", --	[0x00400004]	ori $2, $1, 22136
+		X"3c012345", --	[0x00400008]	lui $1, 9029       
+		X"34236789", --	[0x0040000c]	ori $3, $1, 26505
+		X"3c018765", --	[0x00400010]	lui $1, -30875     
+		X"34244321", --	[0x00400014]	ori $4, $1, 17185
+		X"3c019876", --	[0x00400018]	lui $1, -26506     
+		X"34255432", --	[0x0040001c]	ori $5, $1, 21554
+		X"00000000", --	[0x00400020]	nop                
+		X"00427823", --	[0x00400024]	subu $15, $2, $2   
+		X"00437823", --	[0x00400028]	subu $15, $2, $3   
+		X"00447823", --	[0x0040002c]	subu $15, $2, $4   
+		X"00457823", --	[0x00400030]	subu $15, $2, $5   
+		X"00627823", --	[0x00400034]	subu $15, $3, $2   
+		X"00637823", --	[0x00400038]	subu $15, $3, $3   
+		X"00647823", --	[0x0040003c]	subu $15, $3, $4   
+		X"00657823", --	[0x00400040]	subu $15, $3, $5   
+		X"00827823", --	[0x00400044]	subu $15, $4, $2   
+		X"00837823", --	[0x00400048]	subu $15, $4, $3   
+		X"00847823", --	[0x0040004c]	subu $15, $4, $4   
+		X"00857823", --	[0x00400050]	subu $15, $4, $5   
+		X"00a27823", --	[0x00400054]	subu $15, $5, $2   
+		X"00a37823", --	[0x00400058]	subu $15, $5, $3   
+		X"00a47823", --	[0x0040005c]	subu $15, $5, $4   
+		X"00a57823", --	[0x00400060]	subu $15, $5, $5   
+		X"00000000", --	[0x00400064]	nop                
+		X"00427822", --	[0x00400068]	sub $15, $2, $2    
+		X"00437822", --	[0x0040006c]	sub $15, $2, $3    
+		X"00447822", --	[0x00400070]	sub $15, $2, $4    
+		X"00457822", --	[0x00400074]	sub $15, $2, $5    
+		X"00627822", --	[0x00400078]	sub $15, $3, $2    
+		X"00637822", --	[0x0040007c]	sub $15, $3, $3    
+		X"00647822", --	[0x00400080]	sub $15, $3, $4    
+		X"00657822", --	[0x00400084]	sub $15, $3, $5    
+		X"00827822", --	[0x00400088]	sub $15, $4, $2    
+		X"00837822", --	[0x0040008c]	sub $15, $4, $3    
+		X"00847822", --	[0x00400090]	sub $15, $4, $4    
+		X"00857822", --	[0x00400094]	sub $15, $4, $5    
+		X"00a27822", --	[0x00400098]	sub $15, $5, $2    
+		X"00a37822", --	[0x0040009c]	sub $15, $5, $3    
+		X"00a47822", --	[0x004000a0]	sub $15, $5, $4    
+		X"00a57822", --	[0x004000a4]	sub $15, $5, $5    
+		X"00000000", --	[0x004000a8]	nop                
+		X"08104000", --	[0x004000ac]	j 0x00410000 [main]
+		X"00000000", --	[0x004000b0]	nop                
+		X"00000000", --	[0x004000b4]
+		X"00000000", --	[0x004000b8]
+		X"00000000", --	[0x004000bc]
+		X"00000000", --	[0x004000c0]
+		X"00000000", --	[0x004000c4]
+		X"00000000", --	[0x004000c8]
+		X"00000000", --	[0x004000cc]
+		X"00000000", --	[0x004000d0]
+		X"00000000", --	[0x004000d4]
+		X"00000000", --	[0x004000d8]
+		X"00000000", --	[0x004000dc]
+		X"00000000", --	[0x004000e0]
+		X"00000000", --	[0x004000e4]
+		X"00000000", --	[0x004000e8]
+		X"00000000", --	[0x004000ec]
+		X"00000000", --	[0x004000f0]
+		X"00000000", --	[0x004000f4]
+		X"00000000", --	[0x004000f8]
+		X"00000000"  --	[0x004000fc]
+	);
+
+begin
+
+PROM_READ:
+	dout <= word_array(to_integer(addr));
+
+end itest;
diff --git a/lib/CPUs/MIPS/src/mips_embedded.vhd b/lib/CPUs/MIPS/src/mips_embedded.vhd
new file mode 100644
index 0000000..47d7bd7
--- /dev/null
+++ b/lib/CPUs/MIPS/src/mips_embedded.vhd
@@ -0,0 +1,332 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+
+entity mips_embedded is
+	Port 
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		halt		: in  STD_LOGIC;
+		int			: in  unsigned(5 downto 0);
+		rxd			: in  STD_LOGIC;
+		txd			: out STD_LOGIC;
+		dout		: out word_t
+	);
+end mips_embedded;
+
+architecture rtl of mips_embedded is
+
+	COMPONENT mips_top
+	Port 
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		int			: in  unsigned(5 downto 0);
+		mem_rdy		: in  STD_LOGIC;
+		mem_re		: out STD_LOGIC;
+		mem_en		: out STD_LOGIC;
+		mem_we		: out unsigned(3 downto 0);
+		mem_din		: in  word_t;
+		mem_dout	: out word_t;
+		mem_addr	: out word_t
+		
+	);
+	END COMPONENT;
+
+	signal mem_din		: word_t;
+	signal mem_dout 	: word_t;
+	signal mem_addr 	: word_t;
+	signal mem_re 		: std_logic;
+	signal mem_en 		: std_logic;
+	signal mem_we 		: unsigned(3 downto 0);
+	signal mem_rdy		: std_logic;
+	
+	subtype tick_usec_t	is natural range 0 to 99;
+	signal tick_usec		: tick_usec_t;
+	signal cnt_usec			: word_t;
+	signal cnt_sec			: word_t;
+	signal cnt_usec_preset	: word_t;
+	signal cnt_sec_preset	: word_t;
+	signal cnt_usec_en		: std_logic;
+	signal cnt_usec_we		: std_logic;
+	signal cnt_sec_en		: std_logic;
+	signal cnt_sec_we		: std_logic;
+	
+	COMPONENT uart_tx
+    Port
+    (
+		data_in				: in std_logic_vector(7 downto 0);
+		write_buffer		: in std_logic;
+		reset_buffer		: in std_logic;
+		en_16_x_baud		: in std_logic;
+		serial_out			: out std_logic;
+		buffer_full			: out std_logic;
+		buffer_half_full	: out std_logic;
+		clk					: in std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT uart_rx
+	Port 
+	(
+		serial_in			: in std_logic;
+		data_out			: out std_logic_vector(7 downto 0);
+		read_buffer			: in std_logic;
+		reset_buffer		: in std_logic;
+		en_16_x_baud		: in std_logic;
+		buffer_data_present	: out std_logic;
+		buffer_full			: out std_logic;
+		buffer_half_full	: out std_logic;
+		clk					: in std_logic
+	);
+	END COMPONENT;
+
+	signal baud_count		: unsigned(7 downto 0);
+	signal en_16_x_baud		: std_logic;
+	signal reg_we_uart_tx	: std_logic;
+	signal tx_full			: std_logic;
+	signal tx_half_full		: std_logic;
+	signal reg_uart_tx		: unsigned(7 downto 0);
+	signal reg_re_uart_rx	: std_logic;
+	signal reg_uart_rx		: std_logic_vector(7 downto 0);
+	signal rx_data_present	: std_logic;
+	signal rx_full			: std_logic;
+	signal rx_half_full		: std_logic;
+	signal uart_status_port	: unsigned(7 downto 0);
+	signal reg_uart_ctrl	: unsigned(7 downto 0);
+	signal reg_uart_baud	: unsigned(7 downto 0);
+
+begin
+
+registers_write: 
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			reg_we_uart_tx	<= '0';
+			cnt_usec_we		<= '0';
+			cnt_sec_we		<= '0';
+			if rst = '1' then
+				dout			<= (others => '0');
+				reg_uart_baud	<= to_unsigned(53, 8);
+				reg_uart_ctrl	<= to_unsigned(0, 8);
+			elsif mem_en = '1' then
+				case mem_addr(5 downto 2) is
+				
+				when "0000" =>
+					if mem_we(0) = '1' then
+						dout(7 downto 0) <= mem_dout(7 downto 0);
+					end if;	
+					if mem_we(1) = '1' then
+						dout(15 downto 8) <= mem_dout(15 downto 8);
+					end if;	
+					if mem_we(2) = '1' then
+						dout(23 downto 16) <= mem_dout(23 downto 16);
+					end if;	
+					if mem_we(3) = '1' then
+						dout(31 downto 24) <= mem_dout(31 downto 24);
+					end if;	
+					
+				when "0001" =>
+					if mem_we(0) = '1' then
+						reg_we_uart_tx	<= '1';
+						reg_uart_tx <= mem_dout(7 downto 0);
+					end if;	
+					
+				when "0010" =>
+					if mem_we(0) = '1' then
+						reg_uart_ctrl	<= mem_dout(7 downto 0);
+					end if;	
+					if mem_we(1) = '1' then
+						reg_uart_baud	<= mem_dout(15 downto 8);
+					end if;	
+
+				when "0100" =>
+					if mem_we(3) = '1' then
+						cnt_usec_we		<= '1';
+						cnt_usec_preset	<= mem_dout;
+					end if;	
+
+				when "0101" =>
+					if mem_we(3) = '1' then
+						cnt_sec_we		<= '1';
+						cnt_sec_preset	<= mem_dout;
+					end if;	
+
+				when others => null;
+				end case;
+			end if;	
+		end if;	
+	end process;
+	
+registers_read: 
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			reg_re_uart_rx	<= '0';
+			if mem_en = '1' then
+				mem_din			<= (others => '0');
+				case mem_addr(5 downto 2) is
+
+				when "0000" => null;
+
+				when "0001" =>
+					reg_re_uart_rx			<= '1';
+					mem_din(7 downto 0)		<= unsigned(reg_uart_rx);
+
+				when "0010" =>
+					mem_din(7 downto 0)		<= uart_status_port;
+					mem_din(15 downto 8)	<= reg_uart_baud;
+
+				when "0100" =>
+					mem_din					<= cnt_usec;
+
+				when "0101" =>
+					mem_din					<= cnt_sec;
+
+				when others => null;
+				end case;
+			end if;
+		end if;	
+	end process;
+
+	mem_rdy <= not halt;
+
+inst_mips_top: mips_top
+	PORT MAP
+	(
+		rst				=> rst,
+		clk				=> clk,
+		int				=> int,
+		mem_rdy			=> mem_rdy,
+		mem_en			=> mem_en,
+		mem_we			=> mem_we,
+		mem_din			=> mem_din,
+		mem_dout		=> mem_dout,
+		mem_addr		=> mem_addr
+	);
+
+inst_uart_tx: uart_tx 
+	port map
+	(
+		data_in				=> std_logic_vector(reg_uart_tx), 
+		write_buffer		=> reg_we_uart_tx,
+		reset_buffer		=> rst,
+		en_16_x_baud		=> en_16_x_baud,
+		serial_out			=> txd,
+		buffer_full			=> tx_full,
+		buffer_half_full	=> tx_half_full,
+		clk					=> clk
+	);
+	
+inst_uart_rx: uart_rx
+	port map
+	(
+		serial_in			=> rxd,
+		data_out			=> reg_uart_rx,
+		read_buffer			=> reg_re_uart_rx,
+		reset_buffer		=> rst,
+		en_16_x_baud		=> en_16_x_baud,
+		buffer_data_present => rx_data_present,
+		buffer_full			=> rx_full,
+		buffer_half_full	=> rx_half_full,
+		clk					=> clk
+	);  
+
+	uart_status_port <= (7 downto 5 => '0') & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full;
+
+tick_usec_timer:
+	process(clk)
+	begin
+		if clk'event and clk='1' then
+			cnt_usec_en		<= '0';
+			if rst = '1' then
+				tick_usec	<= 0;
+				cnt_usec_en	<= '0';
+			elsif tick_usec = tick_usec_t'high then
+				tick_usec		<= 0;
+				cnt_usec_en		<= '1';
+			else
+				tick_usec		<= tick_usec + 1;
+			end if;
+		end if;
+	end process;
+
+cnt_usec_timer:
+	process(clk)
+	begin
+		if clk'event and clk='1' then
+			cnt_sec_en		<= '0';
+			if rst = '1' then
+				cnt_usec	<= (others => '0');
+				cnt_sec_en	<= '0';
+			elsif cnt_usec_we = '1' then
+				cnt_usec		<= cnt_usec_preset;
+			elsif cnt_usec_en = '1' then
+				if cnt_usec = to_unsigned(1E6 - 1, word_t'length) then
+					cnt_usec		<= (others => '0');
+					cnt_sec_en		<= '1';
+				else
+					cnt_usec		<= cnt_usec + 1;
+				end if;
+			end if;	
+		end if;
+	end process;
+
+cnt_sec_timer:
+	process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+				cnt_sec		<= (others => '0');
+			elsif cnt_sec_we = '1' then
+				cnt_sec		<= cnt_sec_preset;
+			elsif cnt_sec_en = '1' then
+				cnt_sec		<= cnt_sec + 1;
+			end if;	
+		end if;
+	end process;
+
+baud_timer:
+	process(clk)
+	begin
+		if clk'event and clk='1' then
+			if rst = '1' then
+				baud_count <= (others => '0');
+			elsif baud_count = reg_uart_baud then
+				baud_count <= (others => '0');
+				en_16_x_baud <= '1';
+			else
+				baud_count <= baud_count + 1;
+				en_16_x_baud <= '0';
+			end if;
+		end if;
+	end process;
+
+end rtl;
diff --git a/lib/CPUs/MIPS/src/mips_embedded_syn.vhd b/lib/CPUs/MIPS/src/mips_embedded_syn.vhd
new file mode 100644
index 0000000..9de77e7
--- /dev/null
+++ b/lib/CPUs/MIPS/src/mips_embedded_syn.vhd
@@ -0,0 +1,137 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: JIPS top file 
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+
+entity mips_embedded_syn is
+	Port
+	(
+		sys_rst_n_in		: in  STD_LOGIC;
+		sys_clk_in			: in  STD_LOGIC;
+		sys_dip				: in  STD_LOGIC_VECTOR (7 downto 0);
+		sys_btn				: in  STD_LOGIC_VECTOR (8 downto 0);
+		sys_led				: out STD_LOGIC_VECTOR (7 downto 0);
+		sys_rx				: in  STD_LOGIC;
+		sys_tx				: out STD_LOGIC;
+		sys_error			: out STD_LOGIC_VECTOR (1 downto 0)
+	);
+	
+end mips_embedded_syn;
+
+architecture struct of mips_embedded_syn is
+
+	COMPONENT mips_embedded
+	Port 
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		halt		: in  STD_LOGIC;
+		int			: in  unsigned(5 downto 0);
+		rxd			: in  STD_LOGIC;
+		txd			: out STD_LOGIC;
+		dout		: out word_t
+	);
+	END COMPONENT;
+
+	signal dout			: word_t;
+	signal rst			: STD_LOGIC;
+	signal clk			: STD_LOGIC;
+	signal halt			: STD_LOGIC;
+	signal int			: unsigned(5 downto 0);
+	signal btn_r		: unsigned (8 downto 0);
+	signal dip_r		: unsigned (7 downto 0);
+
+begin
+
+-------------------------------------------------------------------
+inst_mips_embedded: mips_embedded
+	PORT MAP
+	(
+		rst				=> rst,
+		clk				=> clk,
+		halt			=> halt,
+		int				=> int,
+		rxd				=> sys_rx,
+		txd				=> sys_tx,
+		dout			=> dout
+	);
+
+	clk		<= sys_clk_in;
+	rst		<= not sys_rst_n_in;
+
+ERR_LED_reg:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			sys_error <= (others => '1');
+		elsif rising_edge(clk) then
+			sys_error <= STD_LOGIC_VECTOR(dout(31 downto 30));
+		end if;
+	end process;
+
+LED_reg:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			sys_led <= (others => '0');
+		elsif rising_edge(clk) then
+			sys_led <= STD_LOGIC_VECTOR(dout(7 downto 0));
+		end if;
+	end process;
+
+DIP_reg:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			dip_r <= (others => '0');
+		elsif rising_edge(clk) then
+			dip_r <= unsigned(sys_dip);
+		end if;
+	end process;
+
+BTN_reg:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			btn_r <= (others => '0');
+		elsif rising_edge(clk) then
+			btn_r <= unsigned(sys_btn);
+		end if;
+	end process;
+
+	halt <= btn_r(4) after 6.5 ns;
+	int(0)	<= dip_r(0) and btn_r(3) after 1 ns;
+	int(1)	<= dip_r(1) and btn_r(3) after 1 ns;
+	int(2)	<= dip_r(2) and btn_r(3) after 1 ns;
+	int(3)	<= dip_r(3) and btn_r(3) after 1 ns;
+	int(4)	<= dip_r(4) and btn_r(3) after 1 ns;
+	int(5)	<= dip_r(5) and btn_r(3) after 1 ns;
+	
+-------------------------------------------------------------------
+	
+end struct;
diff --git a/lib/CPUs/MIPS/src/mips_muldiv.vhd b/lib/CPUs/MIPS/src/mips_muldiv.vhd
new file mode 100644
index 0000000..34016d9
--- /dev/null
+++ b/lib/CPUs/MIPS/src/mips_muldiv.vhd
@@ -0,0 +1,83 @@
+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The arithmetic logic unit
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.mips_types.all;
+
+entity muldiv is
+	Port 
+	(
+		rst			: in  std_logic;
+		clk			: in  std_logic;
+		din_vld_hi	: in  std_logic;
+		din_vld_lo	: in  std_logic;
+		din_hi		: in  word_t;
+		din_lo		: in  word_t;
+		hilo_sel	: in  std_logic;
+		dout		: out word_t
+	);
+end muldiv;
+
+architecture Behavioral of muldiv is
+
+	signal reg_hi, reg_lo : word_t;
+	
+--------------------------------------------------------------------------
+begin
+
+--------------------------------------------------------------------------
+proc_reg_out:
+	process(hilo_sel, reg_hi, reg_lo)
+	begin
+		if hilo_sel = '1' then
+			dout <= reg_hi;
+		else	
+			dout <= reg_lo;
+		end if;
+	end process;	
+	
+proc_reg_in:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				reg_hi <= (others => '0');
+				reg_lo <= (others => '0');
+			elsif din_vld_hi = '1' then
+				if hilo_sel = '1' then
+					reg_hi <= din_hi;
+				else
+					reg_lo <= din_hi;
+				end if;
+			end if;
+			if din_vld_lo = '1' then
+				reg_lo <= din_lo;
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+end Behavioral;
diff --git a/lib/CPUs/MIPS/src/ram.vhd b/lib/CPUs/MIPS/src/ram.vhd
new file mode 100644
index 0000000..d054c72
--- /dev/null
+++ b/lib/CPUs/MIPS/src/ram.vhd
@@ -0,0 +1,115 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY ram IS
+	Generic 
+	(
+		word_addr_width 	: integer := 6
+	);
+	Port 
+	(
+		clk			: in  STD_LOGIC;
+		we			: in  unsigned(3 downto 0);
+		ce			: in  STD_LOGIC;
+		addr		: in  unsigned(31 downto 0);
+		din			: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+END ram;
+
+ARCHITECTURE behavior OF ram IS 
+
+	constant depth : natural := 2**word_addr_width;
+	
+	type sram_t is array (0 to depth-1) of unsigned(7 downto 0);
+
+	function sram_clear return sram_t is
+
+	variable result : sram_t;
+	begin
+		for i in 0 to sram_t'length-1 loop
+			result(i) := (others => '0');
+		end loop;
+		return result;
+	end sram_clear;
+
+	signal sram0, sram1, sram2, sram3 : sram_t := sram_clear;
+	
+BEGIN
+
+
+SRAM_RW:
+	process(clk)
+	variable index : natural range 0 to depth-1;
+	begin
+		if rising_edge(clk) and ce = '1' then
+			index := to_integer(addr(word_addr_width+1 downto 2));
+			if we(0) = '1' then
+				sram0(index)<= din(7 downto 0);
+			end if;	
+			dout(7 downto 0) <= sram0(index);
+		end if;	
+	end process;
+	
+	process(clk)
+	variable index : natural range 0 to depth-1;
+	begin
+		if rising_edge(clk) and ce = '1' then
+			index := to_integer(addr(word_addr_width+1 downto 2));
+			if we(1) = '1' then
+				sram1(index)<= din(15 downto 8);
+			end if;	
+			dout(15 downto 8) <= sram1(index);
+		end if;	
+	end process;
+
+	process(clk)
+	variable index : natural range 0 to depth-1;
+	begin
+		if rising_edge(clk) and ce = '1' then
+			index := to_integer(addr(word_addr_width+1 downto 2));
+			if we(2) = '1' then
+				sram2(index)<= din(23 downto 16);
+			end if;	
+			dout(23 downto 16) <= sram2(index);
+		end if;	
+	end process;
+
+	process(clk)
+	variable index : natural range 0 to depth-1;
+	begin
+		if rising_edge(clk) and ce = '1' then
+			index := to_integer(addr(word_addr_width+1 downto 2));
+			if we(3) = '1' then
+				sram3(index)<= din(31 downto 24);
+			end if;	
+			dout(31 downto 24) <= sram3(index);
+		end if;	
+	end process;
+
+end behavior;
diff --git a/lib/CPUs/MIPS/src/ram_ld.vhd b/lib/CPUs/MIPS/src/ram_ld.vhd
new file mode 100644
index 0000000..7a36b13
--- /dev/null
+++ b/lib/CPUs/MIPS/src/ram_ld.vhd
@@ -0,0 +1,177 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+ENTITY ram IS
+	Generic 
+	(
+		word_addr_width 	: integer := 6
+	);
+	Port 
+	(
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		we			: in  unsigned(3 downto 0);
+		addr		: in  unsigned(31 downto 0);
+		din			: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+END ram;
+
+ARCHITECTURE behavior OF ram IS 
+
+	COMPONENT dpram_2w2r
+	Generic 
+	(
+		addr_width : integer;
+		data_width : integer
+	);
+	Port
+	(
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+	END COMPONENT;
+	
+	signal jtag_clk		: STD_LOGIC;
+	signal jtag_we		: unsigned(3 downto 0);
+	signal jtag_addr	: unsigned (15 downto 0);
+	signal jtag_dout	: unsigned (31 downto 0);
+	signal jtag_din		: unsigned (31 downto 0);
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (47 downto 0);
+	
+BEGIN
+
+gen_sram:
+	for i in 0 to 3 generate
+	begin
+	inst_dpram_2w2r : dpram_2w2r
+		GENERIC MAP
+		(
+			addr_width	=> word_addr_width,
+			data_width	=> 8
+		)
+		PORT MAP
+		(
+			clk_a		=> clk,
+			en_a		=> ce,
+			we_a		=> we(i),
+			addr_a		=> addr(word_addr_width+1 downto 2),
+			din_a		=> din((i+1)*8-1 downto i*8),
+			dout_a		=> dout((i+1)*8-1 downto i*8),
+
+			clk_b		=> jtag_clk,
+			en_b		=> jtag_we(i),
+			we_b		=> jtag_we(i),
+			addr_b		=> jtag_addr(word_addr_width-1 downto 0),
+			din_b		=> jtag_din((i+1)*8-1 downto i*8),
+			dout_b		=> jtag_dout((i+1)*8-1 downto i*8)
+		);
+	end generate;
+	
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_addr	<= user_regi(user_regi'left downto jtag_dout'length);
+	jtag_din	<= user_regi(jtag_dout'length-1 downto 0);
+	jtag_clk	<= bs_update1;
+	jtag_we		<= (3 downto 0 => bs_sel);
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+end behavior;
diff --git a/lib/CPUs/MIPS/src/ram_sim.vhd b/lib/CPUs/MIPS/src/ram_sim.vhd
new file mode 100644
index 0000000..6d26672
--- /dev/null
+++ b/lib/CPUs/MIPS/src/ram_sim.vhd
@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+ENTITY ram IS
+	Generic 
+	(
+		word_addr_width 	: integer := 6
+	);
+	Port 
+	(
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		we			: in  unsigned(3 downto 0);
+		addr		: in  unsigned(31 downto 0);
+		din			: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+END ram;
+
+ARCHITECTURE behavior OF ram IS 
+
+	constant depth : natural := 2**word_addr_width;
+	
+	type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
+
+	function sram_clear return sram_t is
+
+	variable result : sram_t;
+	begin
+		for i in 0 to sram_t'length-1 loop
+			result(i) := (others => '0');
+		end loop;
+		return result;
+	end sram_clear;
+
+	signal sram : sram_t := sram_clear;
+	
+BEGIN
+
+
+SRAM_RW:
+	process(clk)
+	variable index : natural range 0 to depth-1;
+	begin
+		if rising_edge(clk) and ce = '1' then
+			index := to_integer(addr(word_addr_width+1 downto 2));
+			if we(0) = '1' then
+				sram(index)(7 downto 0)		<= din(7 downto 0);
+			end if;	
+			if we(1) = '1' then
+				sram(index)(15 downto 8)	<= din(15 downto 8);
+			end if;	
+			if we(2) = '1' then
+				sram(index)(23 downto 16)	<= din(23 downto 16);
+			end if;	
+			if we(3) = '1' then
+				sram(index)(31 downto 24)	<= din(31 downto 24);
+			end if;	
+			dout <= sram(index);
+		end if;	
+	end process;
+	
+end behavior;
diff --git a/lib/CPUs/MIPS/src/rmd160_test.ROM_ld.vhd b/lib/CPUs/MIPS/src/rmd160_test.ROM_ld.vhd
new file mode 100644
index 0000000..b0c6fe3
--- /dev/null
+++ b/lib/CPUs/MIPS/src/rmd160_test.ROM_ld.vhd
@@ -0,0 +1,4222 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+ENTITY rom IS
+	Port
+	(
+		clk		: in  STD_LOGIC;
+		ce		: in  STD_LOGIC;
+		addr		: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+END rom;
+
+ARCHITECTURE data OF rom IS
+
+	subtype word_t is unsigned(31 downto 0);
+	type word_array_t is array (0 to 4095) of word_t;
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: unsigned (15 downto 0);
+	signal jtag_ld_dout		: unsigned (31 downto 0);
+	signal jtag_ld_din		: unsigned (31 downto 0);
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (47 downto 0);
+
+	signal word_array : word_array_t :=
+	(
+
+		X"401A6000", -- 00000000
+		X"3C1B0040", -- 00000004
+		X"035BD024", -- 00000008
+		X"375A000C", -- 0000000C
+		X"409A6000", -- 00000010
+		X"401A7800", -- 00000014
+		X"00000000", -- 00000018
+		X"409AF800", -- 0000001C
+		X"3C1D7FFF", -- 00000020
+		X"37BDEFFC", -- 00000024
+		X"3C1A0040", -- 00000028
+		X"275A05B4", -- 0000002C
+		X"0340F809", -- 00000030
+		X"42000010", -- 00000034
+		X"00000000", -- 00000038
+		X"00000000", -- 0000003C
+		X"00000000", -- 00000040
+		X"00000000", -- 00000044
+		X"00000000", -- 00000048
+		X"00000000", -- 0000004C
+		X"00000000", -- 00000050
+		X"00000000", -- 00000054
+		X"00000000", -- 00000058
+		X"00000000", -- 0000005C
+		X"00000000", -- 00000060
+		X"00000000", -- 00000064
+		X"00000000", -- 00000068
+		X"00000000", -- 0000006C
+		X"00000000", -- 00000070
+		X"00000000", -- 00000074
+		X"00000000", -- 00000078
+		X"00000000", -- 0000007C
+		X"00000000", -- 00000080
+		X"00000000", -- 00000084
+		X"00000000", -- 00000088
+		X"00000000", -- 0000008C
+		X"00000000", -- 00000090
+		X"00000000", -- 00000094
+		X"00000000", -- 00000098
+		X"00000000", -- 0000009C
+		X"00000000", -- 000000A0
+		X"00000000", -- 000000A4
+		X"00000000", -- 000000A8
+		X"00000000", -- 000000AC
+		X"00000000", -- 000000B0
+		X"00000000", -- 000000B4
+		X"00000000", -- 000000B8
+		X"00000000", -- 000000BC
+		X"00000000", -- 000000C0
+		X"00000000", -- 000000C4
+		X"00000000", -- 000000C8
+		X"00000000", -- 000000CC
+		X"00000000", -- 000000D0
+		X"00000000", -- 000000D4
+		X"00000000", -- 000000D8
+		X"00000000", -- 000000DC
+		X"00000000", -- 000000E0
+		X"00000000", -- 000000E4
+		X"00000000", -- 000000E8
+		X"00000000", -- 000000EC
+		X"00000000", -- 000000F0
+		X"00000000", -- 000000F4
+		X"00000000", -- 000000F8
+		X"00000000", -- 000000FC
+		X"00000000", -- 00000100
+		X"00000000", -- 00000104
+		X"00000000", -- 00000108
+		X"00000000", -- 0000010C
+		X"00000000", -- 00000110
+		X"00000000", -- 00000114
+		X"00000000", -- 00000118
+		X"00000000", -- 0000011C
+		X"00000000", -- 00000120
+		X"00000000", -- 00000124
+		X"00000000", -- 00000128
+		X"00000000", -- 0000012C
+		X"00000000", -- 00000130
+		X"00000000", -- 00000134
+		X"00000000", -- 00000138
+		X"00000000", -- 0000013C
+		X"00000000", -- 00000140
+		X"00000000", -- 00000144
+		X"00000000", -- 00000148
+		X"00000000", -- 0000014C
+		X"00000000", -- 00000150
+		X"00000000", -- 00000154
+		X"00000000", -- 00000158
+		X"00000000", -- 0000015C
+		X"00000000", -- 00000160
+		X"00000000", -- 00000164
+		X"00000000", -- 00000168
+		X"00000000", -- 0000016C
+		X"00000000", -- 00000170
+		X"00000000", -- 00000174
+		X"00000000", -- 00000178
+		X"00000000", -- 0000017C
+		X"3C010000", -- 00000180
+		X"AC3D0018", -- 00000184
+		X"3C1D0000", -- 00000188
+		X"27BD0018", -- 0000018C
+		X"27BD0004", -- 00000190
+		X"AFA80000", -- 00000194
+		X"27BD0004", -- 00000198
+		X"AFA90000", -- 0000019C
+		X"27BD0004", -- 000001A0
+		X"AFAA0000", -- 000001A4
+		X"27BD0004", -- 000001A8
+		X"AFAB0000", -- 000001AC
+		X"27BD0004", -- 000001B0
+		X"AFAC0000", -- 000001B4
+		X"27BD0004", -- 000001B8
+		X"AFBF0000", -- 000001BC
+		X"400A4000", -- 000001C0
+		X"27BD0004", -- 000001C4
+		X"AFAA0000", -- 000001C8
+		X"400A6000", -- 000001CC
+		X"27BD0004", -- 000001D0
+		X"AFAA0000", -- 000001D4
+		X"400A6800", -- 000001D8
+		X"27BD0004", -- 000001DC
+		X"AFAA0000", -- 000001E0
+		X"000A5742", -- 000001E4
+		X"314B0004", -- 000001E8
+		X"400A7000", -- 000001EC
+		X"27BD0004", -- 000001F0
+		X"AFAA0000", -- 000001F4
+		X"014B5021", -- 000001F8
+		X"27BD0004", -- 000001FC
+		X"AFAA0000", -- 00000200
+		X"3C0B0000", -- 00000204
+		X"256B0156", -- 00000208
+		X"0C100126", -- 0000020C
+		X"00000000", -- 00000210
+		X"3C0B0000", -- 00000214
+		X"256B0118", -- 00000218
+		X"0C100126", -- 0000021C
+		X"00000000", -- 00000220
+		X"8FAA0000", -- 00000224
+		X"27BDFFFC", -- 00000228
+		X"0C1000DE", -- 0000022C
+		X"00000000", -- 00000230
+		X"3C0B0000", -- 00000234
+		X"256B0156", -- 00000238
+		X"0C100126", -- 0000023C
+		X"00000000", -- 00000240
+		X"3C0B0000", -- 00000244
+		X"256B0126", -- 00000248
+		X"0C100126", -- 0000024C
+		X"00000000", -- 00000250
+		X"8FAA0000", -- 00000254
+		X"27BDFFFC", -- 00000258
+		X"0C1000DE", -- 0000025C
+		X"00000000", -- 00000260
+		X"3C0B0000", -- 00000264
+		X"256B0156", -- 00000268
+		X"0C100126", -- 0000026C
+		X"00000000", -- 00000270
+		X"3C0B0000", -- 00000274
+		X"256B0132", -- 00000278
+		X"0C100126", -- 0000027C
+		X"00000000", -- 00000280
+		X"8FAA0000", -- 00000284
+		X"27BDFFFC", -- 00000288
+		X"0C1000DE", -- 0000028C
+		X"00000000", -- 00000290
+		X"3C0B0000", -- 00000294
+		X"256B0156", -- 00000298
+		X"0C100126", -- 0000029C
+		X"00000000", -- 000002A0
+		X"3C0B0000", -- 000002A4
+		X"256B013E", -- 000002A8
+		X"0C100126", -- 000002AC
+		X"00000000", -- 000002B0
+		X"8FAA0000", -- 000002B4
+		X"27BDFFFC", -- 000002B8
+		X"0C1000DE", -- 000002BC
+		X"00000000", -- 000002C0
+		X"3C0B0000", -- 000002C4
+		X"256B0156", -- 000002C8
+		X"0C100126", -- 000002CC
+		X"00000000", -- 000002D0
+		X"3C0B0000", -- 000002D4
+		X"256B014A", -- 000002D8
+		X"0C100126", -- 000002DC
+		X"00000000", -- 000002E0
+		X"8FAA0000", -- 000002E4
+		X"27BDFFFC", -- 000002E8
+		X"0C1000DE", -- 000002EC
+		X"00000000", -- 000002F0
+		X"3C0B0000", -- 000002F4
+		X"256B0156", -- 000002F8
+		X"0C100126", -- 000002FC
+		X"00000000", -- 00000300
+		X"401A6800", -- 00000304
+		X"3C1B8000", -- 00000308
+		X"001AD082", -- 0000030C
+		X"335A000F", -- 00000310
+		X"035BD025", -- 00000314
+		X"AF7A0000", -- 00000318
+		X"401A6800", -- 0000031C
+		X"00000000", -- 00000320
+		X"001AD202", -- 00000324
+		X"335A0001", -- 00000328
+		X"1740FFFB", -- 0000032C
+		X"00000000", -- 00000330
+		X"401A7000", -- 00000334
+		X"8FBF0000", -- 00000338
+		X"27BDFFFC", -- 0000033C
+		X"8FAC0000", -- 00000340
+		X"27BDFFFC", -- 00000344
+		X"8FAB0000", -- 00000348
+		X"27BDFFFC", -- 0000034C
+		X"8FAA0000", -- 00000350
+		X"27BDFFFC", -- 00000354
+		X"8FA90000", -- 00000358
+		X"27BDFFFC", -- 0000035C
+		X"8FA80000", -- 00000360
+		X"27BDFFFC", -- 00000364
+		X"3C1D0000", -- 00000368
+		X"8FBD0018", -- 0000036C
+		X"03400008", -- 00000370
+		X"42000010", -- 00000374
+		X"27BD0004", -- 00000378
+		X"AFBF0000", -- 0000037C
+		X"27BD0004", -- 00000380
+		X"AFAA0000", -- 00000384
+		X"000A5402", -- 00000388
+		X"0C1000ED", -- 0000038C
+		X"00000000", -- 00000390
+		X"8FAA0000", -- 00000394
+		X"27BDFFFC", -- 00000398
+		X"0C1000ED", -- 0000039C
+		X"00000000", -- 000003A0
+		X"8FBF0000", -- 000003A4
+		X"27BDFFFC", -- 000003A8
+		X"03E00008", -- 000003AC
+		X"00000000", -- 000003B0
+		X"27BD0004", -- 000003B4
+		X"AFBF0000", -- 000003B8
+		X"27BD0004", -- 000003BC
+		X"AFAA0000", -- 000003C0
+		X"000A5202", -- 000003C4
+		X"0C1000FC", -- 000003C8
+		X"00000000", -- 000003CC
+		X"8FAA0000", -- 000003D0
+		X"27BDFFFC", -- 000003D4
+		X"0C1000FC", -- 000003D8
+		X"00000000", -- 000003DC
+		X"8FBF0000", -- 000003E0
+		X"27BDFFFC", -- 000003E4
+		X"03E00008", -- 000003E8
+		X"00000000", -- 000003EC
+		X"27BD0004", -- 000003F0
+		X"AFBF0000", -- 000003F4
+		X"27BD0004", -- 000003F8
+		X"AFAA0000", -- 000003FC
+		X"000A5102", -- 00000400
+		X"0C10010B", -- 00000404
+		X"00000000", -- 00000408
+		X"8FAA0000", -- 0000040C
+		X"27BDFFFC", -- 00000410
+		X"0C10010B", -- 00000414
+		X"00000000", -- 00000418
+		X"8FBF0000", -- 0000041C
+		X"27BDFFFC", -- 00000420
+		X"03E00008", -- 00000424
+		X"00000000", -- 00000428
+		X"27BD0004", -- 0000042C
+		X"AFBF0000", -- 00000430
+		X"27BD0004", -- 00000434
+		X"AFAA0000", -- 00000438
+		X"3C0C0000", -- 0000043C
+		X"258C0159", -- 00000440
+		X"314A000F", -- 00000444
+		X"018A6021", -- 00000448
+		X"918A0000", -- 0000044C
+		X"0C10011C", -- 00000450
+		X"00000000", -- 00000454
+		X"8FAA0000", -- 00000458
+		X"27BDFFFC", -- 0000045C
+		X"8FBF0000", -- 00000460
+		X"27BDFFFC", -- 00000464
+		X"03E00008", -- 00000468
+		X"00000000", -- 0000046C
+		X"3C088000", -- 00000470
+		X"35080008", -- 00000474
+		X"91080000", -- 00000478
+		X"3C098000", -- 0000047C
+		X"35290004", -- 00000480
+		X"31080002", -- 00000484
+		X"1500FFF9", -- 00000488
+		X"00000000", -- 0000048C
+		X"03E00008", -- 00000490
+		X"A12A0000", -- 00000494
+		X"27BD0004", -- 00000498
+		X"AFAB0000", -- 0000049C
+		X"27BD0004", -- 000004A0
+		X"AFBF0000", -- 000004A4
+		X"916A0000", -- 000004A8
+		X"256B0001", -- 000004AC
+		X"19400005", -- 000004B0
+		X"00000000", -- 000004B4
+		X"0C10011C", -- 000004B8
+		X"00000000", -- 000004BC
+		X"0810012A", -- 000004C0
+		X"00000000", -- 000004C4
+		X"8FBF0000", -- 000004C8
+		X"27BDFFFC", -- 000004CC
+		X"8FAB0000", -- 000004D0
+		X"27BDFFFC", -- 000004D4
+		X"03E00008", -- 000004D8
+		X"00000000", -- 000004DC
+		X"3C028000", -- 000004E0
+		X"00042600", -- 000004E4
+		X"00042603", -- 000004E8
+		X"34450004", -- 000004EC
+		X"34430008", -- 000004F0
+		X"90620000", -- 000004F4
+		X"00000000", -- 000004F8
+		X"30420002", -- 000004FC
+		X"1440FFFC", -- 00000500
+		X"00000000", -- 00000504
+		X"03E00008", -- 00000508
+		X"A0A40000", -- 0000050C
+		X"27BDFFE0", -- 00000510
+		X"AFB10014", -- 00000514
+		X"AFB00010", -- 00000518
+		X"AFBF0018", -- 0000051C
+		X"00808021", -- 00000520
+		X"80840000", -- 00000524
+		X"08100150", -- 00000528
+		X"02008821", -- 0000052C
+		X"0C100138", -- 00000530
+		X"26100001", -- 00000534
+		X"82040000", -- 00000538
+		X"00000000", -- 0000053C
+		X"1480FFFB", -- 00000540
+		X"02111023", -- 00000544
+		X"8FBF0018", -- 00000548
+		X"8FB10014", -- 0000054C
+		X"8FB00010", -- 00000550
+		X"03E00008", -- 00000554
+		X"27BD0020", -- 00000558
+		X"27BDFFE0", -- 0000055C
+		X"AFB10014", -- 00000560
+		X"AFB00010", -- 00000564
+		X"AFBF0018", -- 00000568
+		X"00808021", -- 0000056C
+		X"24110007", -- 00000570
+		X"00101F02", -- 00000574
+		X"2C62000A", -- 00000578
+		X"2631FFFF", -- 0000057C
+		X"00108100", -- 00000580
+		X"14400002", -- 00000584
+		X"24640030", -- 00000588
+		X"24640037", -- 0000058C
+		X"0C100138", -- 00000590
+		X"00000000", -- 00000594
+		X"0621FFF7", -- 00000598
+		X"00101F02", -- 0000059C
+		X"8FBF0018", -- 000005A0
+		X"8FB10014", -- 000005A4
+		X"8FB00010", -- 000005A8
+		X"03E00008", -- 000005AC
+		X"27BD0020", -- 000005B0
+		X"3C020000", -- 000005B4
+		X"8C420000", -- 000005B8
+		X"3C030000", -- 000005BC
+		X"8C630004", -- 000005C0
+		X"27BDFFB8", -- 000005C4
+		X"AFA20028", -- 000005C8
+		X"AFA3002C", -- 000005CC
+		X"3C020000", -- 000005D0
+		X"8C420008", -- 000005D4
+		X"3C030000", -- 000005D8
+		X"8C63000C", -- 000005DC
+		X"AFA20030", -- 000005E0
+		X"AFA30034", -- 000005E4
+		X"3C020000", -- 000005E8
+		X"8C420010", -- 000005EC
+		X"3C030000", -- 000005F0
+		X"8C630014", -- 000005F4
+		X"3C058000", -- 000005F8
+		X"AFA20038", -- 000005FC
+		X"AFA3003C", -- 00000600
+		X"34A60009", -- 00000604
+		X"24020035", -- 00000608
+		X"34A50008", -- 0000060C
+		X"24030055", -- 00000610
+		X"A0C20000", -- 00000614
+		X"27A40010", -- 00000618
+		X"A0A30000", -- 0000061C
+		X"AFBF0040", -- 00000620
+		X"AFA00010", -- 00000624
+		X"AFA00014", -- 00000628
+		X"AFA00018", -- 0000062C
+		X"AFA0001C", -- 00000630
+		X"0C100193", -- 00000634
+		X"AFA00020", -- 00000638
+		X"0C100144", -- 0000063C
+		X"27A40028", -- 00000640
+		X"08100191", -- 00000644
+		X"00000000", -- 00000648
+		X"3C02C3D2", -- 0000064C
+		X"3442E1F0", -- 00000650
+		X"AC820010", -- 00000654
+		X"3C036745", -- 00000658
+		X"3C02EFCD", -- 0000065C
+		X"34632301", -- 00000660
+		X"3442AB89", -- 00000664
+		X"AC830000", -- 00000668
+		X"AC820004", -- 0000066C
+		X"3C0398BA", -- 00000670
+		X"3C021032", -- 00000674
+		X"3463DCFE", -- 00000678
+		X"34425476", -- 0000067C
+		X"AC830008", -- 00000680
+		X"03E00008", -- 00000684
+		X"AC82000C", -- 00000688
+		X"27BDFF80", -- 0000068C
+		X"AFB30064", -- 00000690
+		X"8C93000C", -- 00000694
+		X"AFB40068", -- 00000698
+		X"8C980004", -- 0000069C
+		X"8C940008", -- 000006A0
+		X"AFBE0078", -- 000006A4
+		X"AFB70074", -- 000006A8
+		X"AFB60070", -- 000006AC
+		X"AFB5006C", -- 000006B0
+		X"AFB20060", -- 000006B4
+		X"AFB1005C", -- 000006B8
+		X"AFB00058", -- 000006BC
+		X"00131027", -- 000006C0
+		X"8CA60014", -- 000006C4
+		X"8CA70000", -- 000006C8
+		X"8C950000", -- 000006CC
+		X"03141826", -- 000006D0
+		X"00541025", -- 000006D4
+		X"00731826", -- 000006D8
+		X"00581026", -- 000006DC
+		X"00671821", -- 000006E0
+		X"02A08821", -- 000006E4
+		X"00461021", -- 000006E8
+		X"3C0B50A2", -- 000006EC
+		X"356B8BE6", -- 000006F0
+		X"02A3A821", -- 000006F4
+		X"00511021", -- 000006F8
+		X"004B8821", -- 000006FC
+		X"8C990010", -- 00000700
+		X"AFA6000C", -- 00000704
+		X"00151D42", -- 00000708
+		X"00144582", -- 0000070C
+		X"00143280", -- 00000710
+		X"001512C0", -- 00000714
+		X"00C8B825", -- 00000718
+		X"00431025", -- 0000071C
+		X"00113E02", -- 00000720
+		X"00111A00", -- 00000724
+		X"0059A821", -- 00000728
+		X"00671825", -- 0000072C
+		X"00171027", -- 00000730
+		X"00798821", -- 00000734
+		X"8CA80038", -- 00000738
+		X"8CA60004", -- 0000073C
+		X"02B81826", -- 00000740
+		X"00581025", -- 00000744
+		X"00771826", -- 00000748
+		X"00511026", -- 0000074C
+		X"0320F021", -- 00000750
+		X"00661821", -- 00000754
+		X"00481021", -- 00000758
+		X"0323C821", -- 0000075C
+		X"005E1021", -- 00000760
+		X"004BF021", -- 00000764
+		X"AFA80024", -- 00000768
+		X"00191C82", -- 0000076C
+		X"00184582", -- 00000770
+		X"00183280", -- 00000774
+		X"00191380", -- 00000778
+		X"00C8B025", -- 0000077C
+		X"00431025", -- 00000780
+		X"001E3DC2", -- 00000784
+		X"001E1A40", -- 00000788
+		X"0053C821", -- 0000078C
+		X"00671825", -- 00000790
+		X"00161027", -- 00000794
+		X"0073F021", -- 00000798
+		X"8CA70008", -- 0000079C
+		X"8CA8001C", -- 000007A0
+		X"03351826", -- 000007A4
+		X"00511025", -- 000007A8
+		X"00761826", -- 000007AC
+		X"005E1026", -- 000007B0
+		X"02609021", -- 000007B4
+		X"00671821", -- 000007B8
+		X"00481021", -- 000007BC
+		X"02639821", -- 000007C0
+		X"00521021", -- 000007C4
+		X"004B9021", -- 000007C8
+		X"AFA70000", -- 000007CC
+		X"00113582", -- 000007D0
+		X"00133C42", -- 000007D4
+		X"00131BC0", -- 000007D8
+		X"00111280", -- 000007DC
+		X"00468825", -- 000007E0
+		X"00671825", -- 000007E4
+		X"001215C2", -- 000007E8
+		X"00123240", -- 000007EC
+		X"00779821", -- 000007F0
+		X"00C23025", -- 000007F4
+		X"00153D82", -- 000007F8
+		X"00111027", -- 000007FC
+		X"00151A80", -- 00000800
+		X"00D79021", -- 00000804
+		X"0067A825", -- 00000808
+		X"8CA60000", -- 0000080C
+		X"8CA7000C", -- 00000810
+		X"02791826", -- 00000814
+		X"005E1025", -- 00000818
+		X"00751826", -- 0000081C
+		X"00521026", -- 00000820
+		X"00671821", -- 00000824
+		X"00461021", -- 00000828
+		X"02E3A021", -- 0000082C
+		X"00571021", -- 00000830
+		X"004BB821", -- 00000834
+		X"AFA60008", -- 00000838
+		X"00143D02", -- 0000083C
+		X"001E3582", -- 00000840
+		X"00141B00", -- 00000844
+		X"001E1280", -- 00000848
+		X"0046F025", -- 0000084C
+		X"00671825", -- 00000850
+		X"00171542", -- 00000854
+		X"001732C0", -- 00000858
+		X"0076A021", -- 0000085C
+		X"00C23025", -- 00000860
+		X"00193D82", -- 00000864
+		X"001E1027", -- 00000868
+		X"00191A80", -- 0000086C
+		X"00D6B821", -- 00000870
+		X"0067C825", -- 00000874
+		X"8CA60010", -- 00000878
+		X"AFA80014", -- 0000087C
+		X"02931826", -- 00000880
+		X"8CA80024", -- 00000884
+		X"00521025", -- 00000888
+		X"00791826", -- 0000088C
+		X"00571026", -- 00000890
+		X"00661821", -- 00000894
+		X"00481021", -- 00000898
+		X"02C3C021", -- 0000089C
+		X"00561021", -- 000008A0
+		X"004BB021", -- 000008A4
+		X"00183EC2", -- 000008A8
+		X"00123582", -- 000008AC
+		X"00181940", -- 000008B0
+		X"00121280", -- 000008B4
+		X"00469025", -- 000008B8
+		X"00671825", -- 000008BC
+		X"001614C2", -- 000008C0
+		X"00163340", -- 000008C4
+		X"0075C021", -- 000008C8
+		X"00C23025", -- 000008CC
+		X"00133D82", -- 000008D0
+		X"00121027", -- 000008D4
+		X"00131A80", -- 000008D8
+		X"00D1B021", -- 000008DC
+		X"00679825", -- 000008E0
+		X"00571025", -- 000008E4
+		X"8FA70000", -- 000008E8
+		X"AFA80010", -- 000008EC
+		X"03141826", -- 000008F0
+		X"8CA80014", -- 000008F4
+		X"00561026", -- 000008F8
+		X"00731826", -- 000008FC
+		X"00471021", -- 00000900
+		X"00681821", -- 00000904
+		X"00511021", -- 00000908
+		X"004B8821", -- 0000090C
+		X"02A3A821", -- 00000910
+		X"00173582", -- 00000914
+		X"00171280", -- 00000918
+		X"0046B825", -- 0000091C
+		X"AFA7001C", -- 00000920
+		X"00111442", -- 00000924
+		X"00153E02", -- 00000928
+		X"00151A00", -- 0000092C
+		X"001133C0", -- 00000930
+		X"00671825", -- 00000934
+		X"00C23025", -- 00000938
+		X"00143D82", -- 0000093C
+		X"00141280", -- 00000940
+		X"0047A025", -- 00000944
+		X"8CA2002C", -- 00000948
+		X"0079A821", -- 0000094C
+		X"00171827", -- 00000950
+		X"AFA2002C", -- 00000954
+		X"00DE8821", -- 00000958
+		X"8FA7002C", -- 0000095C
+		X"8CA60018", -- 00000960
+		X"02B81026", -- 00000964
+		X"00761825", -- 00000968
+		X"00541026", -- 0000096C
+		X"00711826", -- 00000970
+		X"00461021", -- 00000974
+		X"00671821", -- 00000978
+		X"0322C821", -- 0000097C
+		X"007E1821", -- 00000980
+		X"006BF021", -- 00000984
+		X"00193E42", -- 00000988
+		X"00163582", -- 0000098C
+		X"001919C0", -- 00000990
+		X"00161280", -- 00000994
+		X"0046B025", -- 00000998
+		X"00671825", -- 0000099C
+		X"001E1442", -- 000009A0
+		X"001E33C0", -- 000009A4
+		X"0073C821", -- 000009A8
+		X"00C23025", -- 000009AC
+		X"00183D82", -- 000009B0
+		X"00161027", -- 000009B4
+		X"00181A80", -- 000009B8
+		X"00D2F021", -- 000009BC
+		X"0067C025", -- 000009C0
+		X"8CA80010", -- 000009C4
+		X"8CA6001C", -- 000009C8
+		X"03351826", -- 000009CC
+		X"00511025", -- 000009D0
+		X"00781826", -- 000009D4
+		X"005E1026", -- 000009D8
+		X"00661821", -- 000009DC
+		X"00481021", -- 000009E0
+		X"02639821", -- 000009E4
+		X"00521021", -- 000009E8
+		X"004B9021", -- 000009EC
+		X"00133DC2", -- 000009F0
+		X"00113582", -- 000009F4
+		X"00131A40", -- 000009F8
+		X"00111280", -- 000009FC
+		X"00468825", -- 00000A00
+		X"00671825", -- 00000A04
+		X"001216C2", -- 00000A08
+		X"00123140", -- 00000A0C
+		X"00749821", -- 00000A10
+		X"00C23025", -- 00000A14
+		X"00153D82", -- 00000A18
+		X"00111827", -- 00000A1C
+		X"00151280", -- 00000A20
+		X"00D79021", -- 00000A24
+		X"0047A825", -- 00000A28
+		X"AFA80004", -- 00000A2C
+		X"8CA70034", -- 00000A30
+		X"8CA80020", -- 00000A34
+		X"02791026", -- 00000A38
+		X"007E1825", -- 00000A3C
+		X"00551026", -- 00000A40
+		X"00721826", -- 00000A44
+		X"00481021", -- 00000A48
+		X"00671821", -- 00000A4C
+		X"0282A021", -- 00000A50
+		X"00771821", -- 00000A54
+		X"006BB821", -- 00000A58
+		X"AFA70034", -- 00000A5C
+		X"001E3582", -- 00000A60
+		X"00143D42", -- 00000A64
+		X"00141AC0", -- 00000A68
+		X"001E1280", -- 00000A6C
+		X"0046F025", -- 00000A70
+		X"00671825", -- 00000A74
+		X"00171642", -- 00000A78
+		X"001731C0", -- 00000A7C
+		X"0078A021", -- 00000A80
+		X"00C23025", -- 00000A84
+		X"00193D82", -- 00000A88
+		X"001E1827", -- 00000A8C
+		X"00191280", -- 00000A90
+		X"8CAC0018", -- 00000A94
+		X"00D6B821", -- 00000A98
+		X"0047C825", -- 00000A9C
+		X"8CA60024", -- 00000AA0
+		X"02931026", -- 00000AA4
+		X"00721825", -- 00000AA8
+		X"00591026", -- 00000AAC
+		X"00771826", -- 00000AB0
+		X"00461021", -- 00000AB4
+		X"006C1821", -- 00000AB8
+		X"0302C021", -- 00000ABC
+		X"00761821", -- 00000AC0
+		X"006BB021", -- 00000AC4
+		X"00183CC2", -- 00000AC8
+		X"00123582", -- 00000ACC
+		X"00181B40", -- 00000AD0
+		X"00121280", -- 00000AD4
+		X"00469025", -- 00000AD8
+		X"00671825", -- 00000ADC
+		X"00161642", -- 00000AE0
+		X"001631C0", -- 00000AE4
+		X"0075C021", -- 00000AE8
+		X"00C23025", -- 00000AEC
+		X"00133D82", -- 00000AF0
+		X"00121827", -- 00000AF4
+		X"00131280", -- 00000AF8
+		X"00D1B021", -- 00000AFC
+		X"00479825", -- 00000B00
+		X"8CA80028", -- 00000B04
+		X"8CA7003C", -- 00000B08
+		X"03141026", -- 00000B0C
+		X"00771825", -- 00000B10
+		X"00531026", -- 00000B14
+		X"00761826", -- 00000B18
+		X"00481021", -- 00000B1C
+		X"00671821", -- 00000B20
+		X"02A2A821", -- 00000B24
+		X"00711821", -- 00000B28
+		X"AFA70030", -- 00000B2C
+		X"006B8821", -- 00000B30
+		X"00153C82", -- 00000B34
+		X"00173582", -- 00000B38
+		X"00151B80", -- 00000B3C
+		X"00171280", -- 00000B40
+		X"0046B825", -- 00000B44
+		X"00671825", -- 00000B48
+		X"00111602", -- 00000B4C
+		X"00113200", -- 00000B50
+		X"0079A821", -- 00000B54
+		X"00C23025", -- 00000B58
+		X"00143D82", -- 00000B5C
+		X"00171827", -- 00000B60
+		X"00141280", -- 00000B64
+		X"8CAD0020", -- 00000B68
+		X"00DE8821", -- 00000B6C
+		X"0047A025", -- 00000B70
+		X"8CA6002C", -- 00000B74
+		X"02B81026", -- 00000B78
+		X"00761825", -- 00000B7C
+		X"00541026", -- 00000B80
+		X"00711826", -- 00000B84
+		X"00461021", -- 00000B88
+		X"006D1821", -- 00000B8C
+		X"0322C821", -- 00000B90
+		X"007E1821", -- 00000B94
+		X"006BF021", -- 00000B98
+		X"00193C42", -- 00000B9C
+		X"00163582", -- 00000BA0
+		X"00191BC0", -- 00000BA4
+		X"00161280", -- 00000BA8
+		X"0046B025", -- 00000BAC
+		X"00671825", -- 00000BB0
+		X"001E1542", -- 00000BB4
+		X"001E32C0", -- 00000BB8
+		X"0073C821", -- 00000BBC
+		X"00C23025", -- 00000BC0
+		X"00183D82", -- 00000BC4
+		X"00161027", -- 00000BC8
+		X"00181A80", -- 00000BCC
+		X"00D2F021", -- 00000BD0
+		X"0067C025", -- 00000BD4
+		X"8CA80030", -- 00000BD8
+		X"8CA70004", -- 00000BDC
+		X"03351826", -- 00000BE0
+		X"00511025", -- 00000BE4
+		X"00781826", -- 00000BE8
+		X"005E1026", -- 00000BEC
+		X"00681821", -- 00000BF0
+		X"00471021", -- 00000BF4
+		X"02639821", -- 00000BF8
+		X"00521021", -- 00000BFC
+		X"AFA70028", -- 00000C00
+		X"004B9021", -- 00000C04
+		X"00133E82", -- 00000C08
+		X"00113582", -- 00000C0C
+		X"00131980", -- 00000C10
+		X"00111280", -- 00000C14
+		X"00468825", -- 00000C18
+		X"00671825", -- 00000C1C
+		X"00121482", -- 00000C20
+		X"00123380", -- 00000C24
+		X"00749821", -- 00000C28
+		X"00C23025", -- 00000C2C
+		X"00153D82", -- 00000C30
+		X"00111027", -- 00000C34
+		X"00151A80", -- 00000C38
+		X"00D79021", -- 00000C3C
+		X"0067A825", -- 00000C40
+		X"8CA60028", -- 00000C44
+		X"8CA70034", -- 00000C48
+		X"02791826", -- 00000C4C
+		X"005E1025", -- 00000C50
+		X"00751826", -- 00000C54
+		X"00521026", -- 00000C58
+		X"00671821", -- 00000C5C
+		X"00461021", -- 00000C60
+		X"0283A021", -- 00000C64
+		X"00571021", -- 00000C68
+		X"AFA60020", -- 00000C6C
+		X"004BB821", -- 00000C70
+		X"00143E42", -- 00000C74
+		X"001E3582", -- 00000C78
+		X"001419C0", -- 00000C7C
+		X"001E1280", -- 00000C80
+		X"0046F025", -- 00000C84
+		X"00671825", -- 00000C88
+		X"00171482", -- 00000C8C
+		X"00173380", -- 00000C90
+		X"0078A021", -- 00000C94
+		X"00C23025", -- 00000C98
+		X"00193D82", -- 00000C9C
+		X"001E1827", -- 00000CA0
+		X"00191280", -- 00000CA4
+		X"8CB0000C", -- 00000CA8
+		X"00D6B821", -- 00000CAC
+		X"0047C825", -- 00000CB0
+		X"8CA80038", -- 00000CB4
+		X"02931026", -- 00000CB8
+		X"00721825", -- 00000CBC
+		X"00591026", -- 00000CC0
+		X"00771826", -- 00000CC4
+		X"00481021", -- 00000CC8
+		X"00701821", -- 00000CCC
+		X"0302C021", -- 00000CD0
+		X"00761821", -- 00000CD4
+		X"006BB021", -- 00000CD8
+		X"00183DC2", -- 00000CDC
+		X"00181A40", -- 00000CE0
+		X"00671825", -- 00000CE4
+		X"00123582", -- 00000CE8
+		X"00121280", -- 00000CEC
+		X"0075C021", -- 00000CF0
+		X"00469025", -- 00000CF4
+		X"00133D82", -- 00000CF8
+		X"00161502", -- 00000CFC
+		X"00163300", -- 00000D00
+		X"00131A80", -- 00000D04
+		X"00679825", -- 00000D08
+		X"00C23025", -- 00000D0C
+		X"8CA7003C", -- 00000D10
+		X"03141826", -- 00000D14
+		X"00121027", -- 00000D18
+		X"00D1B021", -- 00000D1C
+		X"00571025", -- 00000D20
+		X"8CA60030", -- 00000D24
+		X"00731826", -- 00000D28
+		X"00671821", -- 00000D2C
+		X"00561026", -- 00000D30
+		X"02A3A821", -- 00000D34
+		X"00461021", -- 00000D38
+		X"AFA60018", -- 00000D3C
+		X"00151E02", -- 00000D40
+		X"00511021", -- 00000D44
+		X"00153200", -- 00000D48
+		X"004B8821", -- 00000D4C
+		X"00C33025", -- 00000D50
+		X"00173D82", -- 00000D54
+		X"00171280", -- 00000D58
+		X"0047B825", -- 00000D5C
+		X"00D9A821", -- 00000D60
+		X"00114682", -- 00000D64
+		X"00111980", -- 00000D68
+		X"00143D82", -- 00000D6C
+		X"00141280", -- 00000D70
+		X"0047A025", -- 00000D74
+		X"00681825", -- 00000D78
+		X"00153027", -- 00000D7C
+		X"007E8821", -- 00000D80
+		X"8CA8001C", -- 00000D84
+		X"00D43024", -- 00000D88
+		X"02B81024", -- 00000D8C
+		X"00173827", -- 00000D90
+		X"00F63824", -- 00000D94
+		X"02371824", -- 00000D98
+		X"00461025", -- 00000D9C
+		X"00671825", -- 00000DA0
+		X"00481021", -- 00000DA4
+		X"3C0B5A82", -- 00000DA8
+		X"356B7999", -- 00000DAC
+		X"00591021", -- 00000DB0
+		X"006C1821", -- 00000DB4
+		X"3C0A5C4D", -- 00000DB8
+		X"354AD124", -- 00000DBC
+		X"004BC821", -- 00000DC0
+		X"007E1821", -- 00000DC4
+		X"006AF021", -- 00000DC8
+		X"00194642", -- 00000DCC
+		X"001919C0", -- 00000DD0
+		X"001E4DC2", -- 00000DD4
+		X"00681825", -- 00000DD8
+		X"00163D82", -- 00000DDC
+		X"001E3240", -- 00000DE0
+		X"00161280", -- 00000DE4
+		X"0073C821", -- 00000DE8
+		X"0047B025", -- 00000DEC
+		X"00C93025", -- 00000DF0
+		X"00181D82", -- 00000DF4
+		X"00181280", -- 00000DF8
+		X"00D2F021", -- 00000DFC
+		X"0043C025", -- 00000E00
+		X"00193027", -- 00000E04
+		X"00D83024", -- 00000E08
+		X"03351024", -- 00000E0C
+		X"00163827", -- 00000E10
+		X"00F13824", -- 00000E14
+		X"03D61824", -- 00000E18
+		X"00461025", -- 00000E1C
+		X"8FA6002C", -- 00000E20
+		X"00671825", -- 00000E24
+		X"8CA70010", -- 00000E28
+		X"00661821", -- 00000E2C
+		X"00721821", -- 00000E30
+		X"00471021", -- 00000E34
+		X"006A9021", -- 00000E38
+		X"00531021", -- 00000E3C
+		X"004B9821", -- 00000E40
+		X"00123CC2", -- 00000E44
+		X"00113582", -- 00000E48
+		X"00121B40", -- 00000E4C
+		X"00111280", -- 00000E50
+		X"00468825", -- 00000E54
+		X"00671825", -- 00000E58
+		X"00133682", -- 00000E5C
+		X"00131180", -- 00000E60
+		X"00779021", -- 00000E64
+		X"00461025", -- 00000E68
+		X"00113027", -- 00000E6C
+		X"00549821", -- 00000E70
+		X"00DE3024", -- 00000E74
+		X"02511024", -- 00000E78
+		X"00153D82", -- 00000E7C
+		X"00151A80", -- 00000E80
+		X"00461025", -- 00000E84
+		X"0067A825", -- 00000E88
+		X"00501021", -- 00000E8C
+		X"00131827", -- 00000E90
+		X"8CA80034", -- 00000E94
+		X"00751824", -- 00000E98
+		X"02793024", -- 00000E9C
+		X"00571021", -- 00000EA0
+		X"004AB821", -- 00000EA4
+		X"00C33025", -- 00000EA8
+		X"00C83021", -- 00000EAC
+		X"001E3D82", -- 00000EB0
+		X"00174442", -- 00000EB4
+		X"00171BC0", -- 00000EB8
+		X"001E1280", -- 00000EBC
+		X"0047F025", -- 00000EC0
+		X"00681825", -- 00000EC4
+		X"00D43021", -- 00000EC8
+		X"0076B821", -- 00000ECC
+		X"00CBA021", -- 00000ED0
+		X"001E1027", -- 00000ED4
+		X"00143E02", -- 00000ED8
+		X"00521024", -- 00000EDC
+		X"02FE1824", -- 00000EE0
+		X"00143200", -- 00000EE4
+		X"00C73025", -- 00000EE8
+		X"00621825", -- 00000EEC
+		X"00193D82", -- 00000EF0
+		X"00191280", -- 00000EF4
+		X"0047C825", -- 00000EF8
+		X"8FA20014", -- 00000EFC
+		X"00D8A021", -- 00000F00
+		X"00621821", -- 00000F04
+		X"00761821", -- 00000F08
+		X"00141027", -- 00000F0C
+		X"006AB021", -- 00000F10
+		X"00591024", -- 00000F14
+		X"8CA30004", -- 00000F18
+		X"02933024", -- 00000F1C
+		X"00C23025", -- 00000F20
+		X"00164642", -- 00000F24
+		X"00C33021", -- 00000F28
+		X"00123D82", -- 00000F2C
+		X"001619C0", -- 00000F30
+		X"00121280", -- 00000F34
+		X"00479025", -- 00000F38
+		X"00681825", -- 00000F3C
+		X"0071B021", -- 00000F40
+		X"00123827", -- 00000F44
+		X"00F73824", -- 00000F48
+		X"02D21824", -- 00000F4C
+		X"00D83021", -- 00000F50
+		X"00CBC021", -- 00000F54
+		X"00671825", -- 00000F58
+		X"8FA70008", -- 00000F5C
+		X"001834C2", -- 00000F60
+		X"00181340", -- 00000F64
+		X"00461025", -- 00000F68
+		X"00671821", -- 00000F6C
+		X"0055C021", -- 00000F70
+		X"00133582", -- 00000F74
+		X"00131280", -- 00000F78
+		X"00711821", -- 00000F7C
+		X"00469825", -- 00000F80
+		X"006A8821", -- 00000F84
+		X"00181027", -- 00000F88
+		X"00531024", -- 00000F8C
+		X"03141824", -- 00000F90
+		X"00114502", -- 00000F94
+		X"00113B00", -- 00000F98
+		X"00E83825", -- 00000F9C
+		X"00621825", -- 00000FA0
+		X"8CA80028", -- 00000FA4
+		X"00173582", -- 00000FA8
+		X"00171280", -- 00000FAC
+		X"0046B825", -- 00000FB0
+		X"00FE8821", -- 00000FB4
+		X"00681821", -- 00000FB8
+		X"00173027", -- 00000FBC
+		X"00D63024", -- 00000FC0
+		X"02371024", -- 00000FC4
+		X"00751821", -- 00000FC8
+		X"006BA821", -- 00000FCC
+		X"00461025", -- 00000FD0
+		X"8FA60034", -- 00000FD4
+		X"00153D42", -- 00000FD8
+		X"00151AC0", -- 00000FDC
+		X"00671825", -- 00000FE0
+		X"00461021", -- 00000FE4
+		X"0079A821", -- 00000FE8
+		X"005E1021", -- 00000FEC
+		X"00143582", -- 00000FF0
+		X"00141A80", -- 00000FF4
+		X"0066A025", -- 00000FF8
+		X"004AF021", -- 00000FFC
+		X"00153827", -- 00001000
+		X"00F43824", -- 00001004
+		X"001E4E02", -- 00001008
+		X"02B83024", -- 0000100C
+		X"00164582", -- 00001010
+		X"001E1A00", -- 00001014
+		X"00161280", -- 00001018
+		X"0048B025", -- 0000101C
+		X"00691825", -- 00001020
+		X"00C73025", -- 00001024
+		X"0072F021", -- 00001028
+		X"00CC3021", -- 0000102C
+		X"00161827", -- 00001030
+		X"8FA8000C", -- 00001034
+		X"00711824", -- 00001038
+		X"03D61024", -- 0000103C
+		X"00D93021", -- 00001040
+		X"00CBC821", -- 00001044
+		X"00431025", -- 00001048
+		X"00193DC2", -- 0000104C
+		X"00481021", -- 00001050
+		X"00191A40", -- 00001054
+		X"00671825", -- 00001058
+		X"00521021", -- 0000105C
+		X"0073C821", -- 00001060
+		X"004A9021", -- 00001064
+		X"00181D82", -- 00001068
+		X"00181280", -- 0000106C
+		X"0043C025", -- 00001070
+		X"00113582", -- 00001074
+		X"00191827", -- 00001078
+		X"00111280", -- 0000107C
+		X"00468825", -- 00001080
+		X"001245C2", -- 00001084
+		X"00781824", -- 00001088
+		X"03351024", -- 0000108C
+		X"00123A40", -- 00001090
+		X"00E83825", -- 00001094
+		X"00431025", -- 00001098
+		X"8CA3003C", -- 0000109C
+		X"00F79021", -- 000010A0
+		X"00113027", -- 000010A4
+		X"00DE3024", -- 000010A8
+		X"00431021", -- 000010AC
+		X"02511824", -- 000010B0
+		X"00661825", -- 000010B4
+		X"8FA60020", -- 000010B8
+		X"00531021", -- 000010BC
+		X"004B9821", -- 000010C0
+		X"00661821", -- 000010C4
+		X"00771821", -- 000010C8
+		X"00133642", -- 000010CC
+		X"001311C0", -- 000010D0
+		X"006AB821", -- 000010D4
+		X"00461025", -- 000010D8
+		X"00549821", -- 000010DC
+		X"00174D42", -- 000010E0
+		X"00154582", -- 000010E4
+		X"001E3D82", -- 000010E8
+		X"00171AC0", -- 000010EC
+		X"00153280", -- 000010F0
+		X"001E1280", -- 000010F4
+		X"0047F025", -- 000010F8
+		X"00C8A825", -- 000010FC
+		X"00691825", -- 00001100
+		X"00131027", -- 00001104
+		X"0076B821", -- 00001108
+		X"00551024", -- 0000110C
+		X"02791824", -- 00001110
+		X"001E3027", -- 00001114
+		X"8FA80024", -- 00001118
+		X"00D23024", -- 0000111C
+		X"00621825", -- 00001120
+		X"02FE1024", -- 00001124
+		X"00461025", -- 00001128
+		X"00701821", -- 0000112C
+		X"00741821", -- 00001130
+		X"00481021", -- 00001134
+		X"006BA021", -- 00001138
+		X"00561021", -- 0000113C
+		X"004AB021", -- 00001140
+		X"00141C42", -- 00001144
+		X"001433C0", -- 00001148
+		X"00C33025", -- 0000114C
+		X"00164642", -- 00001150
+		X"00123D82", -- 00001154
+		X"001619C0", -- 00001158
+		X"00121280", -- 0000115C
+		X"00479025", -- 00001160
+		X"00D8A021", -- 00001164
+		X"00681825", -- 00001168
+		X"00193D82", -- 0000116C
+		X"00191280", -- 00001170
+		X"0047C825", -- 00001174
+		X"0071B021", -- 00001178
+		X"00143027", -- 0000117C
+		X"00123827", -- 00001180
+		X"00D93024", -- 00001184
+		X"00F73824", -- 00001188
+		X"02931024", -- 0000118C
+		X"02D21824", -- 00001190
+		X"00461025", -- 00001194
+		X"00671825", -- 00001198
+		X"8CA60030", -- 0000119C
+		X"8FA70030", -- 000011A0
+		X"00461021", -- 000011A4
+		X"00671821", -- 000011A8
+		X"00581021", -- 000011AC
+		X"00711821", -- 000011B0
+		X"004BC021", -- 000011B4
+		X"006A8821", -- 000011B8
+		X"00184642", -- 000011BC
+		X"00114E42", -- 000011C0
+		X"00173D82", -- 000011C4
+		X"001819C0", -- 000011C8
+		X"001131C0", -- 000011CC
+		X"00171280", -- 000011D0
+		X"0047B825", -- 000011D4
+		X"00681825", -- 000011D8
+		X"00C93025", -- 000011DC
+		X"0075C021", -- 000011E0
+		X"00DE8821", -- 000011E4
+		X"00131D82", -- 000011E8
+		X"00173827", -- 000011EC
+		X"00131280", -- 000011F0
+		X"00439825", -- 000011F4
+		X"00F63824", -- 000011F8
+		X"02371824", -- 000011FC
+		X"00183027", -- 00001200
+		X"8CA80000", -- 00001204
+		X"00D33024", -- 00001208
+		X"03141024", -- 0000120C
+		X"00671825", -- 00001210
+		X"00461025", -- 00001214
+		X"006D1821", -- 00001218
+		X"007E1821", -- 0000121C
+		X"00481021", -- 00001220
+		X"006AF021", -- 00001224
+		X"00551021", -- 00001228
+		X"004BA821", -- 0000122C
+		X"001E3D02", -- 00001230
+		X"00163582", -- 00001234
+		X"001E1B00", -- 00001238
+		X"00161280", -- 0000123C
+		X"0046B025", -- 00001240
+		X"00671825", -- 00001244
+		X"00153502", -- 00001248
+		X"00151300", -- 0000124C
+		X"0072F021", -- 00001250
+		X"00461025", -- 00001254
+		X"00163027", -- 00001258
+		X"0059A821", -- 0000125C
+		X"00D13024", -- 00001260
+		X"03D61024", -- 00001264
+		X"00143D82", -- 00001268
+		X"00141A80", -- 0000126C
+		X"00461025", -- 00001270
+		X"8FA60018", -- 00001274
+		X"0067A025", -- 00001278
+		X"00151827", -- 0000127C
+		X"8CA70024", -- 00001280
+		X"00741824", -- 00001284
+		X"00461021", -- 00001288
+		X"02B83024", -- 0000128C
+		X"00C33025", -- 00001290
+		X"00521021", -- 00001294
+		X"004A9021", -- 00001298
+		X"00C73021", -- 0000129C
+		X"00124642", -- 000012A0
+		X"00D93021", -- 000012A4
+		X"00113D82", -- 000012A8
+		X"001219C0", -- 000012AC
+		X"00111280", -- 000012B0
+		X"00478825", -- 000012B4
+		X"00CBC821", -- 000012B8
+		X"00681825", -- 000012BC
+		X"00779021", -- 000012C0
+		X"00193C42", -- 000012C4
+		X"001933C0", -- 000012C8
+		X"00111027", -- 000012CC
+		X"00C73025", -- 000012D0
+		X"005E1024", -- 000012D4
+		X"02511824", -- 000012D8
+		X"00D3C821", -- 000012DC
+		X"8FA80004", -- 000012E0
+		X"00621825", -- 000012E4
+		X"00183D82", -- 000012E8
+		X"00181280", -- 000012EC
+		X"0047C025", -- 000012F0
+		X"00191027", -- 000012F4
+		X"00581024", -- 000012F8
+		X"03353024", -- 000012FC
+		X"00681821", -- 00001300
+		X"00771821", -- 00001304
+		X"00C23025", -- 00001308
+		X"8CA20014", -- 0000130C
+		X"006AB821", -- 00001310
+		X"00174682", -- 00001314
+		X"00C23021", -- 00001318
+		X"001E3D82", -- 0000131C
+		X"00171980", -- 00001320
+		X"001E1280", -- 00001324
+		X"0047F025", -- 00001328
+		X"00681825", -- 0000132C
+		X"0076B821", -- 00001330
+		X"00D33021", -- 00001334
+		X"001E3827", -- 00001338
+		X"00CB9821", -- 0000133C
+		X"00F23824", -- 00001340
+		X"02FE1824", -- 00001344
+		X"001335C2", -- 00001348
+		X"00131240", -- 0000134C
+		X"00671825", -- 00001350
+		X"8FA70010", -- 00001354
+		X"00461025", -- 00001358
+		X"00549821", -- 0000135C
+		X"00153582", -- 00001360
+		X"00671821", -- 00001364
+		X"00151280", -- 00001368
+		X"0046A825", -- 0000136C
+		X"00761821", -- 00001370
+		X"00131027", -- 00001374
+		X"006AB021", -- 00001378
+		X"00551024", -- 0000137C
+		X"02791824", -- 00001380
+		X"00164442", -- 00001384
+		X"00621825", -- 00001388
+		X"00123582", -- 0000138C
+		X"00163BC0", -- 00001390
+		X"00121280", -- 00001394
+		X"00469025", -- 00001398
+		X"00E83825", -- 0000139C
+		X"8FA80000", -- 000013A0
+		X"00F1B021", -- 000013A4
+		X"00123027", -- 000013A8
+		X"00D73024", -- 000013AC
+		X"02D21024", -- 000013B0
+		X"00681821", -- 000013B4
+		X"00741821", -- 000013B8
+		X"00461025", -- 000013BC
+		X"8FA60028", -- 000013C0
+		X"006BA021", -- 000013C4
+		X"00143D42", -- 000013C8
+		X"00141AC0", -- 000013CC
+		X"00461021", -- 000013D0
+		X"00671825", -- 000013D4
+		X"00511021", -- 000013D8
+		X"0078A021", -- 000013DC
+		X"004A8821", -- 000013E0
+		X"00193582", -- 000013E4
+		X"00191A80", -- 000013E8
+		X"0066C825", -- 000013EC
+		X"00114CC2", -- 000013F0
+		X"00143827", -- 000013F4
+		X"00174582", -- 000013F8
+		X"00111B40", -- 000013FC
+		X"00171280", -- 00001400
+		X"0048B825", -- 00001404
+		X"00F93824", -- 00001408
+		X"02933024", -- 0000140C
+		X"00691825", -- 00001410
+		X"007E8821", -- 00001414
+		X"00C73025", -- 00001418
+		X"00171827", -- 0000141C
+		X"8CA70038", -- 00001420
+		X"8FA8001C", -- 00001424
+		X"00761824", -- 00001428
+		X"02371024", -- 0000142C
+		X"00C73021", -- 00001430
+		X"00431025", -- 00001434
+		X"00D83021", -- 00001438
+		X"00481021", -- 0000143C
+		X"00CBC021", -- 00001440
+		X"005E1021", -- 00001444
+		X"004AF021", -- 00001448
+		X"00183E42", -- 0000144C
+		X"001819C0", -- 00001450
+		X"00133582", -- 00001454
+		X"00131280", -- 00001458
+		X"00469825", -- 0000145C
+		X"00671825", -- 00001460
+		X"001E32C0", -- 00001464
+		X"001E3D42", -- 00001468
+		X"0075C021", -- 0000146C
+		X"00C73025", -- 00001470
+		X"00D2F021", -- 00001474
+		X"00181827", -- 00001478
+		X"00163D82", -- 0000147C
+		X"00163280", -- 00001480
+		X"00C7B025", -- 00001484
+		X"00731824", -- 00001488
+		X"8CA6002C", -- 0000148C
+		X"03141024", -- 00001490
+		X"00431025", -- 00001494
+		X"00111827", -- 00001498
+		X"8FA70030", -- 0000149C
+		X"007E1825", -- 000014A0
+		X"00461021", -- 000014A4
+		X"00551021", -- 000014A8
+		X"00761826", -- 000014AC
+		X"004BA821", -- 000014B0
+		X"00671821", -- 000014B4
+		X"3C0A6D70", -- 000014B8
+		X"354A3EF3", -- 000014BC
+		X"001534C2", -- 000014C0
+		X"00721821", -- 000014C4
+		X"00151340", -- 000014C8
+		X"006A9021", -- 000014CC
+		X"00461025", -- 000014D0
+		X"0059A821", -- 000014D4
+		X"001245C2", -- 000014D8
+		X"00143582", -- 000014DC
+		X"00121A40", -- 000014E0
+		X"00141280", -- 000014E4
+		X"0046A025", -- 000014E8
+		X"00681825", -- 000014EC
+		X"00153827", -- 000014F0
+		X"00779021", -- 000014F4
+		X"00F44024", -- 000014F8
+		X"02B81824", -- 000014FC
+		X"00114D82", -- 00001500
+		X"001E1027", -- 00001504
+		X"00113280", -- 00001508
+		X"00C98825", -- 0000150C
+		X"00681825", -- 00001510
+		X"8FA6000C", -- 00001514
+		X"00521025", -- 00001518
+		X"00511026", -- 0000151C
+		X"006D1821", -- 00001520
+		X"00791821", -- 00001524
+		X"00461021", -- 00001528
+		X"006BC821", -- 0000152C
+		X"00571021", -- 00001530
+		X"004AB821", -- 00001534
+		X"00191D02", -- 00001538
+		X"00191300", -- 0000153C
+		X"00431025", -- 00001540
+		X"00173642", -- 00001544
+		X"001719C0", -- 00001548
+		X"0053C821", -- 0000154C
+		X"00661825", -- 00001550
+		X"00181280", -- 00001554
+		X"00183582", -- 00001558
+		X"0076B821", -- 0000155C
+		X"0046C025", -- 00001560
+		X"00F93825", -- 00001564
+		X"001E3582", -- 00001568
+		X"00121027", -- 0000156C
+		X"001E1A80", -- 00001570
+		X"0066F025", -- 00001574
+		X"00F83826", -- 00001578
+		X"8FA30028", -- 0000157C
+		X"00571025", -- 00001580
+		X"005E1026", -- 00001584
+		X"00F03821", -- 00001588
+		X"3C096ED9", -- 0000158C
+		X"3529EBA1", -- 00001590
+		X"00F33821", -- 00001594
+		X"00431021", -- 00001598
+		X"00E99821", -- 0000159C
+		X"00561021", -- 000015A0
+		X"004AB021", -- 000015A4
+		X"00131D42", -- 000015A8
+		X"001312C0", -- 000015AC
+		X"00431025", -- 000015B0
+		X"00163442", -- 000015B4
+		X"00161BC0", -- 000015B8
+		X"00549821", -- 000015BC
+		X"00661825", -- 000015C0
+		X"00153D82", -- 000015C4
+		X"00151280", -- 000015C8
+		X"0071B021", -- 000015CC
+		X"0047A825", -- 000015D0
+		X"00193027", -- 000015D4
+		X"00123D82", -- 000015D8
+		X"00121A80", -- 000015DC
+		X"00679025", -- 000015E0
+		X"00D33025", -- 000015E4
+		X"8CA70028", -- 000015E8
+		X"00171027", -- 000015EC
+		X"00D53026", -- 000015F0
+		X"00561025", -- 000015F4
+		X"00521026", -- 000015F8
+		X"00C73021", -- 000015FC
+		X"00D43021", -- 00001600
+		X"00501021", -- 00001604
+		X"00C9A021", -- 00001608
+		X"00511021", -- 0000160C
+		X"004A8821", -- 00001610
+		X"00141CC2", -- 00001614
+		X"00141340", -- 00001618
+		X"00431025", -- 0000161C
+		X"00113542", -- 00001620
+		X"00111AC0", -- 00001624
+		X"0058A021", -- 00001628
+		X"00661825", -- 0000162C
+		X"00193D82", -- 00001630
+		X"00133027", -- 00001634
+		X"00191280", -- 00001638
+		X"007E8821", -- 0000163C
+		X"0047C825", -- 00001640
+		X"8CA80038", -- 00001644
+		X"00D43025", -- 00001648
+		X"00173D82", -- 0000164C
+		X"00161027", -- 00001650
+		X"00171A80", -- 00001654
+		X"0067B825", -- 00001658
+		X"00D93026", -- 0000165C
+		X"8FA30014", -- 00001660
+		X"00511025", -- 00001664
+		X"00571026", -- 00001668
+		X"00C83021", -- 0000166C
+		X"00D83021", -- 00001670
+		X"00431021", -- 00001674
+		X"00C9C021", -- 00001678
+		X"005E1021", -- 0000167C
+		X"004AF021", -- 00001680
+		X"00181E82", -- 00001684
+		X"00181180", -- 00001688
+		X"00431025", -- 0000168C
+		X"001E3602", -- 00001690
+		X"001E1A00", -- 00001694
+		X"0055C021", -- 00001698
+		X"00661825", -- 0000169C
+		X"00133D82", -- 000016A0
+		X"00131280", -- 000016A4
+		X"0072F021", -- 000016A8
+		X"00479825", -- 000016AC
+		X"00143027", -- 000016B0
+		X"00163D82", -- 000016B4
+		X"00161A80", -- 000016B8
+		X"0067B025", -- 000016BC
+		X"00D83025", -- 000016C0
+		X"8CA70010", -- 000016C4
+		X"00111027", -- 000016C8
+		X"00D33026", -- 000016CC
+		X"005E1025", -- 000016D0
+		X"00561026", -- 000016D4
+		X"00C73021", -- 000016D8
+		X"00D53021", -- 000016DC
+		X"00481021", -- 000016E0
+		X"00C9A821", -- 000016E4
+		X"00521021", -- 000016E8
+		X"004A9021", -- 000016EC
+		X"00151E42", -- 000016F0
+		X"001511C0", -- 000016F4
+		X"00431025", -- 000016F8
+		X"00123682", -- 000016FC
+		X"00121980", -- 00001700
+		X"0059A821", -- 00001704
+		X"00661825", -- 00001708
+		X"00143D82", -- 0000170C
+		X"00141280", -- 00001710
+		X"00779021", -- 00001714
+		X"0047A025", -- 00001718
+		X"00183027", -- 0000171C
+		X"00113D82", -- 00001720
+		X"00111A80", -- 00001724
+		X"00678825", -- 00001728
+		X"00D53025", -- 0000172C
+		X"8CA30024", -- 00001730
+		X"001E1027", -- 00001734
+		X"00D43026", -- 00001738
+		X"00521025", -- 0000173C
+		X"00511026", -- 00001740
+		X"00C33021", -- 00001744
+		X"00D93021", -- 00001748
+		X"004C1021", -- 0000174C
+		X"00C9C821", -- 00001750
+		X"00571021", -- 00001754
+		X"004AB821", -- 00001758
+		X"00191C82", -- 0000175C
+		X"00191380", -- 00001760
+		X"00431025", -- 00001764
+		X"00173682", -- 00001768
+		X"00171980", -- 0000176C
+		X"0053C821", -- 00001770
+		X"00661825", -- 00001774
+		X"00183D82", -- 00001778
+		X"00181280", -- 0000177C
+		X"0076B821", -- 00001780
+		X"0047C025", -- 00001784
+		X"00153027", -- 00001788
+		X"001E3D82", -- 0000178C
+		X"001E1A80", -- 00001790
+		X"0067F025", -- 00001794
+		X"00D93025", -- 00001798
+		X"8CA7003C", -- 0000179C
+		X"00121027", -- 000017A0
+		X"8FA80010", -- 000017A4
+		X"00D83026", -- 000017A8
+		X"00571025", -- 000017AC
+		X"005E1026", -- 000017B0
+		X"00C73021", -- 000017B4
+		X"00D33021", -- 000017B8
+		X"00481021", -- 000017BC
+		X"00C99821", -- 000017C0
+		X"00561021", -- 000017C4
+		X"004AB021", -- 000017C8
+		X"00131DC2", -- 000017CC
+		X"00131240", -- 000017D0
+		X"00431025", -- 000017D4
+		X"00163482", -- 000017D8
+		X"00161B80", -- 000017DC
+		X"00549821", -- 000017E0
+		X"00661825", -- 000017E4
+		X"00153D82", -- 000017E8
+		X"00193027", -- 000017EC
+		X"00151280", -- 000017F0
+		X"0071B021", -- 000017F4
+		X"0047A825", -- 000017F8
+		X"00D33025", -- 000017FC
+		X"00123D82", -- 00001800
+		X"00171027", -- 00001804
+		X"00121A80", -- 00001808
+		X"00679025", -- 0000180C
+		X"00D53026", -- 00001810
+		X"8FA7002C", -- 00001814
+		X"00561025", -- 00001818
+		X"00521026", -- 0000181C
+		X"00CD3021", -- 00001820
+		X"00D43021", -- 00001824
+		X"00471021", -- 00001828
+		X"00C9A021", -- 0000182C
+		X"00511021", -- 00001830
+		X"004A8821", -- 00001834
+		X"00141CC2", -- 00001838
+		X"00141340", -- 0000183C
+		X"00431025", -- 00001840
+		X"00113502", -- 00001844
+		X"00111B00", -- 00001848
+		X"0058A021", -- 0000184C
+		X"00661825", -- 00001850
+		X"00193D82", -- 00001854
+		X"00133027", -- 00001858
+		X"00191280", -- 0000185C
+		X"007E8821", -- 00001860
+		X"0047C825", -- 00001864
+		X"8CA80004", -- 00001868
+		X"00D43025", -- 0000186C
+		X"00173D82", -- 00001870
+		X"00161027", -- 00001874
+		X"00171A80", -- 00001878
+		X"0067B825", -- 0000187C
+		X"00D93026", -- 00001880
+		X"00511025", -- 00001884
+		X"00571026", -- 00001888
+		X"00C83021", -- 0000188C
+		X"00D83021", -- 00001890
+		X"004D1021", -- 00001894
+		X"00C9C021", -- 00001898
+		X"005E1021", -- 0000189C
+		X"004AF021", -- 000018A0
+		X"00181C42", -- 000018A4
+		X"001813C0", -- 000018A8
+		X"00431025", -- 000018AC
+		X"001E34C2", -- 000018B0
+		X"001E1B40", -- 000018B4
+		X"0055C021", -- 000018B8
+		X"00661825", -- 000018BC
+		X"00133D82", -- 000018C0
+		X"00131280", -- 000018C4
+		X"0072F021", -- 000018C8
+		X"00479825", -- 000018CC
+		X"00143027", -- 000018D0
+		X"00163D82", -- 000018D4
+		X"00161A80", -- 000018D8
+		X"0067B025", -- 000018DC
+		X"00D83025", -- 000018E0
+		X"8FA30000", -- 000018E4
+		X"00111027", -- 000018E8
+		X"8FA70018", -- 000018EC
+		X"00D33026", -- 000018F0
+		X"005E1025", -- 000018F4
+		X"00561026", -- 000018F8
+		X"00C33021", -- 000018FC
+		X"00D53021", -- 00001900
+		X"00471021", -- 00001904
+		X"00C9A821", -- 00001908
+		X"00521021", -- 0000190C
+		X"004A9021", -- 00001910
+		X"00151C82", -- 00001914
+		X"00151380", -- 00001918
+		X"00431025", -- 0000191C
+		X"001236C2", -- 00001920
+		X"00121940", -- 00001924
+		X"0059A821", -- 00001928
+		X"00661825", -- 0000192C
+		X"00143D82", -- 00001930
+		X"00183027", -- 00001934
+		X"00141280", -- 00001938
+		X"00779021", -- 0000193C
+		X"0047A025", -- 00001940
+		X"8CA8001C", -- 00001944
+		X"00D53025", -- 00001948
+		X"00113D82", -- 0000194C
+		X"001E1027", -- 00001950
+		X"00111A80", -- 00001954
+		X"00678825", -- 00001958
+		X"00D43026", -- 0000195C
+		X"8FA3001C", -- 00001960
+		X"00521025", -- 00001964
+		X"00511026", -- 00001968
+		X"00C83021", -- 0000196C
+		X"00D93021", -- 00001970
+		X"00431021", -- 00001974
+		X"00C9C821", -- 00001978
+		X"00571021", -- 0000197C
+		X"004AB821", -- 00001980
+		X"00191E02", -- 00001984
+		X"00191200", -- 00001988
+		X"00431025", -- 0000198C
+		X"00173482", -- 00001990
+		X"00171B80", -- 00001994
+		X"0053C821", -- 00001998
+		X"00661825", -- 0000199C
+		X"00183D82", -- 000019A0
+		X"00181280", -- 000019A4
+		X"0076B821", -- 000019A8
+		X"0047C025", -- 000019AC
+		X"00153027", -- 000019B0
+		X"001E3D82", -- 000019B4
+		X"001E1A80", -- 000019B8
+		X"0067F025", -- 000019BC
+		X"00D93025", -- 000019C0
+		X"8CA70000", -- 000019C4
+		X"00121027", -- 000019C8
+		X"8FA80020", -- 000019CC
+		X"00D83026", -- 000019D0
+		X"00571025", -- 000019D4
+		X"005E1026", -- 000019D8
+		X"00C73021", -- 000019DC
+		X"00D33021", -- 000019E0
+		X"00481021", -- 000019E4
+		X"00C99821", -- 000019E8
+		X"00561021", -- 000019EC
+		X"004AB021", -- 000019F0
+		X"00131CC2", -- 000019F4
+		X"00131340", -- 000019F8
+		X"00431025", -- 000019FC
+		X"001634C2", -- 00001A00
+		X"00161B40", -- 00001A04
+		X"00549821", -- 00001A08
+		X"00661825", -- 00001A0C
+		X"00153D82", -- 00001A10
+		X"00193027", -- 00001A14
+		X"00151280", -- 00001A18
+		X"0071B021", -- 00001A1C
+		X"0047A825", -- 00001A20
+		X"00D33025", -- 00001A24
+		X"00123D82", -- 00001A28
+		X"00171027", -- 00001A2C
+		X"00121A80", -- 00001A30
+		X"00679025", -- 00001A34
+		X"00D53026", -- 00001A38
+		X"8FA70008", -- 00001A3C
+		X"00561025", -- 00001A40
+		X"00521026", -- 00001A44
+		X"00CC3021", -- 00001A48
+		X"00D43021", -- 00001A4C
+		X"00471021", -- 00001A50
+		X"00C9A021", -- 00001A54
+		X"00511021", -- 00001A58
+		X"004A8821", -- 00001A5C
+		X"00141E82", -- 00001A60
+		X"00141180", -- 00001A64
+		X"00431025", -- 00001A68
+		X"001134C2", -- 00001A6C
+		X"00111B40", -- 00001A70
+		X"0058A021", -- 00001A74
+		X"8CA80010", -- 00001A78
+		X"00661825", -- 00001A7C
+		X"00193D82", -- 00001A80
+		X"00191280", -- 00001A84
+		X"007E8821", -- 00001A88
+		X"0047C825", -- 00001A8C
+		X"00133027", -- 00001A90
+		X"00173D82", -- 00001A94
+		X"00171A80", -- 00001A98
+		X"AFA80038", -- 00001A9C
+		X"0067B825", -- 00001AA0
+		X"00D43025", -- 00001AA4
+		X"8CA30034", -- 00001AA8
+		X"00161027", -- 00001AAC
+		X"00D93026", -- 00001AB0
+		X"00511025", -- 00001AB4
+		X"00571026", -- 00001AB8
+		X"00C33021", -- 00001ABC
+		X"00D83021", -- 00001AC0
+		X"00481021", -- 00001AC4
+		X"00C9C021", -- 00001AC8
+		X"005E1021", -- 00001ACC
+		X"004AF021", -- 00001AD0
+		X"00181EC2", -- 00001AD4
+		X"00181140", -- 00001AD8
+		X"00431025", -- 00001ADC
+		X"001E3642", -- 00001AE0
+		X"001E19C0", -- 00001AE4
+		X"0055C021", -- 00001AE8
+		X"00661825", -- 00001AEC
+		X"00133D82", -- 00001AF0
+		X"00131280", -- 00001AF4
+		X"0072F021", -- 00001AF8
+		X"00479825", -- 00001AFC
+		X"00143027", -- 00001B00
+		X"00163D82", -- 00001B04
+		X"00111027", -- 00001B08
+		X"00161A80", -- 00001B0C
+		X"0067B025", -- 00001B10
+		X"8FA80034", -- 00001B14
+		X"8CA7002C", -- 00001B18
+		X"00D83025", -- 00001B1C
+		X"005E1025", -- 00001B20
+		X"00D33026", -- 00001B24
+		X"00561026", -- 00001B28
+		X"00C73021", -- 00001B2C
+		X"00481021", -- 00001B30
+		X"00D53021", -- 00001B34
+		X"00521021", -- 00001B38
+		X"00C9A821", -- 00001B3C
+		X"004A9021", -- 00001B40
+		X"00151D02", -- 00001B44
+		X"00123EC2", -- 00001B48
+		X"00151300", -- 00001B4C
+		X"00123140", -- 00001B50
+		X"00431025", -- 00001B54
+		X"00C73025", -- 00001B58
+		X"00141A80", -- 00001B5C
+		X"00143D82", -- 00001B60
+		X"00D79021", -- 00001B64
+		X"0059A821", -- 00001B68
+		X"0067A025", -- 00001B6C
+		X"00181027", -- 00001B70
+		X"00113582", -- 00001B74
+		X"00111A80", -- 00001B78
+		X"00668825", -- 00001B7C
+		X"00551025", -- 00001B80
+		X"8CA30014", -- 00001B84
+		X"00541026", -- 00001B88
+		X"00123027", -- 00001B8C
+		X"00D13024", -- 00001B90
+		X"00431021", -- 00001B94
+		X"025E1824", -- 00001B98
+		X"00661825", -- 00001B9C
+		X"00591021", -- 00001BA0
+		X"006D1821", -- 00001BA4
+		X"3C0B7A6D", -- 00001BA8
+		X"356B76E9", -- 00001BAC
+		X"0049C821", -- 00001BB0
+		X"00771821", -- 00001BB4
+		X"006BB821", -- 00001BB8
+		X"00193642", -- 00001BBC
+		X"001911C0", -- 00001BC0
+		X"00461025", -- 00001BC4
+		X"00174442", -- 00001BC8
+		X"001733C0", -- 00001BCC
+		X"0053C821", -- 00001BD0
+		X"00C83025", -- 00001BD4
+		X"00183D82", -- 00001BD8
+		X"00181280", -- 00001BDC
+		X"00D6B821", -- 00001BE0
+		X"0047C025", -- 00001BE4
+		X"00151827", -- 00001BE8
+		X"001E3582", -- 00001BEC
+		X"001E1280", -- 00001BF0
+		X"0046F025", -- 00001BF4
+		X"00791825", -- 00001BF8
+		X"8CA60030", -- 00001BFC
+		X"00781826", -- 00001C00
+		X"00661821", -- 00001C04
+		X"00173027", -- 00001C08
+		X"00DE3024", -- 00001C0C
+		X"02F21024", -- 00001C10
+		X"00731821", -- 00001C14
+		X"00461025", -- 00001C18
+		X"00699821", -- 00001C1C
+		X"004C1021", -- 00001C20
+		X"001346C2", -- 00001C24
+		X"00153D82", -- 00001C28
+		X"00133140", -- 00001C2C
+		X"00151A80", -- 00001C30
+		X"00561021", -- 00001C34
+		X"0067A825", -- 00001C38
+		X"00C83025", -- 00001C3C
+		X"004BB021", -- 00001C40
+		X"00D49821", -- 00001C44
+		X"00163EC2", -- 00001C48
+		X"00153027", -- 00001C4C
+		X"00161140", -- 00001C50
+		X"00D93024", -- 00001C54
+		X"02751824", -- 00001C58
+		X"00471025", -- 00001C5C
+		X"8CA70004", -- 00001C60
+		X"00661825", -- 00001C64
+		X"0051B021", -- 00001C68
+		X"00671821", -- 00001C6C
+		X"00123582", -- 00001C70
+		X"00121280", -- 00001C74
+		X"3C0A8F1B", -- 00001C78
+		X"354ABCDC", -- 00001C7C
+		X"00469025", -- 00001C80
+		X"00741821", -- 00001C84
+		X"00161027", -- 00001C88
+		X"006AA021", -- 00001C8C
+		X"00521024", -- 00001C90
+		X"02D71824", -- 00001C94
+		X"00144542", -- 00001C98
+		X"00621825", -- 00001C9C
+		X"00193582", -- 00001CA0
+		X"00143AC0", -- 00001CA4
+		X"00191280", -- 00001CA8
+		X"0046C825", -- 00001CAC
+		X"00E83825", -- 00001CB0
+		X"8FA80038", -- 00001CB4
+		X"00F8A021", -- 00001CB8
+		X"00193027", -- 00001CBC
+		X"00D33024", -- 00001CC0
+		X"02991024", -- 00001CC4
+		X"00681821", -- 00001CC8
+		X"00711821", -- 00001CCC
+		X"00461025", -- 00001CD0
+		X"8CA60024", -- 00001CD4
+		X"006B8821", -- 00001CD8
+		X"00113E02", -- 00001CDC
+		X"00111A00", -- 00001CE0
+		X"00461021", -- 00001CE4
+		X"00671825", -- 00001CE8
+		X"00581021", -- 00001CEC
+		X"007E8821", -- 00001CF0
+		X"004AC021", -- 00001CF4
+		X"00173582", -- 00001CF8
+		X"8CA20004", -- 00001CFC
+		X"00171A80", -- 00001D00
+		X"0066B825", -- 00001D04
+		X"00184D02", -- 00001D08
+		X"00181B00", -- 00001D0C
+		X"AFA2003C", -- 00001D10
+		X"00691825", -- 00001D14
+		X"00113827", -- 00001D18
+		X"0075C021", -- 00001D1C
+		X"00F73824", -- 00001D20
+		X"8FA3003C", -- 00001D24
+		X"02363024", -- 00001D28
+		X"00134582", -- 00001D2C
+		X"00131280", -- 00001D30
+		X"00C73025", -- 00001D34
+		X"00489825", -- 00001D38
+		X"00C33021", -- 00001D3C
+		X"00DE3021", -- 00001D40
+		X"00131827", -- 00001D44
+		X"00CBF021", -- 00001D48
+		X"00741824", -- 00001D4C
+		X"8CA6002C", -- 00001D50
+		X"03131024", -- 00001D54
+		X"00431025", -- 00001D58
+		X"00461021", -- 00001D5C
+		X"001E1AC0", -- 00001D60
+		X"001E3542", -- 00001D64
+		X"00661825", -- 00001D68
+		X"00551021", -- 00001D6C
+		X"0072F021", -- 00001D70
+		X"004AA821", -- 00001D74
+		X"00161D82", -- 00001D78
+		X"00161280", -- 00001D7C
+		X"0043B025", -- 00001D80
+		X"00154482", -- 00001D84
+		X"00143582", -- 00001D88
+		X"00153B80", -- 00001D8C
+		X"001E1827", -- 00001D90
+		X"00141280", -- 00001D94
+		X"0046A025", -- 00001D98
+		X"00E83825", -- 00001D9C
+		X"00761824", -- 00001DA0
+		X"03D11024", -- 00001DA4
+		X"00F9A821", -- 00001DA8
+		X"00431025", -- 00001DAC
+		X"00143027", -- 00001DB0
+		X"8CA70028", -- 00001DB4
+		X"00D83024", -- 00001DB8
+		X"02B41824", -- 00001DBC
+		X"00501021", -- 00001DC0
+		X"00661825", -- 00001DC4
+		X"00521021", -- 00001DC8
+		X"004B9021", -- 00001DCC
+		X"00671821", -- 00001DD0
+		X"00123482", -- 00001DD4
+		X"00791821", -- 00001DD8
+		X"00121380", -- 00001DDC
+		X"006AC821", -- 00001DE0
+		X"00461025", -- 00001DE4
+		X"00579021", -- 00001DE8
+		X"00194C42", -- 00001DEC
+		X"00183D82", -- 00001DF0
+		X"00114582", -- 00001DF4
+		X"00191BC0", -- 00001DF8
+		X"00181280", -- 00001DFC
+		X"00113280", -- 00001E00
+		X"0047C025", -- 00001E04
+		X"00C88825", -- 00001E08
+		X"00691825", -- 00001E0C
+		X"00121027", -- 00001E10
+		X"0073C821", -- 00001E14
+		X"00511024", -- 00001E18
+		X"025E1824", -- 00001E1C
+		X"00183027", -- 00001E20
+		X"8FA8002C", -- 00001E24
+		X"00D53024", -- 00001E28
+		X"00621825", -- 00001E2C
+		X"03381024", -- 00001E30
+		X"00461025", -- 00001E34
+		X"8CA60000", -- 00001E38
+		X"00681821", -- 00001E3C
+		X"00771821", -- 00001E40
+		X"00461021", -- 00001E44
+		X"006BB821", -- 00001E48
+		X"00531021", -- 00001E4C
+		X"004A9821", -- 00001E50
+		X"00171C82", -- 00001E54
+		X"00173380", -- 00001E58
+		X"00C33025", -- 00001E5C
+		X"00134482", -- 00001E60
+		X"00153D82", -- 00001E64
+		X"00131B80", -- 00001E68
+		X"00151280", -- 00001E6C
+		X"00D6B821", -- 00001E70
+		X"0047A825", -- 00001E74
+		X"00681825", -- 00001E78
+		X"001E3D82", -- 00001E7C
+		X"001E1280", -- 00001E80
+		X"00749821", -- 00001E84
+		X"0047F025", -- 00001E88
+		X"00153027", -- 00001E8C
+		X"00173827", -- 00001E90
+		X"8FA80030", -- 00001E94
+		X"00D93024", -- 00001E98
+		X"00FE3824", -- 00001E9C
+		X"02751024", -- 00001EA0
+		X"02F21824", -- 00001EA4
+		X"00461025", -- 00001EA8
+		X"00671825", -- 00001EAC
+		X"00681821", -- 00001EB0
+		X"004D1021", -- 00001EB4
+		X"00541021", -- 00001EB8
+		X"00761821", -- 00001EBC
+		X"004AA021", -- 00001EC0
+		X"006BB021", -- 00001EC4
+		X"00144442", -- 00001EC8
+		X"00164E82", -- 00001ECC
+		X"00193D82", -- 00001ED0
+		X"001433C0", -- 00001ED4
+		X"00161980", -- 00001ED8
+		X"00191280", -- 00001EDC
+		X"0047C825", -- 00001EE0
+		X"00C83025", -- 00001EE4
+		X"00691825", -- 00001EE8
+		X"0071B021", -- 00001EEC
+		X"00D8A021", -- 00001EF0
+		X"00121D82", -- 00001EF4
+		X"00193827", -- 00001EF8
+		X"00121280", -- 00001EFC
+		X"00439025", -- 00001F00
+		X"8CA80030", -- 00001F04
+		X"00F33824", -- 00001F08
+		X"02991824", -- 00001F0C
+		X"00163027", -- 00001F10
+		X"00D23024", -- 00001F14
+		X"02D71024", -- 00001F18
+		X"00671825", -- 00001F1C
+		X"8CA70000", -- 00001F20
+		X"00461025", -- 00001F24
+		X"00681821", -- 00001F28
+		X"00781821", -- 00001F2C
+		X"00471021", -- 00001F30
+		X"006AC021", -- 00001F34
+		X"00511021", -- 00001F38
+		X"004B8821", -- 00001F3C
+		X"AFA70040", -- 00001F40
+		X"00133582", -- 00001F44
+		X"00183DC2", -- 00001F48
+		X"00181A40", -- 00001F4C
+		X"00131280", -- 00001F50
+		X"00469825", -- 00001F54
+		X"00671825", -- 00001F58
+		X"00113482", -- 00001F5C
+		X"00111380", -- 00001F60
+		X"0075C021", -- 00001F64
+		X"00461025", -- 00001F68
+		X"00133827", -- 00001F6C
+		X"00173582", -- 00001F70
+		X"00171A80", -- 00001F74
+		X"005E8821", -- 00001F78
+		X"0066B825", -- 00001F7C
+		X"00F43824", -- 00001F80
+		X"8CA30010", -- 00001F84
+		X"03131024", -- 00001F88
+		X"00471025", -- 00001F8C
+		X"00113027", -- 00001F90
+		X"8CAF0014", -- 00001F94
+		X"00D73024", -- 00001F98
+		X"00431021", -- 00001F9C
+		X"02361824", -- 00001FA0
+		X"00551021", -- 00001FA4
+		X"00661825", -- 00001FA8
+		X"004AA821", -- 00001FAC
+		X"006F1821", -- 00001FB0
+		X"00154602", -- 00001FB4
+		X"007E1821", -- 00001FB8
+		X"00143D82", -- 00001FBC
+		X"00153200", -- 00001FC0
+		X"00141280", -- 00001FC4
+		X"0047A025", -- 00001FC8
+		X"00C83025", -- 00001FCC
+		X"006BF021", -- 00001FD0
+		X"00D9A821", -- 00001FD4
+		X"001E1E82", -- 00001FD8
+		X"00141027", -- 00001FDC
+		X"001E3180", -- 00001FE0
+		X"00C33025", -- 00001FE4
+		X"00581024", -- 00001FE8
+		X"02B41824", -- 00001FEC
+		X"00621825", -- 00001FF0
+		X"00163D82", -- 00001FF4
+		X"00161280", -- 00001FF8
+		X"00D2F021", -- 00001FFC
+		X"0047B025", -- 00002000
+		X"8CA60034", -- 00002004
+		X"8CA70030", -- 00002008
+		X"001E1027", -- 0000200C
+		X"AFA70044", -- 00002010
+		X"00561024", -- 00002014
+		X"00661821", -- 00002018
+		X"03D13024", -- 0000201C
+		X"00791821", -- 00002020
+		X"00C23025", -- 00002024
+		X"8FA20044", -- 00002028
+		X"006AC821", -- 0000202C
+		X"001945C2", -- 00002030
+		X"00183D82", -- 00002034
+		X"00C23021", -- 00002038
+		X"00191A40", -- 0000203C
+		X"00181280", -- 00002040
+		X"0047C025", -- 00002044
+		X"00681825", -- 00002048
+		X"00D23021", -- 0000204C
+		X"0073C821", -- 00002050
+		X"00CB9021", -- 00002054
+		X"00183827", -- 00002058
+		X"00F53824", -- 0000205C
+		X"001235C2", -- 00002060
+		X"03381024", -- 00002064
+		X"00121A40", -- 00002068
+		X"00661825", -- 0000206C
+		X"00471025", -- 00002070
+		X"00779021", -- 00002074
+		X"00501021", -- 00002078
+		X"00113582", -- 0000207C
+		X"00111A80", -- 00002080
+		X"00668825", -- 00002084
+		X"00531021", -- 00002088
+		X"00121827", -- 0000208C
+		X"004A9821", -- 00002090
+		X"00711824", -- 00002094
+		X"025E3024", -- 00002098
+		X"8CAE0008", -- 0000209C
+		X"00134482", -- 000020A0
+		X"00C33025", -- 000020A4
+		X"00133B80", -- 000020A8
+		X"00151D82", -- 000020AC
+		X"00151280", -- 000020B0
+		X"0043A825", -- 000020B4
+		X"00E83825", -- 000020B8
+		X"00F49821", -- 000020BC
+		X"00151827", -- 000020C0
+		X"00CE3021", -- 000020C4
+		X"8CA7001C", -- 000020C8
+		X"00791824", -- 000020CC
+		X"02751024", -- 000020D0
+		X"00D73021", -- 000020D4
+		X"00CBB821", -- 000020D8
+		X"00431025", -- 000020DC
+		X"00173502", -- 000020E0
+		X"00171B00", -- 000020E4
+		X"00471021", -- 000020E8
+		X"00661825", -- 000020EC
+		X"00541021", -- 000020F0
+		X"0076B821", -- 000020F4
+		X"004AA021", -- 000020F8
+		X"001E3582", -- 000020FC
+		X"001E1A80", -- 00002100
+		X"0066F025", -- 00002104
+		X"00144EC2", -- 00002108
+		X"00173827", -- 0000210C
+		X"00194582", -- 00002110
+		X"00141940", -- 00002114
+		X"00191280", -- 00002118
+		X"0048C825", -- 0000211C
+		X"00FE3824", -- 00002120
+		X"8FA80034", -- 00002124
+		X"02F23024", -- 00002128
+		X"00691825", -- 0000212C
+		X"0078A021", -- 00002130
+		X"00C73025", -- 00002134
+		X"00191827", -- 00002138
+		X"00731824", -- 0000213C
+		X"02991024", -- 00002140
+		X"00C83021", -- 00002144
+		X"00D63021", -- 00002148
+		X"00431025", -- 0000214C
+		X"8CA3003C", -- 00002150
+		X"00CBB021", -- 00002154
+		X"001635C2", -- 00002158
+		X"00431021", -- 0000215C
+		X"00161A40", -- 00002160
+		X"00661825", -- 00002164
+		X"00581021", -- 00002168
+		X"0071B021", -- 0000216C
+		X"004AC021", -- 00002170
+		X"00121D82", -- 00002174
+		X"00121280", -- 00002178
+		X"00439025", -- 0000217C
+		X"00184682", -- 00002180
+		X"00131D82", -- 00002184
+		X"00183980", -- 00002188
+		X"00163027", -- 0000218C
+		X"00131280", -- 00002190
+		X"00439825", -- 00002194
+		X"00E83825", -- 00002198
+		X"00D23024", -- 0000219C
+		X"8CA80024", -- 000021A0
+		X"02D71824", -- 000021A4
+		X"00661825", -- 000021A8
+		X"00681821", -- 000021AC
+		X"00F5C021", -- 000021B0
+		X"00133027", -- 000021B4
+		X"00711821", -- 000021B8
+		X"006B8821", -- 000021BC
+		X"00D43024", -- 000021C0
+		X"8CA30038", -- 000021C4
+		X"03131024", -- 000021C8
+		X"00461025", -- 000021CC
+		X"00431021", -- 000021D0
+		X"00113502", -- 000021D4
+		X"00551021", -- 000021D8
+		X"00111B00", -- 000021DC
+		X"004AA821", -- 000021E0
+		X"AFA80048", -- 000021E4
+		X"00661825", -- 000021E8
+		X"00174582", -- 000021EC
+		X"00173280", -- 000021F0
+		X"007E8821", -- 000021F4
+		X"00C8B825", -- 000021F8
+		X"00154E02", -- 000021FC
+		X"8CA6001C", -- 00002200
+		X"00143D82", -- 00002204
+		X"00151A00", -- 00002208
+		X"00141280", -- 0000220C
+		X"0047A025", -- 00002210
+		X"00691825", -- 00002214
+		X"00111027", -- 00002218
+		X"AFA6004C", -- 0000221C
+		X"0079A821", -- 00002220
+		X"8FA7004C", -- 00002224
+		X"00571024", -- 00002228
+		X"02361824", -- 0000222C
+		X"00143027", -- 00002230
+		X"00D83024", -- 00002234
+		X"00621825", -- 00002238
+		X"02B41024", -- 0000223C
+		X"00461025", -- 00002240
+		X"00671821", -- 00002244
+		X"007E1821", -- 00002248
+		X"004F1021", -- 0000224C
+		X"006BF021", -- 00002250
+		X"00591021", -- 00002254
+		X"004AC821", -- 00002258
+		X"001E1EC2", -- 0000225C
+		X"001E3140", -- 00002260
+		X"00C33025", -- 00002264
+		X"00194682", -- 00002268
+		X"00183D82", -- 0000226C
+		X"00191980", -- 00002270
+		X"00181280", -- 00002274
+		X"00D2F021", -- 00002278
+		X"0047C025", -- 0000227C
+		X"00681825", -- 00002280
+		X"00163D82", -- 00002284
+		X"00161280", -- 00002288
+		X"0073C821", -- 0000228C
+		X"0047B025", -- 00002290
+		X"00183027", -- 00002294
+		X"001E3827", -- 00002298
+		X"8CA80028", -- 0000229C
+		X"00D53024", -- 000022A0
+		X"00F63824", -- 000022A4
+		X"03381024", -- 000022A8
+		X"03D11824", -- 000022AC
+		X"00461025", -- 000022B0
+		X"00671825", -- 000022B4
+		X"00681821", -- 000022B8
+		X"004C1021", -- 000022BC
+		X"00531021", -- 000022C0
+		X"00721821", -- 000022C4
+		X"004A9821", -- 000022C8
+		X"006B9021", -- 000022CC
+		X"AFA80050", -- 000022D0
+		X"00124C42", -- 000022D4
+		X"001346C2", -- 000022D8
+		X"00153D82", -- 000022DC
+		X"00133140", -- 000022E0
+		X"00121BC0", -- 000022E4
+		X"00151280", -- 000022E8
+		X"0047A825", -- 000022EC
+		X"00C83025", -- 000022F0
+		X"00691825", -- 000022F4
+		X"00779021", -- 000022F8
+		X"00D49821", -- 000022FC
+		X"00113D82", -- 00002300
+		X"00151827", -- 00002304
+		X"00111280", -- 00002308
+		X"00478825", -- 0000230C
+		X"00791824", -- 00002310
+		X"02751024", -- 00002314
+		X"00123027", -- 00002318
+		X"8CA70038", -- 0000231C
+		X"00D13024", -- 00002320
+		X"00431025", -- 00002324
+		X"025E1824", -- 00002328
+		X"00661825", -- 0000232C
+		X"004E1021", -- 00002330
+		X"00541021", -- 00002334
+		X"00671821", -- 00002338
+		X"004AA021", -- 0000233C
+		X"00771821", -- 00002340
+		X"00192D82", -- 00002344
+		X"00191280", -- 00002348
+		X"0045C825", -- 0000234C
+		X"006BB821", -- 00002350
+		X"00141502", -- 00002354
+		X"00142B00", -- 00002358
+		X"00A22825", -- 0000235C
+		X"00173602", -- 00002360
+		X"00171200", -- 00002364
+		X"00461025", -- 00002368
+		X"00B8A021", -- 0000236C
+		X"0056B821", -- 00002370
+		X"00191827", -- 00002374
+		X"001E2D82", -- 00002378
+		X"001E1280", -- 0000237C
+		X"0045F025", -- 00002380
+		X"00731825", -- 00002384
+		X"8FA20004", -- 00002388
+		X"8FA60044", -- 0000238C
+		X"02F22826", -- 00002390
+		X"00741826", -- 00002394
+		X"00621821", -- 00002398
+		X"00BE2826", -- 0000239C
+		X"3C08A953", -- 000023A0
+		X"3508FD4E", -- 000023A4
+		X"00A62821", -- 000023A8
+		X"00781821", -- 000023AC
+		X"0068C021", -- 000023B0
+		X"02C5B021", -- 000023B4
+		X"00133582", -- 000023B8
+		X"00131280", -- 000023BC
+		X"00469825", -- 000023C0
+		X"00182A40", -- 000023C4
+		X"001815C2", -- 000023C8
+		X"00163602", -- 000023CC
+		X"00161A00", -- 000023D0
+		X"00A22825", -- 000023D4
+		X"00661825", -- 000023D8
+		X"00B5C021", -- 000023DC
+		X"0071B021", -- 000023E0
+		X"00131027", -- 000023E4
+		X"00122D82", -- 000023E8
+		X"00121A80", -- 000023EC
+		X"00659025", -- 000023F0
+		X"00541025", -- 000023F4
+		X"8FA30008", -- 000023F8
+		X"00581026", -- 000023FC
+		X"8FA50030", -- 00002400
+		X"00431021", -- 00002404
+		X"02D71826", -- 00002408
+		X"00721826", -- 0000240C
+		X"00651821", -- 00002410
+		X"00551021", -- 00002414
+		X"0048A821", -- 00002418
+		X"02238821", -- 0000241C
+		X"00142D82", -- 00002420
+		X"00141280", -- 00002424
+		X"0045A025", -- 00002428
+		X"001136C2", -- 0000242C
+		X"00151442", -- 00002430
+		X"00152BC0", -- 00002434
+		X"00111940", -- 00002438
+		X"00A22825", -- 0000243C
+		X"00661825", -- 00002440
+		X"00141027", -- 00002444
+		X"00B9A821", -- 00002448
+		X"007E8821", -- 0000244C
+		X"00581025", -- 00002450
+		X"00172D82", -- 00002454
+		X"00171A80", -- 00002458
+		X"0065B825", -- 0000245C
+		X"00551026", -- 00002460
+		X"8FA50050", -- 00002464
+		X"02361826", -- 00002468
+		X"00771826", -- 0000246C
+		X"004F1021", -- 00002470
+		X"00651821", -- 00002474
+		X"00591021", -- 00002478
+		X"0048C821", -- 0000247C
+		X"03C3F021", -- 00002480
+		X"00182D82", -- 00002484
+		X"00181280", -- 00002488
+		X"0045C025", -- 0000248C
+		X"001E3502", -- 00002490
+		X"001916C2", -- 00002494
+		X"00192940", -- 00002498
+		X"001E1B00", -- 0000249C
+		X"00A22825", -- 000024A0
+		X"00661825", -- 000024A4
+		X"00181027", -- 000024A8
+		X"00B3C821", -- 000024AC
+		X"0072F021", -- 000024B0
+		X"8FA60010", -- 000024B4
+		X"00551025", -- 000024B8
+		X"00162D82", -- 000024BC
+		X"00161A80", -- 000024C0
+		X"0065B025", -- 000024C4
+		X"00591026", -- 000024C8
+		X"8FA50038", -- 000024CC
+		X"03D11826", -- 000024D0
+		X"00461021", -- 000024D4
+		X"00761826", -- 000024D8
+		X"00651821", -- 000024DC
+		X"00531021", -- 000024E0
+		X"00489821", -- 000024E4
+		X"02439021", -- 000024E8
+		X"00152D82", -- 000024EC
+		X"00151280", -- 000024F0
+		X"0045A825", -- 000024F4
+		X"001235C2", -- 000024F8
+		X"00131542", -- 000024FC
+		X"00132AC0", -- 00002500
+		X"00121A40", -- 00002504
+		X"00A22825", -- 00002508
+		X"00661825", -- 0000250C
+		X"00151027", -- 00002510
+		X"00B49821", -- 00002514
+		X"00779021", -- 00002518
+		X"8FA60014", -- 0000251C
+		X"00591025", -- 00002520
+		X"00112D82", -- 00002524
+		X"00111A80", -- 00002528
+		X"00658825", -- 0000252C
+		X"00531026", -- 00002530
+		X"8FA5003C", -- 00002534
+		X"025E1826", -- 00002538
+		X"00461021", -- 0000253C
+		X"00711826", -- 00002540
+		X"00651821", -- 00002544
+		X"00541021", -- 00002548
+		X"0048A021", -- 0000254C
+		X"02E3B821", -- 00002550
+		X"00192D82", -- 00002554
+		X"00191280", -- 00002558
+		X"0045C825", -- 0000255C
+		X"00173502", -- 00002560
+		X"00141682", -- 00002564
+		X"00142980", -- 00002568
+		X"00171B00", -- 0000256C
+		X"00A22825", -- 00002570
+		X"00661825", -- 00002574
+		X"00191027", -- 00002578
+		X"00B8A021", -- 0000257C
+		X"0076B821", -- 00002580
+		X"8FA60018", -- 00002584
+		X"00531025", -- 00002588
+		X"001E2D82", -- 0000258C
+		X"001E1A80", -- 00002590
+		X"0065F025", -- 00002594
+		X"00541026", -- 00002598
+		X"02F21826", -- 0000259C
+		X"00461021", -- 000025A0
+		X"007E1826", -- 000025A4
+		X"00581021", -- 000025A8
+		X"006F1821", -- 000025AC
+		X"0048C021", -- 000025B0
+		X"02C3B021", -- 000025B4
+		X"00132D82", -- 000025B8
+		X"00131280", -- 000025BC
+		X"00459825", -- 000025C0
+		X"001636C2", -- 000025C4
+		X"00181602", -- 000025C8
+		X"00182A00", -- 000025CC
+		X"00161940", -- 000025D0
+		X"00A22825", -- 000025D4
+		X"00661825", -- 000025D8
+		X"00131027", -- 000025DC
+		X"00B5C021", -- 000025E0
+		X"0071B021", -- 000025E4
+		X"00541025", -- 000025E8
+		X"00122D82", -- 000025EC
+		X"00121A80", -- 000025F0
+		X"00659025", -- 000025F4
+		X"00581026", -- 000025F8
+		X"02D71826", -- 000025FC
+		X"00721826", -- 00002600
+		X"004E1021", -- 00002604
+		X"00551021", -- 00002608
+		X"006D1821", -- 0000260C
+		X"0048A821", -- 00002610
+		X"02238821", -- 00002614
+		X"00142D82", -- 00002618
+		X"00141280", -- 0000261C
+		X"0045A025", -- 00002620
+		X"00113482", -- 00002624
+		X"001514C2", -- 00002628
+		X"00152B40", -- 0000262C
+		X"00111B80", -- 00002630
+		X"00A22825", -- 00002634
+		X"00661825", -- 00002638
+		X"00B9A821", -- 0000263C
+		X"007E8821", -- 00002640
+		X"00141027", -- 00002644
+		X"00172D82", -- 00002648
+		X"00171A80", -- 0000264C
+		X"0065B825", -- 00002650
+		X"00581025", -- 00002654
+		X"8FA50020", -- 00002658
+		X"8FA6004C", -- 0000265C
+		X"02361826", -- 00002660
+		X"00551026", -- 00002664
+		X"00451021", -- 00002668
+		X"00771826", -- 0000266C
+		X"00661821", -- 00002670
+		X"00591021", -- 00002674
+		X"0048C821", -- 00002678
+		X"03C3F021", -- 0000267C
+		X"00182D82", -- 00002680
+		X"00181280", -- 00002684
+		X"0045C025", -- 00002688
+		X"001E3682", -- 0000268C
+		X"00191502", -- 00002690
+		X"00192B00", -- 00002694
+		X"001E1980", -- 00002698
+		X"00A22825", -- 0000269C
+		X"00661825", -- 000026A0
+		X"00181027", -- 000026A4
+		X"00B3C821", -- 000026A8
+		X"0072F021", -- 000026AC
+		X"00551025", -- 000026B0
+		X"00162D82", -- 000026B4
+		X"00161A80", -- 000026B8
+		X"0065B025", -- 000026BC
+		X"00591026", -- 000026C0
+		X"03D11826", -- 000026C4
+		X"00471021", -- 000026C8
+		X"00761826", -- 000026CC
+		X"00531021", -- 000026D0
+		X"006C1821", -- 000026D4
+		X"00489821", -- 000026D8
+		X"02439021", -- 000026DC
+		X"00152D82", -- 000026E0
+		X"00151280", -- 000026E4
+		X"0045A825", -- 000026E8
+		X"00123602", -- 000026EC
+		X"001316C2", -- 000026F0
+		X"00132940", -- 000026F4
+		X"00121A00", -- 000026F8
+		X"00A22825", -- 000026FC
+		X"00661825", -- 00002700
+		X"00B49821", -- 00002704
+		X"00779021", -- 00002708
+		X"00151027", -- 0000270C
+		X"00112D82", -- 00002710
+		X"00111A80", -- 00002714
+		X"00658825", -- 00002718
+		X"00591025", -- 0000271C
+		X"8FA50028", -- 00002720
+		X"025E1826", -- 00002724
+		X"00531026", -- 00002728
+		X"00451021", -- 0000272C
+		X"00711826", -- 00002730
+		X"00541021", -- 00002734
+		X"006E1821", -- 00002738
+		X"0048A021", -- 0000273C
+		X"02E3B821", -- 00002740
+		X"00192D82", -- 00002744
+		X"00191280", -- 00002748
+		X"0045C825", -- 0000274C
+		X"001734C2", -- 00002750
+		X"00141502", -- 00002754
+		X"00142B00", -- 00002758
+		X"00171B40", -- 0000275C
+		X"00A22825", -- 00002760
+		X"00661825", -- 00002764
+		X"00191027", -- 00002768
+		X"00B8A021", -- 0000276C
+		X"0076B821", -- 00002770
+		X"00531025", -- 00002774
+		X"001E2D82", -- 00002778
+		X"001E1A80", -- 0000277C
+		X"0065F025", -- 00002780
+		X"8FA60034", -- 00002784
+		X"02F21826", -- 00002788
+		X"00541026", -- 0000278C
+		X"00501021", -- 00002790
+		X"007E1826", -- 00002794
+		X"00661821", -- 00002798
+		X"00581021", -- 0000279C
+		X"0048C021", -- 000027A0
+		X"02C3B021", -- 000027A4
+		X"00132D82", -- 000027A8
+		X"00131280", -- 000027AC
+		X"00459825", -- 000027B0
+		X"00163682", -- 000027B4
+		X"001814C2", -- 000027B8
+		X"00182B40", -- 000027BC
+		X"00161980", -- 000027C0
+		X"00A22825", -- 000027C4
+		X"00661825", -- 000027C8
+		X"00131027", -- 000027CC
+		X"00B5C021", -- 000027D0
+		X"0071B021", -- 000027D4
+		X"00541025", -- 000027D8
+		X"00122D82", -- 000027DC
+		X"00121A80", -- 000027E0
+		X"00659025", -- 000027E4
+		X"00581026", -- 000027E8
+		X"02D71826", -- 000027EC
+		X"00721826", -- 000027F0
+		X"004D1021", -- 000027F4
+		X"00671821", -- 000027F8
+		X"00551021", -- 000027FC
+		X"0048A821", -- 00002800
+		X"02238821", -- 00002804
+		X"00142D82", -- 00002808
+		X"00141280", -- 0000280C
+		X"0045A025", -- 00002810
+		X"001136C2", -- 00002814
+		X"00151482", -- 00002818
+		X"00152B80", -- 0000281C
+		X"00111940", -- 00002820
+		X"00A22825", -- 00002824
+		X"00661825", -- 00002828
+		X"00141027", -- 0000282C
+		X"00B9A821", -- 00002830
+		X"007E8821", -- 00002834
+		X"8FA7002C", -- 00002838
+		X"00581025", -- 0000283C
+		X"00172D82", -- 00002840
+		X"00171A80", -- 00002844
+		X"0065B825", -- 00002848
+		X"00551026", -- 0000284C
+		X"8FA50040", -- 00002850
+		X"02361826", -- 00002854
+		X"00471021", -- 00002858
+		X"00771826", -- 0000285C
+		X"00651821", -- 00002860
+		X"00591021", -- 00002864
+		X"0048C821", -- 00002868
+		X"03C3F021", -- 0000286C
+		X"00182D82", -- 00002870
+		X"00181280", -- 00002874
+		X"0045C025", -- 00002878
+		X"001E3442", -- 0000287C
+		X"00191542", -- 00002880
+		X"00192AC0", -- 00002884
+		X"001E1BC0", -- 00002888
+		X"00A22825", -- 0000288C
+		X"00661825", -- 00002890
+		X"00181027", -- 00002894
+		X"00B3C821", -- 00002898
+		X"0072F021", -- 0000289C
+		X"00551025", -- 000028A0
+		X"00162D82", -- 000028A4
+		X"00161A80", -- 000028A8
+		X"0065B025", -- 000028AC
+		X"00591026", -- 000028B0
+		X"03D11826", -- 000028B4
+		X"00761826", -- 000028B8
+		X"004C1021", -- 000028BC
+		X"00701821", -- 000028C0
+		X"00531021", -- 000028C4
+		X"00489821", -- 000028C8
+		X"02439021", -- 000028CC
+		X"00152D82", -- 000028D0
+		X"00151280", -- 000028D4
+		X"0045A825", -- 000028D8
+		X"001234C2", -- 000028DC
+		X"00131602", -- 000028E0
+		X"00132A00", -- 000028E4
+		X"00121B40", -- 000028E8
+		X"00A22825", -- 000028EC
+		X"00661825", -- 000028F0
+		X"00151027", -- 000028F4
+		X"00B49821", -- 000028F8
+		X"00779021", -- 000028FC
+		X"8FA60030", -- 00002900
+		X"00591025", -- 00002904
+		X"00112D82", -- 00002908
+		X"00111A80", -- 0000290C
+		X"00658825", -- 00002910
+		X"8FA70048", -- 00002914
+		X"025E1826", -- 00002918
+		X"00531026", -- 0000291C
+		X"00461021", -- 00002920
+		X"00711826", -- 00002924
+		X"00671821", -- 00002928
+		X"00541021", -- 0000292C
+		X"0048A021", -- 00002930
+		X"02E3B821", -- 00002934
+		X"00192D82", -- 00002938
+		X"00191280", -- 0000293C
+		X"0045C825", -- 00002940
+		X"00141EC2", -- 00002944
+		X"00173542", -- 00002948
+		X"00142940", -- 0000294C
+		X"001712C0", -- 00002950
+		X"00A32825", -- 00002954
+		X"00461025", -- 00002958
+		X"00B8A021", -- 0000295C
+		X"0056B821", -- 00002960
+		X"001E2D82", -- 00002964
+		X"001E1280", -- 00002968
+		X"00191827", -- 0000296C
+		X"0045F025", -- 00002970
+		X"00731825", -- 00002974
+		X"8FA20034", -- 00002978
+		X"00741826", -- 0000297C
+		X"00621821", -- 00002980
+		X"00781821", -- 00002984
+		X"0068C021", -- 00002988
+		X"02F21026", -- 0000298C
+		X"8FA3002C", -- 00002990
+		X"8C860008", -- 00002994
+		X"00133D82", -- 00002998
+		X"00132A80", -- 0000299C
+		X"00A79825", -- 000029A0
+		X"005E1026", -- 000029A4
+		X"00431021", -- 000029A8
+		X"00D33021", -- 000029AC
+		X"02C2B021", -- 000029B0
+		X"00DE3021", -- 000029B4
+		X"00181682", -- 000029B8
+		X"00182980", -- 000029BC
+		X"00161D42", -- 000029C0
+		X"8C8A0004", -- 000029C4
+		X"8C87000C", -- 000029C8
+		X"8C880000", -- 000029CC
+		X"00A22825", -- 000029D0
+		X"00164AC0", -- 000029D4
+		X"AC860004", -- 000029D8
+		X"8C860010", -- 000029DC
+		X"01234825", -- 000029E0
+		X"00B5C021", -- 000029E4
+		X"00121D82", -- 000029E8
+		X"00121280", -- 000029EC
+		X"0131B021", -- 000029F0
+		X"01545021", -- 000029F4
+		X"00D53021", -- 000029F8
+		X"00439025", -- 000029FC
+		X"00F93821", -- 00002A00
+		X"01184021", -- 00002A04
+		X"024A9021", -- 00002A08
+		X"00F13821", -- 00002A0C
+		X"00D63021", -- 00002A10
+		X"01174021", -- 00002A14
+		X"AC920000", -- 00002A18
+		X"AC870008", -- 00002A1C
+		X"AC86000C", -- 00002A20
+		X"AC880010", -- 00002A24
+		X"8FBE0078", -- 00002A28
+		X"8FB70074", -- 00002A2C
+		X"8FB60070", -- 00002A30
+		X"8FB5006C", -- 00002A34
+		X"8FB40068", -- 00002A38
+		X"8FB30064", -- 00002A3C
+		X"8FB20060", -- 00002A40
+		X"8FB1005C", -- 00002A44
+		X"8FB00058", -- 00002A48
+		X"03E00008", -- 00002A4C
+		X"27BD0080", -- 00002A50
+		X"27BDFF98", -- 00002A54
+		X"AFB10054", -- 00002A58
+		X"27B10010", -- 00002A5C
+		X"AFB40060", -- 00002A60
+		X"AFB20058", -- 00002A64
+		X"AFB00050", -- 00002A68
+		X"00C09021", -- 00002A6C
+		X"0080A021", -- 00002A70
+		X"24060040", -- 00002A74
+		X"00A08021", -- 00002A78
+		X"02202021", -- 00002A7C
+		X"00002821", -- 00002A80
+		X"AFB3005C", -- 00002A84
+		X"AFBF0064", -- 00002A88
+		X"0C100AEB", -- 00002A8C
+		X"00E09821", -- 00002A90
+		X"3247003F", -- 00002A94
+		X"10E0000F", -- 00002A98
+		X"00003021", -- 00002A9C
+		X"00062882", -- 00002AA0
+		X"00052880", -- 00002AA4
+		X"92040000", -- 00002AA8
+		X"00B12821", -- 00002AAC
+		X"30C20003", -- 00002AB0
+		X"000210C0", -- 00002AB4
+		X"8CA30000", -- 00002AB8
+		X"00442004", -- 00002ABC
+		X"24C60001", -- 00002AC0
+		X"00641826", -- 00002AC4
+		X"00C7102B", -- 00002AC8
+		X"ACA30000", -- 00002ACC
+		X"1440FFF3", -- 00002AD0
+		X"26100001", -- 00002AD4
+		X"3245003C", -- 00002AD8
+		X"32430003", -- 00002ADC
+		X"00B12821", -- 00002AE0
+		X"000318C0", -- 00002AE4
+		X"24630007", -- 00002AE8
+		X"8CA40000", -- 00002AEC
+		X"24020001", -- 00002AF0
+		X"00621004", -- 00002AF4
+		X"00822026", -- 00002AF8
+		X"2CE30038", -- 00002AFC
+		X"10600012", -- 00002B00
+		X"ACA40000", -- 00002B04
+		X"001318C0", -- 00002B08
+		X"00121742", -- 00002B0C
+		X"00431025", -- 00002B10
+		X"02802021", -- 00002B14
+		X"001218C0", -- 00002B18
+		X"02202821", -- 00002B1C
+		X"AFA30048", -- 00002B20
+		X"0C1001A3", -- 00002B24
+		X"AFA2004C", -- 00002B28
+		X"8FBF0064", -- 00002B2C
+		X"8FB40060", -- 00002B30
+		X"8FB3005C", -- 00002B34
+		X"8FB20058", -- 00002B38
+		X"8FB10054", -- 00002B3C
+		X"8FB00050", -- 00002B40
+		X"03E00008", -- 00002B44
+		X"27BD0068", -- 00002B48
+		X"02802021", -- 00002B4C
+		X"0C1001A3", -- 00002B50
+		X"02202821", -- 00002B54
+		X"02202021", -- 00002B58
+		X"00002821", -- 00002B5C
+		X"0C100AEB", -- 00002B60
+		X"24060040", -- 00002B64
+		X"001318C0", -- 00002B68
+		X"00121742", -- 00002B6C
+		X"00431025", -- 00002B70
+		X"02802021", -- 00002B74
+		X"001218C0", -- 00002B78
+		X"02202821", -- 00002B7C
+		X"AFA30048", -- 00002B80
+		X"0C1001A3", -- 00002B84
+		X"AFA2004C", -- 00002B88
+		X"8FBF0064", -- 00002B8C
+		X"8FB40060", -- 00002B90
+		X"8FB3005C", -- 00002B94
+		X"8FB20058", -- 00002B98
+		X"8FB10054", -- 00002B9C
+		X"8FB00050", -- 00002BA0
+		X"03E00008", -- 00002BA4
+		X"27BD0068", -- 00002BA8
+		X"2CC20010", -- 00002BAC
+		X"14400027", -- 00002BB0
+		X"00801821", -- 00002BB4
+		X"30870003", -- 00002BB8
+		X"10E00009", -- 00002BBC
+		X"2CE20004", -- 00002BC0
+		X"08100AF7", -- 00002BC4
+		X"00000000", -- 00002BC8
+		X"A0650000", -- 00002BCC
+		X"2CE20004", -- 00002BD0
+		X"24C6FFFF", -- 00002BD4
+		X"24630001", -- 00002BD8
+		X"1440FFFB", -- 00002BDC
+		X"24E70001", -- 00002BE0
+		X"30A500FF", -- 00002BE4
+		X"00603821", -- 00002BE8
+		X"10A00005", -- 00002BEC
+		X"00A04021", -- 00002BF0
+		X"00051200", -- 00002BF4
+		X"00A24025", -- 00002BF8
+		X"00081C00", -- 00002BFC
+		X"01034025", -- 00002C00
+		X"000610C2", -- 00002C04
+		X"08100B07", -- 00002C08
+		X"30C60007", -- 00002C0C
+		X"ACE80000", -- 00002C10
+		X"ACE80004", -- 00002C14
+		X"24E70008", -- 00002C18
+		X"1440FFFC", -- 00002C1C
+		X"2442FFFF", -- 00002C20
+		X"2CC20004", -- 00002C24
+		X"14400004", -- 00002C28
+		X"00000000", -- 00002C2C
+		X"ACE80000", -- 00002C30
+		X"24C6FFFC", -- 00002C34
+		X"24E70004", -- 00002C38
+		X"10C00006", -- 00002C3C
+		X"00E01821", -- 00002C40
+		X"A0650000", -- 00002C44
+		X"24C6FFFF", -- 00002C48
+		X"24630001", -- 00002C4C
+		X"14C0FFFC", -- 00002C50
+		X"00000000", -- 00002C54
+		X"03E00008", -- 00002C58
+		X"00801021", -- 00002C5C
+		X"00000000", -- 00002C60
+		X"00000000", -- 00002C64
+		X"00000000", -- 00002C68
+		X"00000000", -- 00002C6C
+		X"00000000", -- 00002C70
+		X"00000000", -- 00002C74
+		X"00000000", -- 00002C78
+		X"00000000", -- 00002C7C
+		X"00000000", -- 00002C80
+		X"00000000", -- 00002C84
+		X"00000000", -- 00002C88
+		X"00000000", -- 00002C8C
+		X"00000000", -- 00002C90
+		X"00000000", -- 00002C94
+		X"00000000", -- 00002C98
+		X"00000000", -- 00002C9C
+		X"00000000", -- 00002CA0
+		X"00000000", -- 00002CA4
+		X"00000000", -- 00002CA8
+		X"00000000", -- 00002CAC
+		X"00000000", -- 00002CB0
+		X"00000000", -- 00002CB4
+		X"00000000", -- 00002CB8
+		X"00000000", -- 00002CBC
+		X"00000000", -- 00002CC0
+		X"00000000", -- 00002CC4
+		X"00000000", -- 00002CC8
+		X"00000000", -- 00002CCC
+		X"00000000", -- 00002CD0
+		X"00000000", -- 00002CD4
+		X"00000000", -- 00002CD8
+		X"00000000", -- 00002CDC
+		X"00000000", -- 00002CE0
+		X"00000000", -- 00002CE4
+		X"00000000", -- 00002CE8
+		X"00000000", -- 00002CEC
+		X"00000000", -- 00002CF0
+		X"00000000", -- 00002CF4
+		X"00000000", -- 00002CF8
+		X"00000000", -- 00002CFC
+		X"00000000", -- 00002D00
+		X"00000000", -- 00002D04
+		X"00000000", -- 00002D08
+		X"00000000", -- 00002D0C
+		X"00000000", -- 00002D10
+		X"00000000", -- 00002D14
+		X"00000000", -- 00002D18
+		X"00000000", -- 00002D1C
+		X"00000000", -- 00002D20
+		X"00000000", -- 00002D24
+		X"00000000", -- 00002D28
+		X"00000000", -- 00002D2C
+		X"00000000", -- 00002D30
+		X"00000000", -- 00002D34
+		X"00000000", -- 00002D38
+		X"00000000", -- 00002D3C
+		X"00000000", -- 00002D40
+		X"00000000", -- 00002D44
+		X"00000000", -- 00002D48
+		X"00000000", -- 00002D4C
+		X"00000000", -- 00002D50
+		X"00000000", -- 00002D54
+		X"00000000", -- 00002D58
+		X"00000000", -- 00002D5C
+		X"00000000", -- 00002D60
+		X"00000000", -- 00002D64
+		X"00000000", -- 00002D68
+		X"00000000", -- 00002D6C
+		X"00000000", -- 00002D70
+		X"00000000", -- 00002D74
+		X"00000000", -- 00002D78
+		X"00000000", -- 00002D7C
+		X"00000000", -- 00002D80
+		X"00000000", -- 00002D84
+		X"00000000", -- 00002D88
+		X"00000000", -- 00002D8C
+		X"00000000", -- 00002D90
+		X"00000000", -- 00002D94
+		X"00000000", -- 00002D98
+		X"00000000", -- 00002D9C
+		X"00000000", -- 00002DA0
+		X"00000000", -- 00002DA4
+		X"00000000", -- 00002DA8
+		X"00000000", -- 00002DAC
+		X"00000000", -- 00002DB0
+		X"00000000", -- 00002DB4
+		X"00000000", -- 00002DB8
+		X"00000000", -- 00002DBC
+		X"00000000", -- 00002DC0
+		X"00000000", -- 00002DC4
+		X"00000000", -- 00002DC8
+		X"00000000", -- 00002DCC
+		X"00000000", -- 00002DD0
+		X"00000000", -- 00002DD4
+		X"00000000", -- 00002DD8
+		X"00000000", -- 00002DDC
+		X"00000000", -- 00002DE0
+		X"00000000", -- 00002DE4
+		X"00000000", -- 00002DE8
+		X"00000000", -- 00002DEC
+		X"00000000", -- 00002DF0
+		X"00000000", -- 00002DF4
+		X"00000000", -- 00002DF8
+		X"00000000", -- 00002DFC
+		X"00000000", -- 00002E00
+		X"00000000", -- 00002E04
+		X"00000000", -- 00002E08
+		X"00000000", -- 00002E0C
+		X"00000000", -- 00002E10
+		X"00000000", -- 00002E14
+		X"00000000", -- 00002E18
+		X"00000000", -- 00002E1C
+		X"00000000", -- 00002E20
+		X"00000000", -- 00002E24
+		X"00000000", -- 00002E28
+		X"00000000", -- 00002E2C
+		X"00000000", -- 00002E30
+		X"00000000", -- 00002E34
+		X"00000000", -- 00002E38
+		X"00000000", -- 00002E3C
+		X"00000000", -- 00002E40
+		X"00000000", -- 00002E44
+		X"00000000", -- 00002E48
+		X"00000000", -- 00002E4C
+		X"00000000", -- 00002E50
+		X"00000000", -- 00002E54
+		X"00000000", -- 00002E58
+		X"00000000", -- 00002E5C
+		X"00000000", -- 00002E60
+		X"00000000", -- 00002E64
+		X"00000000", -- 00002E68
+		X"00000000", -- 00002E6C
+		X"00000000", -- 00002E70
+		X"00000000", -- 00002E74
+		X"00000000", -- 00002E78
+		X"00000000", -- 00002E7C
+		X"00000000", -- 00002E80
+		X"00000000", -- 00002E84
+		X"00000000", -- 00002E88
+		X"00000000", -- 00002E8C
+		X"00000000", -- 00002E90
+		X"00000000", -- 00002E94
+		X"00000000", -- 00002E98
+		X"00000000", -- 00002E9C
+		X"00000000", -- 00002EA0
+		X"00000000", -- 00002EA4
+		X"00000000", -- 00002EA8
+		X"00000000", -- 00002EAC
+		X"00000000", -- 00002EB0
+		X"00000000", -- 00002EB4
+		X"00000000", -- 00002EB8
+		X"00000000", -- 00002EBC
+		X"00000000", -- 00002EC0
+		X"00000000", -- 00002EC4
+		X"00000000", -- 00002EC8
+		X"00000000", -- 00002ECC
+		X"00000000", -- 00002ED0
+		X"00000000", -- 00002ED4
+		X"00000000", -- 00002ED8
+		X"00000000", -- 00002EDC
+		X"00000000", -- 00002EE0
+		X"00000000", -- 00002EE4
+		X"00000000", -- 00002EE8
+		X"00000000", -- 00002EEC
+		X"00000000", -- 00002EF0
+		X"00000000", -- 00002EF4
+		X"00000000", -- 00002EF8
+		X"00000000", -- 00002EFC
+		X"00000000", -- 00002F00
+		X"00000000", -- 00002F04
+		X"00000000", -- 00002F08
+		X"00000000", -- 00002F0C
+		X"00000000", -- 00002F10
+		X"00000000", -- 00002F14
+		X"00000000", -- 00002F18
+		X"00000000", -- 00002F1C
+		X"00000000", -- 00002F20
+		X"00000000", -- 00002F24
+		X"00000000", -- 00002F28
+		X"00000000", -- 00002F2C
+		X"00000000", -- 00002F30
+		X"00000000", -- 00002F34
+		X"00000000", -- 00002F38
+		X"00000000", -- 00002F3C
+		X"00000000", -- 00002F40
+		X"00000000", -- 00002F44
+		X"00000000", -- 00002F48
+		X"00000000", -- 00002F4C
+		X"00000000", -- 00002F50
+		X"00000000", -- 00002F54
+		X"00000000", -- 00002F58
+		X"00000000", -- 00002F5C
+		X"00000000", -- 00002F60
+		X"00000000", -- 00002F64
+		X"00000000", -- 00002F68
+		X"00000000", -- 00002F6C
+		X"00000000", -- 00002F70
+		X"00000000", -- 00002F74
+		X"00000000", -- 00002F78
+		X"00000000", -- 00002F7C
+		X"00000000", -- 00002F80
+		X"00000000", -- 00002F84
+		X"00000000", -- 00002F88
+		X"00000000", -- 00002F8C
+		X"00000000", -- 00002F90
+		X"00000000", -- 00002F94
+		X"00000000", -- 00002F98
+		X"00000000", -- 00002F9C
+		X"00000000", -- 00002FA0
+		X"00000000", -- 00002FA4
+		X"00000000", -- 00002FA8
+		X"00000000", -- 00002FAC
+		X"00000000", -- 00002FB0
+		X"00000000", -- 00002FB4
+		X"00000000", -- 00002FB8
+		X"00000000", -- 00002FBC
+		X"00000000", -- 00002FC0
+		X"00000000", -- 00002FC4
+		X"00000000", -- 00002FC8
+		X"00000000", -- 00002FCC
+		X"00000000", -- 00002FD0
+		X"00000000", -- 00002FD4
+		X"00000000", -- 00002FD8
+		X"00000000", -- 00002FDC
+		X"00000000", -- 00002FE0
+		X"00000000", -- 00002FE4
+		X"00000000", -- 00002FE8
+		X"00000000", -- 00002FEC
+		X"00000000", -- 00002FF0
+		X"00000000", -- 00002FF4
+		X"00000000", -- 00002FF8
+		X"00000000", -- 00002FFC
+		X"00000000", -- 00003000
+		X"00000000", -- 00003004
+		X"00000000", -- 00003008
+		X"00000000", -- 0000300C
+		X"00000000", -- 00003010
+		X"00000000", -- 00003014
+		X"00000000", -- 00003018
+		X"00000000", -- 0000301C
+		X"00000000", -- 00003020
+		X"00000000", -- 00003024
+		X"00000000", -- 00003028
+		X"00000000", -- 0000302C
+		X"00000000", -- 00003030
+		X"00000000", -- 00003034
+		X"00000000", -- 00003038
+		X"00000000", -- 0000303C
+		X"00000000", -- 00003040
+		X"00000000", -- 00003044
+		X"00000000", -- 00003048
+		X"00000000", -- 0000304C
+		X"00000000", -- 00003050
+		X"00000000", -- 00003054
+		X"00000000", -- 00003058
+		X"00000000", -- 0000305C
+		X"00000000", -- 00003060
+		X"00000000", -- 00003064
+		X"00000000", -- 00003068
+		X"00000000", -- 0000306C
+		X"00000000", -- 00003070
+		X"00000000", -- 00003074
+		X"00000000", -- 00003078
+		X"00000000", -- 0000307C
+		X"00000000", -- 00003080
+		X"00000000", -- 00003084
+		X"00000000", -- 00003088
+		X"00000000", -- 0000308C
+		X"00000000", -- 00003090
+		X"00000000", -- 00003094
+		X"00000000", -- 00003098
+		X"00000000", -- 0000309C
+		X"00000000", -- 000030A0
+		X"00000000", -- 000030A4
+		X"00000000", -- 000030A8
+		X"00000000", -- 000030AC
+		X"00000000", -- 000030B0
+		X"00000000", -- 000030B4
+		X"00000000", -- 000030B8
+		X"00000000", -- 000030BC
+		X"00000000", -- 000030C0
+		X"00000000", -- 000030C4
+		X"00000000", -- 000030C8
+		X"00000000", -- 000030CC
+		X"00000000", -- 000030D0
+		X"00000000", -- 000030D4
+		X"00000000", -- 000030D8
+		X"00000000", -- 000030DC
+		X"00000000", -- 000030E0
+		X"00000000", -- 000030E4
+		X"00000000", -- 000030E8
+		X"00000000", -- 000030EC
+		X"00000000", -- 000030F0
+		X"00000000", -- 000030F4
+		X"00000000", -- 000030F8
+		X"00000000", -- 000030FC
+		X"00000000", -- 00003100
+		X"00000000", -- 00003104
+		X"00000000", -- 00003108
+		X"00000000", -- 0000310C
+		X"00000000", -- 00003110
+		X"00000000", -- 00003114
+		X"00000000", -- 00003118
+		X"00000000", -- 0000311C
+		X"00000000", -- 00003120
+		X"00000000", -- 00003124
+		X"00000000", -- 00003128
+		X"00000000", -- 0000312C
+		X"00000000", -- 00003130
+		X"00000000", -- 00003134
+		X"00000000", -- 00003138
+		X"00000000", -- 0000313C
+		X"00000000", -- 00003140
+		X"00000000", -- 00003144
+		X"00000000", -- 00003148
+		X"00000000", -- 0000314C
+		X"00000000", -- 00003150
+		X"00000000", -- 00003154
+		X"00000000", -- 00003158
+		X"00000000", -- 0000315C
+		X"00000000", -- 00003160
+		X"00000000", -- 00003164
+		X"00000000", -- 00003168
+		X"00000000", -- 0000316C
+		X"00000000", -- 00003170
+		X"00000000", -- 00003174
+		X"00000000", -- 00003178
+		X"00000000", -- 0000317C
+		X"00000000", -- 00003180
+		X"00000000", -- 00003184
+		X"00000000", -- 00003188
+		X"00000000", -- 0000318C
+		X"00000000", -- 00003190
+		X"00000000", -- 00003194
+		X"00000000", -- 00003198
+		X"00000000", -- 0000319C
+		X"00000000", -- 000031A0
+		X"00000000", -- 000031A4
+		X"00000000", -- 000031A8
+		X"00000000", -- 000031AC
+		X"00000000", -- 000031B0
+		X"00000000", -- 000031B4
+		X"00000000", -- 000031B8
+		X"00000000", -- 000031BC
+		X"00000000", -- 000031C0
+		X"00000000", -- 000031C4
+		X"00000000", -- 000031C8
+		X"00000000", -- 000031CC
+		X"00000000", -- 000031D0
+		X"00000000", -- 000031D4
+		X"00000000", -- 000031D8
+		X"00000000", -- 000031DC
+		X"00000000", -- 000031E0
+		X"00000000", -- 000031E4
+		X"00000000", -- 000031E8
+		X"00000000", -- 000031EC
+		X"00000000", -- 000031F0
+		X"00000000", -- 000031F4
+		X"00000000", -- 000031F8
+		X"00000000", -- 000031FC
+		X"00000000", -- 00003200
+		X"00000000", -- 00003204
+		X"00000000", -- 00003208
+		X"00000000", -- 0000320C
+		X"00000000", -- 00003210
+		X"00000000", -- 00003214
+		X"00000000", -- 00003218
+		X"00000000", -- 0000321C
+		X"00000000", -- 00003220
+		X"00000000", -- 00003224
+		X"00000000", -- 00003228
+		X"00000000", -- 0000322C
+		X"00000000", -- 00003230
+		X"00000000", -- 00003234
+		X"00000000", -- 00003238
+		X"00000000", -- 0000323C
+		X"00000000", -- 00003240
+		X"00000000", -- 00003244
+		X"00000000", -- 00003248
+		X"00000000", -- 0000324C
+		X"00000000", -- 00003250
+		X"00000000", -- 00003254
+		X"00000000", -- 00003258
+		X"00000000", -- 0000325C
+		X"00000000", -- 00003260
+		X"00000000", -- 00003264
+		X"00000000", -- 00003268
+		X"00000000", -- 0000326C
+		X"00000000", -- 00003270
+		X"00000000", -- 00003274
+		X"00000000", -- 00003278
+		X"00000000", -- 0000327C
+		X"00000000", -- 00003280
+		X"00000000", -- 00003284
+		X"00000000", -- 00003288
+		X"00000000", -- 0000328C
+		X"00000000", -- 00003290
+		X"00000000", -- 00003294
+		X"00000000", -- 00003298
+		X"00000000", -- 0000329C
+		X"00000000", -- 000032A0
+		X"00000000", -- 000032A4
+		X"00000000", -- 000032A8
+		X"00000000", -- 000032AC
+		X"00000000", -- 000032B0
+		X"00000000", -- 000032B4
+		X"00000000", -- 000032B8
+		X"00000000", -- 000032BC
+		X"00000000", -- 000032C0
+		X"00000000", -- 000032C4
+		X"00000000", -- 000032C8
+		X"00000000", -- 000032CC
+		X"00000000", -- 000032D0
+		X"00000000", -- 000032D4
+		X"00000000", -- 000032D8
+		X"00000000", -- 000032DC
+		X"00000000", -- 000032E0
+		X"00000000", -- 000032E4
+		X"00000000", -- 000032E8
+		X"00000000", -- 000032EC
+		X"00000000", -- 000032F0
+		X"00000000", -- 000032F4
+		X"00000000", -- 000032F8
+		X"00000000", -- 000032FC
+		X"00000000", -- 00003300
+		X"00000000", -- 00003304
+		X"00000000", -- 00003308
+		X"00000000", -- 0000330C
+		X"00000000", -- 00003310
+		X"00000000", -- 00003314
+		X"00000000", -- 00003318
+		X"00000000", -- 0000331C
+		X"00000000", -- 00003320
+		X"00000000", -- 00003324
+		X"00000000", -- 00003328
+		X"00000000", -- 0000332C
+		X"00000000", -- 00003330
+		X"00000000", -- 00003334
+		X"00000000", -- 00003338
+		X"00000000", -- 0000333C
+		X"00000000", -- 00003340
+		X"00000000", -- 00003344
+		X"00000000", -- 00003348
+		X"00000000", -- 0000334C
+		X"00000000", -- 00003350
+		X"00000000", -- 00003354
+		X"00000000", -- 00003358
+		X"00000000", -- 0000335C
+		X"00000000", -- 00003360
+		X"00000000", -- 00003364
+		X"00000000", -- 00003368
+		X"00000000", -- 0000336C
+		X"00000000", -- 00003370
+		X"00000000", -- 00003374
+		X"00000000", -- 00003378
+		X"00000000", -- 0000337C
+		X"00000000", -- 00003380
+		X"00000000", -- 00003384
+		X"00000000", -- 00003388
+		X"00000000", -- 0000338C
+		X"00000000", -- 00003390
+		X"00000000", -- 00003394
+		X"00000000", -- 00003398
+		X"00000000", -- 0000339C
+		X"00000000", -- 000033A0
+		X"00000000", -- 000033A4
+		X"00000000", -- 000033A8
+		X"00000000", -- 000033AC
+		X"00000000", -- 000033B0
+		X"00000000", -- 000033B4
+		X"00000000", -- 000033B8
+		X"00000000", -- 000033BC
+		X"00000000", -- 000033C0
+		X"00000000", -- 000033C4
+		X"00000000", -- 000033C8
+		X"00000000", -- 000033CC
+		X"00000000", -- 000033D0
+		X"00000000", -- 000033D4
+		X"00000000", -- 000033D8
+		X"00000000", -- 000033DC
+		X"00000000", -- 000033E0
+		X"00000000", -- 000033E4
+		X"00000000", -- 000033E8
+		X"00000000", -- 000033EC
+		X"00000000", -- 000033F0
+		X"00000000", -- 000033F4
+		X"00000000", -- 000033F8
+		X"00000000", -- 000033FC
+		X"00000000", -- 00003400
+		X"00000000", -- 00003404
+		X"00000000", -- 00003408
+		X"00000000", -- 0000340C
+		X"00000000", -- 00003410
+		X"00000000", -- 00003414
+		X"00000000", -- 00003418
+		X"00000000", -- 0000341C
+		X"00000000", -- 00003420
+		X"00000000", -- 00003424
+		X"00000000", -- 00003428
+		X"00000000", -- 0000342C
+		X"00000000", -- 00003430
+		X"00000000", -- 00003434
+		X"00000000", -- 00003438
+		X"00000000", -- 0000343C
+		X"00000000", -- 00003440
+		X"00000000", -- 00003444
+		X"00000000", -- 00003448
+		X"00000000", -- 0000344C
+		X"00000000", -- 00003450
+		X"00000000", -- 00003454
+		X"00000000", -- 00003458
+		X"00000000", -- 0000345C
+		X"00000000", -- 00003460
+		X"00000000", -- 00003464
+		X"00000000", -- 00003468
+		X"00000000", -- 0000346C
+		X"00000000", -- 00003470
+		X"00000000", -- 00003474
+		X"00000000", -- 00003478
+		X"00000000", -- 0000347C
+		X"00000000", -- 00003480
+		X"00000000", -- 00003484
+		X"00000000", -- 00003488
+		X"00000000", -- 0000348C
+		X"00000000", -- 00003490
+		X"00000000", -- 00003494
+		X"00000000", -- 00003498
+		X"00000000", -- 0000349C
+		X"00000000", -- 000034A0
+		X"00000000", -- 000034A4
+		X"00000000", -- 000034A8
+		X"00000000", -- 000034AC
+		X"00000000", -- 000034B0
+		X"00000000", -- 000034B4
+		X"00000000", -- 000034B8
+		X"00000000", -- 000034BC
+		X"00000000", -- 000034C0
+		X"00000000", -- 000034C4
+		X"00000000", -- 000034C8
+		X"00000000", -- 000034CC
+		X"00000000", -- 000034D0
+		X"00000000", -- 000034D4
+		X"00000000", -- 000034D8
+		X"00000000", -- 000034DC
+		X"00000000", -- 000034E0
+		X"00000000", -- 000034E4
+		X"00000000", -- 000034E8
+		X"00000000", -- 000034EC
+		X"00000000", -- 000034F0
+		X"00000000", -- 000034F4
+		X"00000000", -- 000034F8
+		X"00000000", -- 000034FC
+		X"00000000", -- 00003500
+		X"00000000", -- 00003504
+		X"00000000", -- 00003508
+		X"00000000", -- 0000350C
+		X"00000000", -- 00003510
+		X"00000000", -- 00003514
+		X"00000000", -- 00003518
+		X"00000000", -- 0000351C
+		X"00000000", -- 00003520
+		X"00000000", -- 00003524
+		X"00000000", -- 00003528
+		X"00000000", -- 0000352C
+		X"00000000", -- 00003530
+		X"00000000", -- 00003534
+		X"00000000", -- 00003538
+		X"00000000", -- 0000353C
+		X"00000000", -- 00003540
+		X"00000000", -- 00003544
+		X"00000000", -- 00003548
+		X"00000000", -- 0000354C
+		X"00000000", -- 00003550
+		X"00000000", -- 00003554
+		X"00000000", -- 00003558
+		X"00000000", -- 0000355C
+		X"00000000", -- 00003560
+		X"00000000", -- 00003564
+		X"00000000", -- 00003568
+		X"00000000", -- 0000356C
+		X"00000000", -- 00003570
+		X"00000000", -- 00003574
+		X"00000000", -- 00003578
+		X"00000000", -- 0000357C
+		X"00000000", -- 00003580
+		X"00000000", -- 00003584
+		X"00000000", -- 00003588
+		X"00000000", -- 0000358C
+		X"00000000", -- 00003590
+		X"00000000", -- 00003594
+		X"00000000", -- 00003598
+		X"00000000", -- 0000359C
+		X"00000000", -- 000035A0
+		X"00000000", -- 000035A4
+		X"00000000", -- 000035A8
+		X"00000000", -- 000035AC
+		X"00000000", -- 000035B0
+		X"00000000", -- 000035B4
+		X"00000000", -- 000035B8
+		X"00000000", -- 000035BC
+		X"00000000", -- 000035C0
+		X"00000000", -- 000035C4
+		X"00000000", -- 000035C8
+		X"00000000", -- 000035CC
+		X"00000000", -- 000035D0
+		X"00000000", -- 000035D4
+		X"00000000", -- 000035D8
+		X"00000000", -- 000035DC
+		X"00000000", -- 000035E0
+		X"00000000", -- 000035E4
+		X"00000000", -- 000035E8
+		X"00000000", -- 000035EC
+		X"00000000", -- 000035F0
+		X"00000000", -- 000035F4
+		X"00000000", -- 000035F8
+		X"00000000", -- 000035FC
+		X"00000000", -- 00003600
+		X"00000000", -- 00003604
+		X"00000000", -- 00003608
+		X"00000000", -- 0000360C
+		X"00000000", -- 00003610
+		X"00000000", -- 00003614
+		X"00000000", -- 00003618
+		X"00000000", -- 0000361C
+		X"00000000", -- 00003620
+		X"00000000", -- 00003624
+		X"00000000", -- 00003628
+		X"00000000", -- 0000362C
+		X"00000000", -- 00003630
+		X"00000000", -- 00003634
+		X"00000000", -- 00003638
+		X"00000000", -- 0000363C
+		X"00000000", -- 00003640
+		X"00000000", -- 00003644
+		X"00000000", -- 00003648
+		X"00000000", -- 0000364C
+		X"00000000", -- 00003650
+		X"00000000", -- 00003654
+		X"00000000", -- 00003658
+		X"00000000", -- 0000365C
+		X"00000000", -- 00003660
+		X"00000000", -- 00003664
+		X"00000000", -- 00003668
+		X"00000000", -- 0000366C
+		X"00000000", -- 00003670
+		X"00000000", -- 00003674
+		X"00000000", -- 00003678
+		X"00000000", -- 0000367C
+		X"00000000", -- 00003680
+		X"00000000", -- 00003684
+		X"00000000", -- 00003688
+		X"00000000", -- 0000368C
+		X"00000000", -- 00003690
+		X"00000000", -- 00003694
+		X"00000000", -- 00003698
+		X"00000000", -- 0000369C
+		X"00000000", -- 000036A0
+		X"00000000", -- 000036A4
+		X"00000000", -- 000036A8
+		X"00000000", -- 000036AC
+		X"00000000", -- 000036B0
+		X"00000000", -- 000036B4
+		X"00000000", -- 000036B8
+		X"00000000", -- 000036BC
+		X"00000000", -- 000036C0
+		X"00000000", -- 000036C4
+		X"00000000", -- 000036C8
+		X"00000000", -- 000036CC
+		X"00000000", -- 000036D0
+		X"00000000", -- 000036D4
+		X"00000000", -- 000036D8
+		X"00000000", -- 000036DC
+		X"00000000", -- 000036E0
+		X"00000000", -- 000036E4
+		X"00000000", -- 000036E8
+		X"00000000", -- 000036EC
+		X"00000000", -- 000036F0
+		X"00000000", -- 000036F4
+		X"00000000", -- 000036F8
+		X"00000000", -- 000036FC
+		X"00000000", -- 00003700
+		X"00000000", -- 00003704
+		X"00000000", -- 00003708
+		X"00000000", -- 0000370C
+		X"00000000", -- 00003710
+		X"00000000", -- 00003714
+		X"00000000", -- 00003718
+		X"00000000", -- 0000371C
+		X"00000000", -- 00003720
+		X"00000000", -- 00003724
+		X"00000000", -- 00003728
+		X"00000000", -- 0000372C
+		X"00000000", -- 00003730
+		X"00000000", -- 00003734
+		X"00000000", -- 00003738
+		X"00000000", -- 0000373C
+		X"00000000", -- 00003740
+		X"00000000", -- 00003744
+		X"00000000", -- 00003748
+		X"00000000", -- 0000374C
+		X"00000000", -- 00003750
+		X"00000000", -- 00003754
+		X"00000000", -- 00003758
+		X"00000000", -- 0000375C
+		X"00000000", -- 00003760
+		X"00000000", -- 00003764
+		X"00000000", -- 00003768
+		X"00000000", -- 0000376C
+		X"00000000", -- 00003770
+		X"00000000", -- 00003774
+		X"00000000", -- 00003778
+		X"00000000", -- 0000377C
+		X"00000000", -- 00003780
+		X"00000000", -- 00003784
+		X"00000000", -- 00003788
+		X"00000000", -- 0000378C
+		X"00000000", -- 00003790
+		X"00000000", -- 00003794
+		X"00000000", -- 00003798
+		X"00000000", -- 0000379C
+		X"00000000", -- 000037A0
+		X"00000000", -- 000037A4
+		X"00000000", -- 000037A8
+		X"00000000", -- 000037AC
+		X"00000000", -- 000037B0
+		X"00000000", -- 000037B4
+		X"00000000", -- 000037B8
+		X"00000000", -- 000037BC
+		X"00000000", -- 000037C0
+		X"00000000", -- 000037C4
+		X"00000000", -- 000037C8
+		X"00000000", -- 000037CC
+		X"00000000", -- 000037D0
+		X"00000000", -- 000037D4
+		X"00000000", -- 000037D8
+		X"00000000", -- 000037DC
+		X"00000000", -- 000037E0
+		X"00000000", -- 000037E4
+		X"00000000", -- 000037E8
+		X"00000000", -- 000037EC
+		X"00000000", -- 000037F0
+		X"00000000", -- 000037F4
+		X"00000000", -- 000037F8
+		X"00000000", -- 000037FC
+		X"00000000", -- 00003800
+		X"00000000", -- 00003804
+		X"00000000", -- 00003808
+		X"00000000", -- 0000380C
+		X"00000000", -- 00003810
+		X"00000000", -- 00003814
+		X"00000000", -- 00003818
+		X"00000000", -- 0000381C
+		X"00000000", -- 00003820
+		X"00000000", -- 00003824
+		X"00000000", -- 00003828
+		X"00000000", -- 0000382C
+		X"00000000", -- 00003830
+		X"00000000", -- 00003834
+		X"00000000", -- 00003838
+		X"00000000", -- 0000383C
+		X"00000000", -- 00003840
+		X"00000000", -- 00003844
+		X"00000000", -- 00003848
+		X"00000000", -- 0000384C
+		X"00000000", -- 00003850
+		X"00000000", -- 00003854
+		X"00000000", -- 00003858
+		X"00000000", -- 0000385C
+		X"00000000", -- 00003860
+		X"00000000", -- 00003864
+		X"00000000", -- 00003868
+		X"00000000", -- 0000386C
+		X"00000000", -- 00003870
+		X"00000000", -- 00003874
+		X"00000000", -- 00003878
+		X"00000000", -- 0000387C
+		X"00000000", -- 00003880
+		X"00000000", -- 00003884
+		X"00000000", -- 00003888
+		X"00000000", -- 0000388C
+		X"00000000", -- 00003890
+		X"00000000", -- 00003894
+		X"00000000", -- 00003898
+		X"00000000", -- 0000389C
+		X"00000000", -- 000038A0
+		X"00000000", -- 000038A4
+		X"00000000", -- 000038A8
+		X"00000000", -- 000038AC
+		X"00000000", -- 000038B0
+		X"00000000", -- 000038B4
+		X"00000000", -- 000038B8
+		X"00000000", -- 000038BC
+		X"00000000", -- 000038C0
+		X"00000000", -- 000038C4
+		X"00000000", -- 000038C8
+		X"00000000", -- 000038CC
+		X"00000000", -- 000038D0
+		X"00000000", -- 000038D4
+		X"00000000", -- 000038D8
+		X"00000000", -- 000038DC
+		X"00000000", -- 000038E0
+		X"00000000", -- 000038E4
+		X"00000000", -- 000038E8
+		X"00000000", -- 000038EC
+		X"00000000", -- 000038F0
+		X"00000000", -- 000038F4
+		X"00000000", -- 000038F8
+		X"00000000", -- 000038FC
+		X"00000000", -- 00003900
+		X"00000000", -- 00003904
+		X"00000000", -- 00003908
+		X"00000000", -- 0000390C
+		X"00000000", -- 00003910
+		X"00000000", -- 00003914
+		X"00000000", -- 00003918
+		X"00000000", -- 0000391C
+		X"00000000", -- 00003920
+		X"00000000", -- 00003924
+		X"00000000", -- 00003928
+		X"00000000", -- 0000392C
+		X"00000000", -- 00003930
+		X"00000000", -- 00003934
+		X"00000000", -- 00003938
+		X"00000000", -- 0000393C
+		X"00000000", -- 00003940
+		X"00000000", -- 00003944
+		X"00000000", -- 00003948
+		X"00000000", -- 0000394C
+		X"00000000", -- 00003950
+		X"00000000", -- 00003954
+		X"00000000", -- 00003958
+		X"00000000", -- 0000395C
+		X"00000000", -- 00003960
+		X"00000000", -- 00003964
+		X"00000000", -- 00003968
+		X"00000000", -- 0000396C
+		X"00000000", -- 00003970
+		X"00000000", -- 00003974
+		X"00000000", -- 00003978
+		X"00000000", -- 0000397C
+		X"00000000", -- 00003980
+		X"00000000", -- 00003984
+		X"00000000", -- 00003988
+		X"00000000", -- 0000398C
+		X"00000000", -- 00003990
+		X"00000000", -- 00003994
+		X"00000000", -- 00003998
+		X"00000000", -- 0000399C
+		X"00000000", -- 000039A0
+		X"00000000", -- 000039A4
+		X"00000000", -- 000039A8
+		X"00000000", -- 000039AC
+		X"00000000", -- 000039B0
+		X"00000000", -- 000039B4
+		X"00000000", -- 000039B8
+		X"00000000", -- 000039BC
+		X"00000000", -- 000039C0
+		X"00000000", -- 000039C4
+		X"00000000", -- 000039C8
+		X"00000000", -- 000039CC
+		X"00000000", -- 000039D0
+		X"00000000", -- 000039D4
+		X"00000000", -- 000039D8
+		X"00000000", -- 000039DC
+		X"00000000", -- 000039E0
+		X"00000000", -- 000039E4
+		X"00000000", -- 000039E8
+		X"00000000", -- 000039EC
+		X"00000000", -- 000039F0
+		X"00000000", -- 000039F4
+		X"00000000", -- 000039F8
+		X"00000000", -- 000039FC
+		X"00000000", -- 00003A00
+		X"00000000", -- 00003A04
+		X"00000000", -- 00003A08
+		X"00000000", -- 00003A0C
+		X"00000000", -- 00003A10
+		X"00000000", -- 00003A14
+		X"00000000", -- 00003A18
+		X"00000000", -- 00003A1C
+		X"00000000", -- 00003A20
+		X"00000000", -- 00003A24
+		X"00000000", -- 00003A28
+		X"00000000", -- 00003A2C
+		X"00000000", -- 00003A30
+		X"00000000", -- 00003A34
+		X"00000000", -- 00003A38
+		X"00000000", -- 00003A3C
+		X"00000000", -- 00003A40
+		X"00000000", -- 00003A44
+		X"00000000", -- 00003A48
+		X"00000000", -- 00003A4C
+		X"00000000", -- 00003A50
+		X"00000000", -- 00003A54
+		X"00000000", -- 00003A58
+		X"00000000", -- 00003A5C
+		X"00000000", -- 00003A60
+		X"00000000", -- 00003A64
+		X"00000000", -- 00003A68
+		X"00000000", -- 00003A6C
+		X"00000000", -- 00003A70
+		X"00000000", -- 00003A74
+		X"00000000", -- 00003A78
+		X"00000000", -- 00003A7C
+		X"00000000", -- 00003A80
+		X"00000000", -- 00003A84
+		X"00000000", -- 00003A88
+		X"00000000", -- 00003A8C
+		X"00000000", -- 00003A90
+		X"00000000", -- 00003A94
+		X"00000000", -- 00003A98
+		X"00000000", -- 00003A9C
+		X"00000000", -- 00003AA0
+		X"00000000", -- 00003AA4
+		X"00000000", -- 00003AA8
+		X"00000000", -- 00003AAC
+		X"00000000", -- 00003AB0
+		X"00000000", -- 00003AB4
+		X"00000000", -- 00003AB8
+		X"00000000", -- 00003ABC
+		X"00000000", -- 00003AC0
+		X"00000000", -- 00003AC4
+		X"00000000", -- 00003AC8
+		X"00000000", -- 00003ACC
+		X"00000000", -- 00003AD0
+		X"00000000", -- 00003AD4
+		X"00000000", -- 00003AD8
+		X"00000000", -- 00003ADC
+		X"00000000", -- 00003AE0
+		X"00000000", -- 00003AE4
+		X"00000000", -- 00003AE8
+		X"00000000", -- 00003AEC
+		X"00000000", -- 00003AF0
+		X"00000000", -- 00003AF4
+		X"00000000", -- 00003AF8
+		X"00000000", -- 00003AFC
+		X"00000000", -- 00003B00
+		X"00000000", -- 00003B04
+		X"00000000", -- 00003B08
+		X"00000000", -- 00003B0C
+		X"00000000", -- 00003B10
+		X"00000000", -- 00003B14
+		X"00000000", -- 00003B18
+		X"00000000", -- 00003B1C
+		X"00000000", -- 00003B20
+		X"00000000", -- 00003B24
+		X"00000000", -- 00003B28
+		X"00000000", -- 00003B2C
+		X"00000000", -- 00003B30
+		X"00000000", -- 00003B34
+		X"00000000", -- 00003B38
+		X"00000000", -- 00003B3C
+		X"00000000", -- 00003B40
+		X"00000000", -- 00003B44
+		X"00000000", -- 00003B48
+		X"00000000", -- 00003B4C
+		X"00000000", -- 00003B50
+		X"00000000", -- 00003B54
+		X"00000000", -- 00003B58
+		X"00000000", -- 00003B5C
+		X"00000000", -- 00003B60
+		X"00000000", -- 00003B64
+		X"00000000", -- 00003B68
+		X"00000000", -- 00003B6C
+		X"00000000", -- 00003B70
+		X"00000000", -- 00003B74
+		X"00000000", -- 00003B78
+		X"00000000", -- 00003B7C
+		X"00000000", -- 00003B80
+		X"00000000", -- 00003B84
+		X"00000000", -- 00003B88
+		X"00000000", -- 00003B8C
+		X"00000000", -- 00003B90
+		X"00000000", -- 00003B94
+		X"00000000", -- 00003B98
+		X"00000000", -- 00003B9C
+		X"00000000", -- 00003BA0
+		X"00000000", -- 00003BA4
+		X"00000000", -- 00003BA8
+		X"00000000", -- 00003BAC
+		X"00000000", -- 00003BB0
+		X"00000000", -- 00003BB4
+		X"00000000", -- 00003BB8
+		X"00000000", -- 00003BBC
+		X"00000000", -- 00003BC0
+		X"00000000", -- 00003BC4
+		X"00000000", -- 00003BC8
+		X"00000000", -- 00003BCC
+		X"00000000", -- 00003BD0
+		X"00000000", -- 00003BD4
+		X"00000000", -- 00003BD8
+		X"00000000", -- 00003BDC
+		X"00000000", -- 00003BE0
+		X"00000000", -- 00003BE4
+		X"00000000", -- 00003BE8
+		X"00000000", -- 00003BEC
+		X"00000000", -- 00003BF0
+		X"00000000", -- 00003BF4
+		X"00000000", -- 00003BF8
+		X"00000000", -- 00003BFC
+		X"00000000", -- 00003C00
+		X"00000000", -- 00003C04
+		X"00000000", -- 00003C08
+		X"00000000", -- 00003C0C
+		X"00000000", -- 00003C10
+		X"00000000", -- 00003C14
+		X"00000000", -- 00003C18
+		X"00000000", -- 00003C1C
+		X"00000000", -- 00003C20
+		X"00000000", -- 00003C24
+		X"00000000", -- 00003C28
+		X"00000000", -- 00003C2C
+		X"00000000", -- 00003C30
+		X"00000000", -- 00003C34
+		X"00000000", -- 00003C38
+		X"00000000", -- 00003C3C
+		X"00000000", -- 00003C40
+		X"00000000", -- 00003C44
+		X"00000000", -- 00003C48
+		X"00000000", -- 00003C4C
+		X"00000000", -- 00003C50
+		X"00000000", -- 00003C54
+		X"00000000", -- 00003C58
+		X"00000000", -- 00003C5C
+		X"00000000", -- 00003C60
+		X"00000000", -- 00003C64
+		X"00000000", -- 00003C68
+		X"00000000", -- 00003C6C
+		X"00000000", -- 00003C70
+		X"00000000", -- 00003C74
+		X"00000000", -- 00003C78
+		X"00000000", -- 00003C7C
+		X"00000000", -- 00003C80
+		X"00000000", -- 00003C84
+		X"00000000", -- 00003C88
+		X"00000000", -- 00003C8C
+		X"00000000", -- 00003C90
+		X"00000000", -- 00003C94
+		X"00000000", -- 00003C98
+		X"00000000", -- 00003C9C
+		X"00000000", -- 00003CA0
+		X"00000000", -- 00003CA4
+		X"00000000", -- 00003CA8
+		X"00000000", -- 00003CAC
+		X"00000000", -- 00003CB0
+		X"00000000", -- 00003CB4
+		X"00000000", -- 00003CB8
+		X"00000000", -- 00003CBC
+		X"00000000", -- 00003CC0
+		X"00000000", -- 00003CC4
+		X"00000000", -- 00003CC8
+		X"00000000", -- 00003CCC
+		X"00000000", -- 00003CD0
+		X"00000000", -- 00003CD4
+		X"00000000", -- 00003CD8
+		X"00000000", -- 00003CDC
+		X"00000000", -- 00003CE0
+		X"00000000", -- 00003CE4
+		X"00000000", -- 00003CE8
+		X"00000000", -- 00003CEC
+		X"00000000", -- 00003CF0
+		X"00000000", -- 00003CF4
+		X"00000000", -- 00003CF8
+		X"00000000", -- 00003CFC
+		X"00000000", -- 00003D00
+		X"00000000", -- 00003D04
+		X"00000000", -- 00003D08
+		X"00000000", -- 00003D0C
+		X"00000000", -- 00003D10
+		X"00000000", -- 00003D14
+		X"00000000", -- 00003D18
+		X"00000000", -- 00003D1C
+		X"00000000", -- 00003D20
+		X"00000000", -- 00003D24
+		X"00000000", -- 00003D28
+		X"00000000", -- 00003D2C
+		X"00000000", -- 00003D30
+		X"00000000", -- 00003D34
+		X"00000000", -- 00003D38
+		X"00000000", -- 00003D3C
+		X"00000000", -- 00003D40
+		X"00000000", -- 00003D44
+		X"00000000", -- 00003D48
+		X"00000000", -- 00003D4C
+		X"00000000", -- 00003D50
+		X"00000000", -- 00003D54
+		X"00000000", -- 00003D58
+		X"00000000", -- 00003D5C
+		X"00000000", -- 00003D60
+		X"00000000", -- 00003D64
+		X"00000000", -- 00003D68
+		X"00000000", -- 00003D6C
+		X"00000000", -- 00003D70
+		X"00000000", -- 00003D74
+		X"00000000", -- 00003D78
+		X"00000000", -- 00003D7C
+		X"00000000", -- 00003D80
+		X"00000000", -- 00003D84
+		X"00000000", -- 00003D88
+		X"00000000", -- 00003D8C
+		X"00000000", -- 00003D90
+		X"00000000", -- 00003D94
+		X"00000000", -- 00003D98
+		X"00000000", -- 00003D9C
+		X"00000000", -- 00003DA0
+		X"00000000", -- 00003DA4
+		X"00000000", -- 00003DA8
+		X"00000000", -- 00003DAC
+		X"00000000", -- 00003DB0
+		X"00000000", -- 00003DB4
+		X"00000000", -- 00003DB8
+		X"00000000", -- 00003DBC
+		X"00000000", -- 00003DC0
+		X"00000000", -- 00003DC4
+		X"00000000", -- 00003DC8
+		X"00000000", -- 00003DCC
+		X"00000000", -- 00003DD0
+		X"00000000", -- 00003DD4
+		X"00000000", -- 00003DD8
+		X"00000000", -- 00003DDC
+		X"00000000", -- 00003DE0
+		X"00000000", -- 00003DE4
+		X"00000000", -- 00003DE8
+		X"00000000", -- 00003DEC
+		X"00000000", -- 00003DF0
+		X"00000000", -- 00003DF4
+		X"00000000", -- 00003DF8
+		X"00000000", -- 00003DFC
+		X"00000000", -- 00003E00
+		X"00000000", -- 00003E04
+		X"00000000", -- 00003E08
+		X"00000000", -- 00003E0C
+		X"00000000", -- 00003E10
+		X"00000000", -- 00003E14
+		X"00000000", -- 00003E18
+		X"00000000", -- 00003E1C
+		X"00000000", -- 00003E20
+		X"00000000", -- 00003E24
+		X"00000000", -- 00003E28
+		X"00000000", -- 00003E2C
+		X"00000000", -- 00003E30
+		X"00000000", -- 00003E34
+		X"00000000", -- 00003E38
+		X"00000000", -- 00003E3C
+		X"00000000", -- 00003E40
+		X"00000000", -- 00003E44
+		X"00000000", -- 00003E48
+		X"00000000", -- 00003E4C
+		X"00000000", -- 00003E50
+		X"00000000", -- 00003E54
+		X"00000000", -- 00003E58
+		X"00000000", -- 00003E5C
+		X"00000000", -- 00003E60
+		X"00000000", -- 00003E64
+		X"00000000", -- 00003E68
+		X"00000000", -- 00003E6C
+		X"00000000", -- 00003E70
+		X"00000000", -- 00003E74
+		X"00000000", -- 00003E78
+		X"00000000", -- 00003E7C
+		X"00000000", -- 00003E80
+		X"00000000", -- 00003E84
+		X"00000000", -- 00003E88
+		X"00000000", -- 00003E8C
+		X"00000000", -- 00003E90
+		X"00000000", -- 00003E94
+		X"00000000", -- 00003E98
+		X"00000000", -- 00003E9C
+		X"00000000", -- 00003EA0
+		X"00000000", -- 00003EA4
+		X"00000000", -- 00003EA8
+		X"00000000", -- 00003EAC
+		X"00000000", -- 00003EB0
+		X"00000000", -- 00003EB4
+		X"00000000", -- 00003EB8
+		X"00000000", -- 00003EBC
+		X"00000000", -- 00003EC0
+		X"00000000", -- 00003EC4
+		X"00000000", -- 00003EC8
+		X"00000000", -- 00003ECC
+		X"00000000", -- 00003ED0
+		X"00000000", -- 00003ED4
+		X"00000000", -- 00003ED8
+		X"00000000", -- 00003EDC
+		X"00000000", -- 00003EE0
+		X"00000000", -- 00003EE4
+		X"00000000", -- 00003EE8
+		X"00000000", -- 00003EEC
+		X"00000000", -- 00003EF0
+		X"00000000", -- 00003EF4
+		X"00000000", -- 00003EF8
+		X"00000000", -- 00003EFC
+		X"00000000", -- 00003F00
+		X"00000000", -- 00003F04
+		X"00000000", -- 00003F08
+		X"00000000", -- 00003F0C
+		X"00000000", -- 00003F10
+		X"00000000", -- 00003F14
+		X"00000000", -- 00003F18
+		X"00000000", -- 00003F1C
+		X"00000000", -- 00003F20
+		X"00000000", -- 00003F24
+		X"00000000", -- 00003F28
+		X"00000000", -- 00003F2C
+		X"00000000", -- 00003F30
+		X"00000000", -- 00003F34
+		X"00000000", -- 00003F38
+		X"00000000", -- 00003F3C
+		X"00000000", -- 00003F40
+		X"00000000", -- 00003F44
+		X"00000000", -- 00003F48
+		X"00000000", -- 00003F4C
+		X"00000000", -- 00003F50
+		X"00000000", -- 00003F54
+		X"00000000", -- 00003F58
+		X"00000000", -- 00003F5C
+		X"00000000", -- 00003F60
+		X"00000000", -- 00003F64
+		X"00000000", -- 00003F68
+		X"00000000", -- 00003F6C
+		X"00000000", -- 00003F70
+		X"00000000", -- 00003F74
+		X"00000000", -- 00003F78
+		X"00000000", -- 00003F7C
+		X"00000000", -- 00003F80
+		X"00000000", -- 00003F84
+		X"00000000", -- 00003F88
+		X"00000000", -- 00003F8C
+		X"00000000", -- 00003F90
+		X"00000000", -- 00003F94
+		X"00000000", -- 00003F98
+		X"00000000", -- 00003F9C
+		X"00000000", -- 00003FA0
+		X"00000000", -- 00003FA4
+		X"00000000", -- 00003FA8
+		X"00000000", -- 00003FAC
+		X"00000000", -- 00003FB0
+		X"00000000", -- 00003FB4
+		X"00000000", -- 00003FB8
+		X"00000000", -- 00003FBC
+		X"00000000", -- 00003FC0
+		X"00000000", -- 00003FC4
+		X"00000000", -- 00003FC8
+		X"00000000", -- 00003FCC
+		X"00000000", -- 00003FD0
+		X"00000000", -- 00003FD4
+		X"00000000", -- 00003FD8
+		X"00000000", -- 00003FDC
+		X"00000000", -- 00003FE0
+		X"00000000", -- 00003FE4
+		X"00000000", -- 00003FE8
+		X"00000000", -- 00003FEC
+		X"00000000", -- 00003FF0
+		X"00000000", -- 00003FF4
+		X"00000000", -- 00003FF8
+		X"00000000"  -- 00003FFC
+	);
+
+begin
+
+PROM_READ:
+	process(clk)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= word_array(to_integer(addr(13 downto 2)));
+		end if;
+	end process;
+
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
+	jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;	
+	
+			end if;
+		end if;
+	end process;
+
+PROM_WRITE:
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				word_array(to_integer(jtag_ld_addr(11 downto 0))) <= jtag_ld_din;
+			else
+				jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(11 downto 0)));
+			end if;
+		end if;
+	end process;
+
+end data;
diff --git a/lib/CPUs/MIPS/src/tb_eval_muldiv.vhd b/lib/CPUs/MIPS/src/tb_eval_muldiv.vhd
new file mode 100644
index 0000000..e4bbef2
--- /dev/null
+++ b/lib/CPUs/MIPS/src/tb_eval_muldiv.vhd
@@ -0,0 +1,156 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: Testbench for JCPU
+--            also writes 'opc.lst' for JASM-assembler
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.mips_types.all;
+use work.mips_instr.all;
+
+ENTITY tb_eval_muldiv IS
+END tb_eval_muldiv;
+
+ARCHITECTURE behavior OF tb_eval_muldiv IS 
+
+	constant CLK_PERIOD : time := 10 ns;
+	signal rst 			: std_logic := '1';
+	signal clk 			: std_logic := '1';
+	signal ce  			: std_logic := '0';
+	signal mul_divn		: std_logic := '1';
+	signal op_valid		: std_logic := '0';
+	signal op1_in		: word_t := (others => '-');
+	signal op2_in		: word_t := (others => '-');
+	signal result		: unsigned (2*word_t'length-1 downto 0);
+	signal res_valid 	: std_logic;
+	signal busy 		: std_logic;
+	signal result_reg	: unsigned (2*word_t'length-1 downto 0);
+	subtype pp_t is unsigned (39 downto 0);
+	
+	signal pp0, pp1, pp2, pp3 : pp_t;
+	
+	signal signed_mul	: std_logic := '1';
+	signal sign1 		: std_logic;
+	signal sign2 		: std_logic;
+	signal cy			: std_logic;
+	
+BEGIN
+	
+	sign1	<= signed_mul and op1_in(op1_in'left);
+	sign2	<= signed_mul and op2_in(op1_in'left);
+	cy 		<= sign1;
+	
+	pp0 <= op1_in * op2_in(7 downto 0);
+	pp1 <= op1_in * op2_in(15 downto 8);
+	pp2 <= op1_in * op2_in(23 downto 16);
+	pp3 <= op1_in * op2_in(31 downto 24);
+	
+	result	<= ((63 downto 40 => '0') & pp0)
+			+ ((63 downto 48 => '0') & pp1 & (7 downto 0 => '0'))
+			+ ((63 downto 56 => '0') & pp2 & (15 downto 0 => '0'))
+			+ (pp3 & (23 downto 0 => '0'));
+		
+	result_reg	<= (63 downto 0 => sign1) xor (result + ((63 downto 0 => sign1) and X"0000_0000_0000_0000"));
+	
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(clk);
+		rst <= '0';
+		wait for 10*CLK_PERIOD;
+	
+		wait until rising_edge(clk);
+		ce <= '1';
+
+		wait for 10*CLK_PERIOD;
+		op1_in		<= X"FFFF_FFFA"; -- (-6)
+		op2_in		<= X"0000_0005"; -- (+5)
+		op_valid	<= '1';
+		wait until rising_edge(clk);
+		op_valid	<= '0';
+		
+		wait for 10*CLK_PERIOD;
+		op1_in		<= X"0000_0006"; -- (+6)
+		op2_in		<= X"FFFF_FFFB"; -- (-5)
+		op_valid	<= '1';
+		wait until rising_edge(clk);
+		op_valid	<= '0';
+		
+		wait for 10*CLK_PERIOD;
+		op1_in		<= X"1234_5678";
+		op2_in		<= X"8765_4321";
+		op_valid	<= '1';
+		wait until rising_edge(clk);
+		op_valid	<= '0';
+		
+		wait for 10*CLK_PERIOD;
+		op1_in		<= X"8765_4321";
+		op2_in		<= X"1234_5678";
+		op_valid	<= '1';
+		wait until rising_edge(clk);
+		op_valid	<= '0';
+
+		wait for 10*CLK_PERIOD;
+		op1_in		<= X"1234_5678";
+		op2_in		<= X"1234_5678";
+		op_valid	<= '1';
+		wait until rising_edge(clk);
+		op_valid	<= '0';
+
+		wait for 10*CLK_PERIOD;
+		op1_in		<= X"8765_4321";
+		op2_in		<= X"8765_4321";
+		op_valid	<= '1';
+		wait until rising_edge(clk);
+		op_valid	<= '0';
+
+		wait for 10*CLK_PERIOD;
+		op1_in		<= X"789A_BCDE";
+		op2_in		<= X"8765_4321";
+		op_valid	<= '1';
+		wait until rising_edge(clk);
+		op_valid	<= '0';
+
+		wait for 10*CLK_PERIOD;
+		op1_in		<= X"8765_4321";
+		op2_in		<= X"789A_BCDE";
+		op_valid	<= '1';
+		wait until rising_edge(clk);
+		op_valid	<= '0';
+
+		wait; 
+	
+	end process;
+	
+END;
diff --git a/lib/CPUs/MIPS/src/tb_mips_embedded.vhd b/lib/CPUs/MIPS/src/tb_mips_embedded.vhd
new file mode 100644
index 0000000..cbae0b7
--- /dev/null
+++ b/lib/CPUs/MIPS/src/tb_mips_embedded.vhd
@@ -0,0 +1,82 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: Testbench for JCPU
+--            also writes 'opc.lst' for JASM-assembler
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.mips_types.all;
+
+ENTITY tb_mips_embedded IS
+END tb_mips_embedded;
+
+ARCHITECTURE behavior OF tb_mips_embedded IS 
+
+	COMPONENT mips_embedded
+	Port 
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		halt		: in  STD_LOGIC;
+		dout		: out word_t
+	);
+	END COMPONENT;
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal rst 			: std_logic := '1';
+	signal clk 			: std_logic := '1';
+	signal halt			: std_logic := '0';
+	signal dout		 	: word_t;
+	
+BEGIN
+
+uut: mips_embedded
+	PORT MAP(
+		rst				=> rst,
+		clk				=> clk,
+		halt			=> halt,
+		dout			=> dout
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+STIMULUS: process
+	begin
+
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(clk);
+		rst <= '0';
+	
+		wait; 
+	
+	end process;
+
+END;
diff --git a/lib/CPUs/MIPS/src/tb_mips_embedded_syn.vhd b/lib/CPUs/MIPS/src/tb_mips_embedded_syn.vhd
new file mode 100644
index 0000000..ac471b4
--- /dev/null
+++ b/lib/CPUs/MIPS/src/tb_mips_embedded_syn.vhd
@@ -0,0 +1,123 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: Testbench for JCPU
+--            also writes 'opc.lst' for JASM-assembler
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+ENTITY tb_mips_embedded_syn IS
+END tb_mips_embedded_syn;
+
+ARCHITECTURE behavior OF tb_mips_embedded_syn IS 
+
+	COMPONENT mips_embedded_syn
+	Port 
+	(
+		sys_rst_n_in		: in  STD_LOGIC;
+		sys_clk_in			: in  STD_LOGIC;
+		sys_dip				: in  STD_LOGIC_VECTOR (7 downto 0);
+		sys_btn				: in  STD_LOGIC_VECTOR (8 downto 0);
+		sys_led				: out STD_LOGIC_VECTOR (7 downto 0);
+		sys_rx				: in  STD_LOGIC;
+		sys_tx				: out STD_LOGIC;
+		sys_error			: out STD_LOGIC_VECTOR (1 downto 0)
+	);
+	END COMPONENT;
+
+	constant CLK_PERIOD : time := 10.0 ns;
+
+	signal sys_rst_n_in			: std_logic := '0';
+	signal sys_clk_in			: std_logic := '1';
+	signal sys_led	 			: STD_LOGIC_VECTOR (7 downto 0);
+	signal sys_btn	 			: STD_LOGIC_VECTOR (8 downto 0) := "000000000";
+	signal sys_dip	 			: STD_LOGIC_VECTOR (7 downto 0) := "10001001";
+	signal sys_error 			: STD_LOGIC_VECTOR (1 downto 0);
+	signal sys_rx				: std_logic := '1';
+	signal sys_tx				: std_logic;
+	
+BEGIN
+
+uut: mips_embedded_syn
+	PORT MAP
+	(
+		sys_rst_n_in			=> sys_rst_n_in,
+		sys_clk_in				=> sys_clk_in,
+		sys_btn					=> sys_btn,
+		sys_dip					=> sys_dip,
+		sys_led					=> sys_led,
+		sys_rx					=> sys_rx,
+		sys_tx					=> sys_tx,
+		sys_error				=> sys_error
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		sys_clk_in <= not sys_clk_in;
+	end process;
+
+STIMULUS1: process
+	begin
+
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(sys_clk_in);
+		sys_rst_n_in <= '1';
+	
+		
+		
+--		wait for 9994999*CLK_PERIOD;
+--		for i in 1 to 10000 loop
+--			wait for 100*CLK_PERIOD;
+--			sys_btn(3) <= '1';
+--			wait for 10*CLK_PERIOD;
+--			sys_btn(3) <= '0';
+--		end loop;		
+		
+		wait until rising_edge(sys_clk_in) and now = 38980 ns;
+		sys_btn <= "000001000";
+		wait until rising_edge(sys_clk_in);
+		sys_btn <= "000000000";
+
+		wait; 
+	
+	end process;
+
+STIMULUS2: process
+	begin
+
+	
+		wait for 9999999*CLK_PERIOD;
+		for i in 1 to 10000 loop
+			wait for 137*CLK_PERIOD;
+			sys_btn(4) <= '1';
+			wait for 21*CLK_PERIOD;
+			sys_btn(4) <= '0';
+		end loop;		
+
+		wait; 
+	
+	end process;
+
+END;
diff --git a/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd b/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd
new file mode 100644
index 0000000..8235438
--- /dev/null
+++ b/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd
@@ -0,0 +1,308 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: Testbench for JCPU
+--            also writes 'opc.lst' for JASM-assembler
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+use work.mips_instr.all;
+
+ENTITY tb_mips_muldiv IS
+END tb_mips_muldiv;
+
+ARCHITECTURE behavior OF tb_mips_muldiv IS 
+
+	COMPONENT muldiv is
+	Port 
+	(
+		rst			: in  std_logic;
+		clk			: in  std_logic;
+		hilo_we		: in  std_logic;
+		din_hi		: in  word_t;
+		din_lo		: in  word_t;
+		mul_divn	: in  std_logic;
+		s_un		: in  std_logic;
+		start		: in  std_logic;
+		hilo_sel	: in  std_logic;
+		busy		: out std_logic;
+		dout		: out word_t
+	);
+	END COMPONENT;
+
+	constant CLK_PERIOD : time := 10 ns;
+	signal ENABLE_FAIL_REPORT : boolean := true;
+	signal rst 			: std_logic := '1';
+	signal clk 			: std_logic := '1';
+	signal busy			: std_logic;
+	signal mul_divn		: std_logic := '0';
+	signal s_un			: std_logic := '1';
+	signal hilo_we		: std_logic := '0';
+	signal start		: std_logic := '0';
+	signal din_hi		: word_t := (others => '-');
+	signal din_lo		: word_t := (others => '-');
+	signal ref_hi		: word_t := (others => '-');
+	signal ref_lo		: word_t := (others => '-');
+	signal dout			: word_t;
+	signal hilo_sel		: std_logic := '0';
+	signal result		: unsigned (2*word_t'length-1 downto 0);
+	signal ref_result	: unsigned (2*word_t'length-1 downto 0);
+	
+	type word_array_t is array (natural range <>) of word_t;
+	
+	constant operands : word_array_t(0 to 63) := 
+	(
+		X"00000000",
+		X"00000001",
+		X"00000010",
+		X"00000100",
+		X"00001000",
+		X"00010000",
+		X"00100000",
+		X"01000000",
+		X"10000000",
+		X"0000000F",
+		X"000000FF",
+		X"00000FFF",
+		X"0000FFFF",
+		X"000FFFFF",
+		X"00FFFFFF",
+		X"0FFFFFFF",
+		X"12345678",
+		X"23456789",
+		X"7FFFFFFF",
+		X"80000000",
+		X"A541B3B9",
+		X"80000001",
+		X"80000010",
+		X"80000100",
+		X"80001000",
+		X"80010000",
+		X"80100000",
+		X"81000000",
+		X"87654321",
+		X"98765432",
+		X"FFFFFFFF",
+		X"FFFFFFFE",
+		X"FFFFFFFD",
+		X"FFFFFFFB",
+		X"FFFFFFF7",
+		X"FFFFFFEF",
+		X"FFFFFFDF",
+		X"FFFFFFBF",
+		X"FFFFFF7F",
+		X"FFFFFEFF",
+		X"FFFFFDFF",
+		X"FFFFFBFF",
+		X"FFFFF7FF",
+		X"FFFFEFFF",
+		X"FFFFDFFF",
+		X"FFFFBFFF",
+		X"FFFF7FFF",
+		X"FFFEFFFF",
+		X"FFFDFFFF",
+		X"FFFBFFFF",
+		X"FFF7FFFF",
+		X"FFEFFFFF",
+		X"FFDFFFFF",
+		X"FFBFFFFF",
+		X"FF7FFFFF",
+		X"FEFFFFFF",
+		X"FDFFFFFF",
+		X"FBFFFFFF",
+		X"F7FFFFFF",
+		X"EFFFFFFF",
+		X"DFFFFFFF",
+		X"BFFFFFFF",
+		X"CFFFFFFF",
+		X"7FFFFFFF"
+	);
+	
+BEGIN
+
+uut: muldiv
+	PORT MAP(
+		rst				=> rst,
+		clk				=> clk,
+		hilo_we			=> hilo_we,
+		din_hi			=> din_hi,
+		din_lo			=> din_lo,
+		mul_divn		=> mul_divn,
+		s_un			=> s_un,
+		start			=> start,
+		hilo_sel		=> hilo_sel,
+		busy			=> busy,
+		dout			=> dout
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+REF_GEN: process
+	variable tmp : unsigned (2*word_t'length-1 downto 0);
+	variable tmp2 : unsigned (word_t'length-1 downto 0);
+	begin
+		if mul_divn = '0' then
+			wait until rising_edge(clk) and start = '1';
+			ref_lo	<= din_lo;
+			ref_hi	<= din_hi;
+			wait until rising_edge(clk) and busy = '0';
+			wait until rising_edge(clk);
+			wait until rising_edge(clk);
+			if s_un = '1' then
+				tmp			:= unsigned(signed(result(31 downto 0)) * signed(ref_lo));
+				tmp2 		:= unsigned(signed(tmp(31 downto 0)) + signed(result(63 downto 32)));
+				ref_result	<= X"00000000" & tmp2(31 downto 0);
+			else
+				tmp			:= result(31 downto 0) * ref_lo;
+				tmp2 		:= tmp(31 downto 0) + result(63 downto 32);
+				ref_result	<= X"00000000" & tmp2(31 downto 0);
+			end if;	
+			wait until rising_edge(clk);
+				
+			if ref_lo /= X"00000000" then
+				if ENABLE_FAIL_REPORT  then
+					assert ref_hi = ref_result(31 downto 0) report "Error on divison" severity failure;
+				end if;	
+			end if;	
+		else
+			wait until rising_edge(clk) and start = '1';
+			wait until rising_edge(clk) and busy = '0';
+			if s_un = '1' then
+				ref_result <= unsigned(signed(din_hi) * signed(din_lo));
+			else
+				ref_result <= unsigned(din_hi) * unsigned(din_lo);
+			end if;	
+			wait until rising_edge(clk);
+			wait until rising_edge(clk);
+			wait until rising_edge(clk);
+			if ENABLE_FAIL_REPORT then
+				assert ref_result = result report "Error on multiplication" severity failure;
+			end if;	
+		end if;
+		
+	end process;
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(clk);
+		rst <= '0';
+		wait for 2*CLK_PERIOD;
+	
+		mul_divn	<= '0';
+		s_un		<= '0';
+		for i in 0 to operands'length-1 loop
+			for j in 0 to operands'length-1 loop
+				wait until rising_edge(clk) and busy = '0';
+				din_hi		<= operands(i);
+				din_lo		<= operands(j);
+				start		<= '1';
+				wait until rising_edge(clk);
+				start		<= '0';
+				hilo_sel	<= '0';
+
+				-- Read result
+				wait until rising_edge(clk) and busy = '0';
+				result(31 downto 0) <= dout;
+				hilo_sel	<= '1';
+				wait until rising_edge(clk);
+				result(63 downto 32) <= dout;
+				wait for 2*CLK_PERIOD;
+			end loop;
+		end loop;
+
+		s_un	<= '1';
+		for i in 0 to operands'length-1 loop
+			for j in 0 to operands'length-1 loop
+				wait until rising_edge(clk) and busy = '0';
+				din_hi		<= operands(i);
+				din_lo		<= operands(j);
+				start		<= '1';
+				wait until rising_edge(clk);
+				start		<= '0';
+				hilo_sel	<= '0';
+
+				-- Read result
+				wait until rising_edge(clk) and busy = '0';
+				result(31 downto 0) <= dout;
+				hilo_sel	<= '1';
+				wait until rising_edge(clk);
+				result(63 downto 32) <= dout;
+				wait for 2*CLK_PERIOD;
+			end loop;
+		end loop;
+	
+		mul_divn	<= '1';
+		s_un		<= '0';
+		for i in 0 to operands'length-1 loop
+			for j in 0 to operands'length-1 loop
+				wait until rising_edge(clk) and busy = '0';
+				din_hi		<= operands(i);
+				din_lo		<= operands(j);
+				start		<= '1';
+				wait until rising_edge(clk);
+				start		<= '0';
+				hilo_sel	<= '0';
+
+				-- Read result
+				wait until rising_edge(clk) and busy = '0';
+				result(31 downto 0) <= dout;
+				hilo_sel	<= '1';
+				wait until rising_edge(clk);
+				result(63 downto 32) <= dout;
+			end loop;
+		end loop;
+
+		s_un	<= '1';
+		for i in 0 to operands'length-1 loop
+			for j in 0 to operands'length-1 loop
+				wait until rising_edge(clk) and busy = '0';
+				din_hi		<= operands(i);
+				din_lo		<= operands(j);
+				start		<= '1';
+				wait until rising_edge(clk);
+				start		<= '0';
+				hilo_sel	<= '0';
+
+				-- Read result
+				wait until rising_edge(clk) and busy = '0';
+				result(31 downto 0) <= dout;
+				hilo_sel	<= '1';
+				wait until rising_edge(clk);
+				result(63 downto 32) <= dout;
+			end loop;
+		end loop;
+		
+		wait; 
+	
+	end process;
+	
+END;
diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd
new file mode 100644
index 0000000..0bf5fed
--- /dev/null
+++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd
@@ -0,0 +1,174 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: Testbench for JCPU
+--            also writes 'opc.lst' for JASM-assembler
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.mips_types.all;
+use work.mips_instr.all;
+
+ENTITY tb_mips_top IS
+END tb_mips_top;
+
+ARCHITECTURE behavior OF tb_mips_top IS 
+
+	COMPONENT mips_top
+	Port 
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		halt		: in  STD_LOGIC;
+		imem_din	: in  unsigned (WORD_WIDTH-1 downto 0);
+		imem_addr	: out unsigned (WORD_WIDTH-1 downto 0);
+		dmem_we		: out STD_LOGIC;
+		dmem_re		: out STD_LOGIC;
+		dmem_din	: in  unsigned (WORD_WIDTH-1 downto 0);
+		dmem_dout	: out unsigned (WORD_WIDTH-1 downto 0);
+		dmem_addr	: out unsigned (WORD_WIDTH-1 downto 0)
+		
+	);
+	END COMPONENT;
+
+	COMPONENT rom
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		addr		: in  word_t;
+		dout		: out word_t
+	);
+	END COMPONENT;
+
+	COMPONENT ram
+	Generic 
+	(
+		word_addr_width 	: integer
+	);
+	Port 
+	(
+		clk			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		addr		: in  word_t;
+		din			: in  word_t;
+		dout		: out word_t
+	);
+	END COMPONENT;
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal rst 			: std_logic := '1';
+	signal clk 			: std_logic := '1';
+	signal cpu_halt		: std_logic;
+	signal irom_data	: word_t := (others => '-');
+	signal irom_addr	: word_t;
+	signal dmem_din		: word_t := (others => '-');
+	signal dmem_dout 	: word_t;
+	signal dmem_addr 	: word_t;
+	signal dmem_we 		: std_logic;
+	signal dmem_re 		: std_logic;
+	
+BEGIN
+
+uut: mips_top
+	PORT MAP(
+		rst				=> rst,
+		clk				=> clk,
+		halt			=> cpu_halt,
+		imem_din		=> irom_data,
+		imem_addr		=> irom_addr,
+		dmem_we			=> dmem_we,
+		dmem_re			=> dmem_re,
+		dmem_din		=> dmem_din,
+		dmem_dout		=> dmem_dout,
+		dmem_addr		=> dmem_addr
+	);
+
+inst_rom: rom
+	PORT MAP
+	(
+		clk				=> clk,
+		addr			=> irom_addr,
+		dout 			=> irom_data
+	);
+
+inst_ram: ram
+	GENERIC MAP
+	(
+		word_addr_width	=> 6
+	)
+	PORT MAP
+	(
+		clk			=> clk,
+		we			=> dmem_we,
+		addr		=> dmem_addr,
+		din 		=> dmem_dout,
+		dout 		=> dmem_din
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+HLT_GEN: 
+	process(rst, clk)
+	subtype cnt_t is natural range 0 to 2;
+	variable cnt : cnt_t;
+	begin
+		if rst = '1' then
+			cnt := cnt_t'high;
+			cpu_halt <= '0';
+		elsif rising_edge(clk) then
+			cpu_halt <= '0';
+			if cnt /= 0 then
+				cnt := cnt - 1;
+			else
+				cnt := cnt_t'high;
+				cpu_halt <= '1';
+			end if;	
+		end if;
+	end process;
+
+STIMULUS: process
+
+	begin
+
+--		for i in 0 to instr_name_array'length-1 loop
+--			fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i));
+--		end loop;	
+
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(clk);
+		rst <= '0';
+		wait for 2*CLK_PERIOD;
+	
+--		assert false report "Test finished" severity error;
+		wait; 
+	
+	end process;
+	
+END;
diff --git a/lib/CPUs/MIPS/src/testbench.ROM_ld.vhd b/lib/CPUs/MIPS/src/testbench.ROM_ld.vhd
new file mode 100644
index 0000000..f46253b
--- /dev/null
+++ b/lib/CPUs/MIPS/src/testbench.ROM_ld.vhd
@@ -0,0 +1,4222 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+ENTITY icache IS
+	Port
+	(
+		clk		: in  STD_LOGIC;
+		ce		: in  STD_LOGIC;
+		addr		: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+END icache;
+
+ARCHITECTURE data OF icache IS
+
+	subtype word_t is unsigned(31 downto 0);
+	type word_array_t is array (0 to 4095) of word_t;
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: unsigned (15 downto 0);
+	signal jtag_ld_dout		: unsigned (31 downto 0);
+	signal jtag_ld_din		: unsigned (31 downto 0);
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (47 downto 0);
+
+	signal word_array : word_array_t :=
+	(
+
+		X"3C1A1040", -- 00000000
+		X"375A040C", -- 00000004
+		X"409A6000", -- 00000008
+		X"241A0000", -- 0000000C
+		X"409A6800", -- 00000010
+		X"401A7800", -- 00000014
+		X"00000000", -- 00000018
+		X"409AF800", -- 0000001C
+		X"3C1A0040", -- 00000020
+		X"275A04F4", -- 00000024
+		X"03400008", -- 00000028
+		X"42000010", -- 0000002C
+		X"00000000", -- 00000030
+		X"00000000", -- 00000034
+		X"00000000", -- 00000038
+		X"00000000", -- 0000003C
+		X"00000000", -- 00000040
+		X"00000000", -- 00000044
+		X"00000000", -- 00000048
+		X"00000000", -- 0000004C
+		X"00000000", -- 00000050
+		X"00000000", -- 00000054
+		X"00000000", -- 00000058
+		X"00000000", -- 0000005C
+		X"00000000", -- 00000060
+		X"00000000", -- 00000064
+		X"00000000", -- 00000068
+		X"00000000", -- 0000006C
+		X"00000000", -- 00000070
+		X"00000000", -- 00000074
+		X"00000000", -- 00000078
+		X"00000000", -- 0000007C
+		X"00000000", -- 00000080
+		X"00000000", -- 00000084
+		X"00000000", -- 00000088
+		X"00000000", -- 0000008C
+		X"00000000", -- 00000090
+		X"00000000", -- 00000094
+		X"00000000", -- 00000098
+		X"00000000", -- 0000009C
+		X"00000000", -- 000000A0
+		X"00000000", -- 000000A4
+		X"00000000", -- 000000A8
+		X"00000000", -- 000000AC
+		X"00000000", -- 000000B0
+		X"00000000", -- 000000B4
+		X"00000000", -- 000000B8
+		X"00000000", -- 000000BC
+		X"00000000", -- 000000C0
+		X"00000000", -- 000000C4
+		X"00000000", -- 000000C8
+		X"00000000", -- 000000CC
+		X"00000000", -- 000000D0
+		X"00000000", -- 000000D4
+		X"00000000", -- 000000D8
+		X"00000000", -- 000000DC
+		X"00000000", -- 000000E0
+		X"00000000", -- 000000E4
+		X"00000000", -- 000000E8
+		X"00000000", -- 000000EC
+		X"00000000", -- 000000F0
+		X"00000000", -- 000000F4
+		X"00000000", -- 000000F8
+		X"00000000", -- 000000FC
+		X"00000000", -- 00000100
+		X"00000000", -- 00000104
+		X"00000000", -- 00000108
+		X"00000000", -- 0000010C
+		X"00000000", -- 00000110
+		X"00000000", -- 00000114
+		X"00000000", -- 00000118
+		X"00000000", -- 0000011C
+		X"00000000", -- 00000120
+		X"00000000", -- 00000124
+		X"00000000", -- 00000128
+		X"00000000", -- 0000012C
+		X"00000000", -- 00000130
+		X"00000000", -- 00000134
+		X"00000000", -- 00000138
+		X"00000000", -- 0000013C
+		X"00000000", -- 00000140
+		X"00000000", -- 00000144
+		X"00000000", -- 00000148
+		X"00000000", -- 0000014C
+		X"00000000", -- 00000150
+		X"00000000", -- 00000154
+		X"00000000", -- 00000158
+		X"00000000", -- 0000015C
+		X"00000000", -- 00000160
+		X"00000000", -- 00000164
+		X"00000000", -- 00000168
+		X"00000000", -- 0000016C
+		X"00000000", -- 00000170
+		X"00000000", -- 00000174
+		X"00000000", -- 00000178
+		X"00000000", -- 0000017C
+		X"3C010000", -- 00000180
+		X"AC3D09A0", -- 00000184
+		X"3C1D0000", -- 00000188
+		X"27BD09A0", -- 0000018C
+		X"27BD0004", -- 00000190
+		X"AFA80000", -- 00000194
+		X"27BD0004", -- 00000198
+		X"AFA90000", -- 0000019C
+		X"27BD0004", -- 000001A0
+		X"AFAA0000", -- 000001A4
+		X"27BD0004", -- 000001A8
+		X"AFAB0000", -- 000001AC
+		X"27BD0004", -- 000001B0
+		X"AFAC0000", -- 000001B4
+		X"27BD0004", -- 000001B8
+		X"AFBF0000", -- 000001BC
+		X"400A4000", -- 000001C0
+		X"27BD0004", -- 000001C4
+		X"AFAA0000", -- 000001C8
+		X"400A6000", -- 000001CC
+		X"27BD0004", -- 000001D0
+		X"AFAA0000", -- 000001D4
+		X"400A6800", -- 000001D8
+		X"27BD0004", -- 000001DC
+		X"AFAA0000", -- 000001E0
+		X"000A5742", -- 000001E4
+		X"314B0004", -- 000001E8
+		X"400A7000", -- 000001EC
+		X"27BD0004", -- 000001F0
+		X"AFAA0000", -- 000001F4
+		X"014B5021", -- 000001F8
+		X"27BD0004", -- 000001FC
+		X"AFAA0000", -- 00000200
+		X"3C1A8000", -- 00000204
+		X"275A0009", -- 00000208
+		X"241B000D", -- 0000020C
+		X"A35B0000", -- 00000210
+		X"3C0B0000", -- 00000214
+		X"256B0ADE", -- 00000218
+		X"0C10012B", -- 0000021C
+		X"00000000", -- 00000220
+		X"3C0B0000", -- 00000224
+		X"256B0AA0", -- 00000228
+		X"0C10012B", -- 0000022C
+		X"00000000", -- 00000230
+		X"8FAA0000", -- 00000234
+		X"27BDFFFC", -- 00000238
+		X"0C1000E3", -- 0000023C
+		X"00000000", -- 00000240
+		X"3C0B0000", -- 00000244
+		X"256B0ADE", -- 00000248
+		X"0C10012B", -- 0000024C
+		X"00000000", -- 00000250
+		X"3C0B0000", -- 00000254
+		X"256B0AAE", -- 00000258
+		X"0C10012B", -- 0000025C
+		X"00000000", -- 00000260
+		X"8FAA0000", -- 00000264
+		X"27BDFFFC", -- 00000268
+		X"0C1000E3", -- 0000026C
+		X"00000000", -- 00000270
+		X"3C0B0000", -- 00000274
+		X"256B0ADE", -- 00000278
+		X"0C10012B", -- 0000027C
+		X"00000000", -- 00000280
+		X"3C0B0000", -- 00000284
+		X"256B0ABA", -- 00000288
+		X"0C10012B", -- 0000028C
+		X"00000000", -- 00000290
+		X"8FAA0000", -- 00000294
+		X"27BDFFFC", -- 00000298
+		X"0C1000E3", -- 0000029C
+		X"00000000", -- 000002A0
+		X"3C0B0000", -- 000002A4
+		X"256B0ADE", -- 000002A8
+		X"0C10012B", -- 000002AC
+		X"00000000", -- 000002B0
+		X"3C0B0000", -- 000002B4
+		X"256B0AC6", -- 000002B8
+		X"0C10012B", -- 000002BC
+		X"00000000", -- 000002C0
+		X"8FAA0000", -- 000002C4
+		X"27BDFFFC", -- 000002C8
+		X"0C1000E3", -- 000002CC
+		X"00000000", -- 000002D0
+		X"3C0B0000", -- 000002D4
+		X"256B0ADE", -- 000002D8
+		X"0C10012B", -- 000002DC
+		X"00000000", -- 000002E0
+		X"3C0B0000", -- 000002E4
+		X"256B0AD2", -- 000002E8
+		X"0C10012B", -- 000002EC
+		X"00000000", -- 000002F0
+		X"8FAA0000", -- 000002F4
+		X"27BDFFFC", -- 000002F8
+		X"0C1000E3", -- 000002FC
+		X"00000000", -- 00000300
+		X"3C0B0000", -- 00000304
+		X"256B0ADE", -- 00000308
+		X"0C10012B", -- 0000030C
+		X"00000000", -- 00000310
+		X"401A6800", -- 00000314
+		X"3C1B8000", -- 00000318
+		X"277B0000", -- 0000031C
+		X"001AD082", -- 00000320
+		X"335A000F", -- 00000324
+		X"035BD025", -- 00000328
+		X"AF7A0000", -- 0000032C
+		X"401A6800", -- 00000330
+		X"00000000", -- 00000334
+		X"001AD202", -- 00000338
+		X"335A00FF", -- 0000033C
+		X"1740FFFB", -- 00000340
+		X"00000000", -- 00000344
+		X"401A7000", -- 00000348
+		X"8FBF0000", -- 0000034C
+		X"27BDFFFC", -- 00000350
+		X"8FAC0000", -- 00000354
+		X"27BDFFFC", -- 00000358
+		X"8FAB0000", -- 0000035C
+		X"27BDFFFC", -- 00000360
+		X"8FAA0000", -- 00000364
+		X"27BDFFFC", -- 00000368
+		X"8FA90000", -- 0000036C
+		X"27BDFFFC", -- 00000370
+		X"8FA80000", -- 00000374
+		X"27BDFFFC", -- 00000378
+		X"3C1D0000", -- 0000037C
+		X"8FBD09A0", -- 00000380
+		X"03400008", -- 00000384
+		X"42000010", -- 00000388
+		X"27BD0004", -- 0000038C
+		X"AFBF0000", -- 00000390
+		X"27BD0004", -- 00000394
+		X"AFAA0000", -- 00000398
+		X"000A5402", -- 0000039C
+		X"0C1000F2", -- 000003A0
+		X"00000000", -- 000003A4
+		X"8FAA0000", -- 000003A8
+		X"27BDFFFC", -- 000003AC
+		X"0C1000F2", -- 000003B0
+		X"00000000", -- 000003B4
+		X"8FBF0000", -- 000003B8
+		X"27BDFFFC", -- 000003BC
+		X"03E00008", -- 000003C0
+		X"00000000", -- 000003C4
+		X"27BD0004", -- 000003C8
+		X"AFBF0000", -- 000003CC
+		X"27BD0004", -- 000003D0
+		X"AFAA0000", -- 000003D4
+		X"000A5202", -- 000003D8
+		X"0C100101", -- 000003DC
+		X"00000000", -- 000003E0
+		X"8FAA0000", -- 000003E4
+		X"27BDFFFC", -- 000003E8
+		X"0C100101", -- 000003EC
+		X"00000000", -- 000003F0
+		X"8FBF0000", -- 000003F4
+		X"27BDFFFC", -- 000003F8
+		X"03E00008", -- 000003FC
+		X"00000000", -- 00000400
+		X"27BD0004", -- 00000404
+		X"AFBF0000", -- 00000408
+		X"27BD0004", -- 0000040C
+		X"AFAA0000", -- 00000410
+		X"000A5102", -- 00000414
+		X"0C100110", -- 00000418
+		X"00000000", -- 0000041C
+		X"8FAA0000", -- 00000420
+		X"27BDFFFC", -- 00000424
+		X"0C100110", -- 00000428
+		X"00000000", -- 0000042C
+		X"8FBF0000", -- 00000430
+		X"27BDFFFC", -- 00000434
+		X"03E00008", -- 00000438
+		X"00000000", -- 0000043C
+		X"27BD0004", -- 00000440
+		X"AFBF0000", -- 00000444
+		X"27BD0004", -- 00000448
+		X"AFAA0000", -- 0000044C
+		X"3C0C0000", -- 00000450
+		X"258C0AE1", -- 00000454
+		X"314A000F", -- 00000458
+		X"018A6021", -- 0000045C
+		X"918A0000", -- 00000460
+		X"0C100121", -- 00000464
+		X"00000000", -- 00000468
+		X"8FAA0000", -- 0000046C
+		X"27BDFFFC", -- 00000470
+		X"8FBF0000", -- 00000474
+		X"27BDFFFC", -- 00000478
+		X"03E00008", -- 0000047C
+		X"00000000", -- 00000480
+		X"3C088000", -- 00000484
+		X"25080008", -- 00000488
+		X"91080000", -- 0000048C
+		X"3C098000", -- 00000490
+		X"25290004", -- 00000494
+		X"31080002", -- 00000498
+		X"1500FFF9", -- 0000049C
+		X"00000000", -- 000004A0
+		X"03E00008", -- 000004A4
+		X"A12A0000", -- 000004A8
+		X"27BD0004", -- 000004AC
+		X"AFAB0000", -- 000004B0
+		X"27BD0004", -- 000004B4
+		X"AFBF0000", -- 000004B8
+		X"916A0000", -- 000004BC
+		X"256B0001", -- 000004C0
+		X"19400005", -- 000004C4
+		X"00000000", -- 000004C8
+		X"0C100121", -- 000004CC
+		X"00000000", -- 000004D0
+		X"0810012F", -- 000004D4
+		X"00000000", -- 000004D8
+		X"8FBF0000", -- 000004DC
+		X"27BDFFFC", -- 000004E0
+		X"8FAB0000", -- 000004E4
+		X"27BDFFFC", -- 000004E8
+		X"03E00008", -- 000004EC
+		X"00000000", -- 000004F0
+		X"3C1A8000", -- 000004F4
+		X"275A0009", -- 000004F8
+		X"241B000D", -- 000004FC
+		X"A35B0000", -- 00000500
+		X"3C1D8000", -- 00000504
+		X"27BDEFFC", -- 00000508
+		X"3C1A0040", -- 0000050C
+		X"275A0D90", -- 00000510
+		X"0340F809", -- 00000514
+		X"00000000", -- 00000518
+		X"08100146", -- 0000051C
+		X"00000000", -- 00000520
+		X"3C028000", -- 00000524
+		X"34440004", -- 00000528
+		X"34430008", -- 0000052C
+		X"90620000", -- 00000530
+		X"00000000", -- 00000534
+		X"30420010", -- 00000538
+		X"1040FFFC", -- 0000053C
+		X"00000000", -- 00000540
+		X"90820000", -- 00000544
+		X"00000000", -- 00000548
+		X"00021600", -- 0000054C
+		X"03E00008", -- 00000550
+		X"00021603", -- 00000554
+		X"3C028000", -- 00000558
+		X"00042600", -- 0000055C
+		X"00042603", -- 00000560
+		X"34450004", -- 00000564
+		X"34430008", -- 00000568
+		X"90620000", -- 0000056C
+		X"00000000", -- 00000570
+		X"30420002", -- 00000574
+		X"1440FFFC", -- 00000578
+		X"00000000", -- 0000057C
+		X"03E00008", -- 00000580
+		X"A0A40000", -- 00000584
+		X"3C028000", -- 00000588
+		X"34420014", -- 0000058C
+		X"8C420000", -- 00000590
+		X"10800005", -- 00000594
+		X"00000000", -- 00000598
+		X"AC80000C", -- 0000059C
+		X"AC820000", -- 000005A0
+		X"AC800004", -- 000005A4
+		X"AC800008", -- 000005A8
+		X"03E00008", -- 000005AC
+		X"00000000", -- 000005B0
+		X"3C028000", -- 000005B4
+		X"34450014", -- 000005B8
+		X"10800007", -- 000005BC
+		X"34430010", -- 000005C0
+		X"8CA20000", -- 000005C4
+		X"00000000", -- 000005C8
+		X"AC820000", -- 000005CC
+		X"8C630000", -- 000005D0
+		X"00000000", -- 000005D4
+		X"AC830004", -- 000005D8
+		X"03E00008", -- 000005DC
+		X"00001021", -- 000005E0
+		X"27BDFFD8", -- 000005E4
+		X"AFB20020", -- 000005E8
+		X"AFB1001C", -- 000005EC
+		X"AFB00018", -- 000005F0
+		X"AFBF0024", -- 000005F4
+		X"8C850004", -- 000005F8
+		X"3C06000F", -- 000005FC
+		X"00808021", -- 00000600
+		X"3C028000", -- 00000604
+		X"34C64240", -- 00000608
+		X"27A40010", -- 0000060C
+		X"34520014", -- 00000610
+		X"0C1003B1", -- 00000614
+		X"34510010", -- 00000618
+		X"12000009", -- 0000061C
+		X"00000000", -- 00000620
+		X"8FA20014", -- 00000624
+		X"00000000", -- 00000628
+		X"AE220000", -- 0000062C
+		X"8E030000", -- 00000630
+		X"8FA20010", -- 00000634
+		X"00000000", -- 00000638
+		X"00621821", -- 0000063C
+		X"AE430000", -- 00000640
+		X"8FBF0024", -- 00000644
+		X"8FB20020", -- 00000648
+		X"8FB1001C", -- 0000064C
+		X"8FB00018", -- 00000650
+		X"00001021", -- 00000654
+		X"03E00008", -- 00000658
+		X"27BD0028", -- 0000065C
+		X"8F820988", -- 00000660
+		X"00000000", -- 00000664
+		X"14400004", -- 00000668
+		X"00441821", -- 0000066C
+		X"3C028000", -- 00000670
+		X"2442EFFC", -- 00000674
+		X"00441821", -- 00000678
+		X"03E00008", -- 0000067C
+		X"AF830988", -- 00000680
+		X"24022000", -- 00000684
+		X"ACA20004", -- 00000688
+		X"03E00008", -- 0000068C
+		X"00001021", -- 00000690
+		X"03E00008", -- 00000694
+		X"00001021", -- 00000698
+		X"03E00008", -- 0000069C
+		X"2402FFFF", -- 000006A0
+		X"03E00008", -- 000006A4
+		X"2402FFFF", -- 000006A8
+		X"03E00008", -- 000006AC
+		X"00001021", -- 000006B0
+		X"27BDFFE0", -- 000006B4
+		X"AFB20018", -- 000006B8
+		X"AFB10014", -- 000006BC
+		X"AFB00010", -- 000006C0
+		X"AFBF001C", -- 000006C4
+		X"00C09021", -- 000006C8
+		X"00A08021", -- 000006CC
+		X"18C00007", -- 000006D0
+		X"00008821", -- 000006D4
+		X"82040000", -- 000006D8
+		X"0C100156", -- 000006DC
+		X"26310001", -- 000006E0
+		X"0232102A", -- 000006E4
+		X"1440FFFB", -- 000006E8
+		X"26100001", -- 000006EC
+		X"02201021", -- 000006F0
+		X"8FBF001C", -- 000006F4
+		X"8FB20018", -- 000006F8
+		X"8FB10014", -- 000006FC
+		X"8FB00010", -- 00000700
+		X"03E00008", -- 00000704
+		X"27BD0020", -- 00000708
+		X"03E00008", -- 0000070C
+		X"24020001", -- 00000710
+		X"27BDFFE0", -- 00000714
+		X"AFB10014", -- 00000718
+		X"AFB00010", -- 0000071C
+		X"AFBF0018", -- 00000720
+		X"00808021", -- 00000724
+		X"80840000", -- 00000728
+		X"081001D1", -- 0000072C
+		X"02008821", -- 00000730
+		X"0C100156", -- 00000734
+		X"26100001", -- 00000738
+		X"82040000", -- 0000073C
+		X"00000000", -- 00000740
+		X"1480FFFB", -- 00000744
+		X"02111023", -- 00000748
+		X"8FBF0018", -- 0000074C
+		X"8FB10014", -- 00000750
+		X"8FB00010", -- 00000754
+		X"03E00008", -- 00000758
+		X"27BD0020", -- 0000075C
+		X"27BDFFE0", -- 00000760
+		X"AFB00010", -- 00000764
+		X"00048600", -- 00000768
+		X"AFB10014", -- 0000076C
+		X"AFBF0018", -- 00000770
+		X"00108603", -- 00000774
+		X"24110001", -- 00000778
+		X"00101103", -- 0000077C
+		X"3045000F", -- 00000780
+		X"00101100", -- 00000784
+		X"00028600", -- 00000788
+		X"2CA3000A", -- 0000078C
+		X"2631FFFF", -- 00000790
+		X"00108603", -- 00000794
+		X"14600002", -- 00000798
+		X"24A40030", -- 0000079C
+		X"24A40037", -- 000007A0
+		X"0C100156", -- 000007A4
+		X"00000000", -- 000007A8
+		X"0621FFF4", -- 000007AC
+		X"00101103", -- 000007B0
+		X"8FBF0018", -- 000007B4
+		X"8FB10014", -- 000007B8
+		X"8FB00010", -- 000007BC
+		X"03E00008", -- 000007C0
+		X"27BD0020", -- 000007C4
+		X"27BDFFE0", -- 000007C8
+		X"AFB10014", -- 000007CC
+		X"AFB00010", -- 000007D0
+		X"AFBF0018", -- 000007D4
+		X"00808021", -- 000007D8
+		X"24110003", -- 000007DC
+		X"00102603", -- 000007E0
+		X"0C1001D8", -- 000007E4
+		X"2631FFFF", -- 000007E8
+		X"0621FFFC", -- 000007EC
+		X"00108200", -- 000007F0
+		X"8FBF0018", -- 000007F4
+		X"8FB10014", -- 000007F8
+		X"8FB00010", -- 000007FC
+		X"03E00008", -- 00000800
+		X"27BD0020", -- 00000804
+		X"24080002", -- 00000808
+		X"0107102A", -- 0000080C
+		X"ACC40000", -- 00000810
+		X"1040000A", -- 00000814
+		X"ACC50004", -- 00000818
+		X"24C60008", -- 0000081C
+		X"8CC2FFF8", -- 00000820
+		X"8CC3FFFC", -- 00000824
+		X"25080001", -- 00000828
+		X"00431021", -- 0000082C
+		X"0107202A", -- 00000830
+		X"ACC20000", -- 00000834
+		X"1480FFF9", -- 00000838
+		X"24C60004", -- 0000083C
+		X"03E00008", -- 00000840
+		X"01001021", -- 00000844
+		X"40026000", -- 00000848
+		X"03E00008", -- 0000084C
+		X"00000000", -- 00000850
+		X"40027800", -- 00000854
+		X"03E00008", -- 00000858
+		X"00000000", -- 0000085C
+		X"3C020000", -- 00000860
+		X"8C420098", -- 00000864
+		X"27BDFFC0", -- 00000868
+		X"3C030000", -- 0000086C
+		X"8C63009C", -- 00000870
+		X"AFA20010", -- 00000874
+		X"3C020000", -- 00000878
+		X"8C4200A0", -- 0000087C
+		X"AFA30014", -- 00000880
+		X"AFA20018", -- 00000884
+		X"3C030000", -- 00000888
+		X"8C6300A4", -- 0000088C
+		X"3C020000", -- 00000890
+		X"8C4200A8", -- 00000894
+		X"AFA3001C", -- 00000898
+		X"AFA20020", -- 0000089C
+		X"3C030000", -- 000008A0
+		X"8C6300AC", -- 000008A4
+		X"3C020000", -- 000008A8
+		X"8C4200B0", -- 000008AC
+		X"AFA30024", -- 000008B0
+		X"AFBF0038", -- 000008B4
+		X"AFB10034", -- 000008B8
+		X"AFB00030", -- 000008BC
+		X"0C100212", -- 000008C0
+		X"AFA20028", -- 000008C4
+		X"3C040000", -- 000008C8
+		X"2484003C", -- 000008CC
+		X"0C1001C5", -- 000008D0
+		X"00408821", -- 000008D4
+		X"0C1001F2", -- 000008D8
+		X"02202021", -- 000008DC
+		X"3C040000", -- 000008E0
+		X"0C1001C5", -- 000008E4
+		X"24840078", -- 000008E8
+		X"0C100215", -- 000008EC
+		X"00000000", -- 000008F0
+		X"00028203", -- 000008F4
+		X"321000FF", -- 000008F8
+		X"3C040000", -- 000008FC
+		X"24840048", -- 00000900
+		X"0C1001C5", -- 00000904
+		X"00408821", -- 00000908
+		X"00101880", -- 0000090C
+		X"2610FFFF", -- 00000910
+		X"2E100006", -- 00000914
+		X"3C040000", -- 00000918
+		X"24840054", -- 0000091C
+		X"12000012", -- 00000920
+		X"03A31021", -- 00000924
+		X"8C440010", -- 00000928
+		X"0C1001C5", -- 0000092C
+		X"00000000", -- 00000930
+		X"3C040000", -- 00000934
+		X"0C1001C5", -- 00000938
+		X"2484005C", -- 0000093C
+		X"00112600", -- 00000940
+		X"0C1001D8", -- 00000944
+		X"00042603", -- 00000948
+		X"3C040000", -- 0000094C
+		X"0C1001C5", -- 00000950
+		X"24840078", -- 00000954
+		X"8FBF0038", -- 00000958
+		X"8FB10034", -- 0000095C
+		X"8FB00030", -- 00000960
+		X"03E00008", -- 00000964
+		X"27BD0040", -- 00000968
+		X"0C1001C5", -- 0000096C
+		X"00000000", -- 00000970
+		X"3C040000", -- 00000974
+		X"0C1001C5", -- 00000978
+		X"24840078", -- 0000097C
+		X"8FBF0038", -- 00000980
+		X"8FB10034", -- 00000984
+		X"8FB00030", -- 00000988
+		X"03E00008", -- 0000098C
+		X"27BD0040", -- 00000990
+		X"27BDFFE8", -- 00000994
+		X"24040080", -- 00000998
+		X"AFBF0014", -- 0000099C
+		X"0C1003D6", -- 000009A0
+		X"AFB00010", -- 000009A4
+		X"00402021", -- 000009A8
+		X"3C025555", -- 000009AC
+		X"3C03AAAA", -- 000009B0
+		X"34455555", -- 000009B4
+		X"3466AAAA", -- 000009B8
+		X"2407FFFF", -- 000009BC
+		X"AC800000", -- 000009C0
+		X"AC850004", -- 000009C4
+		X"AC860008", -- 000009C8
+		X"AC87000C", -- 000009CC
+		X"8C830000", -- 000009D0
+		X"3C028000", -- 000009D4
+		X"14600005", -- 000009D8
+		X"34500010", -- 000009DC
+		X"8C820004", -- 000009E0
+		X"00000000", -- 000009E4
+		X"10450008", -- 000009E8
+		X"00000000", -- 000009EC
+		X"0C1003DA", -- 000009F0
+		X"00000000", -- 000009F4
+		X"02001021", -- 000009F8
+		X"8FBF0014", -- 000009FC
+		X"8FB00010", -- 00000A00
+		X"03E00008", -- 00000A04
+		X"27BD0018", -- 00000A08
+		X"8C820008", -- 00000A0C
+		X"00000000", -- 00000A10
+		X"1446FFF6", -- 00000A14
+		X"00000000", -- 00000A18
+		X"8C82000C", -- 00000A1C
+		X"00000000", -- 00000A20
+		X"1447FFF2", -- 00000A24
+		X"00801821", -- 00000A28
+		X"00002821", -- 00000A2C
+		X"3C078000", -- 00000A30
+		X"2406001F", -- 00000A34
+		X"00051043", -- 00000A38
+		X"24C6FFFF", -- 00000A3C
+		X"AC650000", -- 00000A40
+		X"24630004", -- 00000A44
+		X"04C1FFFB", -- 00000A48
+		X"00472825", -- 00000A4C
+		X"00801821", -- 00000A50
+		X"00002821", -- 00000A54
+		X"00003021", -- 00000A58
+		X"0810029D", -- 00000A5C
+		X"3C088000", -- 00000A60
+		X"24C60001", -- 00000A64
+		X"28C20020", -- 00000A68
+		X"10400005", -- 00000A6C
+		X"00E82825", -- 00000A70
+		X"8C620000", -- 00000A74
+		X"00053843", -- 00000A78
+		X"1045FFF9", -- 00000A7C
+		X"24630004", -- 00000A80
+		X"24020020", -- 00000A84
+		X"14C2FFD9", -- 00000A88
+		X"00801821", -- 00000A8C
+		X"00002821", -- 00000A90
+		X"2406001F", -- 00000A94
+		X"00051040", -- 00000A98
+		X"24C6FFFF", -- 00000A9C
+		X"AC650000", -- 00000AA0
+		X"24630004", -- 00000AA4
+		X"04C1FFFB", -- 00000AA8
+		X"34450001", -- 00000AAC
+		X"00801821", -- 00000AB0
+		X"00002821", -- 00000AB4
+		X"081002B4", -- 00000AB8
+		X"00003021", -- 00000ABC
+		X"24C60001", -- 00000AC0
+		X"28C20020", -- 00000AC4
+		X"10400005", -- 00000AC8
+		X"34E50001", -- 00000ACC
+		X"8C620000", -- 00000AD0
+		X"00053840", -- 00000AD4
+		X"1045FFF9", -- 00000AD8
+		X"24630004", -- 00000ADC
+		X"24020020", -- 00000AE0
+		X"14C2FFC2", -- 00000AE4
+		X"00801821", -- 00000AE8
+		X"24050001", -- 00000AEC
+		X"2406001F", -- 00000AF0
+		X"24C6FFFF", -- 00000AF4
+		X"AC650000", -- 00000AF8
+		X"24630004", -- 00000AFC
+		X"04C1FFFC", -- 00000B00
+		X"00052840", -- 00000B04
+		X"00801821", -- 00000B08
+		X"24050001", -- 00000B0C
+		X"081002CA", -- 00000B10
+		X"00003021", -- 00000B14
+		X"24C60001", -- 00000B18
+		X"28C20020", -- 00000B1C
+		X"10400005", -- 00000B20
+		X"00052840", -- 00000B24
+		X"8C620000", -- 00000B28
+		X"00000000", -- 00000B2C
+		X"1045FFF9", -- 00000B30
+		X"24630004", -- 00000B34
+		X"24020020", -- 00000B38
+		X"14C2FFAC", -- 00000B3C
+		X"00801821", -- 00000B40
+		X"2405FFFE", -- 00000B44
+		X"2406001F", -- 00000B48
+		X"00051040", -- 00000B4C
+		X"24C6FFFF", -- 00000B50
+		X"AC650000", -- 00000B54
+		X"24630004", -- 00000B58
+		X"04C1FFFB", -- 00000B5C
+		X"34450001", -- 00000B60
+		X"00801821", -- 00000B64
+		X"2405FFFE", -- 00000B68
+		X"081002E1", -- 00000B6C
+		X"00003021", -- 00000B70
+		X"24C60001", -- 00000B74
+		X"28C20020", -- 00000B78
+		X"10400005", -- 00000B7C
+		X"34E50001", -- 00000B80
+		X"8C620000", -- 00000B84
+		X"00053840", -- 00000B88
+		X"1045FFF9", -- 00000B8C
+		X"24630004", -- 00000B90
+		X"24020020", -- 00000B94
+		X"14C2FF95", -- 00000B98
+		X"00000000", -- 00000B9C
+		X"0810027C", -- 00000BA0
+		X"00008021", -- 00000BA4
+		X"27BDFF88", -- 00000BA8
+		X"3C02AAAA", -- 00000BAC
+		X"AFB3006C", -- 00000BB0
+		X"AFB20068", -- 00000BB4
+		X"AFB00060", -- 00000BB8
+		X"AFBF0070", -- 00000BBC
+		X"AFB10064", -- 00000BC0
+		X"3450AAAA", -- 00000BC4
+		X"00009821", -- 00000BC8
+		X"00002021", -- 00000BCC
+		X"27B20010", -- 00000BD0
+		X"02401021", -- 00000BD4
+		X"24060013", -- 00000BD8
+		X"24C6FFFF", -- 00000BDC
+		X"AC500000", -- 00000BE0
+		X"04C1FFFD", -- 00000BE4
+		X"24420004", -- 00000BE8
+		X"02041026", -- 00000BEC
+		X"24910001", -- 00000BF0
+		X"2442FFFF", -- 00000BF4
+		X"02202821", -- 00000BF8
+		X"27A60010", -- 00000BFC
+		X"24070014", -- 00000C00
+		X"0C100202", -- 00000C04
+		X"00028040", -- 00000C08
+		X"24070002", -- 00000C0C
+		X"26450008", -- 00000C10
+		X"08100309", -- 00000C14
+		X"24060011", -- 00000C18
+		X"04C0000A", -- 00000C1C
+		X"00000000", -- 00000C20
+		X"8CA20000", -- 00000C24
+		X"8CA3FFFC", -- 00000C28
+		X"8CA4FFF8", -- 00000C2C
+		X"00431023", -- 00000C30
+		X"24C6FFFF", -- 00000C34
+		X"1482FFF8", -- 00000C38
+		X"24A50004", -- 00000C3C
+		X"04C1FFF8", -- 00000C40
+		X"24E70001", -- 00000C44
+		X"24060014", -- 00000C48
+		X"10E6000F", -- 00000C4C
+		X"00000000", -- 00000C50
+		X"2A220003", -- 00000C54
+		X"1440FFDE", -- 00000C58
+		X"02202021", -- 00000C5C
+		X"24020003", -- 00000C60
+		X"1662000B", -- 00000C64
+		X"00001821", -- 00000C68
+		X"8FBF0070", -- 00000C6C
+		X"8FB3006C", -- 00000C70
+		X"8FB20068", -- 00000C74
+		X"8FB10064", -- 00000C78
+		X"8FB00060", -- 00000C7C
+		X"00601021", -- 00000C80
+		X"03E00008", -- 00000C84
+		X"27BD0078", -- 00000C88
+		X"08100315", -- 00000C8C
+		X"26730001", -- 00000C90
+		X"3C028000", -- 00000C94
+		X"34430011", -- 00000C98
+		X"8FBF0070", -- 00000C9C
+		X"8FB3006C", -- 00000CA0
+		X"8FB20068", -- 00000CA4
+		X"8FB10064", -- 00000CA8
+		X"8FB00060", -- 00000CAC
+		X"00601021", -- 00000CB0
+		X"03E00008", -- 00000CB4
+		X"27BD0078", -- 00000CB8
+		X"3C041970", -- 00000CBC
+		X"27BDFFD0", -- 00000CC0
+		X"34841031", -- 00000CC4
+		X"AFB30024", -- 00000CC8
+		X"AFBF0028", -- 00000CCC
+		X"AFB20020", -- 00000CD0
+		X"AFB1001C", -- 00000CD4
+		X"AFB00018", -- 00000CD8
+		X"0C100897", -- 00000CDC
+		X"00009821", -- 00000CE0
+		X"0810033D", -- 00000CE4
+		X"24120001", -- 00000CE8
+		X"10800022", -- 00000CEC
+		X"00000000", -- 00000CF0
+		X"0C10089C", -- 00000CF4
+		X"26520001", -- 00000CF8
+		X"00021C00", -- 00000CFC
+		X"00021200", -- 00000D00
+		X"0C10089C", -- 00000D04
+		X"00438026", -- 00000D08
+		X"0C10089C", -- 00000D0C
+		X"00508826", -- 00000D10
+		X"00021C00", -- 00000D14
+		X"00021200", -- 00000D18
+		X"0C10089C", -- 00000D1C
+		X"00438026", -- 00000D20
+		X"00508026", -- 00000D24
+		X"27A40010", -- 00000D28
+		X"02202821", -- 00000D2C
+		X"0C1003B1", -- 00000D30
+		X"02003021", -- 00000D34
+		X"8FA30010", -- 00000D38
+		X"8FA20014", -- 00000D3C
+		X"00700018", -- 00000D40
+		X"00001812", -- 00000D44
+		X"00431021", -- 00000D48
+		X"1051FFE7", -- 00000D4C
+		X"2A4403E8", -- 00000D50
+		X"3C028000", -- 00000D54
+		X"34420012", -- 00000D58
+		X"8FBF0028", -- 00000D5C
+		X"8FB30024", -- 00000D60
+		X"8FB20020", -- 00000D64
+		X"8FB1001C", -- 00000D68
+		X"8FB00018", -- 00000D6C
+		X"03E00008", -- 00000D70
+		X"27BD0030", -- 00000D74
+		X"26730001", -- 00000D78
+		X"2A620064", -- 00000D7C
+		X"1440FFDC", -- 00000D80
+		X"24120001", -- 00000D84
+		X"08100357", -- 00000D88
+		X"00001021", -- 00000D8C
+		X"27BDFFD0", -- 00000D90
+		X"AFB30024", -- 00000D94
+		X"AFB20020", -- 00000D98
+		X"AFB1001C", -- 00000D9C
+		X"AFBF0028", -- 00000DA0
+		X"0C100218", -- 00000DA4
+		X"AFB00018", -- 00000DA8
+		X"3C023FFF", -- 00000DAC
+		X"3453FFFF", -- 00000DB0
+		X"3C128000", -- 00000DB4
+		X"08100399", -- 00000DB8
+		X"00008821", -- 00000DBC
+		X"0C1002EA", -- 00000DC0
+		X"00000000", -- 00000DC4
+		X"0440002B", -- 00000DC8
+		X"00408021", -- 00000DCC
+		X"0C10032F", -- 00000DD0
+		X"00000000", -- 00000DD4
+		X"3C040000", -- 00000DD8
+		X"24840064", -- 00000DDC
+		X"04400025", -- 00000DE0
+		X"00408021", -- 00000DE4
+		X"0C1001C5", -- 00000DE8
+		X"00000000", -- 00000DEC
+		X"0C1001F2", -- 00000DF0
+		X"02202021", -- 00000DF4
+		X"3C040000", -- 00000DF8
+		X"24840070", -- 00000DFC
+		X"0C1001C5", -- 00000E00
+		X"26310001", -- 00000E04
+		X"0C1008CE", -- 00000E08
+		X"00002021", -- 00000E0C
+		X"27A40010", -- 00000E10
+		X"0C1003D1", -- 00000E14
+		X"AFA20010", -- 00000E18
+		X"80440008", -- 00000E1C
+		X"0C1001D8", -- 00000E20
+		X"00408021", -- 00000E24
+		X"3C040000", -- 00000E28
+		X"0C1001C5", -- 00000E2C
+		X"2484007C", -- 00000E30
+		X"82040004", -- 00000E34
+		X"0C1001D8", -- 00000E38
+		X"00000000", -- 00000E3C
+		X"3C040000", -- 00000E40
+		X"0C1001C5", -- 00000E44
+		X"2484007C", -- 00000E48
+		X"82040000", -- 00000E4C
+		X"0C1001D8", -- 00000E50
+		X"00000000", -- 00000E54
+		X"3C040000", -- 00000E58
+		X"0C1001C5", -- 00000E5C
+		X"24840078", -- 00000E60
+		X"02331024", -- 00000E64
+		X"0C100265", -- 00000E68
+		X"AE420000", -- 00000E6C
+		X"0441FFD3", -- 00000E70
+		X"00408021", -- 00000E74
+		X"3C024000", -- 00000E78
+		X"02221025", -- 00000E7C
+		X"3C040000", -- 00000E80
+		X"24840080", -- 00000E84
+		X"0C1001C5", -- 00000E88
+		X"AE420000", -- 00000E8C
+		X"0C1001F2", -- 00000E90
+		X"02002021", -- 00000E94
+		X"3C040000", -- 00000E98
+		X"0C1001C5", -- 00000E9C
+		X"24840094", -- 00000EA0
+		X"8FBF0028", -- 00000EA4
+		X"8FB30024", -- 00000EA8
+		X"8FB20020", -- 00000EAC
+		X"8FB1001C", -- 00000EB0
+		X"8FB00018", -- 00000EB4
+		X"24020001", -- 00000EB8
+		X"03E00008", -- 00000EBC
+		X"27BD0030", -- 00000EC0
+		X"14C00002", -- 00000EC4
+		X"00A6001A", -- 00000EC8
+		X"0007000D", -- 00000ECC
+		X"27BDFFF8", -- 00000ED0
+		X"00001010", -- 00000ED4
+		X"00001812", -- 00000ED8
+		X"04A0000D", -- 00000EDC
+		X"00803821", -- 00000EE0
+		X"00463023", -- 00000EE4
+		X"0440000D", -- 00000EE8
+		X"24640001", -- 00000EEC
+		X"AFA20004", -- 00000EF0
+		X"AFA30000", -- 00000EF4
+		X"8FA40000", -- 00000EF8
+		X"8FA30004", -- 00000EFC
+		X"00E01021", -- 00000F00
+		X"27BD0008", -- 00000F04
+		X"ACE30004", -- 00000F08
+		X"03E00008", -- 00000F0C
+		X"ACE40000", -- 00000F10
+		X"00463021", -- 00000F14
+		X"1840FFF5", -- 00000F18
+		X"2464FFFF", -- 00000F1C
+		X"AFA40000", -- 00000F20
+		X"AFA60004", -- 00000F24
+		X"8FA40000", -- 00000F28
+		X"8FA30004", -- 00000F2C
+		X"00E01021", -- 00000F30
+		X"27BD0008", -- 00000F34
+		X"ACE30004", -- 00000F38
+		X"03E00008", -- 00000F3C
+		X"ACE40000", -- 00000F40
+		X"8F85096C", -- 00000F44
+		X"081003D4", -- 00000F48
+		X"24A5007C", -- 00000F4C
+		X"081006BE", -- 00000F50
+		X"24060001", -- 00000F54
+		X"00802821", -- 00000F58
+		X"8F84096C", -- 00000F5C
+		X"081003DE", -- 00000F60
+		X"00000000", -- 00000F64
+		X"00802821", -- 00000F68
+		X"8F84096C", -- 00000F6C
+		X"08100938", -- 00000F70
+		X"00000000", -- 00000F74
+		X"24A6000B", -- 00000F78
+		X"27BDFFC8", -- 00000F7C
+		X"2CC20017", -- 00000F80
+		X"AFB20018", -- 00000F84
+		X"AFB10014", -- 00000F88
+		X"AFBF0034", -- 00000F8C
+		X"AFBE0030", -- 00000F90
+		X"AFB7002C", -- 00000F94
+		X"AFB60028", -- 00000F98
+		X"AFB50024", -- 00000F9C
+		X"AFB40020", -- 00000FA0
+		X"AFB3001C", -- 00000FA4
+		X"AFB00010", -- 00000FA8
+		X"00809021", -- 00000FAC
+		X"14400005", -- 00000FB0
+		X"24110010", -- 00000FB4
+		X"2402FFF8", -- 00000FB8
+		X"00C28824", -- 00000FBC
+		X"06200004", -- 00000FC0
+		X"2402000C", -- 00000FC4
+		X"0225102B", -- 00000FC8
+		X"10400010", -- 00000FCC
+		X"2402000C", -- 00000FD0
+		X"00001821", -- 00000FD4
+		X"AE420000", -- 00000FD8
+		X"8FBF0034", -- 00000FDC
+		X"8FBE0030", -- 00000FE0
+		X"8FB7002C", -- 00000FE4
+		X"8FB60028", -- 00000FE8
+		X"8FB50024", -- 00000FEC
+		X"8FB40020", -- 00000FF0
+		X"8FB3001C", -- 00000FF4
+		X"8FB20018", -- 00000FF8
+		X"8FB10014", -- 00000FFC
+		X"8FB00010", -- 00001000
+		X"00601021", -- 00001004
+		X"03E00008", -- 00001008
+		X"27BD0038", -- 0000100C
+		X"0C100893", -- 00001010
+		X"02402021", -- 00001014
+		X"2E2201F8", -- 00001018
+		X"10400024", -- 0000101C
+		X"00111A42", -- 00001020
+		X"3C020000", -- 00001024
+		X"24420520", -- 00001028
+		X"02223021", -- 0000102C
+		X"8CD0000C", -- 00001030
+		X"00000000", -- 00001034
+		X"12060059", -- 00001038
+		X"001140C2", -- 0000103C
+		X"8E030004", -- 00001040
+		X"2402FFFC", -- 00001044
+		X"00622024", -- 00001048
+		X"02042021", -- 0000104C
+		X"8C820004", -- 00001050
+		X"8E07000C", -- 00001054
+		X"8E060008", -- 00001058
+		X"34420001", -- 0000105C
+		X"ACE60008", -- 00001060
+		X"AC820004", -- 00001064
+		X"ACC7000C", -- 00001068
+		X"02402021", -- 0000106C
+		X"0C100895", -- 00001070
+		X"00000000", -- 00001074
+		X"26030008", -- 00001078
+		X"8FBF0034", -- 0000107C
+		X"8FBE0030", -- 00001080
+		X"8FB7002C", -- 00001084
+		X"8FB60028", -- 00001088
+		X"8FB50024", -- 0000108C
+		X"8FB40020", -- 00001090
+		X"8FB3001C", -- 00001094
+		X"8FB20018", -- 00001098
+		X"8FB10014", -- 0000109C
+		X"8FB00010", -- 000010A0
+		X"00601021", -- 000010A4
+		X"03E00008", -- 000010A8
+		X"27BD0038", -- 000010AC
+		X"1060000C", -- 000010B0
+		X"001140C2", -- 000010B4
+		X"2C620005", -- 000010B8
+		X"1440003F", -- 000010BC
+		X"00111182", -- 000010C0
+		X"2C620015", -- 000010C4
+		X"14400006", -- 000010C8
+		X"2468005B", -- 000010CC
+		X"2C620055", -- 000010D0
+		X"10400162", -- 000010D4
+		X"2C620155", -- 000010D8
+		X"00111302", -- 000010DC
+		X"2448006E", -- 000010E0
+		X"000810C0", -- 000010E4
+		X"3C040000", -- 000010E8
+		X"24840520", -- 000010EC
+		X"00441821", -- 000010F0
+		X"8C70000C", -- 000010F4
+		X"00000000", -- 000010F8
+		X"1203000F", -- 000010FC
+		X"00000000", -- 00001100
+		X"2406FFFC", -- 00001104
+		X"8E020004", -- 00001108
+		X"00000000", -- 0000110C
+		X"00462024", -- 00001110
+		X"00912823", -- 00001114
+		X"28A20010", -- 00001118
+		X"10400102", -- 0000111C
+		X"00000000", -- 00001120
+		X"04A10102", -- 00001124
+		X"00000000", -- 00001128
+		X"8E10000C", -- 0000112C
+		X"00000000", -- 00001130
+		X"1603FFF4", -- 00001134
+		X"00000000", -- 00001138
+		X"25080001", -- 0000113C
+		X"3C100000", -- 00001140
+		X"8E100530", -- 00001144
+		X"3C0C0000", -- 00001148
+		X"258C0528", -- 0000114C
+		X"120C0032", -- 00001150
+		X"2403FFFC", -- 00001154
+		X"8E020004", -- 00001158
+		X"00000000", -- 0000115C
+		X"00432024", -- 00001160
+		X"00912823", -- 00001164
+		X"28A20010", -- 00001168
+		X"10400073", -- 0000116C
+		X"00000000", -- 00001170
+		X"AD8C000C", -- 00001174
+		X"04A00012", -- 00001178
+		X"AD8C0008", -- 0000117C
+		X"02041821", -- 00001180
+		X"8C620004", -- 00001184
+		X"02402021", -- 00001188
+		X"34420001", -- 0000118C
+		X"0C100895", -- 00001190
+		X"AC620004", -- 00001194
+		X"0810041F", -- 00001198
+		X"26030008", -- 0000119C
+		X"26060008", -- 000011A0
+		X"8CD0000C", -- 000011A4
+		X"00000000", -- 000011A8
+		X"1606FFA4", -- 000011AC
+		X"25080002", -- 000011B0
+		X"08100450", -- 000011B4
+		X"00000000", -- 000011B8
+		X"08100439", -- 000011BC
+		X"24480038", -- 000011C0
+		X"2C820200", -- 000011C4
+		X"104000E2", -- 000011C8
+		X"00042A42", -- 000011CC
+		X"000418C2", -- 000011D0
+		X"3C050000", -- 000011D4
+		X"24A50520", -- 000011D8
+		X"04600155", -- 000011DC
+		X"00602021", -- 000011E0
+		X"000310C0", -- 000011E4
+		X"00453821", -- 000011E8
+		X"00042083", -- 000011EC
+		X"3C020000", -- 000011F0
+		X"8C420524", -- 000011F4
+		X"24030001", -- 000011F8
+		X"8CE60008", -- 000011FC
+		X"00831804", -- 00001200
+		X"00431025", -- 00001204
+		X"AE07000C", -- 00001208
+		X"AE060008", -- 0000120C
+		X"ACA20004", -- 00001210
+		X"ACD0000C", -- 00001214
+		X"ACF00008", -- 00001218
+		X"0500010E", -- 0000121C
+		X"01001021", -- 00001220
+		X"00021083", -- 00001224
+		X"3C0A0000", -- 00001228
+		X"8D4A0524", -- 0000122C
+		X"24030001", -- 00001230
+		X"00433804", -- 00001234
+		X"0147202B", -- 00001238
+		X"1480004C", -- 0000123C
+		X"01471024", -- 00001240
+		X"1440000A", -- 00001244
+		X"2402FFFC", -- 00001248
+		X"00073840", -- 0000124C
+		X"01021024", -- 00001250
+		X"01471824", -- 00001254
+		X"14600005", -- 00001258
+		X"24480004", -- 0000125C
+		X"00073840", -- 00001260
+		X"01471024", -- 00001264
+		X"1040FFFD", -- 00001268
+		X"25080004", -- 0000126C
+		X"3C030000", -- 00001270
+		X"24630520", -- 00001274
+		X"000810C0", -- 00001278
+		X"00433021", -- 0000127C
+		X"01005821", -- 00001280
+		X"00C01821", -- 00001284
+		X"8C70000C", -- 00001288
+		X"00000000", -- 0000128C
+		X"1203000F", -- 00001290
+		X"00000000", -- 00001294
+		X"2409FFFC", -- 00001298
+		X"8E020004", -- 0000129C
+		X"00000000", -- 000012A0
+		X"00492024", -- 000012A4
+		X"00912823", -- 000012A8
+		X"28A20010", -- 000012AC
+		X"104000CD", -- 000012B0
+		X"00000000", -- 000012B4
+		X"04A100DE", -- 000012B8
+		X"00000000", -- 000012BC
+		X"8E10000C", -- 000012C0
+		X"00000000", -- 000012C4
+		X"1603FFF4", -- 000012C8
+		X"00000000", -- 000012CC
+		X"25080001", -- 000012D0
+		X"31020003", -- 000012D4
+		X"1440FFEB", -- 000012D8
+		X"24630008", -- 000012DC
+		X"31620003", -- 000012E0
+		X"24C6FFF8", -- 000012E4
+		X"10400132", -- 000012E8
+		X"256BFFFF", -- 000012EC
+		X"8CC20008", -- 000012F0
+		X"00000000", -- 000012F4
+		X"1046FFFA", -- 000012F8
+		X"31620003", -- 000012FC
+		X"00073840", -- 00001300
+		X"0147102B", -- 00001304
+		X"14400019", -- 00001308
+		X"00000000", -- 0000130C
+		X"10E00017", -- 00001310
+		X"01471024", -- 00001314
+		X"081004CB", -- 00001318
+		X"00000000", -- 0000131C
+		X"00073840", -- 00001320
+		X"01471024", -- 00001324
+		X"25080004", -- 00001328
+		X"1040FFFC", -- 0000132C
+		X"00000000", -- 00001330
+		X"0810049C", -- 00001334
+		X"00000000", -- 00001338
+		X"02114021", -- 0000133C
+		X"34A40001", -- 00001340
+		X"36230001", -- 00001344
+		X"01051021", -- 00001348
+		X"AE030004", -- 0000134C
+		X"AD040004", -- 00001350
+		X"02402021", -- 00001354
+		X"AD88000C", -- 00001358
+		X"AD880008", -- 0000135C
+		X"AC450000", -- 00001360
+		X"AD0C0008", -- 00001364
+		X"0810041C", -- 00001368
+		X"AD0C000C", -- 0000136C
+		X"3C130000", -- 00001370
+		X"8E730528", -- 00001374
+		X"2403FFFC", -- 00001378
+		X"8E620004", -- 0000137C
+		X"00000000", -- 00001380
+		X"0043B024", -- 00001384
+		X"02D1202B", -- 00001388
+		X"14800004", -- 0000138C
+		X"02D12823", -- 00001390
+		X"28A20010", -- 00001394
+		X"10400028", -- 00001398
+		X"02712021", -- 0000139C
+		X"8F820994", -- 000013A0
+		X"241EFFFF", -- 000013A4
+		X"02221821", -- 000013A8
+		X"8F820970", -- 000013AC
+		X"02C0B821", -- 000013B0
+		X"0276A021", -- 000013B4
+		X"105E0004", -- 000013B8
+		X"24750010", -- 000013BC
+		X"2463100F", -- 000013C0
+		X"2402F000", -- 000013C4
+		X"0062A824", -- 000013C8
+		X"02402021", -- 000013CC
+		X"0C1008B8", -- 000013D0
+		X"02A02821", -- 000013D4
+		X"105E0008", -- 000013D8
+		X"00408021", -- 000013DC
+		X"0054102B", -- 000013E0
+		X"1040001F", -- 000013E4
+		X"00000000", -- 000013E8
+		X"3C020000", -- 000013EC
+		X"24420520", -- 000013F0
+		X"1262001B", -- 000013F4
+		X"00000000", -- 000013F8
+		X"3C130000", -- 000013FC
+		X"8E730528", -- 00001400
+		X"00000000", -- 00001404
+		X"8E620004", -- 00001408
+		X"2403FFFC", -- 0000140C
+		X"00431024", -- 00001410
+		X"0051202B", -- 00001414
+		X"14800004", -- 00001418
+		X"00512823", -- 0000141C
+		X"28A20010", -- 00001420
+		X"10400005", -- 00001424
+		X"02712021", -- 00001428
+		X"0C100895", -- 0000142C
+		X"02402021", -- 00001430
+		X"081003F7", -- 00001434
+		X"00001821", -- 00001438
+		X"34A30001", -- 0000143C
+		X"36220001", -- 00001440
+		X"AE620004", -- 00001444
+		X"3C010000", -- 00001448
+		X"AC240528", -- 0000144C
+		X"AC830004", -- 00001450
+		X"0C100895", -- 00001454
+		X"02402021", -- 00001458
+		X"081003F7", -- 0000145C
+		X"26630008", -- 00001460
+		X"3C020000", -- 00001464
+		X"8C420AF4", -- 00001468
+		X"121400C7", -- 0000146C
+		X"00552021", -- 00001470
+		X"8F830970", -- 00001474
+		X"2402FFFF", -- 00001478
+		X"106200BF", -- 0000147C
+		X"02141023", -- 00001480
+		X"00821021", -- 00001484
+		X"3C010000", -- 00001488
+		X"AC220AF4", -- 0000148C
+		X"32030007", -- 00001490
+		X"10600004", -- 00001494
+		X"0000A021", -- 00001498
+		X"24020008", -- 0000149C
+		X"0043A023", -- 000014A0
+		X"02148021", -- 000014A4
+		X"02151021", -- 000014A8
+		X"30420FFF", -- 000014AC
+		X"24031000", -- 000014B0
+		X"00621823", -- 000014B4
+		X"0283A021", -- 000014B8
+		X"02402021", -- 000014BC
+		X"0C1008B8", -- 000014C0
+		X"02802821", -- 000014C4
+		X"00401821", -- 000014C8
+		X"2402FFFF", -- 000014CC
+		X"106200C2", -- 000014D0
+		X"00000000", -- 000014D4
+		X"3C020000", -- 000014D8
+		X"8C420AF4", -- 000014DC
+		X"00701823", -- 000014E0
+		X"00741821", -- 000014E4
+		X"00541021", -- 000014E8
+		X"3C040000", -- 000014EC
+		X"24840520", -- 000014F0
+		X"3C010000", -- 000014F4
+		X"AC220AF4", -- 000014F8
+		X"3C010000", -- 000014FC
+		X"AC300528", -- 00001500
+		X"126400B1", -- 00001504
+		X"34650001", -- 00001508
+		X"2EC20010", -- 0000150C
+		X"10400065", -- 00001510
+		X"26C3FFF4", -- 00001514
+		X"24020001", -- 00001518
+		X"02009821", -- 0000151C
+		X"08100502", -- 00001520
+		X"AE020004", -- 00001524
+		X"0810044F", -- 00001528
+		X"2508FFFF", -- 0000152C
+		X"02041821", -- 00001530
+		X"8C620004", -- 00001534
+		X"8E07000C", -- 00001538
+		X"8E060008", -- 0000153C
+		X"34420001", -- 00001540
+		X"ACE60008", -- 00001544
+		X"AC620004", -- 00001548
+		X"0810041B", -- 0000154C
+		X"ACC7000C", -- 00001550
+		X"10A00006", -- 00001554
+		X"000418C2", -- 00001558
+		X"2CA20005", -- 0000155C
+		X"10400049", -- 00001560
+		X"2CA20015", -- 00001564
+		X"00041182", -- 00001568
+		X"24430038", -- 0000156C
+		X"000310C0", -- 00001570
+		X"3C050000", -- 00001574
+		X"24A50520", -- 00001578
+		X"00453821", -- 0000157C
+		X"8CE60008", -- 00001580
+		X"00000000", -- 00001584
+		X"10C7006C", -- 00001588
+		X"00000000", -- 0000158C
+		X"8CC20004", -- 00001590
+		X"2403FFFC", -- 00001594
+		X"00431024", -- 00001598
+		X"0082102B", -- 0000159C
+		X"1040000B", -- 000015A0
+		X"00000000", -- 000015A4
+		X"8CC60008", -- 000015A8
+		X"00000000", -- 000015AC
+		X"10C70007", -- 000015B0
+		X"00000000", -- 000015B4
+		X"8CC20004", -- 000015B8
+		X"00000000", -- 000015BC
+		X"00431024", -- 000015C0
+		X"0082102B", -- 000015C4
+		X"1440FFF7", -- 000015C8
+		X"00000000", -- 000015CC
+		X"8CC7000C", -- 000015D0
+		X"AE060008", -- 000015D4
+		X"AE07000C", -- 000015D8
+		X"ACF00008", -- 000015DC
+		X"08100487", -- 000015E0
+		X"ACD0000C", -- 000015E4
+		X"02114021", -- 000015E8
+		X"8E07000C", -- 000015EC
+		X"8E060008", -- 000015F0
+		X"36230001", -- 000015F4
+		X"34A40001", -- 000015F8
+		X"01051021", -- 000015FC
+		X"ACE60008", -- 00001600
+		X"AE030004", -- 00001604
+		X"ACC7000C", -- 00001608
+		X"AD040004", -- 0000160C
+		X"AD880008", -- 00001610
+		X"AD88000C", -- 00001614
+		X"AC450000", -- 00001618
+		X"AD0C0008", -- 0000161C
+		X"02402021", -- 00001620
+		X"0C100895", -- 00001624
+		X"AD0C000C", -- 00001628
+		X"0810041F", -- 0000162C
+		X"26030008", -- 00001630
+		X"02041821", -- 00001634
+		X"8C620004", -- 00001638
+		X"8E07000C", -- 0000163C
+		X"8E060008", -- 00001640
+		X"34420001", -- 00001644
+		X"AC620004", -- 00001648
+		X"ACE60008", -- 0000164C
+		X"0810041B", -- 00001650
+		X"ACC7000C", -- 00001654
+		X"08100489", -- 00001658
+		X"25020003", -- 0000165C
+		X"10400004", -- 00001660
+		X"2C620555", -- 00001664
+		X"001113C2", -- 00001668
+		X"08100439", -- 0000166C
+		X"24480077", -- 00001670
+		X"1040FE9B", -- 00001674
+		X"2408007E", -- 00001678
+		X"00111482", -- 0000167C
+		X"08100439", -- 00001680
+		X"2448007C", -- 00001684
+		X"1440FFB9", -- 00001688
+		X"24A3005B", -- 0000168C
+		X"2CA20055", -- 00001690
+		X"10400054", -- 00001694
+		X"2CA20155", -- 00001698
+		X"00041302", -- 0000169C
+		X"0810055C", -- 000016A0
+		X"2443006E", -- 000016A4
+		X"2402FFF8", -- 000016A8
+		X"0062B824", -- 000016AC
+		X"02772021", -- 000016B0
+		X"24030005", -- 000016B4
+		X"AE050004", -- 000016B8
+		X"AC830008", -- 000016BC
+		X"AC830004", -- 000016C0
+		X"8E620004", -- 000016C4
+		X"2EE30010", -- 000016C8
+		X"30420001", -- 000016CC
+		X"00571025", -- 000016D0
+		X"10600012", -- 000016D4
+		X"AE620004", -- 000016D8
+		X"3C130000", -- 000016DC
+		X"8E730528", -- 000016E0
+		X"3C030000", -- 000016E4
+		X"8C630AF4", -- 000016E8
+		X"8F820990", -- 000016EC
+		X"00000000", -- 000016F0
+		X"0043102B", -- 000016F4
+		X"10400002", -- 000016F8
+		X"00000000", -- 000016FC
+		X"AF830990", -- 00001700
+		X"8F82098C", -- 00001704
+		X"00000000", -- 00001708
+		X"0043102B", -- 0000170C
+		X"1040FF3D", -- 00001710
+		X"00000000", -- 00001714
+		X"08100502", -- 00001718
+		X"AF83098C", -- 0000171C
+		X"26650008", -- 00001720
+		X"0C100938", -- 00001724
+		X"02402021", -- 00001728
+		X"081005B7", -- 0000172C
+		X"00000000", -- 00001730
+		X"08100479", -- 00001734
+		X"24640003", -- 00001738
+		X"0460002F", -- 0000173C
+		X"00601021", -- 00001740
+		X"00021083", -- 00001744
+		X"3C040000", -- 00001748
+		X"8C840524", -- 0000174C
+		X"24030001", -- 00001750
+		X"00431804", -- 00001754
+		X"00832025", -- 00001758
+		X"3C020000", -- 0000175C
+		X"24420520", -- 00001760
+		X"AE07000C", -- 00001764
+		X"AE060008", -- 00001768
+		X"AC440004", -- 0000176C
+		X"ACD0000C", -- 00001770
+		X"08100487", -- 00001774
+		X"ACF00008", -- 00001778
+		X"3C010000", -- 0000177C
+		X"AC240AF4", -- 00001780
+		X"08100524", -- 00001784
+		X"AF900970", -- 00001788
+		X"32020FFF", -- 0000178C
+		X"1440FF38", -- 00001790
+		X"02B71821", -- 00001794
+		X"3C130000", -- 00001798
+		X"8E730528", -- 0000179C
+		X"34620001", -- 000017A0
+		X"3C010000", -- 000017A4
+		X"AC240AF4", -- 000017A8
+		X"081005B9", -- 000017AC
+		X"AE620004", -- 000017B0
+		X"00071027", -- 000017B4
+		X"01421024", -- 000017B8
+		X"3C010000", -- 000017BC
+		X"AC220524", -- 000017C0
+		X"081004C0", -- 000017C4
+		X"00405021", -- 000017C8
+		X"3C130000", -- 000017CC
+		X"8E730528", -- 000017D0
+		X"081005B9", -- 000017D4
+		X"AE050004", -- 000017D8
+		X"0000A021", -- 000017DC
+		X"08100536", -- 000017E0
+		X"02001821", -- 000017E4
+		X"10400006", -- 000017E8
+		X"2CA20555", -- 000017EC
+		X"000413C2", -- 000017F0
+		X"0810055C", -- 000017F4
+		X"24430077", -- 000017F8
+		X"081005D1", -- 000017FC
+		X"24620003", -- 00001800
+		X"1040FF5A", -- 00001804
+		X"2403007E", -- 00001808
+		X"00041482", -- 0000180C
+		X"0810055C", -- 00001810
+		X"2443007C", -- 00001814
+		X"27BDFFE8", -- 00001818
+		X"AFB00010", -- 0000181C
+		X"AFBF0014", -- 00001820
+		X"0C100A23", -- 00001824
+		X"00808021", -- 00001828
+		X"00405821", -- 0000182C
+		X"2A0207B2", -- 00001830
+		X"14400086", -- 00001834
+		X"00002021", -- 00001838
+		X"2602F84E", -- 0000183C
+		X"000218C0", -- 00001840
+		X"00621821", -- 00001844
+		X"000318C0", -- 00001848
+		X"00621821", -- 0000184C
+		X"00032080", -- 00001850
+		X"2606F84F", -- 00001854
+		X"00641021", -- 00001858
+		X"04C000A2", -- 0000185C
+		X"AD700004", -- 00001860
+		X"3C0451EB", -- 00001864
+		X"3484851F", -- 00001868
+		X"2607F893", -- 0000186C
+		X"00E40018", -- 00001870
+		X"2603F9BF", -- 00001874
+		X"000347C3", -- 00001878
+		X"00063083", -- 0000187C
+		X"00073FC3", -- 00001880
+		X"00463021", -- 00001884
+		X"3C029249", -- 00001888
+		X"34592493", -- 0000188C
+		X"320E0003", -- 00001890
+		X"01604821", -- 00001894
+		X"240C0001", -- 00001898
+		X"00002810", -- 0000189C
+		X"00052943", -- 000018A0
+		X"00A72823", -- 000018A4
+		X"00640018", -- 000018A8
+		X"00C53023", -- 000018AC
+		X"00001810", -- 000018B0
+		X"000319C3", -- 000018B4
+		X"00681823", -- 000018B8
+		X"02040018", -- 000018BC
+		X"00C36821", -- 000018C0
+		X"00002010", -- 000018C4
+		X"000479C3", -- 000018C8
+		X"0004C143", -- 000018CC
+		X"81230008", -- 000018D0
+		X"2402004A", -- 000018D4
+		X"10620062", -- 000018D8
+		X"24020044", -- 000018DC
+		X"10620044", -- 000018E0
+		X"00002021", -- 000018E4
+		X"15C00009", -- 000018E8
+		X"00102FC3", -- 000018EC
+		X"03051823", -- 000018F0
+		X"00031040", -- 000018F4
+		X"00431021", -- 000018F8
+		X"000210C0", -- 000018FC
+		X"00431021", -- 00001900
+		X"00021080", -- 00001904
+		X"1602006B", -- 00001908
+		X"00000000", -- 0000190C
+		X"01E51823", -- 00001910
+		X"00031040", -- 00001914
+		X"00431021", -- 00001918
+		X"000210C0", -- 0000191C
+		X"00431021", -- 00001920
+		X"00021100", -- 00001924
+		X"12020063", -- 00001928
+		X"00000000", -- 0000192C
+		X"00041040", -- 00001930
+		X"8D25000C", -- 00001934
+		X"00441021", -- 00001938
+		X"24080001", -- 0000193C
+		X"00021100", -- 00001940
+		X"3C030000", -- 00001944
+		X"246300B8", -- 00001948
+		X"0105202A", -- 0000194C
+		X"00435021", -- 00001950
+		X"10800008", -- 00001954
+		X"01A03821", -- 00001958
+		X"01402021", -- 0000195C
+		X"8C820000", -- 00001960
+		X"25080001", -- 00001964
+		X"0105182A", -- 00001968
+		X"00E23821", -- 0000196C
+		X"1460FFFB", -- 00001970
+		X"24840004", -- 00001974
+		X"24E40004", -- 00001978
+		X"00990018", -- 0000197C
+		X"00042FC3", -- 00001980
+		X"8D260014", -- 00001984
+		X"00001810", -- 00001988
+		X"00641821", -- 0000198C
+		X"00031883", -- 00001990
+		X"00651823", -- 00001994
+		X"000310C0", -- 00001998
+		X"00431023", -- 0000199C
+		X"00821823", -- 000019A0
+		X"00C33023", -- 000019A4
+		X"04C00051", -- 000019A8
+		X"00000000", -- 000019AC
+		X"8D240010", -- 000019B0
+		X"00081880", -- 000019B4
+		X"000410C0", -- 000019B8
+		X"00441023", -- 000019BC
+		X"006A1821", -- 000019C0
+		X"00461021", -- 000019C4
+		X"8C65FFFC", -- 000019C8
+		X"2444FFF9", -- 000019CC
+		X"0085182A", -- 000019D0
+		X"14600005", -- 000019D4
+		X"00000000", -- 000019D8
+		X"2484FFF9", -- 000019DC
+		X"0085102A", -- 000019E0
+		X"1040FFFD", -- 000019E4
+		X"00000000", -- 000019E8
+		X"08100680", -- 000019EC
+		X"00E43821", -- 000019F0
+		X"8D220014", -- 000019F4
+		X"00000000", -- 000019F8
+		X"004D3821", -- 000019FC
+		X"00071840", -- 00001A00
+		X"00671821", -- 00001A04
+		X"00032100", -- 00001A08
+		X"00832023", -- 00001A0C
+		X"00041100", -- 00001A10
+		X"8D250018", -- 00001A14
+		X"00441023", -- 00001A18
+		X"8D230020", -- 00001A1C
+		X"000211C0", -- 00001A20
+		X"00451021", -- 00001A24
+		X"00431021", -- 00001A28
+		X"258CFFFF", -- 00001A2C
+		X"AD22001C", -- 00001A30
+		X"0581FFA6", -- 00001A34
+		X"2529001C", -- 00001A38
+		X"8D62001C", -- 00001A3C
+		X"8D630038", -- 00001A40
+		X"24040001", -- 00001A44
+		X"0043102A", -- 00001A48
+		X"AD620000", -- 00001A4C
+		X"8FBF0014", -- 00001A50
+		X"8FB00010", -- 00001A54
+		X"00801021", -- 00001A58
+		X"03E00008", -- 00001A5C
+		X"27BD0018", -- 00001A60
+		X"8D220014", -- 00001A64
+		X"00003021", -- 00001A68
+		X"004D2021", -- 00001A6C
+		X"11C00013", -- 00001A70
+		X"00102FC3", -- 00001A74
+		X"01E51823", -- 00001A78
+		X"00031040", -- 00001A7C
+		X"00431021", -- 00001A80
+		X"000210C0", -- 00001A84
+		X"00431021", -- 00001A88
+		X"00021100", -- 00001A8C
+		X"1602FFDB", -- 00001A90
+		X"00863821", -- 00001A94
+		X"8D220014", -- 00001A98
+		X"00000000", -- 00001A9C
+		X"2842003C", -- 00001AA0
+		X"14400002", -- 00001AA4
+		X"00000000", -- 00001AA8
+		X"24060001", -- 00001AAC
+		X"08100680", -- 00001AB0
+		X"00863821", -- 00001AB4
+		X"0810064C", -- 00001AB8
+		X"24040001", -- 00001ABC
+		X"03051823", -- 00001AC0
+		X"00031040", -- 00001AC4
+		X"00431021", -- 00001AC8
+		X"000210C0", -- 00001ACC
+		X"00431021", -- 00001AD0
+		X"00021080", -- 00001AD4
+		X"1602FFEF", -- 00001AD8
+		X"01E51823", -- 00001ADC
+		X"081006A0", -- 00001AE0
+		X"00031040", -- 00001AE4
+		X"08100619", -- 00001AE8
+		X"2606F852", -- 00001AEC
+		X"0810066C", -- 00001AF0
+		X"24C60007", -- 00001AF4
+		X"27BDFFD0", -- 00001AF8
+		X"AFB50024", -- 00001AFC
+		X"AFB40020", -- 00001B00
+		X"AFB3001C", -- 00001B04
+		X"0080A021", -- 00001B08
+		X"AFB10014", -- 00001B0C
+		X"AFBF0028", -- 00001B10
+		X"00A08821", -- 00001B14
+		X"AFB20018", -- 00001B18
+		X"AFB00010", -- 00001B1C
+		X"0C100A23", -- 00001B20
+		X"00C0A821", -- 00001B24
+		X"00409821", -- 00001B28
+		X"8E850000", -- 00001B2C
+		X"3C02C22E", -- 00001B30
+		X"34424507", -- 00001B34
+		X"00A20018", -- 00001B38
+		X"000527C3", -- 00001B3C
+		X"00001010", -- 00001B40
+		X"00451021", -- 00001B44
+		X"00021403", -- 00001B48
+		X"00444823", -- 00001B4C
+		X"00091840", -- 00001B50
+		X"00691821", -- 00001B54
+		X"00032100", -- 00001B58
+		X"00832023", -- 00001B5C
+		X"00041100", -- 00001B60
+		X"00441023", -- 00001B64
+		X"000211C0", -- 00001B68
+		X"00A24023", -- 00001B6C
+		X"05000091", -- 00001B70
+		X"3C020001", -- 00001B74
+		X"3445517F", -- 00001B78
+		X"00A8182A", -- 00001B7C
+		X"10600007", -- 00001B80
+		X"3C02FFFE", -- 00001B84
+		X"3444AE80", -- 00001B88
+		X"00A01821", -- 00001B8C
+		X"01044021", -- 00001B90
+		X"0068102A", -- 00001B94
+		X"1440FFFD", -- 00001B98
+		X"25290001", -- 00001B9C
+		X"3C0391A2", -- 00001BA0
+		X"3463B3C5", -- 00001BA4
+		X"01030018", -- 00001BA8
+		X"000827C3", -- 00001BAC
+		X"25250004", -- 00001BB0
+		X"00053FC3", -- 00001BB4
+		X"00001810", -- 00001BB8
+		X"00681821", -- 00001BBC
+		X"00031AC3", -- 00001BC0
+		X"00642023", -- 00001BC4
+		X"000410C0", -- 00001BC8
+		X"00441023", -- 00001BCC
+		X"00021140", -- 00001BD0
+		X"00441021", -- 00001BD4
+		X"00021100", -- 00001BD8
+		X"3C038888", -- 00001BDC
+		X"01024023", -- 00001BE0
+		X"34638889", -- 00001BE4
+		X"01030018", -- 00001BE8
+		X"AE240008", -- 00001BEC
+		X"3C049249", -- 00001BF0
+		X"34842493", -- 00001BF4
+		X"000837C3", -- 00001BF8
+		X"00001810", -- 00001BFC
+		X"00681821", -- 00001C00
+		X"00031943", -- 00001C04
+		X"00A40018", -- 00001C08
+		X"00661823", -- 00001C0C
+		X"00031100", -- 00001C10
+		X"00431023", -- 00001C14
+		X"00021080", -- 00001C18
+		X"01021023", -- 00001C1C
+		X"AE220000", -- 00001C20
+		X"00002010", -- 00001C24
+		X"00852021", -- 00001C28
+		X"00042083", -- 00001C2C
+		X"00872023", -- 00001C30
+		X"000410C0", -- 00001C34
+		X"00441023", -- 00001C38
+		X"00A22823", -- 00001C3C
+		X"04A0008B", -- 00001C40
+		X"AE230004", -- 00001C44
+		X"AE250018", -- 00001C48
+		X"05200060", -- 00001C4C
+		X"241007B2", -- 00001C50
+		X"27860978", -- 00001C54
+		X"32020003", -- 00001C58
+		X"001027C3", -- 00001C5C
+		X"1440000E", -- 00001C60
+		X"00002821", -- 00001C64
+		X"3C0351EB", -- 00001C68
+		X"3463851F", -- 00001C6C
+		X"02030018", -- 00001C70
+		X"00001810", -- 00001C74
+		X"00031943", -- 00001C78
+		X"00641823", -- 00001C7C
+		X"00031040", -- 00001C80
+		X"00431021", -- 00001C84
+		X"000210C0", -- 00001C88
+		X"00431021", -- 00001C8C
+		X"00021080", -- 00001C90
+		X"16020017", -- 00001C94
+		X"00000000", -- 00001C98
+		X"3C0351EB", -- 00001C9C
+		X"3463851F", -- 00001CA0
+		X"02030018", -- 00001CA4
+		X"00001810", -- 00001CA8
+		X"000319C3", -- 00001CAC
+		X"00641823", -- 00001CB0
+		X"00031040", -- 00001CB4
+		X"00431021", -- 00001CB8
+		X"000210C0", -- 00001CBC
+		X"00431021", -- 00001CC0
+		X"00021100", -- 00001CC4
+		X"1202000A", -- 00001CC8
+		X"00051080", -- 00001CCC
+		X"00461021", -- 00001CD0
+		X"8C420000", -- 00001CD4
+		X"00000000", -- 00001CD8
+		X"0122182A", -- 00001CDC
+		X"1460000D", -- 00001CE0
+		X"00000000", -- 00001CE4
+		X"01224823", -- 00001CE8
+		X"08100716", -- 00001CEC
+		X"26100001", -- 00001CF0
+		X"24050001", -- 00001CF4
+		X"00051080", -- 00001CF8
+		X"00461021", -- 00001CFC
+		X"8C420000", -- 00001D00
+		X"00000000", -- 00001D04
+		X"0122182A", -- 00001D08
+		X"1060FFF7", -- 00001D0C
+		X"01224823", -- 00001D10
+		X"01224821", -- 00001D14
+		X"00051040", -- 00001D18
+		X"00451021", -- 00001D1C
+		X"00021100", -- 00001D20
+		X"2603F894", -- 00001D24
+		X"3C040000", -- 00001D28
+		X"248400B8", -- 00001D2C
+		X"AE230014", -- 00001D30
+		X"00449021", -- 00001D34
+		X"AE29001C", -- 00001D38
+		X"AE200010", -- 00001D3C
+		X"8E420000", -- 00001D40
+		X"0810075F", -- 00001D44
+		X"0122102A", -- 00001D48
+		X"8E220010", -- 00001D4C
+		X"00000000", -- 00001D50
+		X"24440001", -- 00001D54
+		X"00021080", -- 00001D58
+		X"00521021", -- 00001D5C
+		X"00041880", -- 00001D60
+		X"8C450000", -- 00001D64
+		X"00721821", -- 00001D68
+		X"AE240010", -- 00001D6C
+		X"8C620000", -- 00001D70
+		X"01254823", -- 00001D74
+		X"0122102A", -- 00001D78
+		X"1040FFF3", -- 00001D7C
+		X"25220001", -- 00001D80
+		X"12A0003D", -- 00001D84
+		X"AE22000C", -- 00001D88
+		X"02201021", -- 00001D8C
+		X"AE200020", -- 00001D90
+		X"8FBF0028", -- 00001D94
+		X"8FB50024", -- 00001D98
+		X"8FB40020", -- 00001D9C
+		X"8FB3001C", -- 00001DA0
+		X"8FB20018", -- 00001DA4
+		X"8FB10014", -- 00001DA8
+		X"8FB00010", -- 00001DAC
+		X"03E00008", -- 00001DB0
+		X"27BD0030", -- 00001DB4
+		X"34425180", -- 00001DB8
+		X"01024021", -- 00001DBC
+		X"0500FFFE", -- 00001DC0
+		X"2529FFFF", -- 00001DC4
+		X"081006DE", -- 00001DC8
+		X"3C020001", -- 00001DCC
+		X"3C0251EB", -- 00001DD0
+		X"3447851F", -- 00001DD4
+		X"27860978", -- 00001DD8
+		X"2610FFFF", -- 00001DDC
+		X"32020003", -- 00001DE0
+		X"00002821", -- 00001DE4
+		X"1440000C", -- 00001DE8
+		X"001027C3", -- 00001DEC
+		X"02070018", -- 00001DF0
+		X"00001810", -- 00001DF4
+		X"00031943", -- 00001DF8
+		X"00641823", -- 00001DFC
+		X"00031040", -- 00001E00
+		X"00431021", -- 00001E04
+		X"000210C0", -- 00001E08
+		X"00431021", -- 00001E0C
+		X"00021080", -- 00001E10
+		X"1602000C", -- 00001E14
+		X"00000000", -- 00001E18
+		X"02070018", -- 00001E1C
+		X"00001810", -- 00001E20
+		X"000319C3", -- 00001E24
+		X"00641823", -- 00001E28
+		X"00031040", -- 00001E2C
+		X"00431021", -- 00001E30
+		X"000210C0", -- 00001E34
+		X"00431021", -- 00001E38
+		X"00021100", -- 00001E3C
+		X"16020003", -- 00001E40
+		X"00051080", -- 00001E44
+		X"24050001", -- 00001E48
+		X"00051080", -- 00001E4C
+		X"00461021", -- 00001E50
+		X"8C430000", -- 00001E54
+		X"00000000", -- 00001E58
+		X"01234821", -- 00001E5C
+		X"0520FFDE", -- 00001E60
+		X"00051040", -- 00001E64
+		X"08100748", -- 00001E68
+		X"00451021", -- 00001E6C
+		X"24A20007", -- 00001E70
+		X"08100713", -- 00001E74
+		X"AE220018", -- 00001E78
+		X"0C1008E6", -- 00001E7C
+		X"00000000", -- 00001E80
+		X"8F82099C", -- 00001E84
+		X"00000000", -- 00001E88
+		X"1040001B", -- 00001E8C
+		X"00000000", -- 00001E90
+		X"8E620004", -- 00001E94
+		X"00000000", -- 00001E98
+		X"10500005", -- 00001E9C
+		X"00000000", -- 00001EA0
+		X"0C100606", -- 00001EA4
+		X"02002021", -- 00001EA8
+		X"1040008C", -- 00001EAC
+		X"2402FFFF", -- 00001EB0
+		X"8E620000", -- 00001EB4
+		X"00000000", -- 00001EB8
+		X"10400080", -- 00001EBC
+		X"00000000", -- 00001EC0
+		X"8E840000", -- 00001EC4
+		X"8E62001C", -- 00001EC8
+		X"00000000", -- 00001ECC
+		X"0082102A", -- 00001ED0
+		X"14400007", -- 00001ED4
+		X"00001821", -- 00001ED8
+		X"8E620038", -- 00001EDC
+		X"00000000", -- 00001EE0
+		X"0082102A", -- 00001EE4
+		X"10400002", -- 00001EE8
+		X"00000000", -- 00001EEC
+		X"24030001", -- 00001EF0
+		X"081007C0", -- 00001EF4
+		X"AE230020", -- 00001EF8
+		X"AE200020", -- 00001EFC
+		X"8E230020", -- 00001F00
+		X"24020001", -- 00001F04
+		X"10620068", -- 00001F08
+		X"00000000", -- 00001F0C
+		X"8E690020", -- 00001F10
+		X"3C0491A2", -- 00001F14
+		X"3484B3C5", -- 00001F18
+		X"01240018", -- 00001F1C
+		X"00091FC3", -- 00001F20
+		X"8E270000", -- 00001F24
+		X"8E280004", -- 00001F28
+		X"8E260008", -- 00001F2C
+		X"00002010", -- 00001F30
+		X"00892021", -- 00001F34
+		X"000422C3", -- 00001F38
+		X"00832023", -- 00001F3C
+		X"000410C0", -- 00001F40
+		X"00441023", -- 00001F44
+		X"00021140", -- 00001F48
+		X"00441021", -- 00001F4C
+		X"00021100", -- 00001F50
+		X"3C038888", -- 00001F54
+		X"01224823", -- 00001F58
+		X"34638889", -- 00001F5C
+		X"01230018", -- 00001F60
+		X"00092FC3", -- 00001F64
+		X"00C43023", -- 00001F68
+		X"00C02021", -- 00001F6C
+		X"00001810", -- 00001F70
+		X"00691821", -- 00001F74
+		X"00031943", -- 00001F78
+		X"00651823", -- 00001F7C
+		X"00031100", -- 00001F80
+		X"00431023", -- 00001F84
+		X"00021080", -- 00001F88
+		X"01221023", -- 00001F8C
+		X"00E22823", -- 00001F90
+		X"01034023", -- 00001F94
+		X"28A2003C", -- 00001F98
+		X"1440003F", -- 00001F9C
+		X"01001821", -- 00001FA0
+		X"25080001", -- 00001FA4
+		X"24A2FFC4", -- 00001FA8
+		X"01001821", -- 00001FAC
+		X"AE220000", -- 00001FB0
+		X"2862003C", -- 00001FB4
+		X"14400034", -- 00001FB8
+		X"00000000", -- 00001FBC
+		X"24860001", -- 00001FC0
+		X"2463FFC4", -- 00001FC4
+		X"00C02021", -- 00001FC8
+		X"AE230004", -- 00001FCC
+		X"28820018", -- 00001FD0
+		X"14400027", -- 00001FD4
+		X"00000000", -- 00001FD8
+		X"8E220018", -- 00001FDC
+		X"8E23001C", -- 00001FE0
+		X"24450001", -- 00001FE4
+		X"24630001", -- 00001FE8
+		X"28A20007", -- 00001FEC
+		X"14400031", -- 00001FF0
+		X"AE23001C", -- 00001FF4
+		X"AE200018", -- 00001FF8
+		X"8E22000C", -- 00001FFC
+		X"8E260010", -- 00002000
+		X"24450001", -- 00002004
+		X"2484FFE8", -- 00002008
+		X"00061080", -- 0000200C
+		X"AE240008", -- 00002010
+		X"00521021", -- 00002014
+		X"AE25000C", -- 00002018
+		X"8C420000", -- 0000201C
+		X"00000000", -- 00002020
+		X"0045182A", -- 00002024
+		X"10600006", -- 00002028
+		X"00A21823", -- 0000202C
+		X"24C40001", -- 00002030
+		X"2402000C", -- 00002034
+		X"1082004E", -- 00002038
+		X"AE23000C", -- 0000203C
+		X"AE240010", -- 00002040
+		X"0C1008E8", -- 00002044
+		X"00000000", -- 00002048
+		X"02201021", -- 0000204C
+		X"8FBF0028", -- 00002050
+		X"8FB50024", -- 00002054
+		X"8FB40020", -- 00002058
+		X"8FB3001C", -- 0000205C
+		X"8FB20018", -- 00002060
+		X"8FB10014", -- 00002064
+		X"8FB00010", -- 00002068
+		X"03E00008", -- 0000206C
+		X"27BD0030", -- 00002070
+		X"04800023", -- 00002074
+		X"00000000", -- 00002078
+		X"0C1008E8", -- 0000207C
+		X"AE260008", -- 00002080
+		X"08100814", -- 00002084
+		X"02201021", -- 00002088
+		X"04600019", -- 0000208C
+		X"2462003C", -- 00002090
+		X"081007F4", -- 00002094
+		X"AE280004", -- 00002098
+		X"04A00012", -- 0000209C
+		X"00000000", -- 000020A0
+		X"081007ED", -- 000020A4
+		X"AE250000", -- 000020A8
+		X"8E69003C", -- 000020AC
+		X"081007C6", -- 000020B0
+		X"3C0491A2", -- 000020B4
+		X"081007FF", -- 000020B8
+		X"AE250018", -- 000020BC
+		X"8E840000", -- 000020C0
+		X"8E62001C", -- 000020C4
+		X"00000000", -- 000020C8
+		X"0082102A", -- 000020CC
+		X"1040FF87", -- 000020D0
+		X"00001821", -- 000020D4
+		X"081007B7", -- 000020D8
+		X"00000000", -- 000020DC
+		X"081007C0", -- 000020E0
+		X"AE220020", -- 000020E4
+		X"2508FFFF", -- 000020E8
+		X"081007EB", -- 000020EC
+		X"24A2003C", -- 000020F0
+		X"2486FFFF", -- 000020F4
+		X"00C02021", -- 000020F8
+		X"081007F4", -- 000020FC
+		X"AE220004", -- 00002100
+		X"8E220018", -- 00002104
+		X"8E23001C", -- 00002108
+		X"2445FFFF", -- 0000210C
+		X"04A00024", -- 00002110
+		X"2466FFFF", -- 00002114
+		X"AE250018", -- 00002118
+		X"8E22000C", -- 0000211C
+		X"24830018", -- 00002120
+		X"2442FFFF", -- 00002124
+		X"AE230008", -- 00002128
+		X"14400019", -- 0000212C
+		X"AE22000C", -- 00002130
+		X"8E220010", -- 00002134
+		X"00000000", -- 00002138
+		X"2444FFFF", -- 0000213C
+		X"0480001B", -- 00002140
+		X"00000000", -- 00002144
+		X"AE240010", -- 00002148
+		X"AE26001C", -- 0000214C
+		X"8E220010", -- 00002150
+		X"00000000", -- 00002154
+		X"00021080", -- 00002158
+		X"00521021", -- 0000215C
+		X"8C430000", -- 00002160
+		X"0C1008E8", -- 00002164
+		X"AE23000C", -- 00002168
+		X"08100814", -- 0000216C
+		X"02201021", -- 00002170
+		X"8E220014", -- 00002174
+		X"AE200010", -- 00002178
+		X"24420001", -- 0000217C
+		X"AE220014", -- 00002180
+		X"0C1008E8", -- 00002184
+		X"AE20001C", -- 00002188
+		X"08100814", -- 0000218C
+		X"02201021", -- 00002190
+		X"0C1008E8", -- 00002194
+		X"AE26001C", -- 00002198
+		X"08100814", -- 0000219C
+		X"02201021", -- 000021A0
+		X"24020006", -- 000021A4
+		X"08100847", -- 000021A8
+		X"AE220018", -- 000021AC
+		X"8E220014", -- 000021B0
+		X"00003021", -- 000021B4
+		X"2444FFFF", -- 000021B8
+		X"30830003", -- 000021BC
+		X"2402000B", -- 000021C0
+		X"AE220010", -- 000021C4
+		X"AE240014", -- 000021C8
+		X"1460000E", -- 000021CC
+		X"00042FC3", -- 000021D0
+		X"3C0351EB", -- 000021D4
+		X"3463851F", -- 000021D8
+		X"00830018", -- 000021DC
+		X"00001810", -- 000021E0
+		X"00031943", -- 000021E4
+		X"00651823", -- 000021E8
+		X"00031040", -- 000021EC
+		X"00431021", -- 000021F0
+		X"000210C0", -- 000021F4
+		X"00431021", -- 000021F8
+		X"00021080", -- 000021FC
+		X"1482000E", -- 00002200
+		X"00000000", -- 00002204
+		X"3C0351EB", -- 00002208
+		X"3463851F", -- 0000220C
+		X"00830018", -- 00002210
+		X"00001810", -- 00002214
+		X"000319C3", -- 00002218
+		X"00651823", -- 0000221C
+		X"00031040", -- 00002220
+		X"00431021", -- 00002224
+		X"000210C0", -- 00002228
+		X"00431021", -- 0000222C
+		X"00021100", -- 00002230
+		X"14820002", -- 00002234
+		X"00000000", -- 00002238
+		X"24060001", -- 0000223C
+		X"24C2016D", -- 00002240
+		X"08100854", -- 00002244
+		X"AE22001C", -- 00002248
+		X"03E00008", -- 0000224C
+		X"00000000", -- 00002250
+		X"03E00008", -- 00002254
+		X"00000000", -- 00002258
+		X"8F82096C", -- 0000225C
+		X"00002821", -- 00002260
+		X"AC4400A8", -- 00002264
+		X"03E00008", -- 00002268
+		X"AC4500AC", -- 0000226C
+		X"8F88096C", -- 00002270
+		X"3C045851", -- 00002274
+		X"8D0600A8", -- 00002278
+		X"3484F42D", -- 0000227C
+		X"00C40018", -- 00002280
+		X"3C054C95", -- 00002284
+		X"34A57F2D", -- 00002288
+		X"8D0700AC", -- 0000228C
+		X"00002012", -- 00002290
+		X"00000000", -- 00002294
+		X"00000000", -- 00002298
+		X"00C50019", -- 0000229C
+		X"00001810", -- 000022A0
+		X"00832021", -- 000022A4
+		X"00001012", -- 000022A8
+		X"24420001", -- 000022AC
+		X"2C460001", -- 000022B0
+		X"00E50018", -- 000022B4
+		X"AD0200A8", -- 000022B8
+		X"3C027FFF", -- 000022BC
+		X"3442FFFF", -- 000022C0
+		X"00002812", -- 000022C4
+		X"00851821", -- 000022C8
+		X"00661821", -- 000022CC
+		X"00032002", -- 000022D0
+		X"00441024", -- 000022D4
+		X"03E00008", -- 000022D8
+		X"AD0300AC", -- 000022DC
+		X"27BDFFE8", -- 000022E0
+		X"AFB00010", -- 000022E4
+		X"00808021", -- 000022E8
+		X"00A02021", -- 000022EC
+		X"AFBF0014", -- 000022F0
+		X"0C100198", -- 000022F4
+		X"AF800B1C", -- 000022F8
+		X"00401821", -- 000022FC
+		X"2402FFFF", -- 00002300
+		X"10620006", -- 00002304
+		X"00000000", -- 00002308
+		X"8FBF0014", -- 0000230C
+		X"8FB00010", -- 00002310
+		X"00601021", -- 00002314
+		X"03E00008", -- 00002318
+		X"27BD0018", -- 0000231C
+		X"8F820B1C", -- 00002320
+		X"00000000", -- 00002324
+		X"1040FFF8", -- 00002328
+		X"00000000", -- 0000232C
+		X"081008C3", -- 00002330
+		X"AE020000", -- 00002334
+		X"27BDFFE0", -- 00002338
+		X"AFB00018", -- 0000233C
+		X"00808021", -- 00002340
+		X"8F84096C", -- 00002344
+		X"27A50010", -- 00002348
+		X"AFBF001C", -- 0000234C
+		X"0C100A08", -- 00002350
+		X"00003021", -- 00002354
+		X"04400007", -- 00002358
+		X"2403FFFF", -- 0000235C
+		X"1200000A", -- 00002360
+		X"00000000", -- 00002364
+		X"8FA20010", -- 00002368
+		X"00000000", -- 0000236C
+		X"AE020000", -- 00002370
+		X"00401821", -- 00002374
+		X"8FBF001C", -- 00002378
+		X"8FB00018", -- 0000237C
+		X"00601021", -- 00002380
+		X"03E00008", -- 00002384
+		X"27BD0020", -- 00002388
+		X"8FA20010", -- 0000238C
+		X"081008DE", -- 00002390
+		X"00401821", -- 00002394
+		X"03E00008", -- 00002398
+		X"00000000", -- 0000239C
+		X"03E00008", -- 000023A0
+		X"00000000", -- 000023A4
+		X"27BDFFE0", -- 000023A8
+		X"AFB20018", -- 000023AC
+		X"AFB10014", -- 000023B0
+		X"AFB00010", -- 000023B4
+		X"00809021", -- 000023B8
+		X"AFBF001C", -- 000023BC
+		X"0C100893", -- 000023C0
+		X"00A08021", -- 000023C4
+		X"3C020000", -- 000023C8
+		X"8C420528", -- 000023CC
+		X"02402021", -- 000023D0
+		X"8C430004", -- 000023D4
+		X"2402FFFC", -- 000023D8
+		X"00628824", -- 000023DC
+		X"02308023", -- 000023E0
+		X"26100FEF", -- 000023E4
+		X"00108302", -- 000023E8
+		X"2610FFFF", -- 000023EC
+		X"00108300", -- 000023F0
+		X"2A021000", -- 000023F4
+		X"14400009", -- 000023F8
+		X"00002821", -- 000023FC
+		X"0C1008B8", -- 00002400
+		X"00000000", -- 00002404
+		X"3C030000", -- 00002408
+		X"8C630528", -- 0000240C
+		X"02402021", -- 00002410
+		X"00711821", -- 00002414
+		X"1062000A", -- 00002418
+		X"00102823", -- 0000241C
+		X"0C100895", -- 00002420
+		X"00000000", -- 00002424
+		X"00001021", -- 00002428
+		X"8FBF001C", -- 0000242C
+		X"8FB20018", -- 00002430
+		X"8FB10014", -- 00002434
+		X"8FB00010", -- 00002438
+		X"03E00008", -- 0000243C
+		X"27BD0020", -- 00002440
+		X"0C1008B8", -- 00002444
+		X"02402021", -- 00002448
+		X"02301823", -- 0000244C
+		X"34660001", -- 00002450
+		X"2403FFFF", -- 00002454
+		X"02402021", -- 00002458
+		X"1043000F", -- 0000245C
+		X"00002821", -- 00002460
+		X"3C030000", -- 00002464
+		X"8C630528", -- 00002468
+		X"00000000", -- 0000246C
+		X"AC660004", -- 00002470
+		X"3C020000", -- 00002474
+		X"8C420AF4", -- 00002478
+		X"00000000", -- 0000247C
+		X"00501023", -- 00002480
+		X"3C010000", -- 00002484
+		X"AC220AF4", -- 00002488
+		X"0C100895", -- 0000248C
+		X"02402021", -- 00002490
+		X"0810090B", -- 00002494
+		X"24020001", -- 00002498
+		X"0C1008B8", -- 0000249C
+		X"00000000", -- 000024A0
+		X"3C050000", -- 000024A4
+		X"8CA50528", -- 000024A8
+		X"00401821", -- 000024AC
+		X"00458823", -- 000024B0
+		X"2A220010", -- 000024B4
+		X"02402021", -- 000024B8
+		X"1440FFD8", -- 000024BC
+		X"36260001", -- 000024C0
+		X"8F820970", -- 000024C4
+		X"00000000", -- 000024C8
+		X"00621023", -- 000024CC
+		X"3C010000", -- 000024D0
+		X"AC220AF4", -- 000024D4
+		X"08100908", -- 000024D8
+		X"ACA60004", -- 000024DC
+		X"27BDFFE0", -- 000024E0
+		X"AFB10014", -- 000024E4
+		X"AFB00010", -- 000024E8
+		X"AFBF0018", -- 000024EC
+		X"00A08021", -- 000024F0
+		X"10A0003C", -- 000024F4
+		X"00808821", -- 000024F8
+		X"0C100893", -- 000024FC
+		X"00000000", -- 00002500
+		X"260BFFF8", -- 00002504
+		X"8D640004", -- 00002508
+		X"2402FFFE", -- 0000250C
+		X"00824824", -- 00002510
+		X"01693021", -- 00002514
+		X"8CC30004", -- 00002518
+		X"2402FFFC", -- 0000251C
+		X"00625024", -- 00002520
+		X"3C020000", -- 00002524
+		X"8C420528", -- 00002528
+		X"3C0C0000", -- 0000252C
+		X"258C0520", -- 00002530
+		X"10460053", -- 00002534
+		X"30820001", -- 00002538
+		X"ACCA0004", -- 0000253C
+		X"1440000D", -- 00002540
+		X"00002021", -- 00002544
+		X"8E05FFF8", -- 00002548
+		X"3C020000", -- 0000254C
+		X"24420528", -- 00002550
+		X"01655823", -- 00002554
+		X"8D630008", -- 00002558
+		X"00000000", -- 0000255C
+		X"10620087", -- 00002560
+		X"01254821", -- 00002564
+		X"8D68000C", -- 00002568
+		X"00000000", -- 0000256C
+		X"AD030008", -- 00002570
+		X"AC68000C", -- 00002574
+		X"00CA1821", -- 00002578
+		X"8C620004", -- 0000257C
+		X"00000000", -- 00002580
+		X"30420001", -- 00002584
+		X"1440000D", -- 00002588
+		X"35220001", -- 0000258C
+		X"1480001A", -- 00002590
+		X"012A4821", -- 00002594
+		X"8CC30008", -- 00002598
+		X"3C020000", -- 0000259C
+		X"24420528", -- 000025A0
+		X"10620070", -- 000025A4
+		X"00000000", -- 000025A8
+		X"8CC8000C", -- 000025AC
+		X"00000000", -- 000025B0
+		X"AD030008", -- 000025B4
+		X"AC68000C", -- 000025B8
+		X"35220001", -- 000025BC
+		X"01691821", -- 000025C0
+		X"AD620004", -- 000025C4
+		X"10800012", -- 000025C8
+		X"AC690000", -- 000025CC
+		X"02202021", -- 000025D0
+		X"8FBF0018", -- 000025D4
+		X"8FB10014", -- 000025D8
+		X"8FB00010", -- 000025DC
+		X"08100895", -- 000025E0
+		X"27BD0020", -- 000025E4
+		X"8FBF0018", -- 000025E8
+		X"8FB10014", -- 000025EC
+		X"8FB00010", -- 000025F0
+		X"03E00008", -- 000025F4
+		X"27BD0020", -- 000025F8
+		X"8CC30008", -- 000025FC
+		X"8CC8000C", -- 00002600
+		X"00000000", -- 00002604
+		X"AD030008", -- 00002608
+		X"0810096F", -- 0000260C
+		X"AC68000C", -- 00002610
+		X"2D220200", -- 00002614
+		X"1040002F", -- 00002618
+		X"00092242", -- 0000261C
+		X"000918C2", -- 00002620
+		X"3C050000", -- 00002624
+		X"24A50520", -- 00002628
+		X"0460005E", -- 0000262C
+		X"00602021", -- 00002630
+		X"000310C0", -- 00002634
+		X"00454021", -- 00002638
+		X"00042083", -- 0000263C
+		X"3C020000", -- 00002640
+		X"8C420524", -- 00002644
+		X"24030001", -- 00002648
+		X"8D070008", -- 0000264C
+		X"00831804", -- 00002650
+		X"00431025", -- 00002654
+		X"AD68000C", -- 00002658
+		X"AD670008", -- 0000265C
+		X"ACA20004", -- 00002660
+		X"ACEB000C", -- 00002664
+		X"AD0B0008", -- 00002668
+		X"02202021", -- 0000266C
+		X"8FBF0018", -- 00002670
+		X"8FB10014", -- 00002674
+		X"8FB00010", -- 00002678
+		X"08100895", -- 0000267C
+		X"27BD0020", -- 00002680
+		X"14400009", -- 00002684
+		X"012A4821", -- 00002688
+		X"8E05FFF8", -- 0000268C
+		X"00000000", -- 00002690
+		X"01655823", -- 00002694
+		X"8D68000C", -- 00002698
+		X"8D670008", -- 0000269C
+		X"01254821", -- 000026A0
+		X"AD070008", -- 000026A4
+		X"ACE8000C", -- 000026A8
+		X"8F820974", -- 000026AC
+		X"35230001", -- 000026B0
+		X"0122102B", -- 000026B4
+		X"AD8B0008", -- 000026B8
+		X"1440FFC4", -- 000026BC
+		X"AD630004", -- 000026C0
+		X"8F850994", -- 000026C4
+		X"0C1008EA", -- 000026C8
+		X"02202021", -- 000026CC
+		X"08100975", -- 000026D0
+		X"02202021", -- 000026D4
+		X"1480001D", -- 000026D8
+		X"000918C2", -- 000026DC
+		X"000310C0", -- 000026E0
+		X"004C4021", -- 000026E4
+		X"8D070008", -- 000026E8
+		X"00000000", -- 000026EC
+		X"10E8002F", -- 000026F0
+		X"00000000", -- 000026F4
+		X"8CE20004", -- 000026F8
+		X"2403FFFC", -- 000026FC
+		X"00431024", -- 00002700
+		X"0122102B", -- 00002704
+		X"1040000B", -- 00002708
+		X"00000000", -- 0000270C
+		X"8CE70008", -- 00002710
+		X"00000000", -- 00002714
+		X"10E80007", -- 00002718
+		X"00000000", -- 0000271C
+		X"8CE20004", -- 00002720
+		X"00000000", -- 00002724
+		X"00431024", -- 00002728
+		X"0122102B", -- 0000272C
+		X"1440FFF7", -- 00002730
+		X"00000000", -- 00002734
+		X"8CE8000C", -- 00002738
+		X"AD670008", -- 0000273C
+		X"AD68000C", -- 00002740
+		X"AD0B0008", -- 00002744
+		X"0810099B", -- 00002748
+		X"ACEB000C", -- 0000274C
+		X"2C820005", -- 00002750
+		X"1040000C", -- 00002754
+		X"2C820015", -- 00002758
+		X"00091182", -- 0000275C
+		X"081009B8", -- 00002760
+		X"24430038", -- 00002764
+		X"24040001", -- 00002768
+		X"AC6B000C", -- 0000276C
+		X"AC6B0008", -- 00002770
+		X"AD63000C", -- 00002774
+		X"0810096F", -- 00002778
+		X"AD630008", -- 0000277C
+		X"0810095E", -- 00002780
+		X"24040001", -- 00002784
+		X"1440FFD5", -- 00002788
+		X"2483005B", -- 0000278C
+		X"2C820055", -- 00002790
+		X"10400016", -- 00002794
+		X"2C820155", -- 00002798
+		X"00091302", -- 0000279C
+		X"081009B8", -- 000027A0
+		X"2443006E", -- 000027A4
+		X"0810098D", -- 000027A8
+		X"24640003", -- 000027AC
+		X"04600014", -- 000027B0
+		X"00601021", -- 000027B4
+		X"00021083", -- 000027B8
+		X"3C040000", -- 000027BC
+		X"8C840524", -- 000027C0
+		X"24030001", -- 000027C4
+		X"00431804", -- 000027C8
+		X"00832025", -- 000027CC
+		X"3C020000", -- 000027D0
+		X"24420520", -- 000027D4
+		X"AD68000C", -- 000027D8
+		X"AD670008", -- 000027DC
+		X"AC440004", -- 000027E0
+		X"ACEB000C", -- 000027E4
+		X"0810099B", -- 000027E8
+		X"AD0B0008", -- 000027EC
+		X"10400006", -- 000027F0
+		X"2C820555", -- 000027F4
+		X"000913C2", -- 000027F8
+		X"081009B8", -- 000027FC
+		X"24430077", -- 00002800
+		X"081009EE", -- 00002804
+		X"24620003", -- 00002808
+		X"1040FFB4", -- 0000280C
+		X"2403007E", -- 00002810
+		X"00091482", -- 00002814
+		X"081009B8", -- 00002818
+		X"2443007C", -- 0000281C
+		X"27BDFFE8", -- 00002820
+		X"AFB00010", -- 00002824
+		X"00808021", -- 00002828
+		X"00A02021", -- 0000282C
+		X"00C02821", -- 00002830
+		X"AFBF0014", -- 00002834
+		X"0C10016D", -- 00002838
+		X"AF800B1C", -- 0000283C
+		X"00401821", -- 00002840
+		X"2402FFFF", -- 00002844
+		X"10620006", -- 00002848
+		X"00000000", -- 0000284C
+		X"8FBF0014", -- 00002850
+		X"8FB00010", -- 00002854
+		X"00601021", -- 00002858
+		X"03E00008", -- 0000285C
+		X"27BD0018", -- 00002860
+		X"8F820B1C", -- 00002864
+		X"00000000", -- 00002868
+		X"1040FFF8", -- 0000286C
+		X"00000000", -- 00002870
+		X"AE020000", -- 00002874
+		X"8FBF0014", -- 00002878
+		X"8FB00010", -- 0000287C
+		X"00601021", -- 00002880
+		X"03E00008", -- 00002884
+		X"27BD0018", -- 00002888
+		X"3C020000", -- 0000288C
+		X"03E00008", -- 00002890
+		X"24420928", -- 00002894
+		X"27BDFFE0", -- 00002898
+		X"AFB10014", -- 0000289C
+		X"AFB00010", -- 000028A0
+		X"AFBF0018", -- 000028A4
+		X"8CA20000", -- 000028A8
+		X"00A08821", -- 000028AC
+		X"00808021", -- 000028B0
+		X"14400008", -- 000028B4
+		X"00402821", -- 000028B8
+		X"02002021", -- 000028BC
+		X"02202821", -- 000028C0
+		X"8FBF0018", -- 000028C4
+		X"8FB10014", -- 000028C8
+		X"8FB00010", -- 000028CC
+		X"08100938", -- 000028D0
+		X"27BD0020", -- 000028D4
+		X"0C100A26", -- 000028D8
+		X"00000000", -- 000028DC
+		X"02002021", -- 000028E0
+		X"02202821", -- 000028E4
+		X"8FBF0018", -- 000028E8
+		X"8FB10014", -- 000028EC
+		X"8FB00010", -- 000028F0
+		X"08100938", -- 000028F4
+		X"27BD0020", -- 000028F8
+		X"8F82096C", -- 000028FC
+		X"27BDFFE0", -- 00002900
+		X"AFB10014", -- 00002904
+		X"AFBF001C", -- 00002908
+		X"AFB20018", -- 0000290C
+		X"AFB00010", -- 00002910
+		X"1082001F", -- 00002914
+		X"00808821", -- 00002918
+		X"8C85004C", -- 0000291C
+		X"00000000", -- 00002920
+		X"14A00021", -- 00002924
+		X"00000000", -- 00002928
+		X"8E250040", -- 0000292C
+		X"00000000", -- 00002930
+		X"14A00035", -- 00002934
+		X"00000000", -- 00002938
+		X"8E250148", -- 0000293C
+		X"00000000", -- 00002940
+		X"10A0000B", -- 00002944
+		X"00000000", -- 00002948
+		X"2632014C", -- 0000294C
+		X"10B20008", -- 00002950
+		X"00000000", -- 00002954
+		X"08100A5B", -- 00002958
+		X"00A08021", -- 0000295C
+		X"8E100000", -- 00002960
+		X"0C100938", -- 00002964
+		X"02202021", -- 00002968
+		X"1650FFFC", -- 0000296C
+		X"02002821", -- 00002970
+		X"8E250054", -- 00002974
+		X"00000000", -- 00002978
+		X"14A00036", -- 0000297C
+		X"00000000", -- 00002980
+		X"8E220038", -- 00002984
+		X"00000000", -- 00002988
+		X"14400023", -- 0000298C
+		X"00000000", -- 00002990
+		X"8FBF001C", -- 00002994
+		X"8FB20018", -- 00002998
+		X"8FB10014", -- 0000299C
+		X"8FB00010", -- 000029A0
+		X"03E00008", -- 000029A4
+		X"27BD0020", -- 000029A8
+		X"00009021", -- 000029AC
+		X"00121080", -- 000029B0
+		X"00451021", -- 000029B4
+		X"8C500000", -- 000029B8
+		X"00000000", -- 000029BC
+		X"12000008", -- 000029C0
+		X"00000000", -- 000029C4
+		X"02002821", -- 000029C8
+		X"8E100000", -- 000029CC
+		X"0C100938", -- 000029D0
+		X"02202021", -- 000029D4
+		X"1600FFFC", -- 000029D8
+		X"02002821", -- 000029DC
+		X"8E25004C", -- 000029E0
+		X"26520001", -- 000029E4
+		X"2A42000F", -- 000029E8
+		X"1440FFF1", -- 000029EC
+		X"00121080", -- 000029F0
+		X"0C100938", -- 000029F4
+		X"02202021", -- 000029F8
+		X"8E250040", -- 000029FC
+		X"00000000", -- 00002A00
+		X"10A0FFCD", -- 00002A04
+		X"00000000", -- 00002A08
+		X"0C100938", -- 00002A0C
+		X"02202021", -- 00002A10
+		X"08100A4F", -- 00002A14
+		X"00000000", -- 00002A18
+		X"8E22003C", -- 00002A1C
+		X"00000000", -- 00002A20
+		X"0040F809", -- 00002A24
+		X"02202021", -- 00002A28
+		X"8E2502E0", -- 00002A2C
+		X"00000000", -- 00002A30
+		X"10A0FFD7", -- 00002A34
+		X"00000000", -- 00002A38
+		X"02202021", -- 00002A3C
+		X"8FBF001C", -- 00002A40
+		X"8FB20018", -- 00002A44
+		X"8FB10014", -- 00002A48
+		X"8FB00010", -- 00002A4C
+		X"08100A26", -- 00002A50
+		X"27BD0020", -- 00002A54
+		X"0C100938", -- 00002A58
+		X"02202021", -- 00002A5C
+		X"08100A61", -- 00002A60
+		X"00000000", -- 00002A64
+		X"27BDFFD8", -- 00002A68
+		X"AFB3001C", -- 00002A6C
+		X"AFBF0020", -- 00002A70
+		X"AFB20018", -- 00002A74
+		X"AFB10014", -- 00002A78
+		X"AFB00010", -- 00002A7C
+		X"10800028", -- 00002A80
+		X"00809821", -- 00002A84
+		X"8E720148", -- 00002A88
+		X"00000000", -- 00002A8C
+		X"12400012", -- 00002A90
+		X"00000000", -- 00002A94
+		X"8E510004", -- 00002A98
+		X"00000000", -- 00002A9C
+		X"2631FFFF", -- 00002AA0
+		X"06200009", -- 00002AA4
+		X"00111080", -- 00002AA8
+		X"00521021", -- 00002AAC
+		X"24500008", -- 00002AB0
+		X"8E020000", -- 00002AB4
+		X"00000000", -- 00002AB8
+		X"0040F809", -- 00002ABC
+		X"2631FFFF", -- 00002AC0
+		X"0621FFFB", -- 00002AC4
+		X"2610FFFC", -- 00002AC8
+		X"8E520000", -- 00002ACC
+		X"00000000", -- 00002AD0
+		X"1640FFF0", -- 00002AD4
+		X"00000000", -- 00002AD8
+		X"8E79003C", -- 00002ADC
+		X"00000000", -- 00002AE0
+		X"17200008", -- 00002AE4
+		X"02602021", -- 00002AE8
+		X"8FBF0020", -- 00002AEC
+		X"8FB3001C", -- 00002AF0
+		X"8FB20018", -- 00002AF4
+		X"8FB10014", -- 00002AF8
+		X"8FB00010", -- 00002AFC
+		X"03E00008", -- 00002B00
+		X"27BD0028", -- 00002B04
+		X"8FBF0020", -- 00002B08
+		X"8FB3001C", -- 00002B0C
+		X"8FB20018", -- 00002B10
+		X"8FB10014", -- 00002B14
+		X"8FB00010", -- 00002B18
+		X"03200008", -- 00002B1C
+		X"27BD0028", -- 00002B20
+		X"8F93096C", -- 00002B24
+		X"08100AA2", -- 00002B28
+		X"00000000", -- 00002B2C
+		X"00000000", -- 00002B30
+		X"00000000", -- 00002B34
+		X"00000000", -- 00002B38
+		X"00000000", -- 00002B3C
+		X"00000000", -- 00002B40
+		X"00000000", -- 00002B44
+		X"00000000", -- 00002B48
+		X"00000000", -- 00002B4C
+		X"00000000", -- 00002B50
+		X"00000000", -- 00002B54
+		X"00000000", -- 00002B58
+		X"00000000", -- 00002B5C
+		X"00000000", -- 00002B60
+		X"00000000", -- 00002B64
+		X"00000000", -- 00002B68
+		X"00000000", -- 00002B6C
+		X"00000000", -- 00002B70
+		X"00000000", -- 00002B74
+		X"00000000", -- 00002B78
+		X"00000000", -- 00002B7C
+		X"00000000", -- 00002B80
+		X"00000000", -- 00002B84
+		X"00000000", -- 00002B88
+		X"00000000", -- 00002B8C
+		X"00000000", -- 00002B90
+		X"00000000", -- 00002B94
+		X"00000000", -- 00002B98
+		X"00000000", -- 00002B9C
+		X"00000000", -- 00002BA0
+		X"00000000", -- 00002BA4
+		X"00000000", -- 00002BA8
+		X"00000000", -- 00002BAC
+		X"00000000", -- 00002BB0
+		X"00000000", -- 00002BB4
+		X"00000000", -- 00002BB8
+		X"00000000", -- 00002BBC
+		X"00000000", -- 00002BC0
+		X"00000000", -- 00002BC4
+		X"00000000", -- 00002BC8
+		X"00000000", -- 00002BCC
+		X"00000000", -- 00002BD0
+		X"00000000", -- 00002BD4
+		X"00000000", -- 00002BD8
+		X"00000000", -- 00002BDC
+		X"00000000", -- 00002BE0
+		X"00000000", -- 00002BE4
+		X"00000000", -- 00002BE8
+		X"00000000", -- 00002BEC
+		X"00000000", -- 00002BF0
+		X"00000000", -- 00002BF4
+		X"00000000", -- 00002BF8
+		X"00000000", -- 00002BFC
+		X"00000000", -- 00002C00
+		X"00000000", -- 00002C04
+		X"00000000", -- 00002C08
+		X"00000000", -- 00002C0C
+		X"00000000", -- 00002C10
+		X"00000000", -- 00002C14
+		X"00000000", -- 00002C18
+		X"00000000", -- 00002C1C
+		X"00000000", -- 00002C20
+		X"00000000", -- 00002C24
+		X"00000000", -- 00002C28
+		X"00000000", -- 00002C2C
+		X"00000000", -- 00002C30
+		X"00000000", -- 00002C34
+		X"00000000", -- 00002C38
+		X"00000000", -- 00002C3C
+		X"00000000", -- 00002C40
+		X"00000000", -- 00002C44
+		X"00000000", -- 00002C48
+		X"00000000", -- 00002C4C
+		X"00000000", -- 00002C50
+		X"00000000", -- 00002C54
+		X"00000000", -- 00002C58
+		X"00000000", -- 00002C5C
+		X"00000000", -- 00002C60
+		X"00000000", -- 00002C64
+		X"00000000", -- 00002C68
+		X"00000000", -- 00002C6C
+		X"00000000", -- 00002C70
+		X"00000000", -- 00002C74
+		X"00000000", -- 00002C78
+		X"00000000", -- 00002C7C
+		X"00000000", -- 00002C80
+		X"00000000", -- 00002C84
+		X"00000000", -- 00002C88
+		X"00000000", -- 00002C8C
+		X"00000000", -- 00002C90
+		X"00000000", -- 00002C94
+		X"00000000", -- 00002C98
+		X"00000000", -- 00002C9C
+		X"00000000", -- 00002CA0
+		X"00000000", -- 00002CA4
+		X"00000000", -- 00002CA8
+		X"00000000", -- 00002CAC
+		X"00000000", -- 00002CB0
+		X"00000000", -- 00002CB4
+		X"00000000", -- 00002CB8
+		X"00000000", -- 00002CBC
+		X"00000000", -- 00002CC0
+		X"00000000", -- 00002CC4
+		X"00000000", -- 00002CC8
+		X"00000000", -- 00002CCC
+		X"00000000", -- 00002CD0
+		X"00000000", -- 00002CD4
+		X"00000000", -- 00002CD8
+		X"00000000", -- 00002CDC
+		X"00000000", -- 00002CE0
+		X"00000000", -- 00002CE4
+		X"00000000", -- 00002CE8
+		X"00000000", -- 00002CEC
+		X"00000000", -- 00002CF0
+		X"00000000", -- 00002CF4
+		X"00000000", -- 00002CF8
+		X"00000000", -- 00002CFC
+		X"00000000", -- 00002D00
+		X"00000000", -- 00002D04
+		X"00000000", -- 00002D08
+		X"00000000", -- 00002D0C
+		X"00000000", -- 00002D10
+		X"00000000", -- 00002D14
+		X"00000000", -- 00002D18
+		X"00000000", -- 00002D1C
+		X"00000000", -- 00002D20
+		X"00000000", -- 00002D24
+		X"00000000", -- 00002D28
+		X"00000000", -- 00002D2C
+		X"00000000", -- 00002D30
+		X"00000000", -- 00002D34
+		X"00000000", -- 00002D38
+		X"00000000", -- 00002D3C
+		X"00000000", -- 00002D40
+		X"00000000", -- 00002D44
+		X"00000000", -- 00002D48
+		X"00000000", -- 00002D4C
+		X"00000000", -- 00002D50
+		X"00000000", -- 00002D54
+		X"00000000", -- 00002D58
+		X"00000000", -- 00002D5C
+		X"00000000", -- 00002D60
+		X"00000000", -- 00002D64
+		X"00000000", -- 00002D68
+		X"00000000", -- 00002D6C
+		X"00000000", -- 00002D70
+		X"00000000", -- 00002D74
+		X"00000000", -- 00002D78
+		X"00000000", -- 00002D7C
+		X"00000000", -- 00002D80
+		X"00000000", -- 00002D84
+		X"00000000", -- 00002D88
+		X"00000000", -- 00002D8C
+		X"00000000", -- 00002D90
+		X"00000000", -- 00002D94
+		X"00000000", -- 00002D98
+		X"00000000", -- 00002D9C
+		X"00000000", -- 00002DA0
+		X"00000000", -- 00002DA4
+		X"00000000", -- 00002DA8
+		X"00000000", -- 00002DAC
+		X"00000000", -- 00002DB0
+		X"00000000", -- 00002DB4
+		X"00000000", -- 00002DB8
+		X"00000000", -- 00002DBC
+		X"00000000", -- 00002DC0
+		X"00000000", -- 00002DC4
+		X"00000000", -- 00002DC8
+		X"00000000", -- 00002DCC
+		X"00000000", -- 00002DD0
+		X"00000000", -- 00002DD4
+		X"00000000", -- 00002DD8
+		X"00000000", -- 00002DDC
+		X"00000000", -- 00002DE0
+		X"00000000", -- 00002DE4
+		X"00000000", -- 00002DE8
+		X"00000000", -- 00002DEC
+		X"00000000", -- 00002DF0
+		X"00000000", -- 00002DF4
+		X"00000000", -- 00002DF8
+		X"00000000", -- 00002DFC
+		X"00000000", -- 00002E00
+		X"00000000", -- 00002E04
+		X"00000000", -- 00002E08
+		X"00000000", -- 00002E0C
+		X"00000000", -- 00002E10
+		X"00000000", -- 00002E14
+		X"00000000", -- 00002E18
+		X"00000000", -- 00002E1C
+		X"00000000", -- 00002E20
+		X"00000000", -- 00002E24
+		X"00000000", -- 00002E28
+		X"00000000", -- 00002E2C
+		X"00000000", -- 00002E30
+		X"00000000", -- 00002E34
+		X"00000000", -- 00002E38
+		X"00000000", -- 00002E3C
+		X"00000000", -- 00002E40
+		X"00000000", -- 00002E44
+		X"00000000", -- 00002E48
+		X"00000000", -- 00002E4C
+		X"00000000", -- 00002E50
+		X"00000000", -- 00002E54
+		X"00000000", -- 00002E58
+		X"00000000", -- 00002E5C
+		X"00000000", -- 00002E60
+		X"00000000", -- 00002E64
+		X"00000000", -- 00002E68
+		X"00000000", -- 00002E6C
+		X"00000000", -- 00002E70
+		X"00000000", -- 00002E74
+		X"00000000", -- 00002E78
+		X"00000000", -- 00002E7C
+		X"00000000", -- 00002E80
+		X"00000000", -- 00002E84
+		X"00000000", -- 00002E88
+		X"00000000", -- 00002E8C
+		X"00000000", -- 00002E90
+		X"00000000", -- 00002E94
+		X"00000000", -- 00002E98
+		X"00000000", -- 00002E9C
+		X"00000000", -- 00002EA0
+		X"00000000", -- 00002EA4
+		X"00000000", -- 00002EA8
+		X"00000000", -- 00002EAC
+		X"00000000", -- 00002EB0
+		X"00000000", -- 00002EB4
+		X"00000000", -- 00002EB8
+		X"00000000", -- 00002EBC
+		X"00000000", -- 00002EC0
+		X"00000000", -- 00002EC4
+		X"00000000", -- 00002EC8
+		X"00000000", -- 00002ECC
+		X"00000000", -- 00002ED0
+		X"00000000", -- 00002ED4
+		X"00000000", -- 00002ED8
+		X"00000000", -- 00002EDC
+		X"00000000", -- 00002EE0
+		X"00000000", -- 00002EE4
+		X"00000000", -- 00002EE8
+		X"00000000", -- 00002EEC
+		X"00000000", -- 00002EF0
+		X"00000000", -- 00002EF4
+		X"00000000", -- 00002EF8
+		X"00000000", -- 00002EFC
+		X"00000000", -- 00002F00
+		X"00000000", -- 00002F04
+		X"00000000", -- 00002F08
+		X"00000000", -- 00002F0C
+		X"00000000", -- 00002F10
+		X"00000000", -- 00002F14
+		X"00000000", -- 00002F18
+		X"00000000", -- 00002F1C
+		X"00000000", -- 00002F20
+		X"00000000", -- 00002F24
+		X"00000000", -- 00002F28
+		X"00000000", -- 00002F2C
+		X"00000000", -- 00002F30
+		X"00000000", -- 00002F34
+		X"00000000", -- 00002F38
+		X"00000000", -- 00002F3C
+		X"00000000", -- 00002F40
+		X"00000000", -- 00002F44
+		X"00000000", -- 00002F48
+		X"00000000", -- 00002F4C
+		X"00000000", -- 00002F50
+		X"00000000", -- 00002F54
+		X"00000000", -- 00002F58
+		X"00000000", -- 00002F5C
+		X"00000000", -- 00002F60
+		X"00000000", -- 00002F64
+		X"00000000", -- 00002F68
+		X"00000000", -- 00002F6C
+		X"00000000", -- 00002F70
+		X"00000000", -- 00002F74
+		X"00000000", -- 00002F78
+		X"00000000", -- 00002F7C
+		X"00000000", -- 00002F80
+		X"00000000", -- 00002F84
+		X"00000000", -- 00002F88
+		X"00000000", -- 00002F8C
+		X"00000000", -- 00002F90
+		X"00000000", -- 00002F94
+		X"00000000", -- 00002F98
+		X"00000000", -- 00002F9C
+		X"00000000", -- 00002FA0
+		X"00000000", -- 00002FA4
+		X"00000000", -- 00002FA8
+		X"00000000", -- 00002FAC
+		X"00000000", -- 00002FB0
+		X"00000000", -- 00002FB4
+		X"00000000", -- 00002FB8
+		X"00000000", -- 00002FBC
+		X"00000000", -- 00002FC0
+		X"00000000", -- 00002FC4
+		X"00000000", -- 00002FC8
+		X"00000000", -- 00002FCC
+		X"00000000", -- 00002FD0
+		X"00000000", -- 00002FD4
+		X"00000000", -- 00002FD8
+		X"00000000", -- 00002FDC
+		X"00000000", -- 00002FE0
+		X"00000000", -- 00002FE4
+		X"00000000", -- 00002FE8
+		X"00000000", -- 00002FEC
+		X"00000000", -- 00002FF0
+		X"00000000", -- 00002FF4
+		X"00000000", -- 00002FF8
+		X"00000000", -- 00002FFC
+		X"00000000", -- 00003000
+		X"00000000", -- 00003004
+		X"00000000", -- 00003008
+		X"00000000", -- 0000300C
+		X"00000000", -- 00003010
+		X"00000000", -- 00003014
+		X"00000000", -- 00003018
+		X"00000000", -- 0000301C
+		X"00000000", -- 00003020
+		X"00000000", -- 00003024
+		X"00000000", -- 00003028
+		X"00000000", -- 0000302C
+		X"00000000", -- 00003030
+		X"00000000", -- 00003034
+		X"00000000", -- 00003038
+		X"00000000", -- 0000303C
+		X"00000000", -- 00003040
+		X"00000000", -- 00003044
+		X"00000000", -- 00003048
+		X"00000000", -- 0000304C
+		X"00000000", -- 00003050
+		X"00000000", -- 00003054
+		X"00000000", -- 00003058
+		X"00000000", -- 0000305C
+		X"00000000", -- 00003060
+		X"00000000", -- 00003064
+		X"00000000", -- 00003068
+		X"00000000", -- 0000306C
+		X"00000000", -- 00003070
+		X"00000000", -- 00003074
+		X"00000000", -- 00003078
+		X"00000000", -- 0000307C
+		X"00000000", -- 00003080
+		X"00000000", -- 00003084
+		X"00000000", -- 00003088
+		X"00000000", -- 0000308C
+		X"00000000", -- 00003090
+		X"00000000", -- 00003094
+		X"00000000", -- 00003098
+		X"00000000", -- 0000309C
+		X"00000000", -- 000030A0
+		X"00000000", -- 000030A4
+		X"00000000", -- 000030A8
+		X"00000000", -- 000030AC
+		X"00000000", -- 000030B0
+		X"00000000", -- 000030B4
+		X"00000000", -- 000030B8
+		X"00000000", -- 000030BC
+		X"00000000", -- 000030C0
+		X"00000000", -- 000030C4
+		X"00000000", -- 000030C8
+		X"00000000", -- 000030CC
+		X"00000000", -- 000030D0
+		X"00000000", -- 000030D4
+		X"00000000", -- 000030D8
+		X"00000000", -- 000030DC
+		X"00000000", -- 000030E0
+		X"00000000", -- 000030E4
+		X"00000000", -- 000030E8
+		X"00000000", -- 000030EC
+		X"00000000", -- 000030F0
+		X"00000000", -- 000030F4
+		X"00000000", -- 000030F8
+		X"00000000", -- 000030FC
+		X"00000000", -- 00003100
+		X"00000000", -- 00003104
+		X"00000000", -- 00003108
+		X"00000000", -- 0000310C
+		X"00000000", -- 00003110
+		X"00000000", -- 00003114
+		X"00000000", -- 00003118
+		X"00000000", -- 0000311C
+		X"00000000", -- 00003120
+		X"00000000", -- 00003124
+		X"00000000", -- 00003128
+		X"00000000", -- 0000312C
+		X"00000000", -- 00003130
+		X"00000000", -- 00003134
+		X"00000000", -- 00003138
+		X"00000000", -- 0000313C
+		X"00000000", -- 00003140
+		X"00000000", -- 00003144
+		X"00000000", -- 00003148
+		X"00000000", -- 0000314C
+		X"00000000", -- 00003150
+		X"00000000", -- 00003154
+		X"00000000", -- 00003158
+		X"00000000", -- 0000315C
+		X"00000000", -- 00003160
+		X"00000000", -- 00003164
+		X"00000000", -- 00003168
+		X"00000000", -- 0000316C
+		X"00000000", -- 00003170
+		X"00000000", -- 00003174
+		X"00000000", -- 00003178
+		X"00000000", -- 0000317C
+		X"00000000", -- 00003180
+		X"00000000", -- 00003184
+		X"00000000", -- 00003188
+		X"00000000", -- 0000318C
+		X"00000000", -- 00003190
+		X"00000000", -- 00003194
+		X"00000000", -- 00003198
+		X"00000000", -- 0000319C
+		X"00000000", -- 000031A0
+		X"00000000", -- 000031A4
+		X"00000000", -- 000031A8
+		X"00000000", -- 000031AC
+		X"00000000", -- 000031B0
+		X"00000000", -- 000031B4
+		X"00000000", -- 000031B8
+		X"00000000", -- 000031BC
+		X"00000000", -- 000031C0
+		X"00000000", -- 000031C4
+		X"00000000", -- 000031C8
+		X"00000000", -- 000031CC
+		X"00000000", -- 000031D0
+		X"00000000", -- 000031D4
+		X"00000000", -- 000031D8
+		X"00000000", -- 000031DC
+		X"00000000", -- 000031E0
+		X"00000000", -- 000031E4
+		X"00000000", -- 000031E8
+		X"00000000", -- 000031EC
+		X"00000000", -- 000031F0
+		X"00000000", -- 000031F4
+		X"00000000", -- 000031F8
+		X"00000000", -- 000031FC
+		X"00000000", -- 00003200
+		X"00000000", -- 00003204
+		X"00000000", -- 00003208
+		X"00000000", -- 0000320C
+		X"00000000", -- 00003210
+		X"00000000", -- 00003214
+		X"00000000", -- 00003218
+		X"00000000", -- 0000321C
+		X"00000000", -- 00003220
+		X"00000000", -- 00003224
+		X"00000000", -- 00003228
+		X"00000000", -- 0000322C
+		X"00000000", -- 00003230
+		X"00000000", -- 00003234
+		X"00000000", -- 00003238
+		X"00000000", -- 0000323C
+		X"00000000", -- 00003240
+		X"00000000", -- 00003244
+		X"00000000", -- 00003248
+		X"00000000", -- 0000324C
+		X"00000000", -- 00003250
+		X"00000000", -- 00003254
+		X"00000000", -- 00003258
+		X"00000000", -- 0000325C
+		X"00000000", -- 00003260
+		X"00000000", -- 00003264
+		X"00000000", -- 00003268
+		X"00000000", -- 0000326C
+		X"00000000", -- 00003270
+		X"00000000", -- 00003274
+		X"00000000", -- 00003278
+		X"00000000", -- 0000327C
+		X"00000000", -- 00003280
+		X"00000000", -- 00003284
+		X"00000000", -- 00003288
+		X"00000000", -- 0000328C
+		X"00000000", -- 00003290
+		X"00000000", -- 00003294
+		X"00000000", -- 00003298
+		X"00000000", -- 0000329C
+		X"00000000", -- 000032A0
+		X"00000000", -- 000032A4
+		X"00000000", -- 000032A8
+		X"00000000", -- 000032AC
+		X"00000000", -- 000032B0
+		X"00000000", -- 000032B4
+		X"00000000", -- 000032B8
+		X"00000000", -- 000032BC
+		X"00000000", -- 000032C0
+		X"00000000", -- 000032C4
+		X"00000000", -- 000032C8
+		X"00000000", -- 000032CC
+		X"00000000", -- 000032D0
+		X"00000000", -- 000032D4
+		X"00000000", -- 000032D8
+		X"00000000", -- 000032DC
+		X"00000000", -- 000032E0
+		X"00000000", -- 000032E4
+		X"00000000", -- 000032E8
+		X"00000000", -- 000032EC
+		X"00000000", -- 000032F0
+		X"00000000", -- 000032F4
+		X"00000000", -- 000032F8
+		X"00000000", -- 000032FC
+		X"00000000", -- 00003300
+		X"00000000", -- 00003304
+		X"00000000", -- 00003308
+		X"00000000", -- 0000330C
+		X"00000000", -- 00003310
+		X"00000000", -- 00003314
+		X"00000000", -- 00003318
+		X"00000000", -- 0000331C
+		X"00000000", -- 00003320
+		X"00000000", -- 00003324
+		X"00000000", -- 00003328
+		X"00000000", -- 0000332C
+		X"00000000", -- 00003330
+		X"00000000", -- 00003334
+		X"00000000", -- 00003338
+		X"00000000", -- 0000333C
+		X"00000000", -- 00003340
+		X"00000000", -- 00003344
+		X"00000000", -- 00003348
+		X"00000000", -- 0000334C
+		X"00000000", -- 00003350
+		X"00000000", -- 00003354
+		X"00000000", -- 00003358
+		X"00000000", -- 0000335C
+		X"00000000", -- 00003360
+		X"00000000", -- 00003364
+		X"00000000", -- 00003368
+		X"00000000", -- 0000336C
+		X"00000000", -- 00003370
+		X"00000000", -- 00003374
+		X"00000000", -- 00003378
+		X"00000000", -- 0000337C
+		X"00000000", -- 00003380
+		X"00000000", -- 00003384
+		X"00000000", -- 00003388
+		X"00000000", -- 0000338C
+		X"00000000", -- 00003390
+		X"00000000", -- 00003394
+		X"00000000", -- 00003398
+		X"00000000", -- 0000339C
+		X"00000000", -- 000033A0
+		X"00000000", -- 000033A4
+		X"00000000", -- 000033A8
+		X"00000000", -- 000033AC
+		X"00000000", -- 000033B0
+		X"00000000", -- 000033B4
+		X"00000000", -- 000033B8
+		X"00000000", -- 000033BC
+		X"00000000", -- 000033C0
+		X"00000000", -- 000033C4
+		X"00000000", -- 000033C8
+		X"00000000", -- 000033CC
+		X"00000000", -- 000033D0
+		X"00000000", -- 000033D4
+		X"00000000", -- 000033D8
+		X"00000000", -- 000033DC
+		X"00000000", -- 000033E0
+		X"00000000", -- 000033E4
+		X"00000000", -- 000033E8
+		X"00000000", -- 000033EC
+		X"00000000", -- 000033F0
+		X"00000000", -- 000033F4
+		X"00000000", -- 000033F8
+		X"00000000", -- 000033FC
+		X"00000000", -- 00003400
+		X"00000000", -- 00003404
+		X"00000000", -- 00003408
+		X"00000000", -- 0000340C
+		X"00000000", -- 00003410
+		X"00000000", -- 00003414
+		X"00000000", -- 00003418
+		X"00000000", -- 0000341C
+		X"00000000", -- 00003420
+		X"00000000", -- 00003424
+		X"00000000", -- 00003428
+		X"00000000", -- 0000342C
+		X"00000000", -- 00003430
+		X"00000000", -- 00003434
+		X"00000000", -- 00003438
+		X"00000000", -- 0000343C
+		X"00000000", -- 00003440
+		X"00000000", -- 00003444
+		X"00000000", -- 00003448
+		X"00000000", -- 0000344C
+		X"00000000", -- 00003450
+		X"00000000", -- 00003454
+		X"00000000", -- 00003458
+		X"00000000", -- 0000345C
+		X"00000000", -- 00003460
+		X"00000000", -- 00003464
+		X"00000000", -- 00003468
+		X"00000000", -- 0000346C
+		X"00000000", -- 00003470
+		X"00000000", -- 00003474
+		X"00000000", -- 00003478
+		X"00000000", -- 0000347C
+		X"00000000", -- 00003480
+		X"00000000", -- 00003484
+		X"00000000", -- 00003488
+		X"00000000", -- 0000348C
+		X"00000000", -- 00003490
+		X"00000000", -- 00003494
+		X"00000000", -- 00003498
+		X"00000000", -- 0000349C
+		X"00000000", -- 000034A0
+		X"00000000", -- 000034A4
+		X"00000000", -- 000034A8
+		X"00000000", -- 000034AC
+		X"00000000", -- 000034B0
+		X"00000000", -- 000034B4
+		X"00000000", -- 000034B8
+		X"00000000", -- 000034BC
+		X"00000000", -- 000034C0
+		X"00000000", -- 000034C4
+		X"00000000", -- 000034C8
+		X"00000000", -- 000034CC
+		X"00000000", -- 000034D0
+		X"00000000", -- 000034D4
+		X"00000000", -- 000034D8
+		X"00000000", -- 000034DC
+		X"00000000", -- 000034E0
+		X"00000000", -- 000034E4
+		X"00000000", -- 000034E8
+		X"00000000", -- 000034EC
+		X"00000000", -- 000034F0
+		X"00000000", -- 000034F4
+		X"00000000", -- 000034F8
+		X"00000000", -- 000034FC
+		X"00000000", -- 00003500
+		X"00000000", -- 00003504
+		X"00000000", -- 00003508
+		X"00000000", -- 0000350C
+		X"00000000", -- 00003510
+		X"00000000", -- 00003514
+		X"00000000", -- 00003518
+		X"00000000", -- 0000351C
+		X"00000000", -- 00003520
+		X"00000000", -- 00003524
+		X"00000000", -- 00003528
+		X"00000000", -- 0000352C
+		X"00000000", -- 00003530
+		X"00000000", -- 00003534
+		X"00000000", -- 00003538
+		X"00000000", -- 0000353C
+		X"00000000", -- 00003540
+		X"00000000", -- 00003544
+		X"00000000", -- 00003548
+		X"00000000", -- 0000354C
+		X"00000000", -- 00003550
+		X"00000000", -- 00003554
+		X"00000000", -- 00003558
+		X"00000000", -- 0000355C
+		X"00000000", -- 00003560
+		X"00000000", -- 00003564
+		X"00000000", -- 00003568
+		X"00000000", -- 0000356C
+		X"00000000", -- 00003570
+		X"00000000", -- 00003574
+		X"00000000", -- 00003578
+		X"00000000", -- 0000357C
+		X"00000000", -- 00003580
+		X"00000000", -- 00003584
+		X"00000000", -- 00003588
+		X"00000000", -- 0000358C
+		X"00000000", -- 00003590
+		X"00000000", -- 00003594
+		X"00000000", -- 00003598
+		X"00000000", -- 0000359C
+		X"00000000", -- 000035A0
+		X"00000000", -- 000035A4
+		X"00000000", -- 000035A8
+		X"00000000", -- 000035AC
+		X"00000000", -- 000035B0
+		X"00000000", -- 000035B4
+		X"00000000", -- 000035B8
+		X"00000000", -- 000035BC
+		X"00000000", -- 000035C0
+		X"00000000", -- 000035C4
+		X"00000000", -- 000035C8
+		X"00000000", -- 000035CC
+		X"00000000", -- 000035D0
+		X"00000000", -- 000035D4
+		X"00000000", -- 000035D8
+		X"00000000", -- 000035DC
+		X"00000000", -- 000035E0
+		X"00000000", -- 000035E4
+		X"00000000", -- 000035E8
+		X"00000000", -- 000035EC
+		X"00000000", -- 000035F0
+		X"00000000", -- 000035F4
+		X"00000000", -- 000035F8
+		X"00000000", -- 000035FC
+		X"00000000", -- 00003600
+		X"00000000", -- 00003604
+		X"00000000", -- 00003608
+		X"00000000", -- 0000360C
+		X"00000000", -- 00003610
+		X"00000000", -- 00003614
+		X"00000000", -- 00003618
+		X"00000000", -- 0000361C
+		X"00000000", -- 00003620
+		X"00000000", -- 00003624
+		X"00000000", -- 00003628
+		X"00000000", -- 0000362C
+		X"00000000", -- 00003630
+		X"00000000", -- 00003634
+		X"00000000", -- 00003638
+		X"00000000", -- 0000363C
+		X"00000000", -- 00003640
+		X"00000000", -- 00003644
+		X"00000000", -- 00003648
+		X"00000000", -- 0000364C
+		X"00000000", -- 00003650
+		X"00000000", -- 00003654
+		X"00000000", -- 00003658
+		X"00000000", -- 0000365C
+		X"00000000", -- 00003660
+		X"00000000", -- 00003664
+		X"00000000", -- 00003668
+		X"00000000", -- 0000366C
+		X"00000000", -- 00003670
+		X"00000000", -- 00003674
+		X"00000000", -- 00003678
+		X"00000000", -- 0000367C
+		X"00000000", -- 00003680
+		X"00000000", -- 00003684
+		X"00000000", -- 00003688
+		X"00000000", -- 0000368C
+		X"00000000", -- 00003690
+		X"00000000", -- 00003694
+		X"00000000", -- 00003698
+		X"00000000", -- 0000369C
+		X"00000000", -- 000036A0
+		X"00000000", -- 000036A4
+		X"00000000", -- 000036A8
+		X"00000000", -- 000036AC
+		X"00000000", -- 000036B0
+		X"00000000", -- 000036B4
+		X"00000000", -- 000036B8
+		X"00000000", -- 000036BC
+		X"00000000", -- 000036C0
+		X"00000000", -- 000036C4
+		X"00000000", -- 000036C8
+		X"00000000", -- 000036CC
+		X"00000000", -- 000036D0
+		X"00000000", -- 000036D4
+		X"00000000", -- 000036D8
+		X"00000000", -- 000036DC
+		X"00000000", -- 000036E0
+		X"00000000", -- 000036E4
+		X"00000000", -- 000036E8
+		X"00000000", -- 000036EC
+		X"00000000", -- 000036F0
+		X"00000000", -- 000036F4
+		X"00000000", -- 000036F8
+		X"00000000", -- 000036FC
+		X"00000000", -- 00003700
+		X"00000000", -- 00003704
+		X"00000000", -- 00003708
+		X"00000000", -- 0000370C
+		X"00000000", -- 00003710
+		X"00000000", -- 00003714
+		X"00000000", -- 00003718
+		X"00000000", -- 0000371C
+		X"00000000", -- 00003720
+		X"00000000", -- 00003724
+		X"00000000", -- 00003728
+		X"00000000", -- 0000372C
+		X"00000000", -- 00003730
+		X"00000000", -- 00003734
+		X"00000000", -- 00003738
+		X"00000000", -- 0000373C
+		X"00000000", -- 00003740
+		X"00000000", -- 00003744
+		X"00000000", -- 00003748
+		X"00000000", -- 0000374C
+		X"00000000", -- 00003750
+		X"00000000", -- 00003754
+		X"00000000", -- 00003758
+		X"00000000", -- 0000375C
+		X"00000000", -- 00003760
+		X"00000000", -- 00003764
+		X"00000000", -- 00003768
+		X"00000000", -- 0000376C
+		X"00000000", -- 00003770
+		X"00000000", -- 00003774
+		X"00000000", -- 00003778
+		X"00000000", -- 0000377C
+		X"00000000", -- 00003780
+		X"00000000", -- 00003784
+		X"00000000", -- 00003788
+		X"00000000", -- 0000378C
+		X"00000000", -- 00003790
+		X"00000000", -- 00003794
+		X"00000000", -- 00003798
+		X"00000000", -- 0000379C
+		X"00000000", -- 000037A0
+		X"00000000", -- 000037A4
+		X"00000000", -- 000037A8
+		X"00000000", -- 000037AC
+		X"00000000", -- 000037B0
+		X"00000000", -- 000037B4
+		X"00000000", -- 000037B8
+		X"00000000", -- 000037BC
+		X"00000000", -- 000037C0
+		X"00000000", -- 000037C4
+		X"00000000", -- 000037C8
+		X"00000000", -- 000037CC
+		X"00000000", -- 000037D0
+		X"00000000", -- 000037D4
+		X"00000000", -- 000037D8
+		X"00000000", -- 000037DC
+		X"00000000", -- 000037E0
+		X"00000000", -- 000037E4
+		X"00000000", -- 000037E8
+		X"00000000", -- 000037EC
+		X"00000000", -- 000037F0
+		X"00000000", -- 000037F4
+		X"00000000", -- 000037F8
+		X"00000000", -- 000037FC
+		X"00000000", -- 00003800
+		X"00000000", -- 00003804
+		X"00000000", -- 00003808
+		X"00000000", -- 0000380C
+		X"00000000", -- 00003810
+		X"00000000", -- 00003814
+		X"00000000", -- 00003818
+		X"00000000", -- 0000381C
+		X"00000000", -- 00003820
+		X"00000000", -- 00003824
+		X"00000000", -- 00003828
+		X"00000000", -- 0000382C
+		X"00000000", -- 00003830
+		X"00000000", -- 00003834
+		X"00000000", -- 00003838
+		X"00000000", -- 0000383C
+		X"00000000", -- 00003840
+		X"00000000", -- 00003844
+		X"00000000", -- 00003848
+		X"00000000", -- 0000384C
+		X"00000000", -- 00003850
+		X"00000000", -- 00003854
+		X"00000000", -- 00003858
+		X"00000000", -- 0000385C
+		X"00000000", -- 00003860
+		X"00000000", -- 00003864
+		X"00000000", -- 00003868
+		X"00000000", -- 0000386C
+		X"00000000", -- 00003870
+		X"00000000", -- 00003874
+		X"00000000", -- 00003878
+		X"00000000", -- 0000387C
+		X"00000000", -- 00003880
+		X"00000000", -- 00003884
+		X"00000000", -- 00003888
+		X"00000000", -- 0000388C
+		X"00000000", -- 00003890
+		X"00000000", -- 00003894
+		X"00000000", -- 00003898
+		X"00000000", -- 0000389C
+		X"00000000", -- 000038A0
+		X"00000000", -- 000038A4
+		X"00000000", -- 000038A8
+		X"00000000", -- 000038AC
+		X"00000000", -- 000038B0
+		X"00000000", -- 000038B4
+		X"00000000", -- 000038B8
+		X"00000000", -- 000038BC
+		X"00000000", -- 000038C0
+		X"00000000", -- 000038C4
+		X"00000000", -- 000038C8
+		X"00000000", -- 000038CC
+		X"00000000", -- 000038D0
+		X"00000000", -- 000038D4
+		X"00000000", -- 000038D8
+		X"00000000", -- 000038DC
+		X"00000000", -- 000038E0
+		X"00000000", -- 000038E4
+		X"00000000", -- 000038E8
+		X"00000000", -- 000038EC
+		X"00000000", -- 000038F0
+		X"00000000", -- 000038F4
+		X"00000000", -- 000038F8
+		X"00000000", -- 000038FC
+		X"00000000", -- 00003900
+		X"00000000", -- 00003904
+		X"00000000", -- 00003908
+		X"00000000", -- 0000390C
+		X"00000000", -- 00003910
+		X"00000000", -- 00003914
+		X"00000000", -- 00003918
+		X"00000000", -- 0000391C
+		X"00000000", -- 00003920
+		X"00000000", -- 00003924
+		X"00000000", -- 00003928
+		X"00000000", -- 0000392C
+		X"00000000", -- 00003930
+		X"00000000", -- 00003934
+		X"00000000", -- 00003938
+		X"00000000", -- 0000393C
+		X"00000000", -- 00003940
+		X"00000000", -- 00003944
+		X"00000000", -- 00003948
+		X"00000000", -- 0000394C
+		X"00000000", -- 00003950
+		X"00000000", -- 00003954
+		X"00000000", -- 00003958
+		X"00000000", -- 0000395C
+		X"00000000", -- 00003960
+		X"00000000", -- 00003964
+		X"00000000", -- 00003968
+		X"00000000", -- 0000396C
+		X"00000000", -- 00003970
+		X"00000000", -- 00003974
+		X"00000000", -- 00003978
+		X"00000000", -- 0000397C
+		X"00000000", -- 00003980
+		X"00000000", -- 00003984
+		X"00000000", -- 00003988
+		X"00000000", -- 0000398C
+		X"00000000", -- 00003990
+		X"00000000", -- 00003994
+		X"00000000", -- 00003998
+		X"00000000", -- 0000399C
+		X"00000000", -- 000039A0
+		X"00000000", -- 000039A4
+		X"00000000", -- 000039A8
+		X"00000000", -- 000039AC
+		X"00000000", -- 000039B0
+		X"00000000", -- 000039B4
+		X"00000000", -- 000039B8
+		X"00000000", -- 000039BC
+		X"00000000", -- 000039C0
+		X"00000000", -- 000039C4
+		X"00000000", -- 000039C8
+		X"00000000", -- 000039CC
+		X"00000000", -- 000039D0
+		X"00000000", -- 000039D4
+		X"00000000", -- 000039D8
+		X"00000000", -- 000039DC
+		X"00000000", -- 000039E0
+		X"00000000", -- 000039E4
+		X"00000000", -- 000039E8
+		X"00000000", -- 000039EC
+		X"00000000", -- 000039F0
+		X"00000000", -- 000039F4
+		X"00000000", -- 000039F8
+		X"00000000", -- 000039FC
+		X"00000000", -- 00003A00
+		X"00000000", -- 00003A04
+		X"00000000", -- 00003A08
+		X"00000000", -- 00003A0C
+		X"00000000", -- 00003A10
+		X"00000000", -- 00003A14
+		X"00000000", -- 00003A18
+		X"00000000", -- 00003A1C
+		X"00000000", -- 00003A20
+		X"00000000", -- 00003A24
+		X"00000000", -- 00003A28
+		X"00000000", -- 00003A2C
+		X"00000000", -- 00003A30
+		X"00000000", -- 00003A34
+		X"00000000", -- 00003A38
+		X"00000000", -- 00003A3C
+		X"00000000", -- 00003A40
+		X"00000000", -- 00003A44
+		X"00000000", -- 00003A48
+		X"00000000", -- 00003A4C
+		X"00000000", -- 00003A50
+		X"00000000", -- 00003A54
+		X"00000000", -- 00003A58
+		X"00000000", -- 00003A5C
+		X"00000000", -- 00003A60
+		X"00000000", -- 00003A64
+		X"00000000", -- 00003A68
+		X"00000000", -- 00003A6C
+		X"00000000", -- 00003A70
+		X"00000000", -- 00003A74
+		X"00000000", -- 00003A78
+		X"00000000", -- 00003A7C
+		X"00000000", -- 00003A80
+		X"00000000", -- 00003A84
+		X"00000000", -- 00003A88
+		X"00000000", -- 00003A8C
+		X"00000000", -- 00003A90
+		X"00000000", -- 00003A94
+		X"00000000", -- 00003A98
+		X"00000000", -- 00003A9C
+		X"00000000", -- 00003AA0
+		X"00000000", -- 00003AA4
+		X"00000000", -- 00003AA8
+		X"00000000", -- 00003AAC
+		X"00000000", -- 00003AB0
+		X"00000000", -- 00003AB4
+		X"00000000", -- 00003AB8
+		X"00000000", -- 00003ABC
+		X"00000000", -- 00003AC0
+		X"00000000", -- 00003AC4
+		X"00000000", -- 00003AC8
+		X"00000000", -- 00003ACC
+		X"00000000", -- 00003AD0
+		X"00000000", -- 00003AD4
+		X"00000000", -- 00003AD8
+		X"00000000", -- 00003ADC
+		X"00000000", -- 00003AE0
+		X"00000000", -- 00003AE4
+		X"00000000", -- 00003AE8
+		X"00000000", -- 00003AEC
+		X"00000000", -- 00003AF0
+		X"00000000", -- 00003AF4
+		X"00000000", -- 00003AF8
+		X"00000000", -- 00003AFC
+		X"00000000", -- 00003B00
+		X"00000000", -- 00003B04
+		X"00000000", -- 00003B08
+		X"00000000", -- 00003B0C
+		X"00000000", -- 00003B10
+		X"00000000", -- 00003B14
+		X"00000000", -- 00003B18
+		X"00000000", -- 00003B1C
+		X"00000000", -- 00003B20
+		X"00000000", -- 00003B24
+		X"00000000", -- 00003B28
+		X"00000000", -- 00003B2C
+		X"00000000", -- 00003B30
+		X"00000000", -- 00003B34
+		X"00000000", -- 00003B38
+		X"00000000", -- 00003B3C
+		X"00000000", -- 00003B40
+		X"00000000", -- 00003B44
+		X"00000000", -- 00003B48
+		X"00000000", -- 00003B4C
+		X"00000000", -- 00003B50
+		X"00000000", -- 00003B54
+		X"00000000", -- 00003B58
+		X"00000000", -- 00003B5C
+		X"00000000", -- 00003B60
+		X"00000000", -- 00003B64
+		X"00000000", -- 00003B68
+		X"00000000", -- 00003B6C
+		X"00000000", -- 00003B70
+		X"00000000", -- 00003B74
+		X"00000000", -- 00003B78
+		X"00000000", -- 00003B7C
+		X"00000000", -- 00003B80
+		X"00000000", -- 00003B84
+		X"00000000", -- 00003B88
+		X"00000000", -- 00003B8C
+		X"00000000", -- 00003B90
+		X"00000000", -- 00003B94
+		X"00000000", -- 00003B98
+		X"00000000", -- 00003B9C
+		X"00000000", -- 00003BA0
+		X"00000000", -- 00003BA4
+		X"00000000", -- 00003BA8
+		X"00000000", -- 00003BAC
+		X"00000000", -- 00003BB0
+		X"00000000", -- 00003BB4
+		X"00000000", -- 00003BB8
+		X"00000000", -- 00003BBC
+		X"00000000", -- 00003BC0
+		X"00000000", -- 00003BC4
+		X"00000000", -- 00003BC8
+		X"00000000", -- 00003BCC
+		X"00000000", -- 00003BD0
+		X"00000000", -- 00003BD4
+		X"00000000", -- 00003BD8
+		X"00000000", -- 00003BDC
+		X"00000000", -- 00003BE0
+		X"00000000", -- 00003BE4
+		X"00000000", -- 00003BE8
+		X"00000000", -- 00003BEC
+		X"00000000", -- 00003BF0
+		X"00000000", -- 00003BF4
+		X"00000000", -- 00003BF8
+		X"00000000", -- 00003BFC
+		X"00000000", -- 00003C00
+		X"00000000", -- 00003C04
+		X"00000000", -- 00003C08
+		X"00000000", -- 00003C0C
+		X"00000000", -- 00003C10
+		X"00000000", -- 00003C14
+		X"00000000", -- 00003C18
+		X"00000000", -- 00003C1C
+		X"00000000", -- 00003C20
+		X"00000000", -- 00003C24
+		X"00000000", -- 00003C28
+		X"00000000", -- 00003C2C
+		X"00000000", -- 00003C30
+		X"00000000", -- 00003C34
+		X"00000000", -- 00003C38
+		X"00000000", -- 00003C3C
+		X"00000000", -- 00003C40
+		X"00000000", -- 00003C44
+		X"00000000", -- 00003C48
+		X"00000000", -- 00003C4C
+		X"00000000", -- 00003C50
+		X"00000000", -- 00003C54
+		X"00000000", -- 00003C58
+		X"00000000", -- 00003C5C
+		X"00000000", -- 00003C60
+		X"00000000", -- 00003C64
+		X"00000000", -- 00003C68
+		X"00000000", -- 00003C6C
+		X"00000000", -- 00003C70
+		X"00000000", -- 00003C74
+		X"00000000", -- 00003C78
+		X"00000000", -- 00003C7C
+		X"00000000", -- 00003C80
+		X"00000000", -- 00003C84
+		X"00000000", -- 00003C88
+		X"00000000", -- 00003C8C
+		X"00000000", -- 00003C90
+		X"00000000", -- 00003C94
+		X"00000000", -- 00003C98
+		X"00000000", -- 00003C9C
+		X"00000000", -- 00003CA0
+		X"00000000", -- 00003CA4
+		X"00000000", -- 00003CA8
+		X"00000000", -- 00003CAC
+		X"00000000", -- 00003CB0
+		X"00000000", -- 00003CB4
+		X"00000000", -- 00003CB8
+		X"00000000", -- 00003CBC
+		X"00000000", -- 00003CC0
+		X"00000000", -- 00003CC4
+		X"00000000", -- 00003CC8
+		X"00000000", -- 00003CCC
+		X"00000000", -- 00003CD0
+		X"00000000", -- 00003CD4
+		X"00000000", -- 00003CD8
+		X"00000000", -- 00003CDC
+		X"00000000", -- 00003CE0
+		X"00000000", -- 00003CE4
+		X"00000000", -- 00003CE8
+		X"00000000", -- 00003CEC
+		X"00000000", -- 00003CF0
+		X"00000000", -- 00003CF4
+		X"00000000", -- 00003CF8
+		X"00000000", -- 00003CFC
+		X"00000000", -- 00003D00
+		X"00000000", -- 00003D04
+		X"00000000", -- 00003D08
+		X"00000000", -- 00003D0C
+		X"00000000", -- 00003D10
+		X"00000000", -- 00003D14
+		X"00000000", -- 00003D18
+		X"00000000", -- 00003D1C
+		X"00000000", -- 00003D20
+		X"00000000", -- 00003D24
+		X"00000000", -- 00003D28
+		X"00000000", -- 00003D2C
+		X"00000000", -- 00003D30
+		X"00000000", -- 00003D34
+		X"00000000", -- 00003D38
+		X"00000000", -- 00003D3C
+		X"00000000", -- 00003D40
+		X"00000000", -- 00003D44
+		X"00000000", -- 00003D48
+		X"00000000", -- 00003D4C
+		X"00000000", -- 00003D50
+		X"00000000", -- 00003D54
+		X"00000000", -- 00003D58
+		X"00000000", -- 00003D5C
+		X"00000000", -- 00003D60
+		X"00000000", -- 00003D64
+		X"00000000", -- 00003D68
+		X"00000000", -- 00003D6C
+		X"00000000", -- 00003D70
+		X"00000000", -- 00003D74
+		X"00000000", -- 00003D78
+		X"00000000", -- 00003D7C
+		X"00000000", -- 00003D80
+		X"00000000", -- 00003D84
+		X"00000000", -- 00003D88
+		X"00000000", -- 00003D8C
+		X"00000000", -- 00003D90
+		X"00000000", -- 00003D94
+		X"00000000", -- 00003D98
+		X"00000000", -- 00003D9C
+		X"00000000", -- 00003DA0
+		X"00000000", -- 00003DA4
+		X"00000000", -- 00003DA8
+		X"00000000", -- 00003DAC
+		X"00000000", -- 00003DB0
+		X"00000000", -- 00003DB4
+		X"00000000", -- 00003DB8
+		X"00000000", -- 00003DBC
+		X"00000000", -- 00003DC0
+		X"00000000", -- 00003DC4
+		X"00000000", -- 00003DC8
+		X"00000000", -- 00003DCC
+		X"00000000", -- 00003DD0
+		X"00000000", -- 00003DD4
+		X"00000000", -- 00003DD8
+		X"00000000", -- 00003DDC
+		X"00000000", -- 00003DE0
+		X"00000000", -- 00003DE4
+		X"00000000", -- 00003DE8
+		X"00000000", -- 00003DEC
+		X"00000000", -- 00003DF0
+		X"00000000", -- 00003DF4
+		X"00000000", -- 00003DF8
+		X"00000000", -- 00003DFC
+		X"00000000", -- 00003E00
+		X"00000000", -- 00003E04
+		X"00000000", -- 00003E08
+		X"00000000", -- 00003E0C
+		X"00000000", -- 00003E10
+		X"00000000", -- 00003E14
+		X"00000000", -- 00003E18
+		X"00000000", -- 00003E1C
+		X"00000000", -- 00003E20
+		X"00000000", -- 00003E24
+		X"00000000", -- 00003E28
+		X"00000000", -- 00003E2C
+		X"00000000", -- 00003E30
+		X"00000000", -- 00003E34
+		X"00000000", -- 00003E38
+		X"00000000", -- 00003E3C
+		X"00000000", -- 00003E40
+		X"00000000", -- 00003E44
+		X"00000000", -- 00003E48
+		X"00000000", -- 00003E4C
+		X"00000000", -- 00003E50
+		X"00000000", -- 00003E54
+		X"00000000", -- 00003E58
+		X"00000000", -- 00003E5C
+		X"00000000", -- 00003E60
+		X"00000000", -- 00003E64
+		X"00000000", -- 00003E68
+		X"00000000", -- 00003E6C
+		X"00000000", -- 00003E70
+		X"00000000", -- 00003E74
+		X"00000000", -- 00003E78
+		X"00000000", -- 00003E7C
+		X"00000000", -- 00003E80
+		X"00000000", -- 00003E84
+		X"00000000", -- 00003E88
+		X"00000000", -- 00003E8C
+		X"00000000", -- 00003E90
+		X"00000000", -- 00003E94
+		X"00000000", -- 00003E98
+		X"00000000", -- 00003E9C
+		X"00000000", -- 00003EA0
+		X"00000000", -- 00003EA4
+		X"00000000", -- 00003EA8
+		X"00000000", -- 00003EAC
+		X"00000000", -- 00003EB0
+		X"00000000", -- 00003EB4
+		X"00000000", -- 00003EB8
+		X"00000000", -- 00003EBC
+		X"00000000", -- 00003EC0
+		X"00000000", -- 00003EC4
+		X"00000000", -- 00003EC8
+		X"00000000", -- 00003ECC
+		X"00000000", -- 00003ED0
+		X"00000000", -- 00003ED4
+		X"00000000", -- 00003ED8
+		X"00000000", -- 00003EDC
+		X"00000000", -- 00003EE0
+		X"00000000", -- 00003EE4
+		X"00000000", -- 00003EE8
+		X"00000000", -- 00003EEC
+		X"00000000", -- 00003EF0
+		X"00000000", -- 00003EF4
+		X"00000000", -- 00003EF8
+		X"00000000", -- 00003EFC
+		X"00000000", -- 00003F00
+		X"00000000", -- 00003F04
+		X"00000000", -- 00003F08
+		X"00000000", -- 00003F0C
+		X"00000000", -- 00003F10
+		X"00000000", -- 00003F14
+		X"00000000", -- 00003F18
+		X"00000000", -- 00003F1C
+		X"00000000", -- 00003F20
+		X"00000000", -- 00003F24
+		X"00000000", -- 00003F28
+		X"00000000", -- 00003F2C
+		X"00000000", -- 00003F30
+		X"00000000", -- 00003F34
+		X"00000000", -- 00003F38
+		X"00000000", -- 00003F3C
+		X"00000000", -- 00003F40
+		X"00000000", -- 00003F44
+		X"00000000", -- 00003F48
+		X"00000000", -- 00003F4C
+		X"00000000", -- 00003F50
+		X"00000000", -- 00003F54
+		X"00000000", -- 00003F58
+		X"00000000", -- 00003F5C
+		X"00000000", -- 00003F60
+		X"00000000", -- 00003F64
+		X"00000000", -- 00003F68
+		X"00000000", -- 00003F6C
+		X"00000000", -- 00003F70
+		X"00000000", -- 00003F74
+		X"00000000", -- 00003F78
+		X"00000000", -- 00003F7C
+		X"00000000", -- 00003F80
+		X"00000000", -- 00003F84
+		X"00000000", -- 00003F88
+		X"00000000", -- 00003F8C
+		X"00000000", -- 00003F90
+		X"00000000", -- 00003F94
+		X"00000000", -- 00003F98
+		X"00000000", -- 00003F9C
+		X"00000000", -- 00003FA0
+		X"00000000", -- 00003FA4
+		X"00000000", -- 00003FA8
+		X"00000000", -- 00003FAC
+		X"00000000", -- 00003FB0
+		X"00000000", -- 00003FB4
+		X"00000000", -- 00003FB8
+		X"00000000", -- 00003FBC
+		X"00000000", -- 00003FC0
+		X"00000000", -- 00003FC4
+		X"00000000", -- 00003FC8
+		X"00000000", -- 00003FCC
+		X"00000000", -- 00003FD0
+		X"00000000", -- 00003FD4
+		X"00000000", -- 00003FD8
+		X"00000000", -- 00003FDC
+		X"00000000", -- 00003FE0
+		X"00000000", -- 00003FE4
+		X"00000000", -- 00003FE8
+		X"00000000", -- 00003FEC
+		X"00000000", -- 00003FF0
+		X"00000000", -- 00003FF4
+		X"00000000", -- 00003FF8
+		X"00000000"  -- 00003FFC
+	);
+
+begin
+
+PROM_READ:
+	process(clk)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= word_array(to_integer(addr(13 downto 2)));
+		end if;
+	end process;
+
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
+	jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;	
+	
+			end if;
+		end if;
+	end process;
+
+PROM_WRITE:
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				word_array(to_integer(jtag_ld_addr(11 downto 0))) <= jtag_ld_din;
+			else
+				jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(11 downto 0)));
+			end if;
+		end if;
+	end process;
+
+end data;
diff --git a/lib/CPUs/MIPS/tools/insrom.rb b/lib/CPUs/MIPS/tools/insrom.rb
new file mode 100644
index 0000000..fdbf1ed
--- /dev/null
+++ b/lib/CPUs/MIPS/tools/insrom.rb
@@ -0,0 +1,46 @@
+#!/usr/bin/env ruby
+
+# ----------------------------------------------------------------------
+# Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+# This file: Insertion of code fragments into templates
+#
+# Copyright (C) 2008 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+arg = $*
+rom_filename = arg[0].to_s
+tpl_filename = arg[1].to_s
+
+subst_pattern = "ROM_INSERT_HERE"
+
+# --------------------------------------------------------
+# Open file
+# --------------------------------------------------------
+romfile = File.open(rom_filename, "r")
+tplfile = File.open(tpl_filename, "r")
+re = Regexp.new(subst_pattern)
+
+while (line = tplfile.gets)
+	puts line
+	line.scan(re).each do |word|
+		romfile.each do |raw_line|
+			puts raw_line
+		end	
+	end
+end
diff --git a/lib/CPUs/MIPS/tools/irom.vhd.tpl b/lib/CPUs/MIPS/tools/irom.vhd.tpl
new file mode 100644
index 0000000..5ffd6d7
--- /dev/null
+++ b/lib/CPUs/MIPS/tools/irom.vhd.tpl
@@ -0,0 +1,29 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+-- ROM_INSERT_HERE
+
diff --git a/lib/CPUs/MIPS/tools/irom_ld.vhd.tpl b/lib/CPUs/MIPS/tools/irom_ld.vhd.tpl
new file mode 100644
index 0000000..3bd3afb
--- /dev/null
+++ b/lib/CPUs/MIPS/tools/irom_ld.vhd.tpl
@@ -0,0 +1,147 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+ENTITY irom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		addr		: in  inst_addr_t;
+		dout		: out inst_t
+	);
+	
+END irom;
+
+ARCHITECTURE loadable OF irom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: unsigned (15 downto 0);
+	signal jtag_ld_dout		: unsigned (31 downto 0);
+	signal jtag_ld_din		: unsigned (31 downto 0);
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (47 downto 0);
+	constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
+	jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;
diff --git a/lib/CPUs/MIPS/tools/make b/lib/CPUs/MIPS/tools/make
new file mode 100644
index 0000000..e7f598f
--- /dev/null
+++ b/lib/CPUs/MIPS/tools/make
@@ -0,0 +1,50 @@
+#!/bin/sh
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: rom-file generation for cpu_core
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+TARGET=$2
+DSTDIR=$1
+
+JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
+
+$JASM_HOME/jasm.rb $TARGET.jsm
+
+irom_tcl_snippet="$TARGET.irom.tcl.snip"
+irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
+irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
+xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
+xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
+xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
+
+$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
+$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
+
+$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
+$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
+
+cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
+cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
+$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
+
+rm -f *.snip
diff --git a/lib/CPUs/MIPS/tools/rom.tcl.tpl b/lib/CPUs/MIPS/tools/rom.tcl.tpl
new file mode 100644
index 0000000..9f5c0dc
--- /dev/null
+++ b/lib/CPUs/MIPS/tools/rom.tcl.tpl
@@ -0,0 +1,61 @@
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: The ROM file for upload to target over JTAG 
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+# ---------------------------------------------------------------------
+# For Chipscope 9.1
+# ---------------------------------------------------------------------
+# Source JTAG/TCL frame work
+cd $env(CHIPSCOPE)\\bin\\nt
+source csejtag.tcl
+
+namespace import ::chipscope::*
+
+# Platform USB Cable
+set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
+# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
+
+# Create session
+set handle [::chipscope::csejtag_session create 0]
+
+# Open JTAG and lock
+set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
+set lock_result [::chipscope::csejtag_target lock $handle 1000]
+
+set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
+
+# Get Device ID
+set devtype "Virtex-4SX"
+set devid 2
+set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
+set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
+
+set CSE_OP $CSEJTAG_SHIFT_READWRITE
+set CSE_ES $CSEJTAG_RUN_TEST_IDLE
+
+# Write Program
+# JASM_ROM_INSERT_HERE
+
+::chipscope::csejtag_target unlock $handle
+::chipscope::csejtag_target close $handle
+::chipscope::csejtag_session destroy $handle
+exit
diff --git a/lib/CPUs/MIPS/tools/src/ramgen.c b/lib/CPUs/MIPS/tools/src/ramgen.c
new file mode 100644
index 0000000..a266e35
--- /dev/null
+++ b/lib/CPUs/MIPS/tools/src/ramgen.c
@@ -0,0 +1,125 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#define ARCH_NAME			"data"
+#define ENT_NAME			"ram"
+#define JTAG_ADDR_WIDTH		16
+
+// --------------------------------------------------------------
+void basename(char *pSrc, char *pDst)
+{
+	int i, size;
+
+	size = strlen(pSrc);
+
+	while(pSrc[size] != '.')
+		size--;
+
+	for (i=0; i < size; i++)
+		pDst[i] = pSrc[i];
+
+	pDst[i] = 0;
+
+}
+
+int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, word_addr, filesize, romsize;
+	char binstr_addr[33];
+	char binstr_data[33];
+
+	char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fputs(tpl, pFileOut);
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
+	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
+	fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
+	fprintf(pFileOut, "# User 2\n");
+	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
+
+	word_addr = 0;
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
+		word_addr++;
+	}
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
+	fprintf(pFileOut, "exit\n");
+
+	return 0;
+}
+
+int main(int argc, char *argv[])
+{
+	char *pFilenameIn;
+	char name_prj[1024];
+	char name_rom_tcl[1024];
+
+	FILE *pFileIn;
+	int filesize, romsize, nbits_addr, nbits_data;
+	long start, end;
+	int word, i;
+
+	if (argc < 2)
+	{
+		fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
+		return 1;
+	}
+
+	pFilenameIn = argv[1];
+	if (argc == 3)
+		nbits_addr = atoi(argv[2]);
+
+
+	basename(pFilenameIn, name_prj);
+	sprintf(name_rom_tcl, "%s.tcl", name_prj);
+
+	SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+
+
+	return 0;
+}
+
diff --git a/lib/CPUs/MIPS/tools/src/romgen.c b/lib/CPUs/MIPS/tools/src/romgen.c
new file mode 100644
index 0000000..6d1ec5f
--- /dev/null
+++ b/lib/CPUs/MIPS/tools/src/romgen.c
@@ -0,0 +1,368 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+#define ARCH_NAME			"data"
+#define ENT_NAME			"icache"
+#define JTAG_ADDR_WIDTH		16
+
+// --------------------------------------------------------------
+void basename(char *pSrc, char *pDst)
+{
+	int i, size;
+
+	size = strlen(pSrc);
+
+	while(pSrc[size] != '.')
+		size--;
+
+	for (i=0; i < size; i++)
+		pDst[i] = pSrc[i];
+
+	pDst[i] = 0;
+
+}
+
+int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+
+	return 0;
+}
+
+int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, filesize, romsize;
+
+	char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n        I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n        I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0,       -- Data register output for USER functions\n\t\tRESET => bs_rst,       -- Reset output from TAP controller\n\t\tSEL => bs_sel,         -- USER active output\n\t\tSHIFT => bs_shift,     -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi,        -- TDI output from TAP controller\n\t\tUPDATE => bs_update0,   -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo         -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "LIBRARY IEEE;\n");
+	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
+	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "library UNISIM;\n");
+	fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
+	fprintf(pFileOut, "\tPort\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
+	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "END %s;\n", ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+
+	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
+
+	fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
+	fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
+	fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
+	fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
+	fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
+	fprintf(pFileOut, "\t(\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	word = 0;
+	for (; i < romsize; i += sizeof(int))
+	{
+		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
+		if (i < (romsize-sizeof(int)))
+			fprintf(pFileOut, ", -- %8.8X\n", i);
+		else
+			fprintf(pFileOut, "  -- %8.8X\n", i);
+	}
+	fprintf(pFileOut, "\t);\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "begin\n", ARCH_NAME);
+
+	fprintf(pFileOut, "\n");
+	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(clk)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
+	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "\n");
+	fputs(tpl, pFileOut);
+
+	fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
+	fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
+	fprintf(pFileOut, "\tbegin\n");
+	fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
+	fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
+	fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\telse\n");
+	fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
+	fprintf(pFileOut, "\t\t\tend if;\n");
+	fprintf(pFileOut, "\t\tend if;\n");
+	fprintf(pFileOut, "\tend process;\n");
+	fprintf(pFileOut, "\n");
+
+	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
+	return 0;
+}
+
+int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
+{
+	FILE *pFileIn, *pFileOut;
+	long start, end;
+	int i, word, word_addr, filesize, romsize;
+	char binstr_addr[33];
+	char binstr_data[33];
+
+	char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
+
+	pFileIn = fopen(pFilenameIn, "rb");
+	if (!pFileIn)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
+		return 1;
+	}
+
+	pFileOut = fopen(pFilenameOut, "wb");
+	if (!pFileOut)
+	{
+		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
+		return 1;
+	}
+
+	fseek(pFileIn, 0, SEEK_SET);
+	start = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_END);
+	end = ftell(pFileIn);
+	fseek(pFileIn, 0, SEEK_SET);
+
+	filesize = (end-start);
+	romsize = (int)pow(2, nbits_addr+2);
+
+	// -------------------------------------------------------------------------
+	// Header
+
+	// -------------------------------------------------------------------------
+	fputs(tpl, pFileOut);
+
+	// -------------------------------------------------------------------------
+	// ROM part
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
+	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
+	fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
+	fprintf(pFileOut, "# User 1\n");
+	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
+
+	word_addr = 0;
+	for (i=0; i < filesize; i += sizeof(int))
+	{
+		fread(&word, 1, sizeof(int), pFileIn);
+		fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
+		word_addr++;
+	}
+	fprintf(pFileOut, "\n");
+
+	// -------------------------------------------------------------------------
+	// Trailer
+	// -------------------------------------------------------------------------
+	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
+	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
+	fprintf(pFileOut, "exit\n");
+
+	return 0;
+}
+
+int main(int argc, char *argv[])
+{
+	char *pFilenameIn;
+	char name_prj[1024];
+	char name_rom[1024];
+	char name_rom_v4ld[1024];
+	char name_rom_tcl[1024];
+
+	FILE *pFileIn;
+	int filesize, romsize, nbits_addr, nbits_data;
+	long start, end;
+	int word, i;
+
+	if (argc < 2)
+	{
+		fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
+		return 1;
+	}
+
+	pFilenameIn = argv[1];
+	if (argc == 3)
+		nbits_addr = atoi(argv[2]);
+
+
+	basename(pFilenameIn, name_prj);
+	sprintf(name_rom, "%s.vhd", name_prj);
+	sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
+	sprintf(name_rom_tcl, "%s.tcl", name_prj);
+
+	SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+	SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+	SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
+
+
+	return 0;
+}
+