Initial import

git-svn-id: http://moon:8086/svn/vhdl/trunk@2 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/src/tb_mips_embedded.vhd

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+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: Testbench for JCPU
+--            also writes 'opc.lst' for JASM-assembler
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.mips_types.all;
+
+ENTITY tb_mips_embedded IS
+END tb_mips_embedded;
+
+ARCHITECTURE behavior OF tb_mips_embedded IS 
+
+	COMPONENT mips_embedded
+	Port 
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		halt		: in  STD_LOGIC;
+		dout		: out word_t
+	);
+	END COMPONENT;
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal rst 			: std_logic := '1';
+	signal clk 			: std_logic := '1';
+	signal halt			: std_logic := '0';
+	signal dout		 	: word_t;
+	
+BEGIN
+
+uut: mips_embedded
+	PORT MAP(
+		rst				=> rst,
+		clk				=> clk,
+		halt			=> halt,
+		dout			=> dout
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+STIMULUS: process
+	begin
+
+		wait for 3*CLK_PERIOD;
+		wait until rising_edge(clk);
+		rst <= '0';
+	
+		wait; 
+	
+	end process;
+
+END;