Initial import

git-svn-id: http://moon:8086/svn/vhdl/trunk@2 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/src/mips_muldiv.vhd

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+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: The arithmetic logic unit
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.mips_types.all;
+
+entity muldiv is
+	Port 
+	(
+		rst			: in  std_logic;
+		clk			: in  std_logic;
+		din_vld_hi	: in  std_logic;
+		din_vld_lo	: in  std_logic;
+		din_hi		: in  word_t;
+		din_lo		: in  word_t;
+		hilo_sel	: in  std_logic;
+		dout		: out word_t
+	);
+end muldiv;
+
+architecture Behavioral of muldiv is
+
+	signal reg_hi, reg_lo : word_t;
+	
+--------------------------------------------------------------------------
+begin
+
+--------------------------------------------------------------------------
+proc_reg_out:
+	process(hilo_sel, reg_hi, reg_lo)
+	begin
+		if hilo_sel = '1' then
+			dout <= reg_hi;
+		else	
+			dout <= reg_lo;
+		end if;
+	end process;	
+	
+proc_reg_in:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				reg_hi <= (others => '0');
+				reg_lo <= (others => '0');
+			elsif din_vld_hi = '1' then
+				if hilo_sel = '1' then
+					reg_hi <= din_hi;
+				else
+					reg_lo <= din_hi;
+				end if;
+			end if;
+			if din_vld_lo = '1' then
+				reg_lo <= din_lo;
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+end Behavioral;