Initial import

git-svn-id: http://moon:8086/svn/vhdl/trunk@2 cc03376c-175c-47c8-b038-4cd826a8556b
2008-08-23 07:19:47 +00:00
parent 6badec2df7
commit 335cc4e9d2
138 changed files with 40978 additions and 0 deletions
@@ -0,0 +1,6 @@
+vlib simprim
+
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd
+vcom -93 -work simprim  F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd
@@ -0,0 +1,6 @@
+vlib unisim
+
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd
+vcom -93 -work unisim  F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd
@@ -0,0 +1,13 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/tb_eval_muldiv.vhd"
+vsim -t 1ps   -lib work tb_eval_muldiv
+do {tb_eval_muldiv.wdo}
+view wave
+
+view structure
+view signals
+run 2400ns
@@ -0,0 +1,27 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_eval_muldiv/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op1_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op2_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp0
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp1
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp2
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp3
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result
+add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result_reg
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {693234 ps} 0} {{Cursor 2} {290409 ps} 0}
+configure wave -namecolwidth 149
+configure wave -valuecolwidth 171
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {2520 ns}
@@ -0,0 +1,22 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/core/mips_idecode_rom.vhd"
+vcom -explicit  -93 "../src/core/mips_reg.vhd"
+vcom -explicit  -93 "../src/core/mips_shifter.vhd"
+vcom -explicit  -93 "../src/core/mips_alu.vhd"
+vcom -explicit  -93 "../src/core/mips_bcu.vhd"
+vcom -explicit  -93 "../src/core/mips_pipeline.vhd"
+vcom -explicit  -93 "../src/core/mips_top.vhd"
+vcom -explicit  -93 "../src/ram.vhd"
+vcom -explicit  -93 "../asm/fibonacci.vhd"
+vcom -explicit  -93 "../src/mips_embedded.vhd"
+vcom -explicit  -93 "../src/tb_mips_embedded.vhd"
+vsim -t 1ps   -lib work tb_mips_embedded
+do {tb_mips_embedded.wdo}
+view wave
+view structure
+view signals
+run 20us
@@ -0,0 +1,41 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mips_embedded/rst
+add wave -noupdate -format Logic /tb_mips_embedded/clk
+add wave -noupdate -format Logic /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/exception
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/pc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_ram/sram
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_dout
+add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_re
+add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_din
+add wave -noupdate -format Logic /tb_mips_embedded/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/id_stage
+add wave -noupdate -format Logic /tb_mips_embedded/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/ex_stage
+add wave -noupdate -format Logic /tb_mips_embedded/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/mem_stage
+add wave -noupdate -format Logic /tb_mips_embedded/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/wb_stage
+add wave -noupdate -format Logic /tb_mips_embedded/clk
+add wave -noupdate -format Literal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/hdu
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {624000 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {2520 ns}
@@ -0,0 +1,31 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/core/mips_idecode_rom.vhd"
+vcom -explicit  -93 "../src/core/mips_reg.vhd"
+vcom -explicit  -93 "../src/core/mips_shifter.vhd"
+vcom -explicit  -93 "../src/core/mips_alu.vhd"
+vcom -explicit  -93 "../src/core/mips_bcu.vhd"
+vcom -explicit  -93 "../src/core/mips_pipeline.vhd"
+vcom -explicit  -93 "../src/core/mips_muldiv.vhd"
+vcom -explicit  -93 "../src/core/mips_cop.vhd"
+vcom -explicit  -93 "../src/core/mips_bui.vhd"
+vcom -explicit  -93 "../src/core/mips_top.vhd"
+vcom -explicit  -93 "../src/core/dcache.vhd"
+vcom -explicit  -93 "../asm/testbench.ROM.vhd"
+vcom -explicit  -93 "../src/mips_embedded.vhd"
+vcom -explicit  -93 "../src/mips_embedded_syn.vhd"
+vcom -explicit  -93 "../../../uart/bbfifo_16x8.vhd"
+vcom -explicit  -93 "../../../uart/kcuart_rx.vhd"
+vcom -explicit  -93 "../../../uart/kcuart_tx.vhd"
+vcom -explicit  -93 "../../../uart/uart_rx.vhd"
+vcom -explicit  -93 "../../../uart/uart_tx.vhd"
+vcom -explicit  -93 "../src/tb_mips_embedded_syn.vhd"
+vsim -t 1ps   -lib work tb_mips_embedded_syn
+do {tb_mips_embedded_syn.wdo}
+view wave
+view structure
+view signals
+run 100us
@@ -0,0 +1,13 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+
+vcom -explicit  -93 "../syn/ise9/netgen/par/mips_embedded_syn_timesim.vhd"
+vcom -explicit  -93 "../src/tb_mips_embedded_syn.vhd"
+vsim -t 1ps -sdfmax "/uut=../syn/ise9/netgen/par/mips_embedded_syn_timesim.sdf"  -lib work tb_mips_embedded_syn
+do {tb_mips_embedded_syn.wdo}
+view wave
+#add wave *
+view structure
+view signals
+run 2400ns
@@ -0,0 +1,112 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_rx
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_tx
+add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_rst_n_in
+add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_clk_in
+add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_led
+add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_dip
+add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_btn
+add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_error
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_rst
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_run
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_rx
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_tx
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_ctrl
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_baud
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/uart_status_port
+add wave -noupdate -format Literal -radix decimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_sec
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_rdy
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_en
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_re
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_dout
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_bui/s
+add wave -noupdate -divider DMEM
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_dout
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_en
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_we
+add wave -noupdate -divider IMEM
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/imem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_din
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_en
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc_run
+add wave -noupdate -divider PC
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/hdu
+add wave -noupdate -divider Stages
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/halt
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_reg_dual_a/reg_mem
+add wave -noupdate -divider Cop
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ir_valid
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_id
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_ex
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_ex_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_out
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_entered
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/epc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cause
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/events
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/eflags
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/badvaddr
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/rst
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exception
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_save
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_rest
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_strobe
+add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ip
+add wave -noupdate -divider Stages
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/id_stage
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_dout
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/ex_stage
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/mem_stage
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/wb_stage
+add wave -noupdate -divider Muldiv
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/result
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/start
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/busy
+add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/hilo_sel
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_hi
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_lo
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1121030000 ps} 0} {{Cursor 2} {1436367 ps} 0} {{Cursor 3} {1122030000 ps} 0}
+configure wave -namecolwidth 179
+configure wave -valuecolwidth 89
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {1351336 ps} {1583596 ps}
@@ -0,0 +1,15 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/core/mips_muldiv.vhd"
+vcom -explicit  -93 "../src/tb_mips_muldiv.vhd"
+vsim -t 1ps   -lib work tb_mips_muldiv
+do {tb_mips_muldiv.wdo}
+view wave
+
+view structure
+view signals
+run 5000us
@@ -0,0 +1,19 @@
+## NOTE: Do not edit this file.
+## Auto generated by Project Navigator for Post-Translate Simulation
+##
+vlib work
+## Compile Post-Translate Model
+vcom -explicit  -93 "../syn/eval_muldiv/netgen/translate/muldiv_translate.vhd"
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/tb_mips_muldiv.vhd"
+
+vsim -t 1ps  -lib work tb_mips_muldiv
+#do {tb_mips_muldiv.udo}
+view wave
+add wave *
+view structure
+view signals
+run 1000ns
+## End
@@ -0,0 +1,19 @@
+## NOTE: Do not edit this file.
+## Auto generated by Project Navigator for Post-Translate Simulation
+##
+vlib work
+## Compile Post-Translate Model
+vcom -explicit  -93 "../syn/eval_muldiv/netgen/synthesis/muldiv_synthesis.vhd"
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/tb_mips_muldiv.vhd"
+
+vsim -t 1ps  -lib work tb_mips_muldiv
+do {tb_mips_muldiv.wdo}
+view wave
+#add wave *
+view structure
+view signals
+run 1000ns
+## End
@@ -0,0 +1,79 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mips_muldiv/rst
+add wave -noupdate -format Logic /tb_mips_muldiv/clk
+add wave -noupdate -format Logic /tb_mips_muldiv/mul_divn
+add wave -noupdate -format Logic /tb_mips_muldiv/start
+add wave -noupdate -format Logic /tb_mips_muldiv/busy
+add wave -noupdate -format Logic /tb_mips_muldiv/s_un
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
+add wave -noupdate -format Logic /tb_mips_muldiv/hilo_sel
+add wave -noupdate -format Logic /tb_mips_muldiv/hilo_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/result
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_result
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_lo
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/pre_sum_vld
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/mul_en
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/sum_en
+add wave -noupdate -divider FSM
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
+add wave -noupdate -divider {Multiplier internals}
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_muldiv/uut/pprod
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyi
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyo
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op1
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_res
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op1
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_res
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_reg
+add wave -noupdate -divider {Divider internals}
+add wave -noupdate -format Logic /tb_mips_muldiv/busy
+add wave -noupdate -format Logic /tb_mips_muldiv/s_un
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_start
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_add_cyi
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op1
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_res
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m_n
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_q
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_qbit
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_en
+add wave -noupdate -divider FSM
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt
+add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
+add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {4999822285 ps} 0} {{Cursor 2} {1278050000 ps} 0}
+configure wave -namecolwidth 149
+configure wave -valuecolwidth 171
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {5250 us}
@@ -0,0 +1,22 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/core/mips_idecode_rom.vhd"
+vcom -explicit  -93 "../src/core/mips_reg.vhd"
+vcom -explicit  -93 "../src/core/mips_shifter.vhd"
+vcom -explicit  -93 "../src/core/mips_alu.vhd"
+vcom -explicit  -93 "../src/core/mips_bcu.vhd"
+vcom -explicit  -93 "../src/core/mips_pipeline.vhd"
+vcom -explicit  -93 "../src/core/mips_top.vhd"
+vcom -explicit  -93 "../asm/fibonacci.vhd"
+vcom -explicit  -93 "../src/ram.vhd"
+vcom -explicit  -93 "../src/tb_mips_top.vhd"
+vsim -t 1ps   -lib work tb_mips_top
+do {tb_mips_top.wdo}
+view wave
+view structure
+view signals
+run 40000ns
@@ -0,0 +1,18 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+## Compile Post-Map Model
+vcom -explicit  -93 "../syn/ise9/netgen/map/mips_top_map.vhd"
+vsim -t 1ps -sdfmax "/mips_top=../syn/ise9/netgen/map/mips_top_map.sdf"  -lib work mips_top
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/irom_hello.vhd"
+vcom -explicit  -93 "../src/tb_mips_top.vhd"
+vsim -t 1ps   -lib work tb_mips_top
+do {tb_mips_top.mwdo}
+view wave
+#add wave *
+view structure
+view signals
+run 2400ns
@@ -0,0 +1,31 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mips_top/rst
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Logic /tb_mips_top/ce
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr
+add wave -noupdate -format Logic /tb_mips_top/dmem_we
+add wave -noupdate -format Logic /tb_mips_top/dmem_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_op2
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_result
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {77481 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {729730 ps}
@@ -0,0 +1,16 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../syn/ise9/netgen/synthesis/mips_top_synthesis.vhd"
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/irom_hello.vhd"
+vcom -explicit  -93 "../src/tb_mips_top.vhd"
+vsim -t 1ps   -lib work tb_mips_top
+#do {tb_mips_top.wdo}
+view wave
+add wave *
+view structure
+view signals
+run 2400ns
@@ -0,0 +1,51 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mips_top/rst
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Logic /tb_mips_top/cpu_halt
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout
+add wave -noupdate -format Logic /tb_mips_top/dmem_re
+add wave -noupdate -format Logic /tb_mips_top/dmem_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_ram/sram
+add wave -noupdate -divider ALU
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -divider PC
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/exception
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/stall
+add wave -noupdate -divider PC
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/if_stage
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
+add wave -noupdate -format Logic /tb_mips_top/clk
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 188
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {42 us}
@@ -0,0 +1,17 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+## Compile Post-Map Model
+vcom -explicit  -93 "../syn/ise9/netgen/map/mips_top_syn_map.vhd"
+vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/map/mips_top_syn_map.sdf"  -lib work mips_top_syn
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/irom_hello.vhd"
+vcom -explicit  -93 "../src/tb_mips_top_syn.vhd"
+vsim -t 1ps   -lib work tb_mips_top_syn
+do {tb_mips_top_syn.wdo}
+view wave
+#add wave *
+view structure
+view signals
+run 2400ns
@@ -0,0 +1,17 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+## Compile Post-Map Model
+vcom -explicit  -93 "../syn/ise9/netgen/par/mips_top_syn_timesim.vhd"
+vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/par/mips_top_syn_timesim.sdf"  -lib work mips_top_syn
+vcom -explicit  -93 "../src/core/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_instr.vhd"
+vcom -explicit  -93 "../src/irom_hello.vhd"
+vcom -explicit  -93 "../src/tb_mips_top_syn.vhd"
+vsim -t 1ps   -lib work tb_mips_top_syn
+do {tb_mips_top_syn.wdo}
+view wave
+#add wave *
+view structure
+view signals
+run 2400ns
@@ -0,0 +1,31 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mips_top_syn/rst
+add wave -noupdate -format Logic /tb_mips_top_syn/clk
+add wave -noupdate -format Logic /tb_mips_top_syn/ce
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_addr
+add wave -noupdate -format Logic /tb_mips_top_syn/dmem_we
+add wave -noupdate -format Logic /tb_mips_top_syn/dmem_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_id_stage_boff
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_stage_ex_inst_alu_sum_res
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top_syn/sram
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {118199 ps} 0}
+configure wave -namecolwidth 188
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {2520 ns}