Initial import

git-svn-id: http://moon:8086/svn/vhdl/trunk@2 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/JCpu/src/core/pc.vhd

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+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Programm counter
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity pc is
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		inc			: in  STD_LOGIC;
+		load		: in  STD_LOGIC;
+		pc_in		: in  inst_addr_t;
+		pc_out		: out inst_addr_t;
+		pc_next		: out inst_addr_t
+	);
+end pc;
+
+architecture Behavioral of pc is
+
+begin
+
+proc_pc:
+	process(rst, clk, inc, load, pc_in)
+	variable vpc, vpc_reg: inst_addr_t;
+	begin
+		if rst = '1' then
+			vpc_reg := (others => '0');
+		elsif rising_edge(clk) then
+			if inc = '1' or load = '1' then
+				vpc_reg := vpc;
+			elsif inc = '0'	then
+				pc_next <= vpc;		
+			end if;
+		end if;
+		
+		if load = '1' then
+			vpc := pc_in;	
+		else
+			vpc := vpc_reg + 1;
+		end if;	
+		pc_out <= vpc_reg;
+		
+	end process;
+
+end Behavioral;
+