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git-svn-id: http://moon:8086/svn/vhdl/trunk@2 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2008-08-23 07:19:47 +00:00
parent 6badec2df7
commit 335cc4e9d2
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lib/CPUs/JCpu/src/core/alu.vhd
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--------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The arithmetic logic unit
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.cpu_pkg.all;
entity alu is
Generic (
data_width : integer := 8
);
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
op_en : in STD_LOGIC;
cy_in : in STD_LOGIC;
op1_in : in unsigned (data_width-1 downto 0);
op2_in : in unsigned (data_width-1 downto 0);
opsel : in alu_op_t;
res_out : out unsigned (data_width-1 downto 0);
stat_load : in STD_LOGIC;
stat_in : in alu_status_t;
stat_out : out alu_status_t
);
end alu;
architecture Behavioral of alu is
signal sum_cy, sh_cy, sum_cy_in, sh_cy_in, left_shift, add_subn : STD_LOGIC;
signal result, sum_res, lf_res, sh_res, res_reg : unsigned (data_width-1 downto 0);
signal status, stat_reg : alu_status_t;
--------------------------------------------------------------------------
function test_zero(arg : unsigned) return STD_LOGIC is
variable result : STD_LOGIC;
begin
result := '0';
for i in arg'range loop
result := result or To_X01(arg(i));
end loop;
return not result;
end test_zero;
--------------------------------------------------------------------------
begin
--------------------------------------------------------------------------
proc_logic_func:
process (op1_in, op2_in, opsel)
begin
case opsel is
when op1_and_op2 =>
lf_res <= op1_in and op2_in;
when op1_or_op2 =>
lf_res <= op1_in or op2_in;
when op1_xor_op2 =>
lf_res <= op1_in xor op2_in;
when others =>
lf_res <= (others => '-');
end case;
end process;
--------------------------------------------------------------------------
proc_shift_func:
process (op1_in, left_shift, sh_cy_in)
begin
if left_shift = '1' then
sh_res <= op1_in(op1_in'left-1 downto op1_in'right) & sh_cy_in;
sh_cy <= op1_in(op1_in'left);
else
sh_res <= sh_cy_in & op1_in(op1_in'left downto op1_in'right+1);
sh_cy <= op1_in(op1_in'right);
end if;
end process;
--------------------------------------------------------------------------
proc_alu_out:
process(opsel, op1_in, op2_in, res_reg, stat_reg, lf_res, sum_res, sh_res, sum_cy, sh_cy, cy_in)
begin
case opsel is
when op1_add_op2 | op1_sub_op2 | op1_addc_op2 | op1_subc_op2 =>
status.zero <= test_zero(res_reg);
status.carry <= sum_cy;
result <= sum_res;
when op1_and_op2 | op1_or_op2 | op1_xor_op2 =>
status.zero <= test_zero(res_reg);
status.carry <= stat_reg.carry;
result <= lf_res;
when shl_op | shr_op | rol_op | ror_op | rolc_op | rorc_op =>
status.zero <= test_zero(res_reg);
status.carry <= sh_cy;
result <= sh_res;
when swap_op =>
result <= op1_in(op1_in'left-op1_in'length/2 downto op1_in'right) & op1_in(op1_in'left downto op1_in'right+op1_in'length/2);
status <= stat_reg;
when others =>
result <= op2_in;
status.zero <= stat_reg.zero;
status.carry <= stat_reg.carry or cy_in;
end case;
end process;
--------------------------------------------------------------------------
proc_alu_in:
process(opsel, op1_in, stat_reg)
begin
add_subn <= '-';
sum_cy_in <= '-';
sh_cy_in <= '-';
left_shift <= '-';
case opsel is
when op1_add_op2 =>
sum_cy_in <= '0';
add_subn <= '1';
when op1_sub_op2 =>
sum_cy_in <= '0';
add_subn <= '0';
when op1_addc_op2 =>
sum_cy_in <= stat_reg.carry;
add_subn <= '1';
when op1_subc_op2 =>
sum_cy_in <= stat_reg.carry;
add_subn <= '0';
when shl_op =>
sh_cy_in <= '0';
left_shift <= '1';
when shr_op =>
sh_cy_in <= '0';
left_shift <= '0';
when rol_op =>
sh_cy_in <= op1_in(op1_in'left);
left_shift <= '1';
when ror_op =>
sh_cy_in <= op1_in(op1_in'right);
left_shift <= '0';
when rolc_op =>
sh_cy_in <= stat_reg.carry;
left_shift <= '1';
when rorc_op =>
sh_cy_in <= stat_reg.carry;
left_shift <= '0';
when others => null;
end case;
end process;
--------------------------------------------------------------------------
proc_res_reg:
process(clk, rst, op_en, stat_load, res_reg, stat_reg)
begin
if rst = '1' then
res_reg <= (others => '0');
stat_reg <= (others => '0');
elsif rising_edge(clk) then
if op_en = '1' then
res_reg <= result;
stat_reg <= status;
elsif stat_load = '1' then
stat_reg <= stat_in;
end if;
end if;
res_out <= res_reg;
stat_out <= stat_reg;
end process;
--------------------------------------------------------------------------
alu_addsub:
process(op1_in, op2_in, sum_cy_in, add_subn)
variable sum : unsigned(data_width+1 downto 0);
variable op1, op2 : unsigned(data_width+1 downto 0);
begin
if add_subn = '1' then
op1 := '0' & op1_in & '1';
op2 := '0' & op2_in & sum_cy_in;
sum := op1 + op2;
else
op1 := '0' & op1_in & not sum_cy_in;
op2 := '0' & op2_in & '1';
sum := op1 - op2;
end if;
-- Form sum + carry
sum_res <= sum(data_width downto 1);
sum_cy <= sum(sum'left);
end process;
--------------------------------------------------------------------------
end Behavioral;
lib/CPUs/JCpu/src/core/chipram.vhd
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--------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: On-chip RAM
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.cpu_pkg.all;
entity chipram is
Generic (
addr_width : integer := 3;
data_width : integer := 8
);
Port (
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end chipram;
architecture Behavioral of chipram is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype;
begin
process (clka)
begin
if clka'event and clka = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
end if;
dout_a <= RAM(to_integer(addr_a));
end if;
end if;
end process;
process (clkb)
begin
if clkb'event and clkb = '1' then
if en_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
end if;
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;
lib/CPUs/JCpu/src/core/chipreg.vhd
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--------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: On-Chip registers
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.cpu_pkg.all;
entity chipreg is
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
we : in STD_LOGIC;
addr : in dmem_addr_t;
din : in dmem_data_t;
dout : out dmem_data_t;
ctrl_in : in creg_ctrl_in_t;
ctrl_out : out creg_ctrl_out_t
);
end chipreg;
architecture Behavioral of chipreg is
signal reg_page_sel : page_sel_t;
signal reg_int_ctrl : int_ctrl_in_t;
signal reg_stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
signal reg_cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
begin
proc_assign_ctrl_lines:
process (clk)
begin
if rising_edge(clk) then
ctrl_out.page_sel <= reg_page_sel;
ctrl_out.int_ctrl <= reg_int_ctrl;
ctrl_out.stk_high <= reg_stk_high;
ctrl_out.cmem_high <= reg_cmem_high;
end if;
end process;
proc_reg_write:
process (rst, clk)
begin
if rst = '1' then
reg_stk_high <= (others => '0');
reg_cmem_high <= (others => '0');
reg_page_sel <= (others => '0');
reg_int_ctrl.enable <= '0';
reg_int_ctrl.polarity <= '1';
reg_int_ctrl.edge_sens <= '1';
elsif rising_edge(clk) then
reg_int_ctrl.request <= '0';
if we = '1' then
case addr is
when X"01" =>
reg_page_sel(page_sel_t'range) <= din(page_sel_t'range);
when X"03" =>
reg_int_ctrl.enable <= din(0);
reg_int_ctrl.polarity <= din(1);
reg_int_ctrl.edge_sens <= din(2);
reg_int_ctrl.request <= din(7);
when X"04" =>
reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
when X"05" =>
reg_stk_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
when others => null;
end case;
end if;
end if;
end process;
proc_reg_read:
process (clk)
begin
if rising_edge(clk) then
case addr is
when X"00" => -- Revison
dout <= to_unsigned(REVISION, dmem_data_t'length);
when X"01" => -- Control 0
dout <= (7 downto page_sel_t'length => '0') & reg_page_sel;
when X"02" => -- CPU status
dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero;
when X"03" => -- Interrupt control
dout <= "00000" & reg_int_ctrl.edge_sens & reg_int_ctrl.polarity & reg_int_ctrl.enable;
when X"04" => -- Upper stack bits out
dout <= "0000" & reg_cmem_high;
when X"05" => -- Upper cmem bits out
dout <= "0000" & reg_stk_high;
when others =>
if addr(0) = '0' then
dout <= X"DE";
else
dout <= X"AD";
end if;
end case;
end if;
end process;
end Behavioral;
lib/CPUs/JCpu/src/core/cpu.vhd
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--------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: JCPU top file
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.cpu_pkg.all;
entity cpu is
Generic (
use_instr_register : boolean := false;
use_ctrl_rom : boolean := true
);
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
int_in : in STD_LOGIC;
int_ack : out STD_LOGIC;
xmem_wait : in STD_LOGIC;
xmem_we : out STD_LOGIC;
xmem_re : out STD_LOGIC;
instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0);
instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
io_sel : out std_logic
);
end cpu;
architecture rtl of cpu is
COMPONENT stack_ctrl
GENERIC (
addr_width : integer
);
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
push : in STD_LOGIC;
pop : in STD_LOGIC;
din : in inst_addr_t;
dout : out inst_addr_t;
mem_we : out STD_LOGIC;
ptr_out : out unsigned (addr_width-1 downto 0)
);
END COMPONENT;
COMPONENT pc
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
inc : in STD_LOGIC;
load : in STD_LOGIC;
pc_in : in inst_addr_t;
pc_out : out inst_addr_t;
pc_next : out inst_addr_t
);
END COMPONENT;
COMPONENT dpath_ctrl
GENERIC (
use_rom : boolean
);
Port (
inst_in : in inst_t;
iphase_in : in iphase_t;
status_in : in cpu_status_t;
ctrl_out : out dpath_ctrl_out_t;
idout : out inst_addr_t;
ddout : out dmem_data_t
);
END COMPONENT;
COMPONENT int_ctrl
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ctrl_in : in int_ctrl_in_t;
int_in : in STD_LOGIC;
int_exit : in STD_LOGIC;
iphase_in : in iphase_t;
int_ack_out : out STD_LOGIC;
stat_save_out : out STD_LOGIC;
stat_rest_out : out STD_LOGIC;
pc_addr_out : out inst_addr_t;
pc_load_out : out STD_LOGIC;
stk_push_out : out STD_LOGIC;
stk_pop_out : out STD_LOGIC
);
END COMPONENT;
COMPONENT reg_dual
GENERIC (
addr_width : integer;
data_width : integer
);
Port (
clk : in STD_LOGIC;
we_a : in STD_LOGIC;
ptr_a : in reg_ptr_t;
ptr_b : in reg_ptr_t;
din_a : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
END COMPONENT;
COMPONENT chipram
GENERIC (
addr_width : integer;
data_width : integer
);
Port (
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
END COMPONENT;
COMPONENT chipreg
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
we : in STD_LOGIC;
addr : in dmem_addr_t;
din : in dmem_data_t;
dout : out dmem_data_t;
ctrl_in : in creg_ctrl_in_t;
ctrl_out : out creg_ctrl_out_t
);
END COMPONENT;
COMPONENT alu
GENERIC (
data_width : integer := 8
);
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
op_en : in STD_LOGIC;
cy_in : in STD_LOGIC;
op1_in : in unsigned (data_width-1 downto 0);
op2_in : in unsigned (data_width-1 downto 0);
opsel : in alu_op_t;
res_out : out unsigned (data_width-1 downto 0);
stat_load : in STD_LOGIC;
stat_in : in alu_status_t;
stat_out : out alu_status_t
);
END COMPONENT;
signal cpu_status, status_reg : cpu_status_t; -- := cpu_status_t(others => '0');
signal ctrl : dpath_ctrl_out_t;
signal stk_out : inst_addr_t;
signal stk_in : inst_addr_t;
signal stk_reg : inst_addr_t;
signal pc_in, pc_out, pc_next, idata, int_pc_addr : inst_addr_t;
signal iphase : iphase_t;
signal const_data, reg_a_dout, reg_b_dout : dmem_data_t;
signal reg_din : dmem_data_t;
signal alu_op1, alu_op2, alu_result : dmem_data_t;
signal alu_status : alu_status_t;
signal pc_inc, pc_load, cpu_active, stk_we, cmem_we, creg_we : STD_LOGIC;
signal ctrl_inst : inst_t;
signal ctrl_iphase : iphase_t;
signal was_pcld, was_pop2pc, int_pc_load, int_stk_push, int_stk_pop, stk_push, stk_pop : STD_LOGIC;
signal status_save, status_restore : STD_LOGIC;
signal creg_dout : dmem_data_t;
signal cmem_din, cmem_dout : inst_addr_t;
signal stk_addr, cmem_addr : unsigned(CHIPRAM_SIZE_BITS-1 downto 0);
signal stk_ptr : unsigned(STACK_SIZE_BITS-1 downto 0);
signal creg_ctrl_out : creg_ctrl_out_t;
signal creg_ctrl_in : creg_ctrl_in_t;
signal irq_out : std_logic;
signal xio_sel, cio_sel : std_logic;
signal mem_data : dmem_data_t;
signal mem_addr : dmem_data_t;
begin
io_sel <= xio_sel;
instr_addr <= pc_out;
pc_inc <= cpu_active and ctrl.lines.pc_inc;
stk_addr <= '0' & stk_ptr;
cpu_status.alu <= alu_status;
cpu_status.xmem_wait <= xmem_wait;
creg_ctrl_in.alu <= alu_status;
xmem_dout <= mem_data;
xmem_addr <= mem_addr;
cmem_din <= creg_ctrl_out.cmem_high & mem_data;
cmem_addr <= '1' & creg_ctrl_out.page_sel & mem_addr(MIN(cmem_addr'length-creg_ctrl_out.page_sel'length-1, mem_addr'length)-1 downto 0);
--------------------------------------------------------------------
mem_ctrl_lines:
process(ctrl.lines)
begin
xio_sel <= '0';
xmem_re <= '0';
xmem_we <= '0';
cio_sel <= '0';
cmem_we <= '0';
creg_we <= '0';
case ctrl.lines.mem_access is
when xmem_access =>
xmem_re <= ctrl.lines.mem_read;
xmem_we <= ctrl.lines.mem_write;
when xio_access =>
xio_sel <= '1';
xmem_re <= ctrl.lines.mem_read;
xmem_we <= ctrl.lines.mem_write;
when cmem_access =>
cmem_we <= ctrl.lines.mem_write;
when cio_access =>
cio_sel <= '1';
creg_we <= ctrl.lines.mem_write;
when others => null;
end case;
end process;
iphase_counter:
process(rst, clk, ce)
variable pos : integer;
begin
if rst = '1' then
iphase <= iphase_t'low;
cpu_active <= '0';
elsif rising_edge(clk) then
cpu_active <= '0';
if ce = '1' then
cpu_active <= '1';
if iphase = iphase_t'high then
iphase <= iphase_t'low;
else
iphase <= iphase + 1;
end if;
end if;
end if;
end process;
gen_instr_reg:
if use_instr_register = true generate
instr_reg:
process (rst, clk, ce)
begin
if rst = '1' then
ctrl_inst <= (others => '0');
ctrl_iphase <= 0;
elsif rising_edge(clk) and ce = '1' then
ctrl_inst <= instr_din;
ctrl_iphase <= iphase;
end if;
end process;
end generate;
gen_instr_direct:
if use_instr_register = false generate
ctrl_inst <= instr_din;
ctrl_iphase <= iphase;
end generate;
status_register:
process(clk, status_save)
begin
if rising_edge(clk) and status_save = '1' then
status_reg.alu <= alu_status;
end if;
end process;
pc_pushpop:
process(ctrl.lines, int_pc_load, int_stk_push, int_stk_pop, was_pop2pc)
begin
pc_load <= ctrl.lines.pc_load or int_pc_load;
stk_push <= (ctrl.lines.stk_pushd or ctrl.lines.stk_push) or (int_stk_push and not was_pop2pc);
stk_pop <= ctrl.lines.stk_popd or int_stk_pop or (ctrl.lines.stk_pop and not int_pc_load);
end process;
lines_delay:
process(clk)
begin
if rising_edge(clk) then
was_pcld <= ctrl.lines.pc_load;
was_pop2pc <= ctrl.lines.stk_pop and ctrl.lines.pc_load;
end if;
end process;
stk_mux:
process(ctrl.lines, was_pcld, int_stk_push, pc_next, idata, reg_a_dout, creg_ctrl_out)
begin
if was_pcld = '1' and int_stk_push = '1' then
stk_in <= idata;
elsif ctrl.lines.stk_pushd = '1' then
stk_in <= creg_ctrl_out.stk_high & reg_a_dout;
else
stk_in <= pc_next;
end if;
end process;
pc_mux:
process(ctrl.lines, int_pc_load, int_stk_pop, idata, int_pc_addr, stk_out)
begin
pc_in <= stk_out;
if int_pc_load = '1' then
if int_stk_pop = '0' then
pc_in <= int_pc_addr;
end if;
elsif ctrl.lines.pc_load = '1' then
if ctrl.lines.stk_pop = '0' then
pc_in <= idata;
end if;
end if;
end process;
mem_data_mux:
process(ctrl.lines.ddata_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out)
begin
case ctrl.lines.ddata_src_sel is
when reg_a =>
mem_data <= reg_a_dout;
when reg_b =>
mem_data <= reg_b_dout;
when const =>
mem_data <= const_data;
when others =>
mem_data <= const_data;
end case;
end process;
mem_addr_mux:
process(ctrl.lines.daddr_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out.page_sel)
begin
case ctrl.lines.daddr_src_sel is
when reg_a =>
mem_addr <= reg_a_dout;
when reg_b =>
mem_addr <= reg_b_dout;
when const =>
mem_addr <= const_data;
when others =>
mem_addr <= const_data;
end case;
end process;
reg_in_mux:
process(ctrl.lines.reg_src_sel, cio_sel, xmem_din, alu_result, stk_out, cmem_dout, creg_dout)
variable data : dmem_data_t;
begin
case ctrl.lines.reg_src_sel is
when xmem_src =>
data := xmem_din;
when cmem_src =>
if cio_sel = '0' then
data := cmem_dout(dmem_data_t'range);
else
data := creg_dout(dmem_data_t'range);
end if;
when stk_src =>
data := stk_out(dmem_data_t'range);
when others =>
data := alu_result;
end case;
reg_din <= data;
end process;
alu_op1_mux:
process(ctrl.lines.alu_op1_src_sel, reg_a_dout, reg_b_dout, const_data)
variable data : dmem_data_t;
begin
case ctrl.lines.alu_op1_src_sel is
when reg_a =>
data := reg_a_dout;
when reg_b =>
data := reg_b_dout;
when others =>
data := const_data;
end case;
alu_op1 <= data;
end process;
alu_op2_mux:
process(ctrl.lines.alu_op2_src_sel, reg_a_dout, reg_b_dout, const_data)
variable data : dmem_data_t;
begin
case ctrl.lines.alu_op2_src_sel is
when reg_a =>
data := reg_a_dout;
when reg_b =>
data := reg_b_dout;
when others =>
data := const_data;
end case;
alu_op2 <= data;
end process;
--------------------------------------------------------------------
inst_stack_ctrl: stack_ctrl
GENERIC MAP (
addr_width => STACK_SIZE_BITS
)
PORT MAP(
rst => rst,
clk => clk,
push => stk_push,
pop => stk_pop,
dout => stk_reg,
din => stk_in,
ptr_out => stk_ptr,
mem_we => stk_we
);
inst_pc: pc
PORT MAP(
rst => rst,
clk => clk,
inc => pc_inc,
load => pc_load,
pc_in => pc_in,
pc_out => pc_out,
pc_next => pc_next
);
inst_dpath_ctrl: dpath_ctrl
GENERIC MAP (
use_rom => use_ctrl_rom
)
PORT MAP(
inst_in => ctrl_inst,
iphase_in => ctrl_iphase,
status_in => cpu_status,
ctrl_out => ctrl,
ddout => const_data,
idout => idata
);
inst_int_ctrl: int_ctrl
PORT MAP(
rst => rst,
clk => clk,
ctrl_in => creg_ctrl_out.int_ctrl,
int_in => int_in,
int_ack_out => int_ack,
int_exit => ctrl.lines.int_exit,
iphase_in => ctrl_iphase,
stat_save_out => status_save,
stat_rest_out => status_restore,
pc_addr_out => int_pc_addr,
pc_load_out => int_pc_load,
stk_push_out => int_stk_push,
stk_pop_out => int_stk_pop
);
inst_reg_ab: reg_dual
GENERIC MAP (
addr_width => REG_SIZE_BITS,
data_width => DMEM_DATA_WIDTH
)
PORT MAP(
clk => clk,
we_a => ctrl.lines.reg_we,
ptr_a => ctrl.reg_a_ptr,
ptr_b => ctrl.reg_b_ptr,
din_a => reg_din,
dout_a => reg_a_dout,
dout_b => reg_b_dout
);
inst_chipram: chipram
GENERIC MAP (
addr_width => CHIPRAM_SIZE_BITS,
data_width => IMEM_ADDR_WIDTH
)
PORT MAP(
clka => clk,
clkb => clk,
en_a => cpu_active,
en_b => cpu_active,
we_a => stk_we,
we_b => cmem_we,
addr_a => stk_addr,
addr_b => cmem_addr,
din_a => stk_reg,
din_b => cmem_din,
dout_a => stk_out,
dout_b => cmem_dout
);
inst_chipreg: chipreg
PORT MAP(
rst => rst,
clk => clk,
we => creg_we,
addr => mem_addr,
din => mem_data,
dout => creg_dout,
ctrl_in => creg_ctrl_in,
ctrl_out => creg_ctrl_out
);
inst_alu: alu
GENERIC MAP (
data_width => DMEM_DATA_WIDTH
)
PORT MAP(
rst => rst,
clk => clk,
op_en => ctrl.lines.alu_load,
cy_in => ctrl.lines.alu_cy_in,
op1_in => alu_op1,
op2_in => alu_op2,
opsel => ctrl.lines.alu_opsel,
res_out => alu_result,
stat_load => status_restore,
stat_in => status_reg.alu,
stat_out => alu_status
);
end rtl;
lib/CPUs/JCpu/src/core/cpu_pkg.vhd
+904
View File
@@ -0,0 +1,904 @@
--------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Types, constants and functions for JCPU
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
package cpu_pkg is
-- Revision of the CPU
constant REVISION : integer := 4;
-- Chipram depth (valid values 9..floor(log2(BlockRamBytes)))
constant CHIPRAM_SIZE_BITS : integer := 10;
-- Chipregister file depth
constant CHIPREG_SIZE_BITS : integer := 8;
-- Number of registers (16 registers fixed)
constant REG_SIZE_BITS : integer := 4;
-- Instruction memory
constant IMEM_ADDR_WIDTH : integer := 12;
-- Data memory
constant DMEM_DATA_WIDTH : integer := 8;
constant DMEM_ADDR_WIDTH : integer := 8;
-- Instruction format
constant INST_OPCODE_WIDTH : integer := 6;
constant IMEM_DATA_WIDTH : integer := INST_OPCODE_WIDTH + DMEM_DATA_WIDTH + REG_SIZE_BITS;
-- Microcode ROM
constant MUCODE_ADDR_WIDTH : integer := 10;
-- Stack depth (uses lower half of CHIPRAM)
constant STACK_SIZE_BITS : integer := CHIPRAM_SIZE_BITS-1;
--Types
subtype iphase_t is integer range 0 to 1;
type mem_access_t is (cmem_access, xmem_access, cio_access, xio_access);
type reg_src_t is (alu_src, stk_src, cmem_src, xmem_src);
type alu_src_t is (reg_a, reg_b, const);
type ddata_src_t is (reg_a, reg_b, const);
type daddr_src_t is (reg_a, reg_b, const);
subtype instr_name_t is string(1 to 12);
type instr_name_array_t is array (0 to 63) of instr_name_t;
subtype opcode_t is unsigned (INST_OPCODE_WIDTH-1 downto 0);
subtype inst_data_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
subtype inst_addr_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
subtype inst_t is unsigned (IMEM_DATA_WIDTH-1 downto 0);
subtype dmem_data_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
subtype dmem_addr_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
subtype reg_ptr_t is unsigned (3 downto 0);
type dmem_array_t is array (natural range <>) of dmem_data_t;
type instr_addr_array is array (integer range <>) of inst_addr_t;
subtype page_sel_t is unsigned (CHIPRAM_SIZE_BITS-DMEM_DATA_WIDTH-2 downto 0);
type alu_op_t is
(
pass_op2,
op1_add_op2,
op1_sub_op2,
op1_addc_op2,
op1_subc_op2,
op1_and_op2,
op1_or_op2,
op1_xor_op2,
swap_op,
shl_op,
shr_op,
rol_op,
ror_op,
rolc_op,
rorc_op
);
type alu_status_t is record
zero : STD_LOGIC;
carry : STD_LOGIC;
end record;
type cpu_status_t is record
alu : alu_status_t;
xmem_wait : STD_LOGIC;
end record;
type ctrl_lines_t is record
reg_we : STD_LOGIC;
reg_src_sel : reg_src_t;
alu_op1_src_sel : alu_src_t;
alu_op2_src_sel : alu_src_t;
alu_opsel : alu_op_t;
alu_load : STD_LOGIC;
alu_cy_in : STD_LOGIC;
ddata_src_sel : ddata_src_t;
daddr_src_sel : daddr_src_t;
pc_load : STD_LOGIC;
pc_inc : STD_LOGIC;
stk_push : STD_LOGIC;
stk_pop : STD_LOGIC;
stk_pushd : STD_LOGIC;
stk_popd : STD_LOGIC;
mem_access : mem_access_t;
mem_read : STD_LOGIC;
mem_write : STD_LOGIC;
int_exit : STD_LOGIC;
end record;
type dpath_ctrl_out_t is record
lines : ctrl_lines_t;
reg_a_ptr : reg_ptr_t;
reg_b_ptr : reg_ptr_t;
end record;
type int_ctrl_in_t is record
enable : std_logic;
polarity : std_logic;
edge_sens : std_logic;
request : std_logic;
end record;
type creg_ctrl_out_t is record
page_sel : page_sel_t;
int_ctrl : int_ctrl_in_t;
stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
end record;
type creg_ctrl_in_t is record
alu : alu_status_t;
end record;
type murom_t is array (0 to integer(2**MUCODE_ADDR_WIDTH)-1) of ctrl_lines_t;
constant instr_name_array : instr_name_array_t :=
(
"NOP ", -- 00
"HALT ", -- 01
"MOV|R|R ", -- 02
"MOV|R|K ", -- 03
"MOVX|R|Ri ", -- 04
"MOVX|R|Ki ", -- 05
"MOVX|Ri|R ", -- 06
"MOVX|Ri|K ", -- 07
"MOVX|Ki|R ", -- 08
"MOVC|R|Ri ", -- 09
"MOVC|R|Ki ", -- 0A
"MOVC|Ri|R ", -- 0B
"MOVC|Ri|K ", -- 0C
"MOVC|Ki|R ", -- 0D
"CMP|R|R ", -- 0E
"CMP|R|K ", -- 0F
"ADD|R|R ", -- 10
"ADD|R|K ", -- 11
"ADDC|R|R ", -- 12
"ADDC|R|K ", -- 13
"SUB|R|R ", -- 14
"SUB|R|K ", -- 15
"SUBC|R|R ", -- 16
"SUBC|R|K ", -- 17
"AND|R|R ", -- 18
"AND|R|K ", -- 19
"OR|R|R ", -- 1A
"OR|R|K ", -- 1B
"XOR|R|R ", -- 1C
"XOR|R|K ", -- 1D
"SHL|R ", -- 1E
"SHR|R ", -- 1F
"ROL|R ", -- 20
"ROR|R ", -- 21
"ROLC|R ", -- 22
"RORC|R ", -- 23
"XOUT|Ki|R ", -- 24
"XOUT|Ri|K ", -- 25
"COUT|Ki|R ", -- 26
"COUT|Ri|K ", -- 27
"XIN|R|Ki ", -- 28
"CIN|R|Ki ", -- 29
"SWAP|R ", -- 2A
"SETC ", -- 2B
"UNDEF ", -- 2C
"UNDEF ", -- 2D
"SUB|K|R ", -- 2E
"SUBC|K|R ", -- 2F
"JMP|K ", -- 30
"JZ|K ", -- 31
"JNZ|K ", -- 32
"JC|K ", -- 33
"JNC|K ", -- 34
"JLT|K ", -- 35
"JGT|K ", -- 36
"JLE|K ", -- 37
"JGE|K ", -- 38
"JEQ|K ", -- 39
"JNE|K ", -- 3A
"CALL|K ", -- 3B
"PUSH|R ", -- 3C
"POP|R ", -- 3D
"RET ", -- 3E
"RETI " -- 3F
);
-- Functions
function Instr(opcode : opcode_t) return inst_t;
function Instr(opcode : opcode_t; data : inst_data_t) return inst_t;
function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t;
function Instr(opcode : opcode_t; reg_a : integer) return inst_t;
function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t;
function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t;
function ctrl_lines_default return ctrl_lines_t;
function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
function gen_murom return murom_t;
function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned;
function MIN (X, Y: INTEGER) return INTEGER;
function MAX (X, Y: INTEGER) return INTEGER;
end cpu_pkg;
package body cpu_pkg is
function Instr(opcode : opcode_t) return inst_t is
variable inst : inst_t := (others => '0');
begin
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
return inst;
end Instr;
function Instr(opcode : opcode_t; data : inst_data_t) return inst_t is
variable inst : inst_t := (others => '0');
begin
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_addr_t'length) := data;
return inst;
end Instr;
function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t is
variable inst : inst_t := (others => '0');
begin
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_data_t'length) := data;
inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg, reg_ptr_t'length));
return inst;
end Instr;
function Instr(opcode : opcode_t; reg_a : integer) return inst_t is
variable inst : inst_t := (others => '0');
begin
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
return inst;
end Instr;
function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t is
variable inst : inst_t := (others => '0');
begin
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length));
inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
return inst;
end Instr;
function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t is
variable inst : inst_t := (others => '0');
begin
inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
inst(3*(reg_ptr_t'length)-1 downto 2*reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_c, reg_ptr_t'length));
inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length));
inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
return inst;
end Instr;
function ctrl_lines_default return ctrl_lines_t is
variable result : ctrl_lines_t;
begin
result.pc_load := '0';
result.pc_inc := '0';
result.stk_push := '0';
result.stk_pop := '0';
result.stk_pushd := '0';
result.stk_popd := '0';
result.reg_we := '0';
result.reg_src_sel := alu_src;
result.ddata_src_sel := reg_a;
result.daddr_src_sel := reg_b;
result.alu_opsel := pass_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := reg_b;
result.alu_load := '0';
result.alu_cy_in := '0';
result.mem_access := cmem_access;
result.mem_read := '0';
result.mem_write := '0';
result.int_exit := '0';
return result;
end ctrl_lines_default;
function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
variable instr_name : instr_name_t;
begin
instr_name := instr_name_array(to_integer(opcode));
return idecoder(instr_name, iphase, status);
end idecoder;
function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
variable result : ctrl_lines_t;
variable ze, cy, xmem_wait : STD_LOGIC;
begin
ze := status.alu.zero;
cy := status.alu.carry;
xmem_wait := status.xmem_wait;
result := ctrl_lines_default;
if iphase = 0 then
result.pc_inc := '1';
end if;
case instr_name is
when "HALT " =>
result.pc_inc := '0';
when "SETC " => -- carry <= 1
result.reg_src_sel := alu_src;
result.alu_opsel := pass_op2;
result.alu_op2_src_sel := reg_b;
result.alu_load := '1';
result.alu_cy_in := '1';
when "MOV|R|R " => -- R(a) <= R(b)
result.reg_src_sel := alu_src;
result.alu_opsel := pass_op2;
result.alu_op2_src_sel := reg_b;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "MOV|R|K " => -- R(a) <= #kk
result.reg_src_sel := alu_src;
result.alu_opsel := pass_op2;
result.alu_op2_src_sel := const;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "MOVC|Ri|R " => -- [R(b)] <= R(a)
result.mem_access := cmem_access;
result.daddr_src_sel := reg_b;
result.ddata_src_sel := reg_a;
if iphase = 0 then
result.mem_write := '1';
end if;
when "MOVC|Ri|K " => -- [R(a)] <= kk
result.mem_access := cmem_access;
result.daddr_src_sel := reg_a;
result.ddata_src_sel := const;
if iphase = 0 then
result.mem_write := '1';
end if;
when "COUT|Ri|K " => -- [R(a)] <= kk
result.mem_access := cio_access;
result.daddr_src_sel := reg_a;
result.ddata_src_sel := const;
if iphase = 0 then
result.mem_write := '1';
end if;
when "MOVC|R|Ri " => -- R(a) <= [R(b)]
result.mem_access := cmem_access;
result.reg_src_sel := cmem_src;
result.daddr_src_sel := reg_b;
if iphase = 1 then
result.reg_we := '1';
end if;
when "MOVC|R|Ki " => -- R(a) <= [#addr]
result.mem_access := cmem_access;
result.reg_src_sel := cmem_src;
result.daddr_src_sel := const;
if iphase = 1 then
result.reg_we := '1';
end if;
when "CIN|R|Ki " => -- R(a) <= [#addr]
result.mem_access := cio_access;
result.reg_src_sel := cmem_src;
result.daddr_src_sel := const;
if iphase = 1 then
result.reg_we := '1';
end if;
when "MOVC|Ki|R " => -- [#addr] <= R(a)
result.mem_access := cmem_access;
result.daddr_src_sel := const;
result.ddata_src_sel := reg_a;
if iphase = 0 then
result.mem_write := '1';
end if;
when "COUT|Ki|R " => -- [#addr] <= R(a)
result.mem_access := cio_access;
result.daddr_src_sel := const;
result.ddata_src_sel := reg_a;
if iphase = 0 then
result.mem_write := '1';
end if;
when "MOVX|Ri|R " => -- [R(b)] <= R(a)
result.mem_access := xmem_access;
result.daddr_src_sel := reg_b;
result.ddata_src_sel := reg_a;
if iphase = 0 then
result.mem_write := '1';
end if;
if xmem_wait = '1' then
result.mem_write := '1';
result.pc_inc := '0';
end if;
when "MOVX|Ri|K " => -- [R(a)] <= kk
result.mem_access := xmem_access;
result.daddr_src_sel := reg_a;
result.ddata_src_sel := const;
if iphase = 0 then
result.mem_write := '1';
end if;
if xmem_wait = '1' then
result.mem_write := '1';
result.pc_inc := '0';
end if;
when "XOUT|Ri|K " => -- [R(a)] <= kk
result.mem_access := xio_access;
result.daddr_src_sel := reg_a;
result.ddata_src_sel := const;
if iphase = 0 then
result.mem_write := '1';
end if;
if xmem_wait = '1' then
result.pc_inc := '0';
result.mem_write := '1';
end if;
when "MOVX|R|Ri " => -- R(a) <= [R(b)]
result.mem_access := xmem_access;
result.reg_src_sel := xmem_src;
result.daddr_src_sel := reg_b;
if iphase = 0 then
result.mem_read := '1';
end if;
if xmem_wait = '0' then
if iphase = 1 then
result.reg_we := '1';
end if;
else
result.pc_inc := '0';
result.mem_read := '1';
end if;
when "MOVX|R|Ki " => -- R(a) <= [#addr]
result.mem_access := xmem_access;
result.reg_src_sel := xmem_src;
result.daddr_src_sel := const;
if iphase = 0 then
result.mem_read := '1';
end if;
if xmem_wait = '0' then
if iphase = 1 then
result.reg_we := '1';
end if;
else
result.pc_inc := '0';
result.mem_read := '1';
end if;
when "XIN|R|Ki " => -- R(a) <= [#addr]
result.mem_access := xio_access;
result.reg_src_sel := xmem_src;
result.daddr_src_sel := const;
if iphase = 0 then
result.mem_read := '1';
end if;
if xmem_wait = '0' then
if iphase = 1 then
result.reg_we := '1';
end if;
else
result.pc_inc := '0';
result.mem_read := '1';
end if;
when "MOVX|Ki|R " => -- [#addr] <= R(a)
result.mem_access := xmem_access;
result.daddr_src_sel := const;
result.ddata_src_sel := reg_a;
if iphase = 0 then
result.mem_write := '1';
end if;
if xmem_wait = '1' then
result.pc_inc := '0';
result.mem_write := '1';
end if;
when "XOUT|Ki|R " => -- [#addr] <= R(a)
result.mem_access := xio_access;
result.daddr_src_sel := const;
result.ddata_src_sel := reg_a;
if iphase = 0 then
result.mem_write := '1';
end if;
if xmem_wait = '1' then
result.pc_inc := '0';
result.mem_write := '1';
end if;
when "ADD|R|R " => -- R(a) <= R(a) + R(b)
result.alu_opsel := op1_add_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := reg_b;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "ADD|R|K " => -- R(a) <= R(a) + k
result.alu_opsel := op1_add_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := const;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "ADDC|R|R " => -- R(a) <= R(a) + R(b)
result.alu_opsel := op1_addc_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := reg_b;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "ADDC|R|K " => -- R(a) <= R(a) + k
result.alu_opsel := op1_addc_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := const;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "SUB|R|R " => -- R(a) <= R(a) + R(b)
result.alu_opsel := op1_sub_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := reg_b;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "SUB|R|K " => -- R(a) <= R(a) + k
result.alu_opsel := op1_sub_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := const;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "SUB|K|R " => -- R(a) <= k - R(a)
result.alu_opsel := op1_sub_op2;
result.alu_op1_src_sel := const;
result.alu_op2_src_sel := reg_a;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "SUBC|R|R " => -- R(a) <= R(a) + R(b)
result.alu_opsel := op1_subc_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := reg_b;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "SUBC|R|K " => -- R(a) <= R(a) + k
result.alu_opsel := op1_subc_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := const;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "SUBC|K|R " => -- R(a) <= K - R(a)
result.alu_opsel := op1_subc_op2;
result.alu_op1_src_sel := const;
result.alu_op2_src_sel := reg_a;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "AND|R|R " => -- R(a) <= R(a) and R(b)
result.alu_opsel := op1_and_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := reg_b;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "AND|R|K " => -- R(a) <= R(a) and k
result.alu_opsel := op1_and_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := const;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "OR|R|R " => -- R(a) <= R(a) or R(b)
result.alu_opsel := op1_or_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := reg_b;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "OR|R|K " => -- R(a) <= R(a) or R(b)
result.alu_opsel := op1_or_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := const;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "XOR|R|R " => -- R(a) <= R(a) xor R(b)
result.alu_opsel := op1_xor_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := reg_b;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "XOR|R|K " => -- R(a) <= R(a) xor R(b)
result.alu_opsel := op1_xor_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := const;
result.reg_src_sel := alu_src;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "SWAP|R " => -- R(a) <= R(b)
result.reg_src_sel := alu_src;
result.alu_opsel := swap_op;
result.alu_op1_src_sel := reg_a;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "SHL|R " => -- R(a) <= R(a) xor R(b)
result.reg_src_sel := alu_src;
result.alu_opsel := shl_op;
result.alu_op1_src_sel := reg_a;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "SHR|R " => -- R(a) <= R(a) xor R(b)
result.reg_src_sel := alu_src;
result.alu_opsel := shr_op;
result.alu_op1_src_sel := reg_a;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "ROL|R " => -- R(a) <= R(a) xor R(b)
result.reg_src_sel := alu_src;
result.alu_opsel := rol_op;
result.alu_op1_src_sel := reg_a;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "ROR|R " => -- R(a) <= R(a) xor R(b)
result.reg_src_sel := alu_src;
result.alu_opsel := ror_op;
result.alu_op1_src_sel := reg_a;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "ROLC|R " => -- R(a) <= R(a) xor R(b)
result.reg_src_sel := alu_src;
result.alu_opsel := rolc_op;
result.alu_op1_src_sel := reg_a;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "RORC|R " => -- R(a) <= R(a) xor R(b)
result.reg_src_sel := alu_src;
result.alu_opsel := rorc_op;
result.alu_op1_src_sel := reg_a;
result.alu_load := '1';
if iphase = 1 then
result.reg_we := '1';
end if;
when "CMP|R|R " => --
result.alu_opsel := op1_sub_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := reg_b;
result.alu_load := '1';
when "CMP|R|K " => --
result.alu_opsel := op1_sub_op2;
result.alu_op1_src_sel := reg_a;
result.alu_op2_src_sel := const;
result.alu_load := '1';
when "JMP|K " => -- PC <= #addr
if iphase = 0 then
result.pc_load := '1';
end if;
when "JZ|K " => -- PC <= #addr, zero
if iphase = 0 then
if ze = '1' then
result.pc_load := '1';
end if;
end if;
when "JNZ|K " => -- PC <= #addr, !zero
if iphase = 0 then
if ze = '0' then
result.pc_load := '1';
end if;
end if;
when "JC|K " => -- PC <= #addr, carry
if iphase = 0 then
if cy = '1' then
result.pc_load := '1';
end if;
end if;
when "JNC|K " => -- PC <= #addr, !carry
if iphase = 0 then
if cy = '0' then
result.pc_load := '1';
end if;
end if;
when "JLT|K " => -- PC <= #addr, !carry
if iphase = 0 then
if cy = '1' then
result.pc_load := '1';
end if;
end if;
when "JGT|K " => --
if iphase = 0 then
if (cy or ze) = '0' then
result.pc_load := '1';
end if;
end if;
when "JLE|K " => --
if iphase = 0 then
if (cy xor ze) = '1' then
result.pc_load := '1';
end if;
end if;
when "JGE|K " => --
if iphase = 0 then
if (not cy or ze) = '1' then
result.pc_load := '1';
end if;
end if;
when "JEQ|K " => --
if iphase = 0 then
if ze = '1' then
result.pc_load := '1';
end if;
end if;
when "JNE|K " => --
if iphase = 0 then
if ze = '0' then
result.pc_load := '1';
end if;
end if;
when "PUSH|R " => -- push
if iphase = 0 then
result.stk_pushd := '1';
end if;
when "POP|R " => -- pop
result.reg_src_sel := stk_src;
if iphase = 0 then
result.stk_popd := '1';
elsif iphase = 1 then
result.reg_we := '1';
end if;
when "CALL|K " => -- call
if iphase = 0 then
result.pc_load := '1';
result.stk_push := '1';
end if;
when "RET " => -- return
if iphase = 0 then
result.pc_load := '1';
result.stk_pop := '1';
end if;
when "RETI " => -- return
result.pc_inc := '0';
result.int_exit := '1';
when others => null; -- nop
end case;
return result;
end idecoder;
function gen_murom return murom_t is
variable result : murom_t;
variable opcode : opcode_t;
variable iphase : iphase_t;
variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
variable status : cpu_status_t;
variable pos : integer := 0;
begin
for i in 0 to 2**addr'length-1 loop
addr := to_unsigned(i, addr'length);
opcode := addr(opcode'length-1 downto 0);
pos := opcode'length;
iphase := 0;
if addr(pos) = '1' then
iphase := 1;
end if;
pos := pos + 1;
status.alu.zero := addr(pos);
pos := pos + 1;
status.alu.carry := addr(pos);
pos := pos + 1;
status.xmem_wait := addr(pos);
result(i) := idecoder(opcode, iphase, status);
end loop;
return result;
end gen_murom;
function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned is
variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
begin
addr := status.xmem_wait & status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode;
return addr;
end get_muromaddr;
-------------------------------------------------------------
function MIN (X, Y: INTEGER) return INTEGER is
variable res : integer := X;
begin
if Y < X then
res := Y;
end if;
return res;
end MIN;
-------------------------------------------------------------
function MAX (X, Y: INTEGER) return INTEGER is
variable res : integer := X;
begin
if Y > X then
res := Y;
end if;
return res;
end MAX;
end cpu_pkg;
lib/CPUs/JCpu/src/core/dpath_ctrl.vhd
+87
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@@ -0,0 +1,87 @@
--------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The datapath controller
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.cpu_pkg.all;
entity dpath_ctrl is
Generic (
use_rom : boolean := true
);
Port (
inst_in : in inst_t;
iphase_in : in iphase_t;
status_in : in cpu_status_t;
ctrl_out : out dpath_ctrl_out_t;
idout : out inst_addr_t;
ddout : out dmem_data_t
);
end dpath_ctrl;
architecture Behavioral of dpath_ctrl is
signal opcode : opcode_t;
signal ctrl_lines : ctrl_lines_t;
signal dbg_iname : instr_name_t;
begin
idout <= inst_in(IMEM_ADDR_WIDTH-1 downto 0);
ddout <= inst_in(REG_SIZE_BITS+DMEM_DATA_WIDTH-1 downto REG_SIZE_BITS);
opcode <= inst_in(IMEM_DATA_WIDTH-1 downto IMEM_DATA_WIDTH-INST_OPCODE_WIDTH);
ctrl_out.reg_a_ptr <= inst_in(reg_ptr_t'length-1 downto 0);
ctrl_out.reg_b_ptr <= inst_in(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length);
ctrl_out.lines <= ctrl_lines;
-- pragma translate_off
dbg_iname <= instr_name_array(to_integer(opcode));
-- pragma translate_on
gen_ctrl_rom:
if use_rom = true generate
i_dec:
process(opcode, iphase_in, status_in)
constant rom_data : murom_t := gen_murom;
variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
begin
addr := get_muromaddr(opcode, iphase_in, status_in);
ctrl_lines <= rom_data(to_integer(addr));
end process;
end generate;
gen_ctrl:
if use_rom = false generate
i_dec:
process (opcode, iphase_in, status_in)
begin
ctrl_lines <= idecoder(opcode, iphase_in, status_in);
end process;
end generate;
end Behavioral;
lib/CPUs/JCpu/src/core/int_ctrl.vhd
+177
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@@ -0,0 +1,177 @@
--------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Interrupt controller
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.cpu_pkg.all;
entity int_ctrl is
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ctrl_in : in int_ctrl_in_t;
int_in : in STD_LOGIC;
int_exit : in STD_LOGIC;
iphase_in : in iphase_t;
pc_addr_out : out inst_addr_t;
int_ack_out : out STD_LOGIC;
stat_save_out : out STD_LOGIC;
stat_rest_out : out STD_LOGIC;
pc_load_out : out STD_LOGIC;
stk_push_out : out STD_LOGIC;
stk_pop_out : out STD_LOGIC
);
end int_ctrl;
architecture Behavioral of int_ctrl is
type int_state_t is (int_idle, int_inject, int_active, int_release);
type pin_state_t is (pin_s0, pin_s1, pin_s2);
signal int_state, int_state_next : int_state_t;
signal pin_state, pin_state_next : pin_state_t;
signal pc_load, int_ack, stk_push, stk_pop : STD_LOGIC;
signal int_request : std_logic;
signal int_sampled : std_logic;
begin
int_ack_out <= int_ack;
pc_load_out <= pc_load;
stk_push_out <= stk_push;
stk_pop_out <= stk_pop;
-----------------------------------------------------------------------
irg_ctrl_fsm:
process (int_state, iphase_in, int_request, int_exit)
begin
pc_addr_out <= to_unsigned(1, inst_addr_t'length);
int_state_next <= int_state;
int_ack <= '0';
pc_load <= '0';
stk_push <= '0';
stk_pop <= '0';
case int_state is
when int_idle =>
if int_request = '1' and iphase_in = 1 then
int_state_next <= int_inject;
end if;
when int_inject =>
if iphase_in = 0 then
int_ack <= '1';
pc_load <= '1';
elsif iphase_in = 1 then
stk_push <= '1';
int_state_next <= int_active;
end if;
when int_active =>
if int_exit = '1' and iphase_in = 1 then
int_state_next <= int_release;
end if;
when int_release =>
if iphase_in = 0 then
stk_pop <= '1';
pc_load <= '1';
elsif iphase_in = 1 then
int_state_next <= int_idle;
end if;
when others =>
int_state_next <= int_idle;
end case;
end process;
irq_ctrl_states:
process (rst, clk, int_state_next)
begin
if rst = '1' then
int_state <= int_idle;
elsif rising_edge(clk) then
int_state <= int_state_next;
end if;
end process;
-----------------------------------------------------------------------
pin_sample:
process (clk)
begin
if rising_edge(clk) then
int_sampled <= int_in xor (not ctrl_in.polarity);
end if;
end process;
-----------------------------------------------------------------------
pin_fsm:
process (pin_state, int_sampled, int_ack, ctrl_in)
begin
int_request <= '0';
pin_state_next <= pin_state;
case pin_state is
when pin_s0 =>
if int_sampled = '1' or ctrl_in.request = '1' then
if ctrl_in.enable = '1' then
pin_state_next <= pin_s1;
end if;
end if;
when pin_s1 =>
int_request <= '1';
if int_ack = '1' then
pin_state_next <= pin_s2;
end if;
when pin_s2 =>
if ctrl_in.edge_sens = '0' then
pin_state_next <= pin_s0;
elsif int_sampled = '0' then
pin_state_next <= pin_s0;
end if;
when others =>
pin_state_next <= pin_s0;
end case;
end process;
pin_states:
process (rst, clk, pin_state_next)
begin
if rst = '1' then
pin_state <= pin_s0;
elsif rising_edge(clk) then
pin_state <= pin_state_next;
end if;
end process;
-----------------------------------------------------------------------
stat_save_restore:
process (clk, stk_push, stk_pop)
begin
if rising_edge(clk) then
stat_save_out <= stk_push;
stat_rest_out <= stk_pop;
end if;
end process;
end Behavioral;
lib/CPUs/JCpu/src/core/pc.vhd
+70
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@@ -0,0 +1,70 @@
--------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Programm counter
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.cpu_pkg.all;
entity pc is
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
inc : in STD_LOGIC;
load : in STD_LOGIC;
pc_in : in inst_addr_t;
pc_out : out inst_addr_t;
pc_next : out inst_addr_t
);
end pc;
architecture Behavioral of pc is
begin
proc_pc:
process(rst, clk, inc, load, pc_in)
variable vpc, vpc_reg: inst_addr_t;
begin
if rst = '1' then
vpc_reg := (others => '0');
elsif rising_edge(clk) then
if inc = '1' or load = '1' then
vpc_reg := vpc;
elsif inc = '0' then
pc_next <= vpc;
end if;
end if;
if load = '1' then
vpc := pc_in;
else
vpc := vpc_reg + 1;
end if;
pc_out <= vpc_reg;
end process;
end Behavioral;
lib/CPUs/JCpu/src/core/reg_dual.vhd
+81
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@@ -0,0 +1,81 @@
--------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: On-Chip work registers
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.cpu_pkg.all;
entity reg_dual is
Generic (
addr_width : integer := 3;
data_width : integer := 8
);
Port (
clk : in STD_LOGIC;
we_a : in STD_LOGIC;
ptr_a : in reg_ptr_t;
ptr_b : in reg_ptr_t;
din_a : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end reg_dual;
architecture Behavioral of reg_dual is
constant depth : integer := 2**addr_width;
type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal addr_a, addr_b : unsigned (addr_width-1 downto 0) := (others => '0');
signal mem : mem_t;
begin
addr_a <= TO_01(ptr_a(addr_width-1 downto 0));
addr_b <= TO_01(ptr_b(addr_width-1 downto 0));
reg_in_ab:
process(clk)
begin
if rising_edge(clk) then
if we_a = '1' then
mem(to_integer(addr_a)) <= din_a;
end if;
end if;
end process;
reg_out_a:
process(mem, addr_a)
begin
dout_a <= TO_01(mem(to_integer(addr_a)));
end process;
reg_out_b:
process(mem, addr_b)
begin
dout_b <= TO_01(mem(to_integer(addr_b)));
end process;
end Behavioral;
lib/CPUs/JCpu/src/core/stack_ctrl.vhd
+73
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--------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The call/return/data stack
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.cpu_pkg.all;
entity stack_ctrl is
Generic (
addr_width : integer := 3
);
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
push : in STD_LOGIC;
pop : in STD_LOGIC;
ptr_out : out unsigned (addr_width-1 downto 0);
din : in inst_addr_t;
dout : out inst_addr_t;
mem_we : out STD_LOGIC
);
end stack_ctrl;
architecture Behavioral of stack_ctrl is
signal ptr : unsigned (addr_width-1 downto 0);
begin
ptr_out <= ptr;
stk_ptr:
process(rst, clk, ptr, push, pop)
begin
if rst = '1' then
ptr <= (others => '0');
dout <= (others => '0');
mem_we <= '0';
elsif rising_edge(clk) then
mem_we <= push;
if push = '1' then
ptr <= ptr + 1;
dout <= din;
elsif pop = '1' then
ptr <= ptr - 1;
end if;
end if;
end process;
end Behavioral;