Initial import
git-svn-id: http://moon:8086/svn/vhdl/trunk@2 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,56 @@
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; -------------------------------------------------
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; PROJECT "dctest"
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; -------------------------------------------------
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include "../../../jasm/cregs.inc.jsm"
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; -------------------------------------------------
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xmem
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org 4
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konst: dc 0x01, 0x12,"A"
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gap1: db 16
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mesg: dc "Hallo", 13,0x0A, 0
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name: dc "Jens",0
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msg1: dc "Welcome to JASM CPU",0
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msg2: dc "Ready",0
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msg3: dc "Testing",0
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msg4: dc "Passed",0
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msg5: dc "Error",0
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crlf: dc 0x0D, 0x0A
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org 0x00
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shit: db 4
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cmem 0
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org 8
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cram1: db 16
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cram2: db 6
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cram3: db 4
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cmem 1
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cram4: db 8
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cram5: db 8
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org 0x20
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cram6: db 8
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cram7: db 4
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reg_revision: equ 0x00
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reg_testid: equ 0x01
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; -------------------------------------------------
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code
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org 0x000
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reset: jmp start
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; -------------------------------------------------
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org 0x001
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int_vec: jmp isr
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; -------------------------------------------------
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org 0x010
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start: jmp start
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; -------------------------------------------------
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isr: reti
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@@ -0,0 +1,212 @@
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# ----------------------------------------------------------------------
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# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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# This file: The ROM file for upload to target over JTAG
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#
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# Copyright (C) 2007 J. Ahrensfeld
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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# For questions and ideas, please contact the author at jens@jayfield.org
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#
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# ---------------------------------------------------------------------
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# ---------------------------------------------------------------------
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# For Chipscope 9.1
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# ---------------------------------------------------------------------
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# Source JTAG/TCL frame work
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cd $env(CHIPSCOPE)\\bin\\nt
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source csejtag.tcl
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namespace import ::chipscope::*
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# Platform USB Cable
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set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
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# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
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# Create session
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set handle [::chipscope::csejtag_session create 0]
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# Open JTAG and lock
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set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
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set lock_result [::chipscope::csejtag_target lock $handle 1000]
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set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
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# Get Device ID
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set devtype "Virtex-4SX"
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set devid 2
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set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
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set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
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set CSE_OP $CSEJTAG_SHIFT_READWRITE
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set CSE_ES $CSEJTAG_RUN_TEST_IDLE
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# Write Program
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# JASM_ROM_INSERT_HERE
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# Assembled from dctest.jsm
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# ---------------------------------------------------------------
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# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
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# User 1
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set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
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# 0x000: JMP 0x010
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010"
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# 0x001: JMP 0x011
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130011"
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# 0x002:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000"
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# 0x003:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000"
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# 0x004:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000"
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# 0x005:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
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# 0x006:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000"
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# 0x007:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
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# 0x008:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000"
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# 0x009:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
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# 0x00A:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000"
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# 0x00B:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
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# 0x00C:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000"
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# 0x00D:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
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# 0x00E:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000"
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# 0x00F:
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
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# 0x010: JMP 0x010
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01030010"
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# 0x011: RETI
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0113F000"
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# Assembled from dctest.jsm
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# ---------------------------------------------------------------
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# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
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# User 2
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set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0000"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0100"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0300"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0401"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0512"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0641"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1748"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1861"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "196C"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A6C"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B6F"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C0D"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D0A"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F4A"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2065"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "216E"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2273"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2457"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2565"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "266C"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2763"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "286F"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "296D"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A65"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B20"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C74"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D6F"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E20"
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F4A"
|
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3041"
|
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3153"
|
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "324D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3320"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3443"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3550"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3655"
|
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::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3852"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3965"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A61"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B64"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C79"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E54"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F65"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4073"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4174"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4269"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "436E"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4467"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4650"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4761"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4873"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4973"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A65"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B64"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D45"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E72"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F72"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "506F"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5172"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "530D"
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "540A"
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -0,0 +1,858 @@
|
||||
; -------------------------------------------------
|
||||
; PROJECT "itest"
|
||||
; -------------------------------------------------
|
||||
|
||||
include "../../../jasm/cregs.inc.jsm"
|
||||
|
||||
; -------------------------------------------------
|
||||
xmem
|
||||
msg: dc "Hallo", 0
|
||||
xram: db 256
|
||||
|
||||
cmem 0
|
||||
cram: db 256
|
||||
|
||||
reg_revision: equ 0x00
|
||||
reg_testid: equ 0x01
|
||||
|
||||
; -------------------------------------------------
|
||||
code
|
||||
org 0x000
|
||||
reset: jmp start
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x001
|
||||
int_vec: jmp isr
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x010
|
||||
|
||||
start: call init
|
||||
cin R0, (cpu_revision)
|
||||
xout (reg_revision), R0
|
||||
|
||||
; Test 0
|
||||
call test0
|
||||
|
||||
; Test 1
|
||||
mov R0, 1
|
||||
xout (reg_testid), R0
|
||||
call test1
|
||||
|
||||
; Test 2
|
||||
mov R0, 2
|
||||
xout (reg_testid), R0
|
||||
call test2
|
||||
|
||||
; Test 3
|
||||
mov R0, 3
|
||||
xout (reg_testid), R0
|
||||
call test3
|
||||
|
||||
; Test 4
|
||||
mov R0, 4
|
||||
xout (reg_testid), R0
|
||||
call test4
|
||||
|
||||
; Test 5
|
||||
mov R0, 5
|
||||
xout (reg_testid), R0
|
||||
call test5
|
||||
|
||||
; Test 6
|
||||
mov R0, 6
|
||||
xout (reg_testid), R0
|
||||
call test6
|
||||
|
||||
; Test 7
|
||||
mov R0, 7
|
||||
xout (reg_testid), R0
|
||||
call test7
|
||||
|
||||
; Test 8
|
||||
mov R0, 8
|
||||
xout (reg_testid), R0
|
||||
call test8
|
||||
|
||||
; Test 9
|
||||
mov R0, 9
|
||||
xout (reg_testid), R0
|
||||
call test9
|
||||
|
||||
; Test 10
|
||||
mov R0, 10
|
||||
xout (reg_testid), R0
|
||||
call test10
|
||||
|
||||
; Test 11
|
||||
mov R0, 11
|
||||
xout (reg_testid), R0
|
||||
call test11
|
||||
|
||||
; Test 12
|
||||
mov R0, 12
|
||||
xout (reg_testid), R0
|
||||
call test12
|
||||
|
||||
; End of test
|
||||
mov R0, 0xFF
|
||||
xout (reg_testid), R0
|
||||
|
||||
jmp ok
|
||||
|
||||
; -------------------------------------------------
|
||||
init: mov R0, 0
|
||||
mov R1, 0
|
||||
mov R2, 0
|
||||
mov R3, 0
|
||||
mov R4, 0
|
||||
mov R5, 0
|
||||
mov R6, 0
|
||||
mov R7, 0
|
||||
mov R8, 0
|
||||
mov R9, 0
|
||||
mov R10, 0
|
||||
mov R11, 0
|
||||
mov R12, 0
|
||||
mov R13, 0
|
||||
mov R14, 0
|
||||
mov R15, 0
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; MOV|R|K
|
||||
; MOV|R|R
|
||||
test0: mov R0, 0x10
|
||||
cmp R0, 0x10
|
||||
jne error
|
||||
add R0, 1
|
||||
|
||||
mov R1, R0
|
||||
cmp R1, 0x11
|
||||
jne error
|
||||
add R1, 1
|
||||
|
||||
mov R2, R1
|
||||
cmp R2, 0x12
|
||||
jne error
|
||||
add R2, 1
|
||||
|
||||
mov R3, R2
|
||||
cmp R3, 0x13
|
||||
jne error
|
||||
add R3, 1
|
||||
|
||||
mov R4, R3
|
||||
cmp R4, 0x14
|
||||
jne error
|
||||
add R4, 1
|
||||
|
||||
mov R5, R4
|
||||
cmp R5, 0x15
|
||||
jne error
|
||||
add R5, 1
|
||||
|
||||
mov R6, R5
|
||||
cmp R6, 0x16
|
||||
jne error
|
||||
add R6, 1
|
||||
|
||||
mov R7, R6
|
||||
cmp R7, 0x17
|
||||
jne error
|
||||
add R7, 1
|
||||
|
||||
mov R8, R7
|
||||
cmp R8, 0x18
|
||||
jne error
|
||||
add R8, 1
|
||||
|
||||
mov R9, R8
|
||||
cmp R9, 0x19
|
||||
jne error
|
||||
add R9, 1
|
||||
|
||||
mov R10, R9
|
||||
cmp R10, 0x1A
|
||||
jne error
|
||||
add R10, 1
|
||||
|
||||
mov R11, R10
|
||||
cmp R11, 0x1B
|
||||
jne error
|
||||
add R11, 1
|
||||
|
||||
mov R12, R11
|
||||
cmp R12, 0x1C
|
||||
jne error
|
||||
add R12, 1
|
||||
|
||||
mov R13, R12
|
||||
cmp R13, 0x1D
|
||||
jne error
|
||||
add R13, 1
|
||||
|
||||
mov R14, R13
|
||||
cmp R14, 0x1E
|
||||
jne error
|
||||
add R14, 1
|
||||
|
||||
mov R15, R14
|
||||
cmp R15, 0x1F
|
||||
jne error
|
||||
add R15, 1
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Instruction test
|
||||
; TST|R
|
||||
; CMP|R|K
|
||||
; JNZ|K
|
||||
; JC|K
|
||||
; JNE|K
|
||||
; JLT|K
|
||||
; JGT|K
|
||||
; JLE|K
|
||||
; JGE|K
|
||||
; JMP|K
|
||||
test1: mov R0, 0 ; R0 <= 0
|
||||
tst R0
|
||||
jnz error
|
||||
jc error
|
||||
cmp R0, 0
|
||||
jne error
|
||||
jlt error
|
||||
jgt error
|
||||
jle t1_ok10
|
||||
jmp error
|
||||
|
||||
t1_ok10: jeq t1_ok20
|
||||
jmp error
|
||||
|
||||
t1_ok20: jge t1_ok30
|
||||
jmp error
|
||||
|
||||
t1_ok30: cmp R0, 0x55
|
||||
jeq error
|
||||
jlt t1_ok40
|
||||
jmp error
|
||||
|
||||
t1_ok40: jle t1_ok50
|
||||
jmp error
|
||||
|
||||
t1_ok50: jge error
|
||||
jgt error
|
||||
|
||||
mov R0, 0x55 ; R0 <= 0xAA
|
||||
tst R0
|
||||
jz error
|
||||
jc error
|
||||
|
||||
cmp R0, 0xAA
|
||||
jeq error
|
||||
jne t1_ok60
|
||||
jmp error
|
||||
|
||||
t1_ok60: jlt t1_ok70
|
||||
jmp error
|
||||
|
||||
t1_ok70: jle t1_ok80
|
||||
jmp error
|
||||
|
||||
t1_ok80: jgt error
|
||||
|
||||
cmp R0, 0x55
|
||||
jeq t1_ok90
|
||||
jmp error
|
||||
|
||||
t1_ok90: jne error
|
||||
jlt error
|
||||
|
||||
jle t1_ok100
|
||||
jmp error
|
||||
|
||||
t1_ok100: jgt error
|
||||
jge t1_ok110
|
||||
jmp error
|
||||
|
||||
t1_ok110: mov R0, 0xAA ; R0 <= 0x55
|
||||
tst R0
|
||||
jz error
|
||||
jc error
|
||||
|
||||
cmp R0, 0x55
|
||||
jeq error
|
||||
jne t1_ok120
|
||||
jmp error
|
||||
|
||||
t1_ok120: jgt t1_ok130
|
||||
jmp error
|
||||
|
||||
t1_ok130: jge t1_ok140
|
||||
jmp error
|
||||
|
||||
t1_ok140: jlt error
|
||||
jle error
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; ADD|R|K
|
||||
; ADDC|R|K
|
||||
; ToDo: ADD|R|R
|
||||
; ToDo: ADDC|R|R
|
||||
; CMP|R|R
|
||||
test2: mov R0, 0
|
||||
mov R1, 0
|
||||
mov R2, R0
|
||||
mov R3, R1
|
||||
|
||||
t2_loop: add R0, 0x01
|
||||
addc R1, 0x00
|
||||
add R2, 1
|
||||
cmp R2, 0
|
||||
jne t2_L1
|
||||
add R3, 1
|
||||
cmp R3, 0x02
|
||||
t2_L1: jne t2_loop
|
||||
cmp R0, R2
|
||||
jne error
|
||||
cmp R1, R3
|
||||
jne error
|
||||
mov R0, 0
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; SUB|R|K
|
||||
; SUBC|R|K
|
||||
; ToDo: SUB|R|R
|
||||
; ToDo: SUBC|R|R
|
||||
; CMP|R|R
|
||||
test3: mov R0, 0x00
|
||||
mov R1, 0x03
|
||||
mov R2, R0
|
||||
mov R3, R1
|
||||
|
||||
t3_loop: sub R0, 0x01
|
||||
subc R1, 0x00
|
||||
sub R2, 1
|
||||
cmp R2, 0xFF
|
||||
jne t3_L1
|
||||
sub R3, 1
|
||||
cmp R3, 0x00
|
||||
t3_L1: jne t3_loop
|
||||
cmp R0, R2
|
||||
jne error
|
||||
cmp R1, R3
|
||||
jne error
|
||||
mov R0, 0
|
||||
|
||||
ret
|
||||
; -------------------------------------------------
|
||||
; SUB|K|R
|
||||
; SUB|R|R
|
||||
; SUBC|R|R
|
||||
; SUBC|K|R
|
||||
; CMP|R|R
|
||||
test4: mov R0, 0x03
|
||||
mov R1, 0x05
|
||||
sub 0x05, R0
|
||||
sub R1, 0x03
|
||||
cmp R0, R1
|
||||
jne error
|
||||
mov R0, 0x03
|
||||
mov R1, 0x05
|
||||
sub R0, R1
|
||||
subc 0, R0
|
||||
cmp R0, 0x01
|
||||
jne error
|
||||
add R0, 0
|
||||
subc R1, R0
|
||||
cmp R1, 0x04
|
||||
jne error
|
||||
mov R0, 0
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; MOVC|R|Ri
|
||||
; MOVC|R|Ki
|
||||
; MOVC|Ri|R
|
||||
; MOVC|Ri|K
|
||||
; MOVC|Ki|R
|
||||
test5: mov R0, 1
|
||||
movc (cram+0x5A), R0
|
||||
dec R0
|
||||
movc (cram+0), R0
|
||||
movc R1, (cram+0x5A)
|
||||
movc (R1), 0xA5
|
||||
movc R0, (R1)
|
||||
movc R1, (R1)
|
||||
add R1, 0xFF-0xA5
|
||||
movc R0, (R1)
|
||||
t5_loop1: movc (R0), R0
|
||||
movc R2, (R0)
|
||||
cmp R2, R0
|
||||
jne error
|
||||
movc (R2), R1
|
||||
movc R2, (R2)
|
||||
cmp R2, R1
|
||||
jne error
|
||||
dec R1
|
||||
inc R0
|
||||
jnz t5_loop1
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; MOVX|R|Ri
|
||||
; MOVX|R|Ki
|
||||
; MOVX|Ri|R
|
||||
; MOVX|Ri|K
|
||||
; MOVX|Ki|R
|
||||
test6: mov R0, 1
|
||||
movx (xram+0x5A), R0
|
||||
dec R0
|
||||
movx (xram+0), R0
|
||||
movx R1, (xram+0x5A)
|
||||
movx (R1), 0xA5
|
||||
movx R0, (R1)
|
||||
movx R1, (R1)
|
||||
add R1, 0xFF-0xA5
|
||||
movx R0, (R1)
|
||||
t6_loop1: movx (R0), R0
|
||||
movx R2, (R0)
|
||||
cmp R2, R0
|
||||
jne error
|
||||
movx (R2), R1
|
||||
movx R2, (R2)
|
||||
cmp R2, R1
|
||||
jne error
|
||||
dec R1
|
||||
inc R0
|
||||
jnz t6_loop1
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; PUSH|R
|
||||
; POP|R
|
||||
test7: mov R0, 0xAA
|
||||
mov R1, 0
|
||||
t7_loop1: push R0
|
||||
inc R0
|
||||
dec R1
|
||||
jnz t7_loop1
|
||||
t7_loop2: pop R0
|
||||
dec R1
|
||||
jnz t7_loop2
|
||||
cmp R0, 0xAA
|
||||
jne error
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; JMP|K
|
||||
; CALL|K
|
||||
; RET
|
||||
test8: mov R0, 0x55
|
||||
push R0
|
||||
mov R0, 0
|
||||
mov R1, 0xFF
|
||||
call t8_rec
|
||||
pop R0
|
||||
cmp R0, 0x55
|
||||
jne error
|
||||
|
||||
; Stack manipulations 1
|
||||
mov R0, return1'high
|
||||
mov R1, return1'low
|
||||
cout (cpu_stack_high), R0
|
||||
push R1
|
||||
|
||||
mov R0, init'high
|
||||
mov R1, init'low
|
||||
cout (cpu_stack_high), R0
|
||||
push R1
|
||||
ret
|
||||
|
||||
; Stack manipulations 2
|
||||
return1: mov R0, return2'high
|
||||
mov R1, return2'low
|
||||
cout (cpu_stack_high), R0
|
||||
push R1
|
||||
|
||||
mov R0, init'high
|
||||
mov R1, init'low
|
||||
cout (cpu_stack_high), R0
|
||||
push R1
|
||||
return2: ret
|
||||
|
||||
t8_rec: cmp R0, R1
|
||||
jeq ex_t8_rec
|
||||
inc R0
|
||||
jmp t8_rstub
|
||||
ex_t8_rec: dec R0
|
||||
dec R1
|
||||
ret
|
||||
|
||||
t8_rstub: call t8_rec
|
||||
jmp ex_t8_rec
|
||||
|
||||
; -------------------------------------------------
|
||||
; SWAP|R
|
||||
; SHL|R
|
||||
; SHR|R
|
||||
; ROL|R
|
||||
; ROR|R
|
||||
; ROLC|R
|
||||
; RORC|R
|
||||
test9: mov R0, 0xA5 ; SWAP test
|
||||
mov R1, 0x5A
|
||||
swap R0
|
||||
cmp R0, 0x5A
|
||||
jne error
|
||||
swap R0
|
||||
cmp R0, 0xA5
|
||||
jne error
|
||||
mov R0, 0xD2
|
||||
swap R0
|
||||
cmp R0, 0x2D
|
||||
jne error
|
||||
swap R1
|
||||
cmp R0, 0x2D
|
||||
jne error
|
||||
cmp R1, 0xA5
|
||||
jne error
|
||||
|
||||
mov R0, 0x2D
|
||||
shl R0 ; SHL test
|
||||
cmp R0, 0x5A
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0xB4
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0x68
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0xD0
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0xA0
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0x40
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0x80
|
||||
jne error
|
||||
shl R0
|
||||
cmp R0, 0x00
|
||||
jne error
|
||||
|
||||
mov R1, 0x84
|
||||
shr R1 ; SHR test
|
||||
cmp R1, 0x42
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x21
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x10
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x08
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x04
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x02
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x01
|
||||
jne error
|
||||
shr R1
|
||||
cmp R1, 0x00
|
||||
jne error
|
||||
|
||||
mov R0, 0xC5 ; ROL test
|
||||
rol R0
|
||||
cmp R0, 0x8B
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0x17
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0x2E
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0x5C
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0xB8
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0x71
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0xE2
|
||||
jne error
|
||||
rol R0
|
||||
cmp R0, 0xC5
|
||||
jne error
|
||||
|
||||
mov R1, 0x63 ; ROR test
|
||||
ror R1
|
||||
cmp R1, 0xB1
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0xD8
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x6C
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x36
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x1B
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x8D
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0xC6
|
||||
jne error
|
||||
ror R1
|
||||
cmp R1, 0x63
|
||||
jne error
|
||||
|
||||
|
||||
xor R0, R0 ; ROLC generate
|
||||
mov R0, 0xC5
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
push R0
|
||||
rolc R0
|
||||
|
||||
cmp R0, 0xC5 ; ROLC verify
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x62
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0xB1
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x58
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0xAC
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x56
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x2B
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x15
|
||||
jne error
|
||||
pop R0
|
||||
cmp R0, 0x8A
|
||||
jne error
|
||||
|
||||
xor R1, R1 ; RORC generate
|
||||
mov R1, 0x63
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
push R1
|
||||
rorc R1
|
||||
|
||||
cmp R1, 0x63 ; RORC verify
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0xC6
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x8C
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x19
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x33
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x66
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0xCC
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x98
|
||||
jne error
|
||||
pop R1
|
||||
cmp R1, 0x31
|
||||
jne error
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; AND|R|R
|
||||
; AND|R|K
|
||||
; OR|R|R
|
||||
; OR|R|K
|
||||
; XOR|R|R
|
||||
; XOR|R|K
|
||||
test10: mov R0, 0xA5 ; AND
|
||||
swap R0
|
||||
push R0
|
||||
and R0, 0x0F
|
||||
cmp R0, 0x0A
|
||||
jne error
|
||||
pop R0
|
||||
push R0
|
||||
and R0, 0x0F
|
||||
cmp R0, 0x0A
|
||||
pop R1
|
||||
jne error
|
||||
swap R1
|
||||
mov R2, 0x0F
|
||||
and R1, R2
|
||||
cmp R1, 0x05
|
||||
jne error
|
||||
|
||||
mov R0, 0x05 ; OR
|
||||
mov R2, 0xA0
|
||||
swap R0
|
||||
or R2, R0
|
||||
cmp R2, 0xF0
|
||||
jne error
|
||||
swap R0
|
||||
or R0, 0x50
|
||||
cmp R0, 0x55
|
||||
jne error
|
||||
|
||||
mov R1, 0x01
|
||||
mov R0, 0x01
|
||||
xor R0, 0x01
|
||||
jnz error
|
||||
xor R0, R1
|
||||
cmp R0, 0x01
|
||||
jne error
|
||||
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
test11:
|
||||
mov R0, 0x03
|
||||
cout (cpu_int_ctrl), R0
|
||||
|
||||
xin R0, (2)
|
||||
or R0, 1
|
||||
xout (2), R0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
xin R0, (2)
|
||||
and R0, 0xFE
|
||||
xout (2), R0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x80
|
||||
cout (cpu_int_ctrl), R0
|
||||
nop
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x80
|
||||
cout (cpu_int_ctrl), R0
|
||||
nop
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x80
|
||||
cout (cpu_int_ctrl), R0
|
||||
nop
|
||||
cin R0, (cpu_int_ctrl)
|
||||
or R0, 0x80
|
||||
cout (cpu_int_ctrl), R0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
; Tests clrc, setc
|
||||
test12: sub R0, 0
|
||||
jc error
|
||||
setc
|
||||
jnc error
|
||||
nop
|
||||
sub R0, 0
|
||||
jc error
|
||||
|
||||
mov R0, 0
|
||||
clrc
|
||||
jc error
|
||||
setc
|
||||
jnc error
|
||||
nop
|
||||
clrc
|
||||
jc error
|
||||
ret
|
||||
|
||||
; -------------------------------------------------
|
||||
isr: inc R14
|
||||
reti
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x3FF
|
||||
error: jmp error
|
||||
|
||||
; -------------------------------------------------
|
||||
org 0x2FF
|
||||
ok: jmp ok
|
||||
|
||||
; -------------------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,50 @@
|
||||
#!/bin/sh
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: rom-file generation for cpu_core
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
TARGET=$2
|
||||
DSTDIR=$1
|
||||
|
||||
JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
|
||||
|
||||
$JASM_HOME/jasm.rb $TARGET.jsm
|
||||
|
||||
irom_tcl_snippet="$TARGET.irom.tcl.snip"
|
||||
irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
|
||||
irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
|
||||
xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
|
||||
xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
|
||||
xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
|
||||
|
||||
$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
|
||||
$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
|
||||
|
||||
$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
|
||||
$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
|
||||
|
||||
cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
|
||||
cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
|
||||
$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
|
||||
|
||||
rm -f *.snip
|
||||
@@ -0,0 +1,29 @@
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
|
||||
; Chip register
|
||||
include "../../../jasm/cregs.inc.jsm"
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
|
||||
org 0x000
|
||||
reset: jmp init
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
init: mov R0, 0x45
|
||||
mov R1, 0xF5
|
||||
|
||||
call mul8x8
|
||||
stop: jmp stop
|
||||
|
||||
|
||||
; -------------------------------------------------
|
||||
include "../../../jasm/mul8x8.inc.jsm"
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,154 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
# Assembled from mul8x8.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
|
||||
# User 1
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
|
||||
|
||||
# 0x000: JMP 0x001
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030001"
|
||||
|
||||
# 0x001: MOV R00, 0x45
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00103450"
|
||||
|
||||
# 0x002: MOV R01, 0xF5
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203F51"
|
||||
|
||||
# 0x003: CALL 0x005
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0033B005"
|
||||
|
||||
# 0x004: JMP 0x004
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00430004"
|
||||
|
||||
# 0x005: PUSH R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0053C002"
|
||||
|
||||
# 0x006: PUSH R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0063C003"
|
||||
|
||||
# 0x007: PUSH R04
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0073C004"
|
||||
|
||||
# 0x008: MOV R04, R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00802014"
|
||||
|
||||
# 0x009: MOV R01, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00903001"
|
||||
|
||||
# 0x00A: MOV R02, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A03002"
|
||||
|
||||
# 0x00B: MOV R03, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B03003"
|
||||
|
||||
# 0x00C: CMP R04, 0x01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C0F014"
|
||||
|
||||
# 0x00D: JEQ 0x015
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D39015"
|
||||
|
||||
# 0x00E: SHR R04
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E1F004"
|
||||
|
||||
# 0x00F: JNC 0x012
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F34012"
|
||||
|
||||
# 0x010: ADD R02, R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01010002"
|
||||
|
||||
# 0x011: ADDC R03, R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01112013"
|
||||
|
||||
# 0x012: SHL R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0121E000"
|
||||
|
||||
# 0x013: ROLC R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01322001"
|
||||
|
||||
# 0x014: JMP 0x00C
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143000C"
|
||||
|
||||
# 0x015: ADD R00, R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01510020"
|
||||
|
||||
# 0x016: ADDC R01, R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01612031"
|
||||
|
||||
# 0x017: POP R04
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0173D004"
|
||||
|
||||
# 0x018: POP R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
|
||||
|
||||
# 0x019: POP R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193D002"
|
||||
|
||||
# 0x01A: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A3E000"
|
||||
|
||||
# Assembled from mul8x8.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
|
||||
# User 2
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
|
||||
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -0,0 +1,50 @@
|
||||
; -------------------------------------------------
|
||||
; Constants
|
||||
; -------------------------------------------------
|
||||
|
||||
; Chip register
|
||||
cpu_revision: equ 0x00 ; RO
|
||||
cpu_control: equ 0x01 ; R/W
|
||||
cpu_status: equ 0x02 ; RO
|
||||
cpu_int_ctrl: equ 0x03 ; R/W
|
||||
|
||||
; -------------------------------------------------
|
||||
; Program
|
||||
; -------------------------------------------------
|
||||
code
|
||||
reset: jmp init
|
||||
|
||||
org 0x001
|
||||
; nop
|
||||
reti
|
||||
|
||||
; -------------------------------------------------
|
||||
; Main
|
||||
; -------------------------------------------------
|
||||
init: mov R0, 0x05
|
||||
cout (cpu_int_ctrl), R0
|
||||
mov R0, 0x00
|
||||
loop: nop
|
||||
inc R0
|
||||
nop
|
||||
call subr
|
||||
nop
|
||||
push R3
|
||||
nop
|
||||
push R2
|
||||
nop
|
||||
push R1
|
||||
nop
|
||||
push R0
|
||||
nop
|
||||
pop R0
|
||||
nop
|
||||
pop R1
|
||||
nop
|
||||
pop R2
|
||||
nop
|
||||
pop R3
|
||||
nop
|
||||
jmp loop
|
||||
|
||||
subr: ret
|
||||
@@ -0,0 +1,157 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
# Assembled from reti_issue.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
|
||||
# User 1
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
|
||||
|
||||
# 0x000: JMP 0x002
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002"
|
||||
|
||||
# 0x001: RETI
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000"
|
||||
|
||||
# 0x002: MOV R00, 0x05
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203050"
|
||||
|
||||
# 0x003: COUT (0x03), R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00326030"
|
||||
|
||||
# 0x004: MOV R00, 0x00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00403000"
|
||||
|
||||
# 0x005: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
|
||||
|
||||
# 0x006: INC R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00611010"
|
||||
|
||||
# 0x007: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
|
||||
|
||||
# 0x008: CALL 0x01B
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0083B01B"
|
||||
|
||||
# 0x009: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
|
||||
|
||||
# 0x00A: PUSH R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A3C003"
|
||||
|
||||
# 0x00B: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
|
||||
|
||||
# 0x00C: PUSH R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C3C002"
|
||||
|
||||
# 0x00D: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
|
||||
|
||||
# 0x00E: PUSH R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E3C001"
|
||||
|
||||
# 0x00F: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
|
||||
|
||||
# 0x010: PUSH R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103C000"
|
||||
|
||||
# 0x011: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01100000"
|
||||
|
||||
# 0x012: POP R00
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0123D000"
|
||||
|
||||
# 0x013: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01300000"
|
||||
|
||||
# 0x014: POP R01
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143D001"
|
||||
|
||||
# 0x015: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01500000"
|
||||
|
||||
# 0x016: POP R02
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163D002"
|
||||
|
||||
# 0x017: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01700000"
|
||||
|
||||
# 0x018: POP R03
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
|
||||
|
||||
# 0x019: NOP
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01900000"
|
||||
|
||||
# 0x01A: JMP 0x005
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A30005"
|
||||
|
||||
# 0x01B: RET
|
||||
::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B3E000"
|
||||
|
||||
# Assembled from reti_issue.jsm
|
||||
# ---------------------------------------------------------------
|
||||
# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
|
||||
# User 2
|
||||
set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
|
||||
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
Reference in New Issue
Block a user