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- Shortened BUS-cycle by one clock

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git-svn-id: http://moon:8086/svn/vhdl/trunk@64 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-17 14:25:30 +00:00
parent f8962066f0
commit 329c639c1a
2 changed files with 0 additions and 3 deletions
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lib/CPUs/MIPS/src/core/dcache.vhd
-1
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@@ -378,7 +378,6 @@ cache_state:
end if; end if;
end if; end if;
when upd_cache => when upd_cache =>
CYC_O <= '1';
tram_addr_wr <= cache_index_reg; tram_addr_wr <= cache_index_reg;
tram_we <= '1'; tram_we <= '1';
cache_entry_in.valid <= '1'; cache_entry_in.valid <= '1';
lib/CPUs/MIPS/src/core/icache.vhd
-2
View File
@@ -296,14 +296,12 @@ cache_state:
end if; end if;
end if; end if;
when upd_cache => when upd_cache =>
CYC_O <= '1';
tag_ram_addr_wr <= cache_index_reg; tag_ram_addr_wr <= cache_index_reg;
tag_ram_we <= '1'; tag_ram_we <= '1';
cache_entry_in.valid <= '1'; cache_entry_in.valid <= '1';
sn <= rd_cache; sn <= rd_cache;
when rd_cache => when rd_cache =>
-- CYC_O <= '1';
tag_ram_re <= '1'; tag_ram_re <= '1';
data_ram_re <= '1'; data_ram_re <= '1';
was_miss <= '1'; was_miss <= '1';