- major changes
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@262 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -15,6 +15,26 @@ vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
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vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_sync_dist.vhd"
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# UART
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vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd"
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vcom -explicit -93 "../../../uart/kcuart_rx.vhd"
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vcom -explicit -93 "../../../uart/kcuart_tx.vhd"
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vcom -explicit -93 "../../../uart/uart_rx.vhd"
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vcom -explicit -93 "../../../uart/uart_tx.vhd"
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vcom -explicit -93 "../../../uart/uart_wb.vhd"
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# GPIO
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vcom -explicit -93 "../../../misc/gpio_wb.vhd"
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# Async port
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vcom -explicit -93 "../../../misc/async_types.vhd"
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vcom -explicit -93 "../../../misc/async_port_wb.vhd"
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vcom -explicit -93 "../src/async_defs.vhd"
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# ROM
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vcom -explicit -93 "../src/bootloader.ROM.vhd"
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vcom -explicit -93 "../../../misc/rom_wb.vhd"
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# MIPS
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vcom -explicit -93 "../src/core/mips_types.vhd"
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vcom -explicit -93 "../src/core/mips_instr.vhd"
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@@ -30,10 +50,11 @@ vcom -explicit -93 "../src/core/mips_biu.vhd"
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vcom -explicit -93 "../src/core/mips_bcu.vhd"
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vcom -explicit -93 "../src/core/mips_pipeline.vhd"
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vcom -explicit -93 "../src/core/mips_top.vhd"
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vcom -explicit -93 "../src/tb_mips_top.vhd"
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vsim -t 1ps -lib work tb_mips_top
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do {tb_mips_top.wdo}
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view wave
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view structure
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view signals
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run 40000ns
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run 1200us
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@@ -1,9 +1,9 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -divider {TOP interface}
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal /tb_mips_top/debug
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add wave -noupdate -format Logic /tb_mips_top/rst_i
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add wave -noupdate -format Logic /tb_mips_top/clk_i
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add wave -noupdate -format Logic /tb_mips_top/stb_o
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add wave -noupdate -format Logic /tb_mips_top/ack_i
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add wave -noupdate -format Logic /tb_mips_top/srdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
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@@ -12,20 +12,45 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o
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add wave -noupdate -format Logic /tb_mips_top/we_o
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add wave -noupdate -format Literal /tb_mips_top/sel_o
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add wave -noupdate -format Logic /tb_mips_top/cyc_o
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add wave -noupdate -format Logic /tb_mips_top/stb_o
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add wave -noupdate -format Logic /tb_mips_top/mrdy_o
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add wave -noupdate -format Literal /tb_mips_top/int
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add wave -noupdate -divider {External components}
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Logic /tb_mips_top/rx
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add wave -noupdate -format Logic /tb_mips_top/tx
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal /tb_mips_top/mem_area
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
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add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
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add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
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add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
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add wave -noupdate -format Literal /tb_mips_top/sram_wr_n
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add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
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add wave -noupdate -divider ALU
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
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add wave -noupdate -divider PC
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc
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add wave -noupdate -divider PC
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {21313433 ps} 0}
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WaveRestoreCursors {{Cursor 1} {1199854590 ps} 0}
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configure wave -namecolwidth 188
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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@@ -39,4 +64,4 @@ configure wave -gridperiod 100
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configure wave -griddelta 40
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configure wave -timeline 1
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update
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WaveRestoreZoom {0 ps} {42 us}
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WaveRestoreZoom {0 ps} {1260 us}
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@@ -30,37 +30,23 @@ use std.textio.all; -- Imports the standard textio package.
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library work;
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use work.mips_types.all;
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use work.mips_instr.all;
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use work.async_types.all;
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use work.async_defs.all;
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ENTITY tb_mips_top IS
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END tb_mips_top;
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ARCHITECTURE behavior OF tb_mips_top IS
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COMPONENT mips_top
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PORT
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(
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debug : out unsigned(1 downto 0);
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RST_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC;
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ACK_I : in STD_LOGIC;
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SRDY_I : in STD_LOGIC;
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ADDR_O : out word_t;
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DAT_I : in word_t;
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DAT_O : out word_t;
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WE_O : out STD_LOGIC;
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SEL_O : out unsigned(3 downto 0);
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CYC_O : out STD_LOGIC;
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STB_O : out STD_LOGIC;
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MRDY_O : out STD_LOGIC;
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INT : in unsigned (5 downto 0)
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);
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END COMPONENT;
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constant CLK_PERIOD : time := 10 ns;
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constant CLK_PERIOD : time := 10 ns;
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constant SRAM_ADDR_WIDTH : integer := 16; -- words
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constant FLASH_ADDR_WIDTH : integer := 16; -- words
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signal debug : unsigned(1 downto 0);
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signal RST_I : STD_LOGIC := '1';
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signal CLK_I : STD_LOGIC := '0';
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-- Master
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signal rst : STD_LOGIC := '1';
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signal clk : STD_LOGIC := '0';
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signal ACK_I : STD_LOGIC := '0';
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signal SRDY_I : STD_LOGIC := '0';
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signal ADDR_O : word_t;
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@@ -73,14 +59,142 @@ ARCHITECTURE behavior OF tb_mips_top IS
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signal MRDY_O : STD_LOGIC;
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signal INT : unsigned (5 downto 0) := (others => '0');
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-- Slaves
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signal CYC_I_rom : std_logic;
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signal ACK_O_rom : std_logic;
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signal SRDY_O_rom : std_logic;
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signal DAT_O_rom : unsigned(31 downto 0);
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signal CYC_I_flash : std_logic;
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signal ACK_O_flash : std_logic;
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signal SRDY_O_flash : std_logic;
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signal DAT_O_flash : unsigned(31 downto 0);
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signal CYC_I_sram : std_logic;
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signal ACK_O_sram : std_logic;
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signal SRDY_O_sram : std_logic;
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signal DAT_O_sram : unsigned(31 downto 0);
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signal CYC_I_gpio : std_logic;
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signal ACK_O_gpio : std_logic;
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signal SRDY_O_gpio : std_logic;
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signal DAT_O_gpio : unsigned(31 downto 0);
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signal CYC_I_uart : std_logic;
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signal ACK_O_uart : std_logic;
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signal SRDY_O_uart : std_logic;
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signal DAT_O_uart : unsigned(31 downto 0);
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signal flash_cs_n : std_logic;
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signal flash_oe_n : std_logic;
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signal sram_cs_n : std_logic;
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signal sram_wr_n : unsigned(3 downto 0);
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signal sram_oe_n : std_logic;
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signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
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signal sram_d : unsigned(31 downto 0);
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signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0);
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signal flash_d : unsigned(31 downto 0);
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signal gpo0 : unsigned(31 downto 0);
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signal gpo1 : unsigned(31 downto 0);
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signal gpi0 : unsigned(31 downto 0);
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signal gpi1 : unsigned(31 downto 0);
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signal int_uart_rx : std_logic;
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signal rx : std_logic;
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signal tx : std_logic;
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type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart);
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signal mem_area : mem_area_t;
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type word_array_t is array (natural range <>) of word_t;
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signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
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signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
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BEGIN
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uut: mips_top
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------------------------------------------------------------------
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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clk <= not clk;
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end process;
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------------------------------------------------------------------
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-- Memory mux
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------------------------------------------------------------------
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mem_mux:
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process(ADDR_O)
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begin
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mem_area <= mem_dead;
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if ADDR_O(31 downto 28) = X"0" then
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mem_area <= mem_flash;
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elsif ADDR_O(31 downto 28) = X"A" then
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if ADDR_O(27 downto 26) = "00" then
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if ADDR_O(18 downto 16) = "000" then
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mem_area <= mem_gpio;
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elsif ADDR_O(18 downto 16) = "001" then
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mem_area <= mem_uart;
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end if;
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elsif ADDR_O(27 downto 26) = "01" then
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mem_area <= mem_flash;
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end if;
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elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
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mem_area <= mem_rom;
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elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
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mem_area <= mem_sram;
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end if;
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end process;
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signal_mux:
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process(mem_area, CYC_O)
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begin
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CYC_I_uart <= '0';
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CYC_I_gpio <= '0';
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CYC_I_flash <= '0';
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CYC_I_rom <= '0';
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CYC_I_sram <= '0';
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case mem_area is
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when mem_gpio =>
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CYC_I_gpio <= CYC_O;
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when mem_uart =>
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CYC_I_uart <= CYC_O;
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when mem_flash =>
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CYC_I_flash <= CYC_O;
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when mem_rom =>
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CYC_I_rom <= CYC_O;
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when mem_sram =>
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CYC_I_sram <= CYC_O;
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when others => null;
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end case;
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end process;
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SRDY_I <= SRDY_O_flash or SRDY_O_sram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio;
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ACK_I <= ACK_O_flash or ACK_O_sram or ACK_O_rom or ACK_O_uart or ACK_O_gpio;
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DAT_I <= DAT_O_sram when CYC_I_sram = '1' else
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DAT_O_rom when CYC_I_rom = '1' else
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DAT_O_flash when CYC_I_flash = '1' else
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DAT_O_uart when CYC_I_uart = '1' else
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DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
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------------------------------------------------------------------
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uut: entity work.mips_top
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PORT MAP
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(
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debug => debug,
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RST_I => RST_I,
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CLK_I => CLK_I,
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RST_I => rst,
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CLK_I => clk,
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ACK_I => ACK_I,
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SRDY_I => SRDY_I,
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ADDR_O => ADDR_O,
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@@ -93,21 +207,197 @@ uut: mips_top
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MRDY_O => MRDY_O,
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INT => INT
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);
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INT(1) <= int_uart_rx;
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inst_rom : entity work.rom_wb
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_rom,
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STB_I => STB_O,
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ACK_O => ACK_O_rom,
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MRDY_I => MRDY_O,
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SRDY_O => SRDY_O_rom,
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ADDR_I => ADDR_O,
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DAT_O => DAT_O_rom
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);
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CLK_GEN: process
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inst_gpio : entity work.gpio_wb
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_gpio,
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STB_I => STB_O,
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SEL_I => SEL_O,
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WE_I => WE_O,
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ACK_O => ACK_O_gpio,
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SRDY_O => SRDY_O_gpio,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_gpio,
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sys_gpo0 => gpo0,
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sys_gpo1 => gpo1,
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sys_gpi0 => gpi0,
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sys_gpi1 => gpi1
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);
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inst_flash_port : entity work.async_port_wb
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GENERIC MAP
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(
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addr_width => FLASH_ADDR_WIDTH,
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data_width => 32,
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byte_sel_width => 1,
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async_timespec => ts_flash
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)
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PORT MAP
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||||
(
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_flash,
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STB_I => STB_O,
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WE_I => WE_O,
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||||
ACK_O => ACK_O_flash,
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||||
SRDY_O => SRDY_O_flash,
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MRDY_I => MRDY_O,
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SEL_I => SEL_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_flash,
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async_a => flash_a,
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async_d => flash_d,
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async_cs => flash_cs_n,
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async_wr => open,
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async_rd => flash_oe_n,
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async_rst => open
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||||
);
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||||
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||||
inst_sram_port : entity work.async_port_wb
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||||
GENERIC MAP
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||||
(
|
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addr_width => SRAM_ADDR_WIDTH,
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||||
data_width => 32,
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||||
byte_sel_width => 4,
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||||
async_timespec => ts_sram
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||||
)
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||||
PORT MAP
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||||
(
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||||
CLK_I => clk,
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||||
RST_I => rst,
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CYC_I => CYC_I_sram,
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STB_I => STB_O,
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WE_I => WE_O,
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ACK_O => ACK_O_sram,
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SRDY_O => SRDY_O_sram,
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MRDY_I => MRDY_O,
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SEL_I => SEL_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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||||
DAT_O => DAT_O_sram,
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||||
async_a => sram_a,
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async_d => sram_d,
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||||
async_cs => sram_cs_n,
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||||
async_wr => sram_wr_n,
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||||
async_rd => sram_oe_n,
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||||
async_rst => open
|
||||
);
|
||||
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||||
inst_uart : entity work.uart_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_uart,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_uart,
|
||||
SRDY_O => SRDY_O_uart,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => DAT_O,
|
||||
DAT_O => DAT_O_uart,
|
||||
INT_RX_O => int_uart_rx,
|
||||
INT_TX_O => open,
|
||||
ser_rx => rx,
|
||||
ser_tx => tx
|
||||
);
|
||||
|
||||
------------------------------------------------------------------
|
||||
SRAM_READ:
|
||||
process(sram_a, sram_cs_n, sram_oe_n)
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK_I <= not CLK_I;
|
||||
sram_d <= (others => 'Z');
|
||||
if sram_oe_n = '0' then
|
||||
if sram_cs_n = '0' then
|
||||
sram_d <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
SRAM_WRITE:
|
||||
process(sram_a, sram_cs_n, sram_wr_n)
|
||||
begin
|
||||
if rising_edge(sram_wr_n(0)) then
|
||||
if sram_cs_n = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
if rising_edge(sram_wr_n(1)) then
|
||||
if sram_cs_n = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
|
||||
end if;
|
||||
end if;
|
||||
if rising_edge(sram_wr_n(2)) then
|
||||
if sram_cs_n = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
|
||||
end if;
|
||||
end if;
|
||||
if rising_edge(sram_wr_n(3)) then
|
||||
if sram_cs_n = '0' then
|
||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
FLASH_READ:
|
||||
process(rst, flash_cs_n, flash_oe_n, flash_a)
|
||||
type file_t is file of integer;
|
||||
file load_flash : file_t open read_mode is "hello.flash.bin";
|
||||
variable instr : integer;
|
||||
variable index : natural;
|
||||
variable temp : signed(31 downto 0);
|
||||
begin
|
||||
if rst = '1' then
|
||||
index := 0;
|
||||
while not endfile(load_flash) loop
|
||||
read(load_flash, instr);
|
||||
temp := to_signed(instr, word_t'length);
|
||||
flash_data(index) <= unsigned(temp);
|
||||
index := index + 1;
|
||||
end loop;
|
||||
else
|
||||
flash_d <= (others => 'Z') after 10 ns;
|
||||
if flash_oe_n = '0' and flash_cs_n = '0' then
|
||||
index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
|
||||
flash_d <= flash_data(index) after 10 ns;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_I);
|
||||
RST_I <= '0';
|
||||
wait until rising_edge(clk);
|
||||
rst <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user