From 31bd88a707c80b9c74133d05f99dccf825bfe798 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 18 Jan 2009 22:15:12 +0000 Subject: [PATCH] - major changes Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@262 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/sim/tb_mips_top.fdo | 23 +- lib/CPUs/MIPS/sim/tb_mips_top.wdo | 35 ++- lib/CPUs/MIPS/src/tb_mips_top.vhd | 354 +++++++++++++++++++++++++++--- 3 files changed, 374 insertions(+), 38 deletions(-) diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.fdo b/lib/CPUs/MIPS/sim/tb_mips_top.fdo index 53c9dae..c843b12 100644 --- a/lib/CPUs/MIPS/sim/tb_mips_top.fdo +++ b/lib/CPUs/MIPS/sim/tb_mips_top.fdo @@ -15,6 +15,26 @@ vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" vcom -explicit -93 "../../../FIFO/src/fifo_sync_dist.vhd" +# UART +vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd" +vcom -explicit -93 "../../../uart/kcuart_rx.vhd" +vcom -explicit -93 "../../../uart/kcuart_tx.vhd" +vcom -explicit -93 "../../../uart/uart_rx.vhd" +vcom -explicit -93 "../../../uart/uart_tx.vhd" +vcom -explicit -93 "../../../uart/uart_wb.vhd" + +# GPIO +vcom -explicit -93 "../../../misc/gpio_wb.vhd" + +# Async port +vcom -explicit -93 "../../../misc/async_types.vhd" +vcom -explicit -93 "../../../misc/async_port_wb.vhd" +vcom -explicit -93 "../src/async_defs.vhd" + +# ROM +vcom -explicit -93 "../src/bootloader.ROM.vhd" +vcom -explicit -93 "../../../misc/rom_wb.vhd" + # MIPS vcom -explicit -93 "../src/core/mips_types.vhd" vcom -explicit -93 "../src/core/mips_instr.vhd" @@ -30,10 +50,11 @@ vcom -explicit -93 "../src/core/mips_biu.vhd" vcom -explicit -93 "../src/core/mips_bcu.vhd" vcom -explicit -93 "../src/core/mips_pipeline.vhd" vcom -explicit -93 "../src/core/mips_top.vhd" + vcom -explicit -93 "../src/tb_mips_top.vhd" vsim -t 1ps -lib work tb_mips_top do {tb_mips_top.wdo} view wave view structure view signals -run 40000ns +run 1200us diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo index 4b62a91..a47ae79 100644 --- a/lib/CPUs/MIPS/sim/tb_mips_top.wdo +++ b/lib/CPUs/MIPS/sim/tb_mips_top.wdo @@ -1,9 +1,9 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -divider {TOP interface} +add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal /tb_mips_top/debug -add wave -noupdate -format Logic /tb_mips_top/rst_i -add wave -noupdate -format Logic /tb_mips_top/clk_i +add wave -noupdate -format Logic /tb_mips_top/stb_o add wave -noupdate -format Logic /tb_mips_top/ack_i add wave -noupdate -format Logic /tb_mips_top/srdy_i add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o @@ -12,20 +12,45 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o add wave -noupdate -format Logic /tb_mips_top/we_o add wave -noupdate -format Literal /tb_mips_top/sel_o add wave -noupdate -format Logic /tb_mips_top/cyc_o -add wave -noupdate -format Logic /tb_mips_top/stb_o add wave -noupdate -format Logic /tb_mips_top/mrdy_o add wave -noupdate -format Literal /tb_mips_top/int +add wave -noupdate -divider {External components} +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1 +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Logic /tb_mips_top/rx +add wave -noupdate -format Logic /tb_mips_top/tx +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal /tb_mips_top/mem_area +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d +add wave -noupdate -format Logic /tb_mips_top/flash_cs_n +add wave -noupdate -format Logic /tb_mips_top/flash_oe_n +add wave -noupdate -format Logic /tb_mips_top/sram_cs_n +add wave -noupdate -format Literal /tb_mips_top/sram_wr_n +add wave -noupdate -format Logic /tb_mips_top/sram_oe_n add wave -noupdate -divider ALU +add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu add wave -noupdate -divider PC +add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc add wave -noupdate -divider PC +add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage +add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage +add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage +add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {21313433 ps} 0} +WaveRestoreCursors {{Cursor 1} {1199854590 ps} 0} configure wave -namecolwidth 188 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -39,4 +64,4 @@ configure wave -gridperiod 100 configure wave -griddelta 40 configure wave -timeline 1 update -WaveRestoreZoom {0 ps} {42 us} +WaveRestoreZoom {0 ps} {1260 us} diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd index 5b171a7..52a2e69 100644 --- a/lib/CPUs/MIPS/src/tb_mips_top.vhd +++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd @@ -30,37 +30,23 @@ use std.textio.all; -- Imports the standard textio package. library work; use work.mips_types.all; use work.mips_instr.all; +use work.async_types.all; +use work.async_defs.all; ENTITY tb_mips_top IS END tb_mips_top; ARCHITECTURE behavior OF tb_mips_top IS - COMPONENT mips_top - PORT - ( - debug : out unsigned(1 downto 0); - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out word_t; - DAT_I : in word_t; - DAT_O : out word_t; - WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - MRDY_O : out STD_LOGIC; - INT : in unsigned (5 downto 0) - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - + constant CLK_PERIOD : time := 10 ns; + constant SRAM_ADDR_WIDTH : integer := 16; -- words + constant FLASH_ADDR_WIDTH : integer := 16; -- words + signal debug : unsigned(1 downto 0); - signal RST_I : STD_LOGIC := '1'; - signal CLK_I : STD_LOGIC := '0'; + + -- Master + signal rst : STD_LOGIC := '1'; + signal clk : STD_LOGIC := '0'; signal ACK_I : STD_LOGIC := '0'; signal SRDY_I : STD_LOGIC := '0'; signal ADDR_O : word_t; @@ -73,14 +59,142 @@ ARCHITECTURE behavior OF tb_mips_top IS signal MRDY_O : STD_LOGIC; signal INT : unsigned (5 downto 0) := (others => '0'); + -- Slaves + signal CYC_I_rom : std_logic; + signal ACK_O_rom : std_logic; + signal SRDY_O_rom : std_logic; + signal DAT_O_rom : unsigned(31 downto 0); + + signal CYC_I_flash : std_logic; + signal ACK_O_flash : std_logic; + signal SRDY_O_flash : std_logic; + signal DAT_O_flash : unsigned(31 downto 0); + + signal CYC_I_sram : std_logic; + signal ACK_O_sram : std_logic; + signal SRDY_O_sram : std_logic; + signal DAT_O_sram : unsigned(31 downto 0); + + signal CYC_I_gpio : std_logic; + signal ACK_O_gpio : std_logic; + signal SRDY_O_gpio : std_logic; + signal DAT_O_gpio : unsigned(31 downto 0); + + signal CYC_I_uart : std_logic; + signal ACK_O_uart : std_logic; + signal SRDY_O_uart : std_logic; + signal DAT_O_uart : unsigned(31 downto 0); + + signal flash_cs_n : std_logic; + signal flash_oe_n : std_logic; + signal sram_cs_n : std_logic; + signal sram_wr_n : unsigned(3 downto 0); + signal sram_oe_n : std_logic; + signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0); + signal sram_d : unsigned(31 downto 0); + signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0); + signal flash_d : unsigned(31 downto 0); + + signal gpo0 : unsigned(31 downto 0); + signal gpo1 : unsigned(31 downto 0); + signal gpi0 : unsigned(31 downto 0); + signal gpi1 : unsigned(31 downto 0); + + signal int_uart_rx : std_logic; + signal rx : std_logic; + signal tx : std_logic; + + type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart); + signal mem_area : mem_area_t; + + type word_array_t is array (natural range <>) of word_t; + signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1); + signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1); + BEGIN -uut: mips_top +------------------------------------------------------------------ +CLK_GEN: process + begin + wait for CLK_PERIOD/2; + clk <= not clk; + end process; + +------------------------------------------------------------------ +-- Memory mux +------------------------------------------------------------------ +mem_mux: + process(ADDR_O) + begin + mem_area <= mem_dead; + if ADDR_O(31 downto 28) = X"0" then + mem_area <= mem_flash; + elsif ADDR_O(31 downto 28) = X"A" then + if ADDR_O(27 downto 26) = "00" then + if ADDR_O(18 downto 16) = "000" then + mem_area <= mem_gpio; + elsif ADDR_O(18 downto 16) = "001" then + mem_area <= mem_uart; + end if; + elsif ADDR_O(27 downto 26) = "01" then + mem_area <= mem_flash; + end if; + elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then + mem_area <= mem_rom; + elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then + mem_area <= mem_sram; + end if; + end process; + +signal_mux: + process(mem_area, CYC_O) + begin + + CYC_I_uart <= '0'; + CYC_I_gpio <= '0'; + CYC_I_flash <= '0'; + CYC_I_rom <= '0'; + CYC_I_sram <= '0'; + + case mem_area is + + when mem_gpio => + CYC_I_gpio <= CYC_O; + + when mem_uart => + CYC_I_uart <= CYC_O; + + when mem_flash => + CYC_I_flash <= CYC_O; + + when mem_rom => + CYC_I_rom <= CYC_O; + + when mem_sram => + CYC_I_sram <= CYC_O; + + when others => null; + + end case; + + end process; + + SRDY_I <= SRDY_O_flash or SRDY_O_sram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio; + ACK_I <= ACK_O_flash or ACK_O_sram or ACK_O_rom or ACK_O_uart or ACK_O_gpio; + DAT_I <= DAT_O_sram when CYC_I_sram = '1' else + DAT_O_rom when CYC_I_rom = '1' else + DAT_O_flash when CYC_I_flash = '1' else + DAT_O_uart when CYC_I_uart = '1' else + DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF"; + + +------------------------------------------------------------------ +uut: entity work.mips_top PORT MAP ( debug => debug, - RST_I => RST_I, - CLK_I => CLK_I, + RST_I => rst, + CLK_I => clk, ACK_I => ACK_I, SRDY_I => SRDY_I, ADDR_O => ADDR_O, @@ -93,21 +207,197 @@ uut: mips_top MRDY_O => MRDY_O, INT => INT ); + INT(1) <= int_uart_rx; + +inst_rom : entity work.rom_wb + PORT MAP + ( + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_I_rom, + STB_I => STB_O, + ACK_O => ACK_O_rom, + MRDY_I => MRDY_O, + SRDY_O => SRDY_O_rom, + ADDR_I => ADDR_O, + DAT_O => DAT_O_rom + ); -CLK_GEN: process +inst_gpio : entity work.gpio_wb + PORT MAP + ( + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_I_gpio, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_O_gpio, + SRDY_O => SRDY_O_gpio, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_O_gpio, + + sys_gpo0 => gpo0, + sys_gpo1 => gpo1, + sys_gpi0 => gpi0, + sys_gpi1 => gpi1 + ); + +inst_flash_port : entity work.async_port_wb + GENERIC MAP + ( + addr_width => FLASH_ADDR_WIDTH, + data_width => 32, + byte_sel_width => 1, + async_timespec => ts_flash + ) + PORT MAP + ( + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_I_flash, + STB_I => STB_O, + WE_I => WE_O, + ACK_O => ACK_O_flash, + SRDY_O => SRDY_O_flash, + MRDY_I => MRDY_O, + SEL_I => SEL_O, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_O_flash, + async_a => flash_a, + async_d => flash_d, + async_cs => flash_cs_n, + async_wr => open, + async_rd => flash_oe_n, + async_rst => open + ); + +inst_sram_port : entity work.async_port_wb + GENERIC MAP + ( + addr_width => SRAM_ADDR_WIDTH, + data_width => 32, + byte_sel_width => 4, + async_timespec => ts_sram + ) + PORT MAP + ( + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_I_sram, + STB_I => STB_O, + WE_I => WE_O, + ACK_O => ACK_O_sram, + SRDY_O => SRDY_O_sram, + MRDY_I => MRDY_O, + SEL_I => SEL_O, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_O_sram, + async_a => sram_a, + async_d => sram_d, + async_cs => sram_cs_n, + async_wr => sram_wr_n, + async_rd => sram_oe_n, + async_rst => open + ); + +inst_uart : entity work.uart_wb + PORT MAP + ( + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_I_uart, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_O_uart, + SRDY_O => SRDY_O_uart, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_O_uart, + INT_RX_O => int_uart_rx, + INT_TX_O => open, + ser_rx => rx, + ser_tx => tx + ); + +------------------------------------------------------------------ +SRAM_READ: + process(sram_a, sram_cs_n, sram_oe_n) begin - wait for CLK_PERIOD/2; - CLK_I <= not CLK_I; + sram_d <= (others => 'Z'); + if sram_oe_n = '0' then + if sram_cs_n = '0' then + sram_d <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2))); + end if; + end if; end process; +SRAM_WRITE: + process(sram_a, sram_cs_n, sram_wr_n) + begin + if rising_edge(sram_wr_n(0)) then + if sram_cs_n = '0' then + sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0); + end if; + end if; + if rising_edge(sram_wr_n(1)) then + if sram_cs_n = '0' then + sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8); + end if; + end if; + if rising_edge(sram_wr_n(2)) then + if sram_cs_n = '0' then + sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16); + end if; + end if; + if rising_edge(sram_wr_n(3)) then + if sram_cs_n = '0' then + sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24); + end if; + end if; + end process; + +------------------------------------------------------------------ +FLASH_READ: + process(rst, flash_cs_n, flash_oe_n, flash_a) + type file_t is file of integer; + file load_flash : file_t open read_mode is "hello.flash.bin"; + variable instr : integer; + variable index : natural; + variable temp : signed(31 downto 0); + begin + if rst = '1' then + index := 0; + while not endfile(load_flash) loop + read(load_flash, instr); + temp := to_signed(instr, word_t'length); + flash_data(index) <= unsigned(temp); + index := index + 1; + end loop; + else + flash_d <= (others => 'Z') after 10 ns; + if flash_oe_n = '0' and flash_cs_n = '0' then + index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2)); + flash_d <= flash_data(index) after 10 ns; + end if; + end if; + end process; + +------------------------------------------------------------------ STIMULUS: process begin wait for 3*CLK_PERIOD; - wait until rising_edge(CLK_I); - RST_I <= '0'; + wait until rising_edge(clk); + rst <= '0'; wait;