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- added BLITTER tests

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git-svn-id: http://moon:8086/svn/vhdl/trunk@670 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-22 13:50:34 +00:00
parent 935645a97e
commit 3157b3297b
1 changed files with 104 additions and 8 deletions
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lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+101 -5
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@@ -65,6 +65,8 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
signal SDAT_O : unsigned(31 downto 0) := (others => '-'); signal SDAT_O : unsigned(31 downto 0) := (others => '-');
signal rdy : std_logic := '0'; signal rdy : std_logic := '0';
signal read_reg : unsigned(31 downto 0) := (others => '-');
-- VGA signals -- VGA signals
signal vga_clk : std_logic := '1'; signal vga_clk : std_logic := '1';
signal vga_red : unsigned(7 downto 0); signal vga_red : unsigned(7 downto 0);
@@ -158,21 +160,28 @@ VGA_CLK_GEN: process
type arr64_t is array (11 downto 0) of unsigned(63 downto 0); type arr64_t is array (11 downto 0) of unsigned(63 downto 0);
variable dat_v : arr64_t; variable dat_v : arr64_t;
variable res: unsigned(63 downto 0); variable res: unsigned(63 downto 0);
variable count: unsigned(31 downto 0); variable scan_count: unsigned(31 downto 0);
variable blit_count: unsigned(31 downto 0);
begin begin
if rising_edge(CLK_O) then if rising_edge(CLK_O) then
if RST_O = '1' then if RST_O = '1' then
count := X"00000000"; scan_count := X"00000000";
blit_count := X"00000000";
for i in 0 to 11 loop for i in 0 to 11 loop
dat_v(i) := X"FFFFFFFF_FFFFFFFF"; dat_v(i) := X"FFFFFFFF_FFFFFFFF";
ack_v(i) := '0'; ack_v(i) := '0';
end loop; end loop;
else else
if (CYC_I and STB_I) = '1' and rdy = '1' then if (CYC_I and STB_I) = '1' and rdy = '1' and WE_I = '0' then
res := ADDR_I & count; if ADDR_I(24) = '0' then
res := ADDR_I & scan_count;
scan_count := scan_count + 8;
else
res := ADDR_I & blit_count;
blit_count := blit_count + 8;
end if;
dat_v := dat_v(10 downto 0) & res; dat_v := dat_v(10 downto 0) & res;
ack_v := ack_v(10 downto 0) & '1'; ack_v := ack_v(10 downto 0) & '1';
count := count + 8;
else else
dat_v := dat_v(10 downto 0) & X"FFFFFFFF_FFFFFFFF"; dat_v := dat_v(10 downto 0) & X"FFFFFFFF_FFFFFFFF";
ack_v := ack_v(10 downto 0) & '0'; ack_v := ack_v(10 downto 0) & '0';
@@ -183,6 +192,17 @@ VGA_CLK_GEN: process
end if; end if;
end process; end process;
process(CLK_O)
begin
if rising_edge(CLK_O) then
if RST_O = '1' then
read_reg <= X"00000000";
elsif ACK_I = '1' then
read_reg <= SDAT_I;
end if;
end if;
end process;
-- Master -- Master
STIMULUS: process STIMULUS: process
@@ -329,7 +349,83 @@ STIMULUS: process
wait until rising_edge(CLK_O); wait until rising_edge(CLK_O);
CYC_O <= '0'; CYC_O <= '0';
wait for 60000*CLK_PERIOD;
-- BLIT test
-- Read status
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
-- set src addr
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0000";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0140";
ADDR_O <= X"0000_002C";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst addr
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0000";
ADDR_O <= X"0000_0028";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0140";
ADDR_O <= X"0000_0034";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set nx
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_007F";
ADDR_O <= X"0000_0038";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set ny
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_00FF";
ADDR_O <= X"0000_003C";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= read_reg or X"0000_0100";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait; wait;