diff --git a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
index a14c2e0..9ec5f25 100644
--- a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+++ b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
@@ -65,6 +65,8 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
 	signal SDAT_O			: unsigned(31 downto 0) := (others => '-');
 	signal rdy				: std_logic := '0';
 
+	signal read_reg			: unsigned(31 downto 0) := (others => '-');
+
 	-- VGA signals
 	signal vga_clk			: std_logic := '1';
 	signal vga_red			: unsigned(7 downto 0);
@@ -158,21 +160,28 @@ VGA_CLK_GEN: process
 	type arr64_t is array (11 downto 0) of unsigned(63 downto 0);
 	variable dat_v : arr64_t;
 	variable res: unsigned(63 downto 0);
-	variable count: unsigned(31 downto 0);
+	variable scan_count: unsigned(31 downto 0);
+	variable blit_count: unsigned(31 downto 0);
 	begin
 		if rising_edge(CLK_O) then
 			if RST_O = '1' then
-				count	:= X"00000000";
+				scan_count	:= X"00000000";
+				blit_count	:= X"00000000";
 				for i in 0 to 11 loop
 					dat_v(i)	:= X"FFFFFFFF_FFFFFFFF";
 					ack_v(i)	:= '0';
 				end loop;
 			else
-				if (CYC_I and STB_I) = '1' and rdy = '1' then
-					res		:= ADDR_I & count;
-					dat_v	:= dat_v(10 downto 0) & res;
-					ack_v	:= ack_v(10 downto 0) & '1';
-					count 	:= count + 8;
+				if (CYC_I and STB_I) = '1' and rdy = '1' and WE_I = '0' then
+					if ADDR_I(24) = '0' then
+						res			:= ADDR_I & scan_count;
+						scan_count 	:= scan_count + 8;
+					else
+						res			:= ADDR_I & blit_count;
+						blit_count 	:= blit_count + 8;
+					end if;
+					dat_v		:= dat_v(10 downto 0) & res;
+					ack_v		:= ack_v(10 downto 0) & '1';
 				else
 					dat_v	:= dat_v(10 downto 0) & X"FFFFFFFF_FFFFFFFF";
 					ack_v	:= ack_v(10 downto 0) & '0';
@@ -183,6 +192,17 @@ VGA_CLK_GEN: process
 		end if;
 	end process;
 
+	process(CLK_O)
+	begin
+		if rising_edge(CLK_O) then
+			if RST_O = '1' then
+				read_reg	<= X"00000000";
+			elsif ACK_I = '1' then
+				read_reg	<= SDAT_I;
+			end if;
+		end if;
+	end process;
+
 -- Master
 STIMULUS: process
 
@@ -329,8 +349,84 @@ STIMULUS: process
 		wait until rising_edge(CLK_O);
 		CYC_O	<= '0';
 
-		
+		wait for 60000*CLK_PERIOD;
 
+		-- BLIT test
+		-- Read status
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		-- set src addr
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_O	<= X"4100_0000";
+		ADDR_O	<= X"0000_0020";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		-- set src dim-x
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_O	<= X"0000_0140";
+		ADDR_O	<= X"0000_002C";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		-- set dst addr
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_O	<= X"4200_0000";
+		ADDR_O	<= X"0000_0028";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		-- set dst dim-x
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_O	<= X"0000_0140";
+		ADDR_O	<= X"0000_0034";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		-- set nx
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_O	<= X"0000_007F";
+		ADDR_O	<= X"0000_0038";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		-- set ny
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_O	<= X"0000_00FF";
+		ADDR_O	<= X"0000_003C";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		-- set blit request
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_O	<= read_reg or X"0000_0100";
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		CYC_O	<= '0';
+		WE_O	<= '0';
+		
 		wait; 
 	
 	end process;