CRLF

git-svn-id: http://moon:8086/svn/vhdl/trunk@1050 cc03376c-175c-47c8-b038-4cd826a8556b

lib/radio/decimator/CIC/src/cic_i_pipe.vhd

@@ -1,81 +1,81 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage_pre - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cic_i_pipe is
-Generic
-(
-	max_width		: integer := 32;
-	max_width_frac	: integer := 20
-);
-Port
-(
-	clk			: in std_logic;
-	rst			: in std_logic;
-	vld_in		: in std_logic;
-	din			: in sfixed;
-	dout		: out sfixed;
-	vld_out 	: out std_logic
-);
-end cic_i_pipe;
-
-architecture Behavioral of cic_i_pipe is
-
-signal accu			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-
-------------------------------------------------------------
-begin
-
-	dout	<= resize(accu, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
-	
-------------------------------------------------------------
-integ_proc: 
-	process(clk)
-	variable x : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-	begin
-		if rising_edge(clk) then
-			vld_out <= '0';
-			if rst = '1' then
-				accu <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
-			elsif vld_in = '1' then
-				vld_out <= '1';
-				x		:= resize(din, x);
-				accu	<= resize(x + accu, accu);
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------
-end Behavioral;
-
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    12:16:14 10/02/05
+-- Design Name:    
+-- Module Name:    cordic_stage_pre - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+library ieee_proposed;
+use ieee_proposed.math_utility_pkg.all;
+use ieee_proposed.fixed_pkg.all;
+
+library work;
+use work.fixed_util_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity cic_i_pipe is
+Generic
+(
+	max_width		: integer := 32;
+	max_width_frac	: integer := 20
+);
+Port
+(
+	clk			: in std_logic;
+	rst			: in std_logic;
+	vld_in		: in std_logic;
+	din			: in sfixed;
+	dout		: out sfixed;
+	vld_out 	: out std_logic
+);
+end cic_i_pipe;
+
+architecture Behavioral of cic_i_pipe is
+
+signal accu			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
+
+------------------------------------------------------------
+begin
+
+	dout	<= resize(accu, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
+	
+------------------------------------------------------------
+integ_proc: 
+	process(clk)
+	variable x : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
+	begin
+		if rising_edge(clk) then
+			vld_out <= '0';
+			if rst = '1' then
+				accu <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
+			elsif vld_in = '1' then
+				vld_out <= '1';
+				x		:= resize(din, x);
+				accu	<= resize(x + accu, accu);
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------
+end Behavioral;
+