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git-svn-id: http://moon:8086/svn/vhdl/trunk@1050 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2014-07-23 20:11:52 +00:00
parent 52acc7bd34
commit 30184e5502
8 changed files with 993 additions and 993 deletions
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lib/radio/decimator/CIC/src/cic_c_pipe.vhd
+104 -104
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@@ -1,104 +1,104 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:16:14 10/02/05
-- Design Name:
-- Module Name: cordic_stage_pre - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cic_c_pipe is
Generic
(
max_diff_delay : integer := 1;
max_width : integer := 32;
max_width_frac : integer := 20
);
Port
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
diff_delay : in natural range 1 to max_diff_delay;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
end cic_c_pipe;
architecture Behavioral of cic_c_pipe is
subtype word_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
type word_pipe_t is array (1 to max_diff_delay) of word_t;
signal word_pipe : word_pipe_t;
------------------------------------------------------------
begin
------------------------------------------------------------
delay_pipe_proc:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
-- for i in 1 to max_diff_delay loop
-- word_pipe(i) <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
-- end loop;
elsif vld_in = '1' then
word_pipe(1) <= resize(din, word_pipe(1));
for i in 2 to max_diff_delay loop
word_pipe(i) <= word_pipe(i-1);
end loop;
end if;
end if;
end process;
------------------------------------------------------------
comb_proc:
process(clk)
variable x0, x1 : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
begin
if rising_edge(clk) then
vld_out <= '0';
x0 := resize(din, x0);
x1 := word_pipe(diff_delay);
if rst = '1' then
dout <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
elsif vld_in = '1' then
vld_out <= '1';
dout <= resize(x0 - x1, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
end if;
end if;
end process;
------------------------------------------------------------
end Behavioral;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:16:14 10/02/05
-- Design Name:
-- Module Name: cordic_stage_pre - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cic_c_pipe is
Generic
(
max_diff_delay : integer := 1;
max_width : integer := 32;
max_width_frac : integer := 20
);
Port
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
diff_delay : in natural range 1 to max_diff_delay;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
end cic_c_pipe;
architecture Behavioral of cic_c_pipe is
subtype word_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
type word_pipe_t is array (1 to max_diff_delay) of word_t;
signal word_pipe : word_pipe_t;
------------------------------------------------------------
begin
------------------------------------------------------------
delay_pipe_proc:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
-- for i in 1 to max_diff_delay loop
-- word_pipe(i) <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
-- end loop;
elsif vld_in = '1' then
word_pipe(1) <= resize(din, word_pipe(1));
for i in 2 to max_diff_delay loop
word_pipe(i) <= word_pipe(i-1);
end loop;
end if;
end if;
end process;
------------------------------------------------------------
comb_proc:
process(clk)
variable x0, x1 : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
begin
if rising_edge(clk) then
vld_out <= '0';
x0 := resize(din, x0);
x1 := word_pipe(diff_delay);
if rst = '1' then
dout <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
elsif vld_in = '1' then
vld_out <= '1';
dout <= resize(x0 - x1, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
end if;
end if;
end process;
------------------------------------------------------------
end Behavioral;
lib/radio/decimator/CIC/src/cic_decim_pipe.vhd
+203 -203
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@@ -1,203 +1,203 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_mix_cpx
-- Module Name: tb_mix_cpx.vhd
-- Project Name: mix_cpx
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
use work.utils_pkg.all;
ENTITY cic_decim_pipe IS
Generic
(
nstages : integer := 3;
diff_delay : integer := 1;
ratio : integer := 64;
scale_nbits : integer := 9;
in_width : integer := 32;
in_width_frac : integer := 20;
out_width : integer := 32;
out_width_frac : integer := 20
);
Port
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END cic_decim_pipe;
ARCHITECTURE behavior OF cic_decim_pipe IS
COMPONENT cic_i_pipe
GENERIC
(
max_width : integer;
max_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
COMPONENT cic_c_pipe
GENERIC
(
max_diff_delay : integer;
max_width : integer;
max_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
diff_delay : in natural range 1 to max_diff_delay;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
constant max_gain_bits : natural := natural(NextExpBaseTwo(real(ratio)**real(nstages)));
constant integ_nbits : natural := in_width + max_gain_bits;
constant integ_nbits_frac : natural := integ_nbits - (in_width - in_width_frac);
constant comb_nbits : natural := out_width+1;
constant comb_nbits_frac : natural := out_width_frac+1;
subtype word_i_t is sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
type word_i_pipe_t is array (0 to nstages) of word_i_t;
signal word_i_pipe : word_i_pipe_t;
signal vld_i_pipe : unsigned (0 to nstages);
signal vld_i : std_logic;
subtype word_c_t is sfixed(shi(comb_nbits, comb_nbits_frac) downto slo(comb_nbits, comb_nbits_frac));
type word_c_pipe_t is array (0 to nstages) of word_c_t;
signal word_c_pipe : word_c_pipe_t;
signal vld_c_pipe : unsigned (0 to nstages);
signal vld_c : std_logic;
signal resample_cnt : natural range 1 to ratio;
signal resample_vld : std_logic;
BEGIN
assert false report "max_gain_bits = " & natural'image(max_gain_bits) & "." severity note;
assert false report "integ. prec. = " & natural'image(integ_nbits) & ":" & natural'image(integ_nbits_frac) & "." severity note;
assert false report "comb prec. = " & natural'image(comb_nbits) & ":" & natural'image(comb_nbits_frac) & "." severity note;
vld_i <= vld_i_pipe(nstages);
input_scale:
process(clk)
variable x : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
variable xs : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
variable xsi : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
begin
if rising_edge(clk) then
x := resize(din, x);
xs := x sra scale_nbits;
word_i_pipe(0) <= xs;
vld_i_pipe(0) <= vld_in;
end if;
end process;
gen_i_stages:
for i in 1 to nstages generate
begin
inst_cic_i_pipe: cic_i_pipe
GENERIC MAP
(
max_width => integ_nbits,
max_width_frac => integ_nbits_frac
)
PORT MAP
(
clk => clk,
rst => rst,
vld_in => vld_i_pipe(i-1),
din => word_i_pipe(i-1),
dout => word_i_pipe(i),
vld_out => vld_i_pipe(i)
);
end generate;
word_c_pipe(0) <= resize(word_i_pipe(nstages), word_c_pipe(0), fixed_wrap, fixed_truncate);
vld_c_pipe(0) <= resample_vld;
vld_c <= vld_c_pipe(nstages);
vld_out <= vld_c;
gen_c_stages:
for i in 1 to nstages generate
begin
inst_cic_c_pipe: cic_c_pipe
GENERIC MAP
(
max_diff_delay => diff_delay,
max_width => comb_nbits,
max_width_frac => comb_nbits_frac
)
PORT MAP
(
clk => clk,
rst => rst,
vld_in => vld_c_pipe(i-1),
diff_delay => diff_delay,
din => word_c_pipe(i-1),
dout => word_c_pipe(i),
vld_out => vld_c_pipe(i)
);
end generate;
resampler_proc:
process(clk)
begin
if rising_edge(clk) then
resample_vld <= '0';
if rst = '1' then
resample_cnt <= 1;
elsif vld_i = '1' then
if resample_cnt = ratio then
resample_vld <= '1';
resample_cnt <= 1;
else
resample_cnt <= resample_cnt + 1;
end if ;
end if;
end if;
end process;
dout <= resize(word_c_pipe(nstages), shi(out_width, out_width_frac), slo(out_width, out_width_frac));
END;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_mix_cpx
-- Module Name: tb_mix_cpx.vhd
-- Project Name: mix_cpx
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
use work.utils_pkg.all;
ENTITY cic_decim_pipe IS
Generic
(
nstages : integer := 3;
diff_delay : integer := 1;
ratio : integer := 64;
scale_nbits : integer := 9;
in_width : integer := 32;
in_width_frac : integer := 20;
out_width : integer := 32;
out_width_frac : integer := 20
);
Port
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END cic_decim_pipe;
ARCHITECTURE behavior OF cic_decim_pipe IS
COMPONENT cic_i_pipe
GENERIC
(
max_width : integer;
max_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
COMPONENT cic_c_pipe
GENERIC
(
max_diff_delay : integer;
max_width : integer;
max_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
diff_delay : in natural range 1 to max_diff_delay;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
constant max_gain_bits : natural := natural(NextExpBaseTwo(real(ratio)**real(nstages)));
constant integ_nbits : natural := in_width + max_gain_bits;
constant integ_nbits_frac : natural := integ_nbits - (in_width - in_width_frac);
constant comb_nbits : natural := out_width+1;
constant comb_nbits_frac : natural := out_width_frac+1;
subtype word_i_t is sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
type word_i_pipe_t is array (0 to nstages) of word_i_t;
signal word_i_pipe : word_i_pipe_t;
signal vld_i_pipe : unsigned (0 to nstages);
signal vld_i : std_logic;
subtype word_c_t is sfixed(shi(comb_nbits, comb_nbits_frac) downto slo(comb_nbits, comb_nbits_frac));
type word_c_pipe_t is array (0 to nstages) of word_c_t;
signal word_c_pipe : word_c_pipe_t;
signal vld_c_pipe : unsigned (0 to nstages);
signal vld_c : std_logic;
signal resample_cnt : natural range 1 to ratio;
signal resample_vld : std_logic;
BEGIN
assert false report "max_gain_bits = " & natural'image(max_gain_bits) & "." severity note;
assert false report "integ. prec. = " & natural'image(integ_nbits) & ":" & natural'image(integ_nbits_frac) & "." severity note;
assert false report "comb prec. = " & natural'image(comb_nbits) & ":" & natural'image(comb_nbits_frac) & "." severity note;
vld_i <= vld_i_pipe(nstages);
input_scale:
process(clk)
variable x : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
variable xs : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
variable xsi : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
begin
if rising_edge(clk) then
x := resize(din, x);
xs := x sra scale_nbits;
word_i_pipe(0) <= xs;
vld_i_pipe(0) <= vld_in;
end if;
end process;
gen_i_stages:
for i in 1 to nstages generate
begin
inst_cic_i_pipe: cic_i_pipe
GENERIC MAP
(
max_width => integ_nbits,
max_width_frac => integ_nbits_frac
)
PORT MAP
(
clk => clk,
rst => rst,
vld_in => vld_i_pipe(i-1),
din => word_i_pipe(i-1),
dout => word_i_pipe(i),
vld_out => vld_i_pipe(i)
);
end generate;
word_c_pipe(0) <= resize(word_i_pipe(nstages), word_c_pipe(0), fixed_wrap, fixed_truncate);
vld_c_pipe(0) <= resample_vld;
vld_c <= vld_c_pipe(nstages);
vld_out <= vld_c;
gen_c_stages:
for i in 1 to nstages generate
begin
inst_cic_c_pipe: cic_c_pipe
GENERIC MAP
(
max_diff_delay => diff_delay,
max_width => comb_nbits,
max_width_frac => comb_nbits_frac
)
PORT MAP
(
clk => clk,
rst => rst,
vld_in => vld_c_pipe(i-1),
diff_delay => diff_delay,
din => word_c_pipe(i-1),
dout => word_c_pipe(i),
vld_out => vld_c_pipe(i)
);
end generate;
resampler_proc:
process(clk)
begin
if rising_edge(clk) then
resample_vld <= '0';
if rst = '1' then
resample_cnt <= 1;
elsif vld_i = '1' then
if resample_cnt = ratio then
resample_vld <= '1';
resample_cnt <= 1;
else
resample_cnt <= resample_cnt + 1;
end if ;
end if;
end if;
end process;
dout <= resize(word_c_pipe(nstages), shi(out_width, out_width_frac), slo(out_width, out_width_frac));
END;
lib/radio/decimator/CIC/src/cic_i_pipe.vhd
+81 -81
View File
@@ -1,81 +1,81 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:16:14 10/02/05
-- Design Name:
-- Module Name: cordic_stage_pre - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cic_i_pipe is
Generic
(
max_width : integer := 32;
max_width_frac : integer := 20
);
Port
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
end cic_i_pipe;
architecture Behavioral of cic_i_pipe is
signal accu : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
------------------------------------------------------------
begin
dout <= resize(accu, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
------------------------------------------------------------
integ_proc:
process(clk)
variable x : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
begin
if rising_edge(clk) then
vld_out <= '0';
if rst = '1' then
accu <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
elsif vld_in = '1' then
vld_out <= '1';
x := resize(din, x);
accu <= resize(x + accu, accu);
end if;
end if;
end process;
------------------------------------------------------------
end Behavioral;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:16:14 10/02/05
-- Design Name:
-- Module Name: cordic_stage_pre - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cic_i_pipe is
Generic
(
max_width : integer := 32;
max_width_frac : integer := 20
);
Port
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
end cic_i_pipe;
architecture Behavioral of cic_i_pipe is
signal accu : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
------------------------------------------------------------
begin
dout <= resize(accu, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
------------------------------------------------------------
integ_proc:
process(clk)
variable x : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
begin
if rising_edge(clk) then
vld_out <= '0';
if rst = '1' then
accu <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
elsif vld_in = '1' then
vld_out <= '1';
x := resize(din, x);
accu <= resize(x + accu, accu);
end if;
end if;
end process;
------------------------------------------------------------
end Behavioral;
lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd
+98 -98
View File
@@ -1,98 +1,98 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_mix_cpx
-- Module Name: tb_mix_cpx.vhd
-- Project Name: mix_cpx
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
entity syn_cic_c_pipe is
Generic
(
max_diff_delay : integer := 2;
max_width : integer := 32;
max_width_frac : integer := 20
);
Port
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
diff_delay : in natural range 1 to max_diff_delay;
din : in signed(max_width-1 downto 0);
dout : out signed(max_width-1 downto 0);
vld_out : out std_logic
);
end syn_cic_c_pipe;
ARCHITECTURE behavior OF syn_cic_c_pipe IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cic_c_pipe
GENERIC
(
max_diff_delay : integer;
max_width : integer;
max_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
diff_delay : in natural range 1 to max_diff_delay;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
--Inputs
SIGNAL sdin : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
--Outputs
SIGNAL sdout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cic_c_pipe
GENERIC MAP
(
max_diff_delay => max_diff_delay,
max_width => max_width,
max_width_frac => max_width_frac
)
PORT MAP
(
clk => clk,
rst => rst,
vld_in => vld_in,
diff_delay => diff_delay,
din => sdin,
dout => sdout,
vld_out => vld_out
);
sdin <= to_sfixed(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
dout <= signed(sdout);
END;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_mix_cpx
-- Module Name: tb_mix_cpx.vhd
-- Project Name: mix_cpx
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
entity syn_cic_c_pipe is
Generic
(
max_diff_delay : integer := 2;
max_width : integer := 32;
max_width_frac : integer := 20
);
Port
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
diff_delay : in natural range 1 to max_diff_delay;
din : in signed(max_width-1 downto 0);
dout : out signed(max_width-1 downto 0);
vld_out : out std_logic
);
end syn_cic_c_pipe;
ARCHITECTURE behavior OF syn_cic_c_pipe IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cic_c_pipe
GENERIC
(
max_diff_delay : integer;
max_width : integer;
max_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
diff_delay : in natural range 1 to max_diff_delay;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
--Inputs
SIGNAL sdin : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
--Outputs
SIGNAL sdout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cic_c_pipe
GENERIC MAP
(
max_diff_delay => max_diff_delay,
max_width => max_width,
max_width_frac => max_width_frac
)
PORT MAP
(
clk => clk,
rst => rst,
vld_in => vld_in,
diff_delay => diff_delay,
din => sdin,
dout => sdout,
vld_out => vld_out
);
sdin <= to_sfixed(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
dout <= signed(sdout);
END;
lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd
+92 -92
View File
@@ -1,92 +1,92 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_mix_cpx
-- Module Name: tb_mix_cpx.vhd
-- Project Name: mix_cpx
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
entity syn_cic_i_pipe is
Generic
(
max_width : integer := 32;
max_width_frac : integer := 20
);
Port
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in signed(max_width-1 downto 0);
dout : out signed(max_width-1 downto 0);
vld_out : out std_logic
);
end syn_cic_i_pipe;
ARCHITECTURE behavior OF syn_cic_i_pipe IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cic_i_pipe
GENERIC
(
max_width : integer;
max_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
--Inputs
SIGNAL sdin : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
--Outputs
SIGNAL sdout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cic_i_pipe
GENERIC MAP
(
max_width => max_width,
max_width_frac => max_width_frac
)
PORT MAP
(
clk => clk,
rst => rst,
vld_in => vld_in,
din => sdin,
dout => sdout,
vld_out => vld_out
);
sdin <= to_sfixed(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
dout <= signed(sdout);
END;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_mix_cpx
-- Module Name: tb_mix_cpx.vhd
-- Project Name: mix_cpx
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
entity syn_cic_i_pipe is
Generic
(
max_width : integer := 32;
max_width_frac : integer := 20
);
Port
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in signed(max_width-1 downto 0);
dout : out signed(max_width-1 downto 0);
vld_out : out std_logic
);
end syn_cic_i_pipe;
ARCHITECTURE behavior OF syn_cic_i_pipe IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cic_i_pipe
GENERIC
(
max_width : integer;
max_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
--Inputs
SIGNAL sdin : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
--Outputs
SIGNAL sdout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cic_i_pipe
GENERIC MAP
(
max_width => max_width,
max_width_frac => max_width_frac
)
PORT MAP
(
clk => clk,
rst => rst,
vld_in => vld_in,
din => sdin,
dout => sdout,
vld_out => vld_out
);
sdin <= to_sfixed(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
dout <= signed(sdout);
END;
lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd
+136 -136
View File
@@ -1,136 +1,136 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_mix_cpx
-- Module Name: tb_mix_cpx.vhd
-- Project Name: mix_cpx
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.PCK_FIO.all;
use work.fixed_util_pkg.all;
ENTITY tb_cic_c_pipe IS
Generic
(
max_width : integer := 32;
max_width_frac : integer := 20
);
END tb_cic_c_pipe;
ARCHITECTURE behavior OF tb_cic_c_pipe IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cic_c_pipe
GENERIC
(
max_diff_delay : integer;
max_width : integer;
max_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
diff_delay : in natural range 1 to max_diff_delay;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
--Constants
constant PERIOD : time := 10 ns;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL srst : std_logic := '1';
SIGNAL vld_in : std_logic := '0';
SIGNAL din : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
SIGNAL diff_delay : natural := 1;
--Outputs
SIGNAL dout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
SIGNAL vld_out : std_logic;
SIGNAL fileout_enable : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cic_c_pipe
GENERIC MAP
(
max_diff_delay => 2,
max_width => max_width,
max_width_frac => max_width_frac
)
PORT MAP
(
clk => clk,
rst => srst,
vld_in => vld_in,
diff_delay => diff_delay,
din => din,
dout => dout,
vld_out => vld_out
);
tb_clk : PROCESS
BEGIN
clk <= not clk;
wait for PERIOD/2;
END PROCESS;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 4*PERIOD;
srst <= '0';
------------------------------------------
wait for 2*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.0, din);
vld_in <= '1';
wait for 9*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.5, din);
wait for 9*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.0, din);
wait for 9*PERIOD;
wait until rising_edge(clk);
vld_in <= '0';
wait for 20*PERIOD;
assert false report "Test finished" severity error;
wait;
END PROCESS;
END;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_mix_cpx
-- Module Name: tb_mix_cpx.vhd
-- Project Name: mix_cpx
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.PCK_FIO.all;
use work.fixed_util_pkg.all;
ENTITY tb_cic_c_pipe IS
Generic
(
max_width : integer := 32;
max_width_frac : integer := 20
);
END tb_cic_c_pipe;
ARCHITECTURE behavior OF tb_cic_c_pipe IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cic_c_pipe
GENERIC
(
max_diff_delay : integer;
max_width : integer;
max_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
diff_delay : in natural range 1 to max_diff_delay;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
--Constants
constant PERIOD : time := 10 ns;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL srst : std_logic := '1';
SIGNAL vld_in : std_logic := '0';
SIGNAL din : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
SIGNAL diff_delay : natural := 1;
--Outputs
SIGNAL dout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
SIGNAL vld_out : std_logic;
SIGNAL fileout_enable : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cic_c_pipe
GENERIC MAP
(
max_diff_delay => 2,
max_width => max_width,
max_width_frac => max_width_frac
)
PORT MAP
(
clk => clk,
rst => srst,
vld_in => vld_in,
diff_delay => diff_delay,
din => din,
dout => dout,
vld_out => vld_out
);
tb_clk : PROCESS
BEGIN
clk <= not clk;
wait for PERIOD/2;
END PROCESS;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 4*PERIOD;
srst <= '0';
------------------------------------------
wait for 2*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.0, din);
vld_in <= '1';
wait for 9*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.5, din);
wait for 9*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.0, din);
wait for 9*PERIOD;
wait until rising_edge(clk);
vld_in <= '0';
wait for 20*PERIOD;
assert false report "Test finished" severity error;
wait;
END PROCESS;
END;
lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd
+153 -153
View File
@@ -1,153 +1,153 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_mix_cpx
-- Module Name: tb_mix_cpx.vhd
-- Project Name: mix_cpx
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.PCK_FIO.all;
use work.fixed_util_pkg.all;
ENTITY tb_cic_decim_pipe IS
Generic
(
nstages : integer := 3;
ratio : integer := 64;
scale_nbits : integer := 18;
in_width : integer := 18;
in_width_frac : integer := 16;
out_width : integer := 18;
out_width_frac : integer := 16
);
END tb_cic_decim_pipe;
ARCHITECTURE behavior OF tb_cic_decim_pipe IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cic_decim_pipe
GENERIC
(
nstages : integer;
ratio : integer;
scale_nbits : integer;
in_width : integer;
in_width_frac : integer;
out_width : integer;
out_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
--Constants
constant PERIOD : time := 10 ns;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL srst : std_logic := '1';
SIGNAL vld_in : std_logic := '0';
SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
--Outputs
SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
SIGNAL vld_out : std_logic;
SIGNAL fileout_enable : std_logic := '0';
signal XR, YR : real;
BEGIN
XR <= to_real(din);
YR <= to_real(dout);
-- Instantiate the Unit Under Test (UUT)
uut : cic_decim_pipe
GENERIC MAP
(
nstages => nstages,
ratio => ratio,
scale_nbits => scale_nbits,
in_width => in_width,
in_width_frac => in_width_frac,
out_width => out_width,
out_width_frac => out_width_frac
)
PORT MAP
(
clk => clk,
rst => srst,
vld_in => vld_in,
din => din,
dout => dout,
vld_out => vld_out
);
tb_clk : PROCESS
BEGIN
clk <= not clk;
wait for PERIOD/2;
END PROCESS;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 4*PERIOD;
srst <= '0';
------------------------------------------
wait for 2*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.0, din);
vld_in <= '1';
wait for 49*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.5, din);
wait for 4999*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(-0.5, din);
wait for 99*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.0, din);
wait for 499*PERIOD;
wait until rising_edge(clk);
vld_in <= '0';
wait;
END PROCESS;
END;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_mix_cpx
-- Module Name: tb_mix_cpx.vhd
-- Project Name: mix_cpx
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.PCK_FIO.all;
use work.fixed_util_pkg.all;
ENTITY tb_cic_decim_pipe IS
Generic
(
nstages : integer := 3;
ratio : integer := 64;
scale_nbits : integer := 18;
in_width : integer := 18;
in_width_frac : integer := 16;
out_width : integer := 18;
out_width_frac : integer := 16
);
END tb_cic_decim_pipe;
ARCHITECTURE behavior OF tb_cic_decim_pipe IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cic_decim_pipe
GENERIC
(
nstages : integer;
ratio : integer;
scale_nbits : integer;
in_width : integer;
in_width_frac : integer;
out_width : integer;
out_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
--Constants
constant PERIOD : time := 10 ns;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL srst : std_logic := '1';
SIGNAL vld_in : std_logic := '0';
SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
--Outputs
SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
SIGNAL vld_out : std_logic;
SIGNAL fileout_enable : std_logic := '0';
signal XR, YR : real;
BEGIN
XR <= to_real(din);
YR <= to_real(dout);
-- Instantiate the Unit Under Test (UUT)
uut : cic_decim_pipe
GENERIC MAP
(
nstages => nstages,
ratio => ratio,
scale_nbits => scale_nbits,
in_width => in_width,
in_width_frac => in_width_frac,
out_width => out_width,
out_width_frac => out_width_frac
)
PORT MAP
(
clk => clk,
rst => srst,
vld_in => vld_in,
din => din,
dout => dout,
vld_out => vld_out
);
tb_clk : PROCESS
BEGIN
clk <= not clk;
wait for PERIOD/2;
END PROCESS;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 4*PERIOD;
srst <= '0';
------------------------------------------
wait for 2*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.0, din);
vld_in <= '1';
wait for 49*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.5, din);
wait for 4999*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(-0.5, din);
wait for 99*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.0, din);
wait for 499*PERIOD;
wait until rising_edge(clk);
vld_in <= '0';
wait;
END PROCESS;
END;
lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd
+126 -126
View File
@@ -1,126 +1,126 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_mix_cpx
-- Module Name: tb_mix_cpx.vhd
-- Project Name: mix_cpx
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.PCK_FIO.all;
use work.fixed_util_pkg.all;
ENTITY tb_cic_i_pipe IS
Generic
(
max_width : integer := 32;
max_width_frac : integer := 20
);
END tb_cic_i_pipe;
ARCHITECTURE behavior OF tb_cic_i_pipe IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cic_i_pipe
GENERIC
(
max_width : integer;
max_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
--Constants
constant PERIOD : time := 10 ns;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL srst : std_logic := '1';
SIGNAL vld_in : std_logic := '0';
SIGNAL din : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
--Outputs
SIGNAL dout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
SIGNAL vld_out : std_logic;
SIGNAL fileout_enable : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cic_i_pipe
GENERIC MAP
(
max_width => max_width,
max_width_frac => max_width_frac
)
PORT MAP
(
clk => clk,
rst => srst,
vld_in => vld_in,
din => din,
dout => dout,
vld_out => vld_out
);
tb_clk : PROCESS
BEGIN
clk <= not clk;
wait for PERIOD/2;
END PROCESS;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 4*PERIOD;
srst <= '0';
------------------------------------------
wait for 2*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.0, din);
vld_in <= '1';
wait for 9*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.5, din);
wait for 9*PERIOD;
wait until rising_edge(clk);
vld_in <= '0';
wait for 20*PERIOD;
assert false report "Test finished" severity error;
wait;
END PROCESS;
END;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_mix_cpx
-- Module Name: tb_mix_cpx.vhd
-- Project Name: mix_cpx
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.PCK_FIO.all;
use work.fixed_util_pkg.all;
ENTITY tb_cic_i_pipe IS
Generic
(
max_width : integer := 32;
max_width_frac : integer := 20
);
END tb_cic_i_pipe;
ARCHITECTURE behavior OF tb_cic_i_pipe IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cic_i_pipe
GENERIC
(
max_width : integer;
max_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
--Constants
constant PERIOD : time := 10 ns;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL srst : std_logic := '1';
SIGNAL vld_in : std_logic := '0';
SIGNAL din : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
--Outputs
SIGNAL dout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
SIGNAL vld_out : std_logic;
SIGNAL fileout_enable : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cic_i_pipe
GENERIC MAP
(
max_width => max_width,
max_width_frac => max_width_frac
)
PORT MAP
(
clk => clk,
rst => srst,
vld_in => vld_in,
din => din,
dout => dout,
vld_out => vld_out
);
tb_clk : PROCESS
BEGIN
clk <= not clk;
wait for PERIOD/2;
END PROCESS;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 4*PERIOD;
srst <= '0';
------------------------------------------
wait for 2*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.0, din);
vld_in <= '1';
wait for 9*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.5, din);
wait for 9*PERIOD;
wait until rising_edge(clk);
vld_in <= '0';
wait for 20*PERIOD;
assert false report "Test finished" severity error;
wait;
END PROCESS;
END;