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- added port 'eb' for Endian-big selection

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git-svn-id: http://moon:8086/svn/vhdl/trunk@433 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-04-15 13:23:30 +00:00
parent b8890b0132
commit 2fb198d941
5 changed files with 29 additions and 5 deletions
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projects/mips_sys/src/mips_sys.vhd
+4
View File
@@ -127,6 +127,7 @@ ARCHITECTURE behavior OF mips_sys IS
Port
(
debug : out unsigned(1 downto 0);
eb : in STD_LOGIC;
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
@@ -305,6 +306,7 @@ ARCHITECTURE behavior OF mips_sys IS
signal rst : std_logic;
signal clk : std_logic;
signal eb : std_logic;
signal clk270 : std_logic;
signal clk270var : std_logic;
signal rst_in : std_logic;
@@ -423,6 +425,7 @@ ARCHITECTURE behavior OF mips_sys IS
BEGIN
eb <= sys_dip(7);
gpi0(4 downto 0) <= sys_btn;
gpi1(7 downto 0) <= sys_dip;
sys_led <= gpo0(8 downto 0);
@@ -578,6 +581,7 @@ inst_mips_top: mips_top
PORT MAP
(
debug => debug,
eb => eb,
RST_I => rst,
CLK_I => clk,
ACK_I => ACK_I_cpu,
projects/mips_sys/src/mips_sys_sim.vhd
+4
View File
@@ -138,6 +138,7 @@ ARCHITECTURE behavior OF mips_sys IS
Port
(
debug : out unsigned(1 downto 0);
eb : in STD_LOGIC;
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
@@ -349,6 +350,7 @@ ARCHITECTURE behavior OF mips_sys IS
signal rst : std_logic;
signal clk : std_logic;
signal eb : std_logic;
signal clk270 : std_logic;
signal clk270var : std_logic;
signal rst_in : std_logic;
@@ -487,6 +489,7 @@ ARCHITECTURE behavior OF mips_sys IS
BEGIN
eb <= sys_dip(7);
gpi0(4 downto 0) <= sys_btn;
gpi1(7 downto 0) <= sys_dip;
sys_led <= gpo0(8 downto 0);
@@ -676,6 +679,7 @@ inst_mips_top: mips_top
PORT MAP
(
debug => debug,
eb => eb,
RST_I => rst,
CLK_I => clk,
ACK_I => ACK_I_cpu,