From 2fb198d941876a184ed639d11d6cb658ed975967 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 15 Apr 2009 13:23:30 +0000 Subject: [PATCH] - added port 'eb' for Endian-big selection Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@433 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_cop.vhd | 15 +++++++++++++-- lib/CPUs/MIPS/src/core/mips_top.vhd | 3 +++ lib/CPUs/MIPS/src/tb_mips_top.vhd | 8 +++++--- projects/mips_sys/src/mips_sys.vhd | 4 ++++ projects/mips_sys/src/mips_sys_sim.vhd | 4 ++++ 5 files changed, 29 insertions(+), 5 deletions(-) diff --git a/lib/CPUs/MIPS/src/core/mips_cop.vhd b/lib/CPUs/MIPS/src/core/mips_cop.vhd index 512a52f..4252339 100644 --- a/lib/CPUs/MIPS/src/core/mips_cop.vhd +++ b/lib/CPUs/MIPS/src/core/mips_cop.vhd @@ -40,6 +40,7 @@ entity cop is ( rst : in STD_LOGIC; clk : in STD_LOGIC; + eb : in STD_LOGIC; int : in unsigned(5 downto 0); ir_en : in STD_LOGIC; ir : in word_t; @@ -72,7 +73,7 @@ architecture Behavioral of cop is signal status_save : STD_LOGIC; signal status_rest : STD_LOGIC; signal eflags : exc_flags_t; - signal exc_enable : STD_LOGIC; + signal EB_reg : STD_LOGIC; signal icache_info : unsigned(7 downto 0); signal dcache_info : unsigned(7 downto 0); @@ -122,7 +123,7 @@ begin cop_pipe_ID.re <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "111000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00000")) else '0'; cop_pipe_ID.we <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "110000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00100")) else '0'; cop_pipe_ID.RFE <= cop_pipe_ID.cs when (cop_pipe_ID.CO = '1' and cop_pipe_ID.func = "010000") else '0'; - ctrl_out.RE <= status(25); + ctrl_out.EB <= EB_reg xor (status(25) and status(1)); ctrl_out.user_mode <= status(1); ctrl_out.int <= eval_int(ip) and status(0); @@ -211,6 +212,16 @@ exception_state: end case; end process; +sample_endian: + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + EB_reg <= eb; + end if; + end if; + end process; + exception_last_imem_addr: process(clk) begin diff --git a/lib/CPUs/MIPS/src/core/mips_top.vhd b/lib/CPUs/MIPS/src/core/mips_top.vhd index fa36d2f..15d23e2 100644 --- a/lib/CPUs/MIPS/src/core/mips_top.vhd +++ b/lib/CPUs/MIPS/src/core/mips_top.vhd @@ -39,6 +39,7 @@ entity mips_top is Port ( debug : out unsigned(1 downto 0); + eb : in STD_LOGIC; RST_I : in STD_LOGIC; CLK_I : in STD_LOGIC; ACK_I : in STD_LOGIC; @@ -128,6 +129,7 @@ architecture rtl of mips_top is ( rst : in STD_LOGIC; clk : in STD_LOGIC; + eb : in STD_LOGIC; int : in unsigned (5 downto 0); ir_en : in STD_LOGIC; ir : in word_t; @@ -249,6 +251,7 @@ inst_cop: cop ( rst => cpu_rst, clk => CLK_I, + eb => eb, int => INT, ir_en => pipe_cop_ir_en, ir => pipe_cop_ir, diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd index 138d365..52b7f53 100644 --- a/lib/CPUs/MIPS/src/tb_mips_top.vhd +++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd @@ -38,14 +38,15 @@ END tb_mips_top; ARCHITECTURE behavior OF tb_mips_top IS constant CLK_PERIOD : time := 10 ns; - constant SRAM_ADDR_WIDTH : integer := 15; -- bits - constant FLASH_ADDR_WIDTH : integer := 15; -- bits + constant SRAM_ADDR_WIDTH : integer := 17; -- bits + constant FLASH_ADDR_WIDTH : integer := 17; -- bits signal debug : unsigned(1 downto 0); -- Master signal rst : STD_LOGIC := '1'; signal clk : STD_LOGIC := '0'; + signal eb : STD_LOGIC := '0'; signal ACK_I : STD_LOGIC := '0'; signal SRDY_I : STD_LOGIC := '0'; signal ADDR_O : unsigned(31 downto 0); @@ -200,6 +201,7 @@ uut: entity work.mips_top PORT MAP ( debug => debug, + eb => eb, RST_I => rst, CLK_I => clk, ACK_I => ACK_I, @@ -385,7 +387,7 @@ SRAM_WRITE: FLASH_READ: process(rst, flash_cs_n, flash_oe_n, flash_a) type file_t is file of integer; - file load_flash : file_t open read_mode is "test_timer.flash.bin"; + file load_flash : file_t open read_mode is "test_endianess.flash.bin"; variable instr : integer; variable index : natural; variable temp : signed(31 downto 0); diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd index 3e5cd7d..1b57adc 100644 --- a/projects/mips_sys/src/mips_sys.vhd +++ b/projects/mips_sys/src/mips_sys.vhd @@ -127,6 +127,7 @@ ARCHITECTURE behavior OF mips_sys IS Port ( debug : out unsigned(1 downto 0); + eb : in STD_LOGIC; RST_I : in STD_LOGIC; CLK_I : in STD_LOGIC; ACK_I : in STD_LOGIC; @@ -305,6 +306,7 @@ ARCHITECTURE behavior OF mips_sys IS signal rst : std_logic; signal clk : std_logic; + signal eb : std_logic; signal clk270 : std_logic; signal clk270var : std_logic; signal rst_in : std_logic; @@ -423,6 +425,7 @@ ARCHITECTURE behavior OF mips_sys IS BEGIN + eb <= sys_dip(7); gpi0(4 downto 0) <= sys_btn; gpi1(7 downto 0) <= sys_dip; sys_led <= gpo0(8 downto 0); @@ -578,6 +581,7 @@ inst_mips_top: mips_top PORT MAP ( debug => debug, + eb => eb, RST_I => rst, CLK_I => clk, ACK_I => ACK_I_cpu, diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd index f08540f..8f3b0d4 100644 --- a/projects/mips_sys/src/mips_sys_sim.vhd +++ b/projects/mips_sys/src/mips_sys_sim.vhd @@ -138,6 +138,7 @@ ARCHITECTURE behavior OF mips_sys IS Port ( debug : out unsigned(1 downto 0); + eb : in STD_LOGIC; RST_I : in STD_LOGIC; CLK_I : in STD_LOGIC; ACK_I : in STD_LOGIC; @@ -349,6 +350,7 @@ ARCHITECTURE behavior OF mips_sys IS signal rst : std_logic; signal clk : std_logic; + signal eb : std_logic; signal clk270 : std_logic; signal clk270var : std_logic; signal rst_in : std_logic; @@ -487,6 +489,7 @@ ARCHITECTURE behavior OF mips_sys IS BEGIN + eb <= sys_dip(7); gpi0(4 downto 0) <= sys_btn; gpi1(7 downto 0) <= sys_dip; sys_led <= gpo0(8 downto 0); @@ -676,6 +679,7 @@ inst_mips_top: mips_top PORT MAP ( debug => debug, + eb => eb, RST_I => rst, CLK_I => clk, ACK_I => ACK_I_cpu,