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git-svn-id: http://moon:8086/svn/vhdl/trunk@1290 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2015-06-10 19:27:35 +00:00
parent 8eb6b3ff9e
commit 2edaa4d7cb
217 changed files with 152127 additions and 0 deletions
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lib/models/memory/sdram/mt48lc64m4a2/base.do
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vcom util1164.vhd
vcom stdlogar.vhd
vcom io_utils.vhd
vcom mti_pkg.vhd
lib/models/memory/sdram/mt48lc64m4a2/ed_comnd.vhd
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---------------------------------------------------------------------------------
--COMMAND FORMAT --
-- --
-- write(column address(integer), bank(bit_vector), first data(integer), dqm(bit), cke(bit));--
-- read(column address(integer), bank(bit_vector), dqm(bit), cke(bit)); --
-- active(row address(integer), bank(bit_vector), data bus (integer), dqm(bit), cke(bit));--
-- precharge(bank(bit_vector), address (integer), data bus(integer), dqm(bit), cke(bit)); --
-- nop(data bus(integer), dqm(bit), cke(bit), cs(bit)); --
-- burst_term(data bus(integer), dqm(bit), cke(bit)); --
-- load_array('1'); --
-- load_mode_reg(register(integer), cke(bit)); --
-- next_cycle(clk); This is used after every command(incl. nop) to clock --
-- at the correct clock frequency entered in the clock --
-- period constant below --
-- unload_array(row_start(integer), row_end(integer), bank(bit_vector)) --
-- load_mode_reg(op_code(integer)) --
-- --
---------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.generate_vectors.all;
ENTITY vector_generate IS
END vector_generate;
ARCHITECTURE vector_generate OF vector_generate IS
SIGNAL stim_done : BOOLEAN := FALSE;
SIGNAL clk : BIT := '0';
CONSTANT clk_start : time := 15 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT Z : INTEGER := -100;
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1' AND clk'EVENT;
--------------------ENTER COMMANDS BELOW THIS LINE-----------------------------
--******************DO NOT USE -100 FOR A DQ VALUE*************************----
--*******************Z WILL PLACE HI-Z ON THE BUS**************************----
--*******USE next_cycle(clk) FOR ADVANCING TO NEXT CLOCK CYCLE*************----
nop(Z, '0', '1', '1'); --Always begin with one nop when using Micron's testbench
--next_cycle(clk);
--load_array('1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
precharge("00", 1024, Z, '0', '1');
FOR i IN 1 to 2 LOOP
next_cycle(clk);
nop(Z, '0', '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, '0', '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, '0', '1', '1');
END LOOP;
next_cycle(clk);
load_mode_reg(51, '1'); -- 19 / 35 / 51 -> lat=3,bl=8,mode=seq
next_cycle(clk);
nop(Z, '0', '1', '1');
-- Write Section
next_cycle(clk);
active(0, "00", Z, '0', '1'); -- Activate Bank 0
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk); -- Write Bank 0
write(10, "00", 0, '0', '1');
next_cycle(clk);
nop(1, '0', '1', '1');
next_cycle(clk);
active(0, "01", 2, '0', '1'); -- Activate Bank 1
next_cycle(clk);
nop(3, '0', '1', '1');
next_cycle(clk);
nop(4, '0', '1', '1');
next_cycle(clk);
nop(5, '0', '1', '1');
next_cycle(clk);
nop(6, '0', '1', '1');
next_cycle(clk);
nop(7, '0', '1', '1');
next_cycle(clk);
write(20, "01", 8, '0', '1'); -- Write Bank 1
next_cycle(clk);
precharge("00", 0, 9, '0', '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", 10, '0', '1'); -- Activate Bank 2
next_cycle(clk);
nop(11, '0', '1', '1');
next_cycle(clk);
nop(12, '0', '1', '1');
next_cycle(clk);
nop(13, '0', '1', '1');
next_cycle(clk);
nop(14, '0', '1', '1');
next_cycle(clk);
nop(15, '0', '1', '1');
next_cycle(clk);
write(30, "10", 0, '0', '1'); -- Write Bank 2
next_cycle(clk);
precharge("01", 0, 1, '0', '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", 2, '0', '1'); -- Activate Bank 3
next_cycle(clk);
nop(3, '0', '1', '1');
next_cycle(clk);
nop(4, '0', '1', '1');
next_cycle(clk);
nop(5, '0', '1', '1');
next_cycle(clk);
nop(6, '0', '1', '1');
next_cycle(clk);
nop(7, '0', '1', '1');
next_cycle(clk);
write(40, "11", 8, '0', '1'); -- Write Bank 3
next_cycle(clk);
precharge("10", 0, 9, '0', '1'); -- Precharge Bank 2
next_cycle(clk);
active(0, "00", 10, '0', '1'); -- Activate Bank 0
next_cycle(clk);
nop(11, '0', '1', '1');
next_cycle(clk);
nop(12, '0', '1', '1');
next_cycle(clk);
nop(13, '0', '1', '1');
next_cycle(clk);
nop(14, '0', '1', '1');
next_cycle(clk);
nop(15, '0', '1', '1');
-- Read Section
next_cycle(clk);
read(10, "00", '0', '1'); -- Read Bank 0
next_cycle(clk);
precharge("11", 0, Z, '0', '1'); -- Precharge Bank 3
next_cycle(clk);
active(0, "01", Z, '0', '1'); -- Activate Bank 1
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
read(20, "01", '0', '1'); -- Read Bank 1
next_cycle(clk);
precharge("00", 0, Z, '0', '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", Z, '0', '1'); -- Activate Bank 2
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
read(30, "10", '0', '1'); -- Read Bank 2
next_cycle(clk);
precharge("01", 0, Z, '0', '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", Z, '0', '1'); -- Activate Bank 3
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
read(40, "11", '0', '1'); -- Read Bank 3
next_cycle(clk);
precharge("10", 0, Z, '0', '1'); -- Precharge Bank 2
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
precharge("11", 0, Z, '0', '1'); -- Precharge Bank 3
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
--next_cycle(clk);
--unload_array(0, 0, '0');
next_cycle(clk);
nop(Z, '0', '1', '1');
stim_done <= TRUE; --always include this line at the end of your stimulus
-------------------------------------------------------------------------------
--*************************************************************************----
END PROCESS;
clock:
PROCESS
VARIABLE done_time : time;
VARIABLE cycle_var : integer := 0;
BEGIN
cycle <= 0;
clk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
clk <= '1';
cycle <= cycle_var;
WAIT for clk_period/2;
cycle_var := cycle_var + 1;
clk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT (FALSE)
REPORT "Test Vectors Generated"
SEVERITY note;
WAIT;
END PROCESS;
END;
lib/models/memory/sdram/mt48lc64m4a2/io_utils.vhd
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LIBRARY ieee;
USE std.textio.ALL;
USE ieee.std_logic_1164.ALL;
PACKAGE io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0);
TYPE radix IS (binary, octal, decimal, hex);
-- read a number from the line
-- use this if you have hex numbers that are not in VHDL pound-sign format
PROCEDURE read(l : INOUT line; value : OUT integer; radix : IN positive);
-- read a number that might be in VHDL pound-sign format
PROCEDURE read_based(l : INOUT line; value : OUT integer);
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
END io_utils;
PACKAGE BODY io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0)
IS
BEGIN
write(l, value, justified, field);
END;
PROCEDURE shrink_line(l : INOUT line; pos : integer) IS
VARIABLE tmpl : line;
BEGIN
tmpl := l;
l := NEW string'(tmpl(pos TO tmpl'high));
deallocate(tmpl);
END;
PROCEDURE read(l : INOUT line;
value : OUT integer;
radix : IN positive)
IS
CONSTANT not_digit : integer := -999;
-- convert a character to a value from 0 to 15
FUNCTION digit_value(c : character) RETURN integer IS
BEGIN
IF (c >= '0') AND (c <= '9') THEN
RETURN (character'pos(c) - character'pos('0'));
ELSIF (c >= 'a') AND (c <= 'f') THEN
RETURN (character'pos(c) - character'pos('a') + 10);
ELSIF (c >= 'A') AND (c <= 'F') THEN
RETURN (character'pos(c) - character'pos('A') + 10);
ELSE
RETURN not_digit;
END IF;
END;
-- skip leading white space in the line
PROCEDURE skip_white(VARIABLE l : IN line; pos : OUT integer) IS
BEGIN
pos := l'low;
FOR i IN l'low TO l'high LOOP
CASE l(i) IS
WHEN ' ' | ht =>
pos := i + 1;
WHEN OTHERS =>
EXIT;
END CASE;
END LOOP;
END;
VARIABLE digit : integer;
VARIABLE result : integer := 0;
VARIABLE pos : integer;
BEGIN
-- skip white space
skip_white(l, pos);
-- calculate the value
FOR i IN pos TO l'right LOOP
digit := digit_value(l(i));
EXIT WHEN (digit = not_digit) OR (digit >= radix);
result := result * radix + digit;
pos := i + 1;
END LOOP;
value := result;
-- remove the "used" characters from the line
shrink_line(l, pos);
END;
PROCEDURE read_based(l : INOUT line; value : OUT integer) IS
VARIABLE digit : integer;
VARIABLE num : integer;
VARIABLE base : integer;
BEGIN
read(l, num, 10);
IF (l'length > 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
base := num;
read(l, num, base);
IF (l'length >= 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
END IF;
END IF;
value := num;
END;
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_int(bv : std_logic_vector) RETURN integer
IS
VARIABLE result : integer := 0;
BEGIN
FOR i IN bv'RANGE LOOP
result := result * 2;
IF (bv(i) = '1') THEN
result := result + 1;
END IF;
END LOOP;
RETURN result;
END;
TYPE array_of_widths IS ARRAY(radix) OF natural;
CONSTANT nibble_widths : array_of_widths := (
binary => 1,
octal => 3,
hex => 4,
decimal=> 32);
CONSTANT hex_digit : string(1 TO 16) := "0123456789ABCDEF";
ALIAS input_val : std_logic_vector(value'length DOWNTO 1) IS value;
CONSTANT nibble_width : natural := nibble_widths(base);
CONSTANT result_width : natural := (value'length + nibble_width - 1)/nibble_width;
VARIABLE result : string(1 TO result_width); -- longest possible value
VARIABLE result_pos : positive := 1;
VARIABLE nibble_val : integer;
VARIABLE bitcnt : integer;
BEGIN
IF base = decimal THEN
write(l, to_int(value), justified, field, base, use_pound);
RETURN;
END IF;
bitcnt := value'length MOD nibble_width;
IF (bitcnt = 0) THEN
bitcnt := nibble_width;
END IF;
FOR i IN input_val'RANGE LOOP
nibble_val := nibble_val * 2;
IF (input_val(i) = '1') THEN
nibble_val := nibble_val + 1;
END IF;
bitcnt := bitcnt - 1;
IF (bitcnt = 0) THEN
result(result_pos) := hex_digit(nibble_val + 1);
result_pos := result_pos + 1;
nibble_val := 0;
bitcnt := nibble_width;
END IF;
END LOOP;
write(l, result, justified, field);
END;
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_bv(int : integer) RETURN std_logic_vector
IS
VARIABLE bv : std_logic_vector(32 DOWNTO 1) := (OTHERS => '0');
VARIABLE pos : integer := 0;
VARIABLE tmpval : integer := int;
BEGIN
FOR i IN 1 TO 32 LOOP
pos := pos + 1;
IF (tmpval MOD 2) = 1 THEN
bv(i) := '1';
END IF;
tmpval := tmpval / 2;
EXIT WHEN tmpval = 0;
END LOOP;
RETURN bv(pos DOWNTO 1);
END;
VARIABLE tmp : line;
BEGIN
IF (base = decimal) THEN
IF (use_pound) THEN
write_string(tmp, "10#");
END IF;
write(tmp, value);
IF (use_pound) THEN
write_string(tmp, "#");
END IF;
write(l, tmp.ALL, justified, field);
deallocate(tmp);
ELSE
write(l, to_bv(value), justified, field, base, use_pound);
END IF;
END;
END io_utils;
-- test the hex number reader
--ENTITY test IS END;
--USE std.textio.ALL;
--USE work.io_utils.ALL;
--ARCHITECTURE hex_test OF test IS
--BEGIN
-- PROCESS
-- VARIABLE val : integer;
-- FILE myfile : text IS IN "values";
-- VARIABLE inline : line;
-- VARIABLE outline : line;
-- BEGIN
-- WHILE NOT endfile(myfile) LOOP
-- readline(myfile, inline);
-- write(outline, inline.ALL);
--
-- read_based(inline, val);
-- write_string(outline, " binary: ");
-- write(outline, val, base => binary);
-- write_string(outline, " octal: ");
-- write(outline, val, base => octal);
-- write_string(outline, " decimal: ");
-- write(outline, val, base => decimal);
-- write_string(outline, " hex: ");
-- write(outline, val, base => hex);
-- writeline(output, outline);
-- END LOOP;
-- WAIT;
-- END PROCESS;
--END;
lib/models/memory/sdram/mt48lc64m4a2/mt48lc64m4a2.vhd
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lib/models/memory/sdram/mt48lc64m4a2/mti_pkg.vhd
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--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE mti_pkg IS
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver integer to bit_vector
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN
outputlen := 32;
offset := output'LENGTH - 32;
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0';
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1';
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH;
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0';
ELSE
output(output'HIGH-j-offset) := '1';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0';
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1';
ELSE
output(output'HIGH-j-offset) := '0';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1';
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
lib/models/memory/sdram/mt48lc64m4a2/readme.txt
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To operate the test bench for the Micron SDRAM VHDL model, follow the directions
given below:
1. Be sure all supporting files for the SDRAM are compiled into your library:
util1164.vhd
stdlogar.vhd
io_utils.vhd
mti_pkg.vhd
2. Next, compile the mt48lc64m4a2.vhd file and the test.vhd file.
3. Simulate the "tb" architecture. This is the testbench for the 256Mb SDRAM.
lib/models/memory/sdram/mt48lc64m4a2/stdlogar.vhd
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lib/models/memory/sdram/mt48lc64m4a2/test.do
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vcom mt48lc64m4a2.vhd
vcom test.vhd
vsim tb
do wave.do
run -all
lib/models/memory/sdram/mt48lc64m4a2/test.txt
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0 ns 1 1 1 1 1 0 00 0 -100
22 ns 1 1 1 1 1 0 00 0 -100
32 ns 1 1 1 1 1 0 00 0 -100
42 ns 1 1 1 1 1 0 00 0 -100
52 ns 1 1 1 1 1 0 00 0 -100
62 ns 1 0 0 1 0 0 00 1024 -100
72 ns 1 1 1 1 1 0 00 0 -100
82 ns 1 1 1 1 1 0 00 0 -100
92 ns 1 0 0 0 1 0 00 0 -100
102 ns 1 1 1 1 1 0 00 0 -100
112 ns 1 1 1 1 1 0 00 0 -100
122 ns 1 1 1 1 1 0 00 0 -100
132 ns 1 1 1 1 1 0 00 0 -100
142 ns 1 1 1 1 1 0 00 0 -100
152 ns 1 1 1 1 1 0 00 0 -100
162 ns 1 1 1 1 1 0 00 0 -100
172 ns 1 1 1 1 1 0 00 0 -100
182 ns 1 0 0 0 1 0 00 0 -100
192 ns 1 1 1 1 1 0 00 0 -100
202 ns 1 1 1 1 1 0 00 0 -100
212 ns 1 1 1 1 1 0 00 0 -100
222 ns 1 1 1 1 1 0 00 0 -100
232 ns 1 1 1 1 1 0 00 0 -100
242 ns 1 1 1 1 1 0 00 0 -100
252 ns 1 1 1 1 1 0 00 0 -100
262 ns 1 1 1 1 1 0 00 0 -100
272 ns 1 0 0 0 0 0 00 51 -100
282 ns 1 1 1 1 1 0 00 0 -100
292 ns 1 0 0 1 1 0 00 0 -100
302 ns 1 1 1 1 1 0 00 0 -100
312 ns 1 0 1 0 0 0 00 10 0
322 ns 1 1 1 1 1 0 00 0 1
332 ns 1 0 0 1 1 0 01 0 2
342 ns 1 1 1 1 1 0 00 0 3
352 ns 1 1 1 1 1 0 00 0 4
362 ns 1 1 1 1 1 0 00 0 5
372 ns 1 1 1 1 1 0 00 0 6
382 ns 1 1 1 1 1 0 00 0 7
392 ns 1 0 1 0 0 0 01 20 8
402 ns 1 0 0 1 0 0 00 0 9
412 ns 1 0 0 1 1 0 10 0 10
422 ns 1 1 1 1 1 0 00 0 11
432 ns 1 1 1 1 1 0 00 0 12
442 ns 1 1 1 1 1 0 00 0 13
452 ns 1 1 1 1 1 0 00 0 14
462 ns 1 1 1 1 1 0 00 0 15
472 ns 1 0 1 0 0 0 10 30 0
482 ns 1 0 0 1 0 0 01 0 1
492 ns 1 0 0 1 1 0 11 0 2
502 ns 1 1 1 1 1 0 00 0 3
512 ns 1 1 1 1 1 0 00 0 4
522 ns 1 1 1 1 1 0 00 0 5
532 ns 1 1 1 1 1 0 00 0 6
542 ns 1 1 1 1 1 0 00 0 7
552 ns 1 0 1 0 0 0 11 40 8
562 ns 1 0 0 1 0 0 10 0 9
572 ns 1 0 0 1 1 0 00 0 10
582 ns 1 1 1 1 1 0 00 0 11
592 ns 1 1 1 1 1 0 00 0 12
602 ns 1 1 1 1 1 0 00 0 13
612 ns 1 1 1 1 1 0 00 0 14
622 ns 1 1 1 1 1 0 00 0 15
632 ns 1 0 1 0 1 0 00 10 -100
642 ns 1 0 0 1 0 0 11 0 -100
652 ns 1 0 0 1 1 0 01 0 -100
662 ns 1 1 1 1 1 0 00 0 -100
672 ns 1 1 1 1 1 0 00 0 -100
682 ns 1 1 1 1 1 0 00 0 -100
692 ns 1 1 1 1 1 0 00 0 -100
702 ns 1 1 1 1 1 0 00 0 -100
712 ns 1 0 1 0 1 0 01 20 -100
722 ns 1 0 0 1 0 0 00 0 -100
732 ns 1 0 0 1 1 0 10 0 -100
742 ns 1 1 1 1 1 0 00 0 -100
752 ns 1 1 1 1 1 0 00 0 -100
762 ns 1 1 1 1 1 0 00 0 -100
772 ns 1 1 1 1 1 0 00 0 -100
782 ns 1 1 1 1 1 0 00 0 -100
792 ns 1 0 1 0 1 0 10 30 -100
802 ns 1 0 0 1 0 0 01 0 -100
812 ns 1 0 0 1 1 0 11 0 -100
822 ns 1 1 1 1 1 0 00 0 -100
832 ns 1 1 1 1 1 0 00 0 -100
842 ns 1 1 1 1 1 0 00 0 -100
852 ns 1 1 1 1 1 0 00 0 -100
862 ns 1 1 1 1 1 0 00 0 -100
872 ns 1 0 1 0 1 0 11 40 -100
882 ns 1 0 0 1 0 0 10 0 -100
892 ns 1 1 1 1 1 0 00 0 -100
902 ns 1 1 1 1 1 0 00 0 -100
912 ns 1 1 1 1 1 0 00 0 -100
922 ns 1 1 1 1 1 0 00 0 -100
932 ns 1 1 1 1 1 0 00 0 -100
942 ns 1 1 1 1 1 0 00 0 -100
952 ns 1 0 0 1 0 0 11 0 -100
962 ns 1 1 1 1 1 0 00 0 -100
972 ns 1 1 1 1 1 0 00 0 -100
982 ns 1 1 1 1 1 0 00 0 -100
lib/models/memory/sdram/mt48lc64m4a2/test.vhd
+168
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.ALL;
USE work.std_logic_arith.ALL;
USE work.util_1164.ALL;
USE work.mti_pkg.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE test OF tb IS
CONSTANT addr_bits : INTEGER := 13;
CONSTANT data_bits : INTEGER := 4;
CONSTANT clk_start : time := 5 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT continue_time : time := 10 ns;
COMPONENT mt48lc64m4a2
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC := '0'
);
END COMPONENT;
FOR ALL : mt48lc64m4a2 USE ENTITY work.mt48lc64m4a2 (behave);
SIGNAL pDq : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
SIGNAL pAddr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
SIGNAL pBa : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pClk : STD_LOGIC;
SIGNAL pCke : STD_LOGIC;
SIGNAL pCs : STD_LOGIC;
SIGNAL pCas : STD_LOGIC;
SIGNAL pRas : STD_LOGIC;
SIGNAL pWe : STD_LOGIC;
SIGNAL pDqm : STD_LOGIC;
SIGNAL stim_done : boolean := false;
SIGNAL clk_done : boolean := false;
BEGIN
u1: mt48lc64m4a2
PORT MAP(
Dq => pDq,
Addr => pAddr,
Ba => pBa,
Clk => pClk,
Cke => pCke,
Cs_n => pCs,
Ras_n => pRas,
Cas_n => pCas,
We_n => pWe,
Dqm => pDqm
);
stimulator : PROCESS
FILE stim_file:text IS IN "test.txt";
VARIABLE l : line;
VARIABLE time_var : TIME;
VARIABLE pCke_var : STD_LOGIC;
VARIABLE pCs_var : STD_LOGIC;
VARIABLE pRas_var : STD_LOGIC;
VARIABLE PCas_var : STD_LOGIC;
VARIABLE pWe_var : STD_LOGIC;
VARIABLE pDqm_var : STD_LOGIC;
VARIABLE pBa_var : STD_LOGIC_VECTOR (1 DOWNTO 0);
VARIABLE pAddr_var : INTEGER;
VARIABLE pDq_var : INTEGER; -- -100 is converted to hi-Z state
VARIABLE pMa_var_vect : STD_LOGIC_VECTOR(addr_bits - 1 DOWNTO 0);
CONSTANT HiZ : STD_LOGIC_VECTOR(data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
BEGIN
WHILE not ENDFILE(stim_file) LOOP
readline(stim_file,l);
IF l'length > 0 THEN
read(l, time_var);
read(l, pCke_var);
read(l, pCs_var);
read(l, pRas_var);
read(l, pCas_var);
read(l, pWe_var);
read(l, pDqm_var);
read(l, pBa_var);
read(l, pAddr_var);
read(l, pDq_var);
IF now > time_var THEN
ASSERT false
REPORT "Detected a time in the stim file that is in the past"
SEVERITY error;
ELSE
WAIT FOR time_var-now;
IF pWe_var='1' THEN
pCke <= pCke_var;
pCs <= pCs_var;
pRas <= pRas_var;
pCas <= pCas_var;
pWe <= pWe_var;
pDqm <= pDqm_var;
pBa <= pBa_var;
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
ELSE
pCke <= pCke_var;
pCs <= pCs_var;
pRas <= pRas_var;
pCas <= pCas_var;
pWe <= pWe_var;
pDqm <= pDqm_var;
pBa <= pBa_var;
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
END IF;
END IF;
END IF;
END LOOP;
ASSERT false
REPORT "End of Stimulation File Detected!"
SEVERITY note;
stim_done <= true;
WAIT;
END PROCESS;
clock : PROCESS
VARIABLE done_time : time;
BEGIN
pclk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
done_time := now+continue_time;
WHILE now < done_time LOOP --one last clock to finish last command
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT false
REPORT "Suspending clock activity"
SEVERITY note;
clk_done <= true;
WAIT;
END PROCESS;
END test;
lib/models/memory/sdram/mt48lc64m4a2/util1164.vhd
+124
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE STD.textio.ALL;
PACKAGE util_1164 IS
PROCEDURE read(l: INOUT line; value: OUT std_logic);
PROCEDURE read(l: INOUT line; value: OUT std_logic_vector);
PROCEDURE write(l: INOUT line; value: IN std_logic_vector;
JUSTIFIED: IN SIDE := right;
FIELD: IN WIDTH := 0);
PROCEDURE Grow_line(L : inout LINE; incr : in integer);
END util_1164;
PACKAGE BODY util_1164 IS
FUNCTION white_space(value:character) RETURN boolean IS
VARIABLE result:boolean;
BEGIN
IF (value = ' ') OR (value = HT) THEN
RETURN true;
ELSE
RETURN false;
END IF;
END white_space;
PROCEDURE read(l: INOUT line; value: OUT std_logic) IS
VARIABLE char_var: character:= ' ';
BEGIN
WHILE l'LENGTH > 0 LOOP
read(l,char_var);
IF NOT white_space(char_var) THEN
EXIT;
END IF;
END LOOP;
IF white_space(char_var) THEN
ASSERT false REPORT "No std_logic value found in file"
SEVERITY error;
value := 'X';
RETURN;
END IF;
CASE char_var IS
WHEN 'U'|'u' => value := 'U';
WHEN '0' => value := '0';
WHEN '1' => value := '1';
WHEN 'X'|'x' => value := 'X';
WHEN 'L'|'l' => value := 'L';
WHEN 'H'|'h' => value := 'H';
WHEN 'W'|'w' => value := 'W';
WHEN 'Z'|'z' => value := 'Z';
WHEN '-' => value := '-';
WHEN OTHERS =>
ASSERT false REPORT "Unrecognized value read for std_logic"
SEVERITY error;
value := 'X';
END CASE;
END read;
PROCEDURE read(l: INOUT line; value: OUT std_logic_vector) IS
BEGIN
FOR i IN value'HIGH DOWNTO value'LOW LOOP
IF l'LENGTH > 0 THEN
read(l,value(i));
ELSE
ASSERT false REPORT "Not enough values for std_logic_vector in file"
SEVERITY error;
RETURN;
END IF;
END LOOP;
END read;
procedure Grow_line(L : inout LINE; incr : in integer)
is
variable old_L : LINE := L;
variable bfp: integer; -- Blank fill pointer.
begin
assert incr > 0
report "Textio: Grow_line called with zero increment."
severity error;
if L = null then
bfp := 0;
L := new string(1 to incr);
else
bfp := old_L'high;
L := new string(old_L'low to old_L'high + incr);
L(old_L'low to old_L'high) := old_L.all;
Deallocate(old_L);
end if;
for i in 1 to incr loop
L(bfp + i) := ' ';
end loop;
end;
PROCEDURE write(l: INOUT line; value: IN std_logic_vector;
JUSTIFIED: IN SIDE := right;
FIELD: IN WIDTH := 0) IS
variable fw: integer := VALUE'length;
variable bp: integer;
variable offset: integer := 0;
alias normal : std_logic_vector(0 to value'length - 1) is value;
begin
if L /= null then
bp := L'high + 1;
else bp := 1;
end if;
if FIELD > VALUE'length then
fw := FIELD;
if JUSTIFIED = right then
offset := fw - VALUE'length;
end if;
end if;
Grow_line(L, fw);
for i in normal'range loop
L(bp + i + offset) := character'val(
std_logic'pos(normal(i)) + character'pos('0'));
end loop;
end;
END util_1164;
lib/models/memory/sdram/mt48lc64m4a2/vec_gen.vhd
+372
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-------------------------------------------------------------------------------
-- --
-- This is a data generator for the testbench for Micron's Synchronous --
-- DRAM. This generator reads a text file line-by-line and generates --
-- a file of test vectors that is then read by the testbench and --
-- applied to the part. --
-- --
-- This VHDL program creates a text file of test vectors that is used by the --
-- test bench. Place your commands in a file (a copy of VEC_GEN.VHD) and run --
-- VEC_GEN.VHD in your VHDL simulator (make sure you have compiled this --
-- package prior to running the program VEC_GEN.VHD). This will produce the --
-- vectors that are required to run the included testbench. Change the name --
-- of the vector file to save your vectors in separate files. The default --
-- file name for the output vectors generated from this pacakage is --
-- "test.txt." --
-- --
-- Now compile and run the testbench program embedtb.vhd. The testbench uses --
-- the default test.txt as input vectors. --
-- --
-- --
-- Copyright 1997 Micron Technology, Inc. --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.io_utils.all;
PACKAGE generate_vectors IS
CONSTANT set_up : TIME;
CONSTANT hold : TIME;
CONSTANT cycle_start : TIME;
SIGNAL cycle : INTEGER := 0;
SIGNAL sim_time : TIME := 0 ns;
FILE output_file:TEXT IS OUT "test.txt";
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0);
first_data : IN INTEGER; dqm : IN BIT; cke : IN BIT);
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT; cke : IN BIT);
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT);
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT; cke : IN BIT);
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT; cs : IN BIT);
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT);
PROCEDURE auto_refresh;
PROCEDURE next_cycle(SIGNAL clk : IN BIT);
PROCEDURE load_array(load : IN BIT);
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT);
PROCEDURE unload_array(row_start : IN INTEGER; row_end : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0));
END generate_vectors;
PACKAGE BODY generate_vectors IS
CONSTANT set_up : TIME := 3 ns;
CONSTANT hold : TIME := 1 ns;
CONSTANT cycle_start : TIME := 0 ns;
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); first_data : IN INTEGER;
dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, first_data, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, row_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT; cs : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, cs, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE auto_refresh IS
VARIABLE l : LINE;
VARIABLE dqm : BIT := '0';
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE next_cycle(SIGNAL clk : IN BIT) IS
BEGIN
WAIT UNTIL clk = '1';
END;
PROCEDURE load_array(load : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT := '0';
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 1, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE unload_array(row_start : IN INTEGER; row_end : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0)) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT := '0';
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 1, right, 4); --unload
--write(l, row_start, right, 6); --row_address_start
--write(l, row_end, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT := '0';
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, op_code, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
END generate_vectors;
lib/models/memory/sdram/mt48lc64m4a2/vector.do
+4
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@@ -0,0 +1,4 @@
vcom vec_gen.vhd
vcom ed_comnd.vhd
vsim vector_generate
run -all
lib/models/memory/sdram/mt48lc64m4a2/wave.do
+31
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@@ -0,0 +1,31 @@
onerror {resume}
add wave -logic -height 20 /tb/u1/clk
add wave -logic -height 20 /tb/u1/cke
add wave -logic -height 20 /tb/u1/cs_n
add wave -logic -height 20 /tb/u1/ras_n
add wave -logic -height 20 /tb/u1/cas_n
add wave -logic -height 20 /tb/u1/we_n
add wave -logic -unsigned -height 20 /tb/u1/addr
add wave -logic -height 20 /tb/u1/ba
add wave -logic -unsigned -height 20 /tb/u1/dq
add wave -logic -height 20 /tb/u1/dqm
add wave -literal -ascii -height 20 /tb/u1/operation
add wave -logic -unsigned -height 20 /tb/u1/mode_reg
add wave -logic -height 20 /tb/u1/active_enable
add wave -logic -height 20 /tb/u1/aref_enable
add wave -logic -height 20 /tb/u1/burst_term
add wave -logic -height 20 /tb/u1/mode_reg_enable
add wave -logic -height 20 /tb/u1/prech_enable
add wave -logic -height 20 /tb/u1/read_enable
add wave -logic -height 20 /tb/u1/write_enable
add wave -logic -height 20 /tb/u1/burst_length_1
add wave -logic -height 20 /tb/u1/burst_length_2
add wave -logic -height 20 /tb/u1/burst_length_4
add wave -logic -height 20 /tb/u1/burst_length_8
add wave -logic -height 20 /tb/u1/cas_latency_2
add wave -logic -height 20 /tb/u1/cas_latency_3
add wave -logic -height 20 /tb/u1/pre_chk
add wave -logic -height 20 /tb/u1/act_chk
add wave -logic -height 20 /tb/u1/bank_chk
add wave -logic -unsigned -height 20 /tb/u1/row_chk
add wave -logic -unsigned -height 20 /tb/u1/col_chk