- added models

git-svn-id: http://moon:8086/svn/vhdl/trunk@1290 cc03376c-175c-47c8-b038-4cd826a8556b

lib/models/memory/sdram/mt48lc16m16a2/test.vhd

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+LIBRARY ieee;
+    USE ieee.std_logic_1164.ALL;
+    USE ieee.std_logic_arith.ALL;
+LIBRARY STD;
+    USE std.textio.ALL;
+LIBRARY work;
+    USE work.mti_pkg.ALL;
+
+ENTITY tb IS
+END tb;
+
+
+ARCHITECTURE test OF tb IS
+    CONSTANT addr_bits     : INTEGER := 13;
+    CONSTANT data_bits     : INTEGER := 16;
+    CONSTANT clk_start     : time    :=  5 ns;
+    CONSTANT clk_period    : time    := 10 ns;
+    CONSTANT continue_time : time    := 10 ns;
+
+    COMPONENT mt48lc16m16a2
+        PORT (
+            Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+            Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+            Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+            Clk   : IN    STD_LOGIC := '0';
+            Cke   : IN    STD_LOGIC := '1';
+            Cs_n  : IN    STD_LOGIC := '1';
+            Cas_n : IN    STD_LOGIC := '1';
+            Ras_n : IN    STD_LOGIC := '1';
+            We_n  : IN    STD_LOGIC := '1';
+            Dqm   : IN    STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
+            Load  : IN    STD_LOGIC := '0';     -- FOR LOADING MEMORY ARRAY
+            Dump  : IN    STD_LOGIC := '0'      -- FOR DUMPING MEMORY ARRAY
+        ); 
+    END COMPONENT;
+  
+    FOR ALL : mt48lc16m16a2 USE ENTITY work.mt48lc16m16a2 (behave);
+
+    SIGNAL pDq       : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
+    SIGNAL pAddr     : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+    SIGNAL pBa       : STD_LOGIC_VECTOR (1 DOWNTO 0);
+    SIGNAL pClk      : STD_LOGIC;
+    SIGNAL pCke      : STD_LOGIC;
+    SIGNAL pCs       : STD_LOGIC;
+    SIGNAL pCas      : STD_LOGIC;
+    SIGNAL pRas      : STD_LOGIC;
+    SIGNAL pWe       : STD_LOGIC;
+    SIGNAL pDqm      : STD_LOGIC_VECTOR (1 DOWNTO 0);
+    SIGNAL pLoad     : STD_LOGIC;
+    SIGNAL pDump     : STD_LOGIC;
+    SIGNAL stim_done : boolean := false;
+    SIGNAL clk_done : boolean := false;
+
+
+BEGIN
+    u1: mt48lc16m16a2
+        PORT MAP(
+            Dq      => pDq,
+            Addr    => pAddr,
+            Ba      => pBa,
+            Clk     => pClk,
+            Cke     => pCke,
+            Cs_n    => pCs,
+            Ras_n   => pRas,
+            Cas_n   => pCas,
+            We_n    => pWe,
+            Dqm     => pDqm,
+            Load    => pLoad,
+            Dump    => pDump
+        );
+
+    stimulator : PROCESS
+        FILE stim_file:text IS IN "test.txt";
+        VARIABLE l : line;
+        VARIABLE time_var     : TIME;
+        VARIABLE pCke_var     : bit;
+        VARIABLE pCs_var      : bit;
+        VARIABLE pRas_var     : bit;
+        VARIABLE PCas_var     : bit;
+        VARIABLE pWe_var      : bit;
+        VARIABLE pDqm_var     : bit_vector (1 DOWNTO 0);
+        VARIABLE pBa_var      : bit_vector (1 DOWNTO 0);
+        VARIABLE pAddr_var    : INTEGER;
+        VARIABLE pDq_var      : INTEGER;            -- -100 is converted to hi-Z state
+        VARIABLE PLoad_var    : bit;
+        VARIABLE pDump_var    : bit;
+        VARIABLE pMa_var_vect : STD_LOGIC_VECTOR(addr_bits - 1 DOWNTO 0);
+        CONSTANT HiZ          : STD_LOGIC_VECTOR(data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+        BEGIN
+        WHILE not ENDFILE(stim_file) LOOP
+            readline(stim_file,l);
+            IF l'length > 0 THEN
+                read(l, time_var);
+                read(l, pCke_var);
+                read(l, pCs_var);
+                read(l, pRas_var);
+                read(l, pCas_var);
+                read(l, pWe_var);
+                read(l, pDqm_var);
+                read(l, pBa_var);
+                read(l, pAddr_var);
+                read(l, pDq_var);
+                read(l, PLoad_var);
+                read(l, pDump_var);
+                IF now > time_var THEN
+                    ASSERT false 
+                        REPORT "Detected a time in the stim file that is in the past"
+                        SEVERITY error;
+                ELSE
+                    WAIT FOR time_var-now;
+                    pCke <= TO_StdLogic(pCke_var);
+                    pCs  <= TO_StdLogic(pCs_var);
+                    pRas <= TO_StdLogic(pRas_var);
+                    pCas <= TO_StdLogic(pCas_var);
+                    pWe  <= TO_StdLogic(pWe_var);
+                    pDqm <= TO_StdLogicVector(pDqm_var);
+                    pBa  <= TO_StdLogicVector(pBa_var);
+                    pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
+                    pAddr <= pMa_var_vect;
+                    IF pDq_var = -100 THEN
+                        pDq <= HiZ;
+                    ELSE  
+                        pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);            
+                    END IF;
+                    pLoad <= TO_StdLogic(PLoad_var);
+                    pDump <= TO_StdLogic(pDump_var);
+                END IF;
+            END IF;
+        END LOOP;
+        ASSERT false
+            REPORT "End of Stimulation File Detected!"
+            SEVERITY note;
+        stim_done <= true;
+        WAIT;
+    END PROCESS;
+
+    clock : PROCESS
+    VARIABLE done_time : time;
+    BEGIN
+        pclk <= '0';
+        WAIT for clk_start;
+            WHILE not stim_done loop
+                pclk <= '1';
+                WAIT for clk_period/2;
+                pclk <= '0';
+                WAIT for clk_period/2;
+            END LOOP;
+            done_time := now+continue_time;
+            WHILE now < done_time LOOP            --one last clock to finish last command
+                pclk <= '1';
+                WAIT for clk_period/2;
+                pclk <= '0';
+                WAIT for clk_period/2;
+            END LOOP;
+            ASSERT false 
+                REPORT "Suspending clock activity"
+                SEVERITY note;
+            clk_done <= true;
+            WAIT;
+    END PROCESS;
+
+END test;
+
+