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git-svn-id: http://moon:8086/svn/vhdl/trunk@1290 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-06-10 19:27:35 +00:00
parent 8eb6b3ff9e
commit 2edaa4d7cb
217 changed files with 152127 additions and 0 deletions
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lib/models/memory/sdram/mt48lc16m16a2/dumpdata.txt
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# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)
# BA ROWS COLS DQ
# -- ------------- --------- ----------------
00 0000000000000 000000000 0000000001100100
00 0000000000000 000000001 0000000001100101
00 0000000000000 000000010 0000000001100110
00 0000000000000 000000011 0000000001100111
00 0000000000000 000000100 0000000001101000
00 0000000000000 000000101 0000000001101001
00 0000000000000 000000110 0000000001101010
00 0000000000000 000000111 0000000001101011
00 0000000000000 000001000 0011111111111110
00 0000000000000 000001001 0011111111111110
00 0000000000000 000001010 0011111111111110
01 0000000000000 000000000 0000000011001000
01 0000000000000 000000001 0000000011001001
01 0000000000000 000000010 0000000011001010
01 0000000000000 000000011 0000000011001011
01 0000000000000 000000100 0000000011001100
01 0000000000000 000000101 0000000011001101
01 0000000000000 000000110 0000000011001110
01 0000000000000 000000111 0000000011001111
01 0000000000000 000001000 0111111111111101
01 0000000000000 000001001 0111111111111101
01 0000000000000 000001010 0111111111111101
10 0000000000000 000000000 0000000100101100
10 0000000000000 000000001 0000000100101101
10 0000000000000 000000010 0000000100101110
10 0000000000000 000000011 0000000100101111
10 0000000000000 000000100 0000000100110000
10 0000000000000 000000101 0000000100110001
10 0000000000000 000000110 0000000100110010
10 0000000000000 000000111 0000000100110011
10 0000000000000 000001000 1011111111111011
10 0000000000000 000001001 1011111111111011
10 0000000000000 000001010 1011111111111011
11 0000000000000 000000000 0000000110010000
11 0000000000000 000000001 0000000110010001
11 0000000000000 000000010 0000000110010010
11 0000000000000 000000011 0000000110010011
11 0000000000000 000000100 0000000110010100
11 0000000000000 000000101 0000000110010101
11 0000000000000 000000110 0000000110010110
11 0000000000000 000000111 0000000110010111
11 0000000000000 000001000 1111111111110111
11 0000000000000 000001001 1111111111110111
11 0000000000000 000001010 1111111111110111
lib/models/memory/sdram/mt48lc16m16a2/ed_comnd.vhd
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---------------------------------------------------------------------------------
--COMMAND FORMAT --
-- --
-- write(column address(integer), bank(bit_vector), first data(integer), dqm(bit), cke(bit));--
-- read(column address(integer), bank(bit_vector), dqm(bit), cke(bit)); --
-- active(row address(integer), bank(bit_vector), data bus (integer), dqm(bit), cke(bit));--
-- precharge(bank(bit_vector), address (integer), data bus(integer), dqm(bit), cke(bit)); --
-- nop(data bus(integer), dqm(bit), cke(bit), cs(bit)); --
-- burst_term(data bus(integer), dqm(bit_vector), cke(bit)); --
-- load_array('1'); --
-- load_mode_reg(register(integer), cke(bit)); --
-- next_cycle(clk); This is used after every command(incl. nop) to clock --
-- at the correct clock frequency entered in the clock --
-- period constant below --
-- unload_array(row_start(integer), row_end(integer), bank(bit_vector)) --
-- load_mode_reg(op_code(integer)) --
-- --
---------------------------------------------------------------------------------
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.generate_vectors.all;
ENTITY vector_generate IS
END vector_generate;
ARCHITECTURE vector_generate OF vector_generate IS
SIGNAL stim_done : BOOLEAN := FALSE;
SIGNAL clk : BIT := '0';
CONSTANT clk_start : time := 15 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT Z : INTEGER := -100;
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1' AND clk'EVENT;
--------------------ENTER COMMANDS BELOW THIS LINE-----------------------------
--******************DO NOT USE -100 FOR A DQ VALUE*************************----
--*******************Z WILL PLACE HI-Z ON THE BUS**************************----
--*******USE next_cycle(clk) FOR ADVANCING TO NEXT CLOCK CYCLE*************----
nop(Z, "00", '1', '1'); --Always begin with one nop when using Micron's testbench
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
load_array;
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
precharge("00", 1024, Z, "00", '1');
FOR i IN 1 to 2 LOOP
next_cycle(clk);
nop(Z, "00", '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, "00", '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, "00", '1', '1');
END LOOP;
next_cycle(clk);
load_mode_reg(51, '1'); -- 19 / 35 / 51 -> lat=3,bl=8,mode=seq
next_cycle(clk);
nop(Z, "00", '1', '1');
-- Write Section
next_cycle(clk);
active(0, "00", Z, "00", '1'); -- Activate Bank 0
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk); -- Write Bank 0
write(0, "00", 100, "00", '1');
next_cycle(clk);
nop(101, "00", '1', '1');
next_cycle(clk);
active(0, "01", 102, "00", '1'); -- Activate Bank 1
next_cycle(clk);
nop(103, "00", '1', '1');
next_cycle(clk);
nop(104, "00", '1', '1');
next_cycle(clk);
nop(105, "00", '1', '1');
next_cycle(clk);
nop(106, "00", '1', '1');
next_cycle(clk);
nop(107, "00", '1', '1');
next_cycle(clk);
write(0, "01", 200, "00", '1'); -- Write Bank 1
next_cycle(clk);
precharge("00", 0, 201, "00", '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", 202, "00", '1'); -- Activate Bank 2
next_cycle(clk);
nop(203, "00", '1', '1');
next_cycle(clk);
nop(204, "00", '1', '1');
next_cycle(clk);
nop(205, "00", '1', '1');
next_cycle(clk);
nop(206, "00", '1', '1');
next_cycle(clk);
nop(207, "00", '1', '1');
next_cycle(clk);
write(0, "10", 300, "00", '1'); -- Write Bank 2
next_cycle(clk);
precharge("01", 0, 301, "00", '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", 302, "00", '1'); -- Activate Bank 3
next_cycle(clk);
nop(303, "00", '1', '1');
next_cycle(clk);
nop(304, "00", '1', '1');
next_cycle(clk);
nop(305, "00", '1', '1');
next_cycle(clk);
nop(306, "00", '1', '1');
next_cycle(clk);
nop(307, "00", '1', '1');
next_cycle(clk);
write(0, "11", 400, "00", '1'); -- Write Bank 3
next_cycle(clk);
precharge("10", 0, 401, "00", '1'); -- Precharge Bank 2
next_cycle(clk);
active(0, "00", 402, "00", '1'); -- Activate Bank 0
next_cycle(clk);
nop(403, "00", '1', '1');
next_cycle(clk);
nop(404, "00", '1', '1');
next_cycle(clk);
nop(405, "00", '1', '1');
next_cycle(clk);
nop(406, "00", '1', '1');
next_cycle(clk);
nop(407, "00", '1', '1');
-- Read Section
next_cycle(clk);
read(0, "00", "00", '1'); -- Read Bank 0
next_cycle(clk);
precharge("11", 0, Z, "00", '1'); -- Precharge Bank 3
next_cycle(clk);
active(0, "01", Z, "00", '1'); -- Activate Bank 1
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
read(0, "01", "00", '1'); -- Read Bank 1
next_cycle(clk);
precharge("00", 0, Z, "00", '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", Z, "00", '1'); -- Activate Bank 2
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
read(0, "10", "00", '1'); -- Read Bank 2
next_cycle(clk);
precharge("01", 0, Z, "00", '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", Z, "00", '1'); -- Activate Bank 3
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
read(0, "11", "00", '1'); -- Read Bank 3
next_cycle(clk);
precharge("10", 0, Z, "00", '1'); -- Precharge Bank 2
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
precharge("11", 0, Z, "00", '1'); -- Precharge Bank 3
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
unload_array;
next_cycle(clk);
nop(Z, "00", '1', '1');
stim_done <= TRUE; --always include this line at the end of your stimulus
-------------------------------------------------------------------------------
--*************************************************************************----
END PROCESS;
clock:
PROCESS
VARIABLE done_time : time;
VARIABLE cycle_var : integer := 0;
BEGIN
cycle <= 0;
clk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
clk <= '1';
cycle <= cycle_var;
WAIT for clk_period/2;
cycle_var := cycle_var + 1;
clk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT (FALSE)
REPORT "Test Vectors Generated"
SEVERITY note;
WAIT;
END PROCESS;
END;
lib/models/memory/sdram/mt48lc16m16a2/loaddata.txt
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# Micron Technology, Inc. (FILE LOAD / MEMORY INITIALIZE)
# BA ROWS COLS DQ
# -- ------------- --------- ----------------
00 0000000000000 000000000 0011111111111110
00 0000000000000 000000001 0011111111111110
00 0000000000000 000000010 0011111111111110
00 0000000000000 000000011 0011111111111110
00 0000000000000 000000100 0011111111111110
00 0000000000000 000000101 0011111111111110
00 0000000000000 000000110 0011111111111110
00 0000000000000 000000111 0011111111111110
00 0000000000000 000001000 0011111111111110
00 0000000000000 000001001 0011111111111110
00 0000000000000 000001010 0011111111111110
01 0000000000000 000000000 0111111111111101
01 0000000000000 000000001 0111111111111101
01 0000000000000 000000010 0111111111111101
01 0000000000000 000000011 0111111111111101
01 0000000000000 000000100 0111111111111101
01 0000000000000 000000101 0111111111111101
01 0000000000000 000000110 0111111111111101
01 0000000000000 000000111 0111111111111101
01 0000000000000 000001000 0111111111111101
01 0000000000000 000001001 0111111111111101
01 0000000000000 000001010 0111111111111101
10 0000000000000 000000000 1011111111111011
10 0000000000000 000000001 1011111111111011
10 0000000000000 000000010 1011111111111011
10 0000000000000 000000011 1011111111111011
10 0000000000000 000000100 1011111111111011
10 0000000000000 000000101 1011111111111011
10 0000000000000 000000110 1011111111111011
10 0000000000000 000000111 1011111111111011
10 0000000000000 000001000 1011111111111011
10 0000000000000 000001001 1011111111111011
10 0000000000000 000001010 1011111111111011
11 0000000000000 000000000 1111111111110111
11 0000000000000 000000001 1111111111110111
11 0000000000000 000000010 1111111111110111
11 0000000000000 000000011 1111111111110111
11 0000000000000 000000100 1111111111110111
11 0000000000000 000000101 1111111111110111
11 0000000000000 000000110 1111111111110111
11 0000000000000 000000111 1111111111110111
11 0000000000000 000001000 1111111111110111
11 0000000000000 000001001 1111111111110111
11 0000000000000 000001010 1111111111110111
lib/models/memory/sdram/mt48lc16m16a2/mt48lc16m16a2.vhd
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lib/models/memory/sdram/mt48lc16m16a2/mti_pkg.vhd
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--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE mti_pkg IS
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to STD_LOGIC
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
BEGIN
CASE s IS
WHEN '0' => RETURN ('0');
WHEN '1' => RETURN ('1');
WHEN OTHERS => RETURN ('0');
END CASE;
END;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver INTEGER to BIT_VECTOR
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN
outputlen := 32;
offset := output'LENGTH - 32;
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0';
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1';
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH;
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0';
ELSE
output(output'HIGH-j-offset) := '1';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0';
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1';
ELSE
output(output'HIGH-j-offset) := '0';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1';
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
lib/models/memory/sdram/mt48lc16m16a2/test.do
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# Macro for running Micron SDRAM VHDL model
#
# Compile Package Library (Require)
vcom mti_pkg.vhd
# Compile Micron Test Vector Generator (optional or use your own test)
vcom vec_gen.vhd
vcom ed_comnd.vhd
vsim vector_generate
run -all
# Compile Micron SDRAM
vcom mt48lc16m16a2.vhd
# Compile Micron Testbench (optional or use your own test bench)
vcom test.vhd
# Simulate Test
vsim tb
# Display waveform
onerror {resume}
add wave -logic /tb/u1/clk
add wave -logic /tb/u1/cke
add wave -logic /tb/u1/cs_n
add wave -logic /tb/u1/ras_n
add wave -logic /tb/u1/cas_n
add wave -logic /tb/u1/we_n
add wave -literal -decimal /tb/u1/addr
add wave -literal -unsigned /tb/u1/ba
add wave -literal -decimal /tb/u1/dq
add wave -literal /tb/u1/dqm
add wave -literal /tb/u1/operation
add wave -literal -decimal /tb/u1/mode_reg
add wave -logic /tb/u1/active_enable
add wave -logic /tb/u1/aref_enable
add wave -logic /tb/u1/burst_term
add wave -logic /tb/u1/mode_reg_enable
add wave -logic /tb/u1/prech_enable
add wave -logic /tb/u1/read_enable
add wave -logic /tb/u1/write_enable
add wave -logic /tb/u1/burst_length_1
add wave -logic /tb/u1/burst_length_2
add wave -logic /tb/u1/burst_length_4
add wave -logic /tb/u1/burst_length_8
add wave -logic /tb/u1/cas_latency_2
add wave -logic /tb/u1/cas_latency_3
add wave -literal /tb/u1/pre_chk
add wave -literal /tb/u1/act_chk
add wave -literal /tb/u1/bank_chk
add wave -literal -decimal /tb/u1/row_chk
add wave -literal -decimal /tb/u1/col_chk
add wave -logic /tb/u1/dq_in_chk
add wave -logic /tb/u1/dq_out_chk
# Run all test
run -all
lib/models/memory/sdram/mt48lc16m16a2/test.txt
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0 ns 1 1 1 1 1 00 00 0 -100 0 0
22 ns 1 1 1 1 1 00 00 0 -100 0 0
32 ns 1 0 1 1 1 00 00 0 -100 1 0
42 ns 1 1 1 1 1 00 00 0 -100 0 0
52 ns 1 1 1 1 1 00 00 0 -100 0 0
62 ns 1 1 1 1 1 00 00 0 -100 0 0
72 ns 1 1 1 1 1 00 00 0 -100 0 0
82 ns 1 0 0 1 0 00 00 1024 -100 0 0
92 ns 1 1 1 1 1 00 00 0 -100 0 0
102 ns 1 1 1 1 1 00 00 0 -100 0 0
112 ns 1 0 0 0 1 00 00 0 -100 0 0
122 ns 1 1 1 1 1 00 00 0 -100 0 0
132 ns 1 1 1 1 1 00 00 0 -100 0 0
142 ns 1 1 1 1 1 00 00 0 -100 0 0
152 ns 1 1 1 1 1 00 00 0 -100 0 0
162 ns 1 1 1 1 1 00 00 0 -100 0 0
172 ns 1 1 1 1 1 00 00 0 -100 0 0
182 ns 1 1 1 1 1 00 00 0 -100 0 0
192 ns 1 1 1 1 1 00 00 0 -100 0 0
202 ns 1 0 0 0 1 00 00 0 -100 0 0
212 ns 1 1 1 1 1 00 00 0 -100 0 0
222 ns 1 1 1 1 1 00 00 0 -100 0 0
232 ns 1 1 1 1 1 00 00 0 -100 0 0
242 ns 1 1 1 1 1 00 00 0 -100 0 0
252 ns 1 1 1 1 1 00 00 0 -100 0 0
262 ns 1 1 1 1 1 00 00 0 -100 0 0
272 ns 1 1 1 1 1 00 00 0 -100 0 0
282 ns 1 1 1 1 1 00 00 0 -100 0 0
292 ns 1 0 0 0 0 00 00 51 -100 0 0
302 ns 1 1 1 1 1 00 00 0 -100 0 0
312 ns 1 0 0 1 1 00 00 0 -100 0 0
322 ns 1 1 1 1 1 00 00 0 -100 0 0
332 ns 1 0 1 0 0 00 00 0 100 0 0
342 ns 1 1 1 1 1 00 00 0 101 0 0
352 ns 1 0 0 1 1 00 01 0 102 0 0
362 ns 1 1 1 1 1 00 00 0 103 0 0
372 ns 1 1 1 1 1 00 00 0 104 0 0
382 ns 1 1 1 1 1 00 00 0 105 0 0
392 ns 1 1 1 1 1 00 00 0 106 0 0
402 ns 1 1 1 1 1 00 00 0 107 0 0
412 ns 1 0 1 0 0 00 01 0 200 0 0
422 ns 1 0 0 1 0 00 00 0 201 0 0
432 ns 1 0 0 1 1 00 10 0 202 0 0
442 ns 1 1 1 1 1 00 00 0 203 0 0
452 ns 1 1 1 1 1 00 00 0 204 0 0
462 ns 1 1 1 1 1 00 00 0 205 0 0
472 ns 1 1 1 1 1 00 00 0 206 0 0
482 ns 1 1 1 1 1 00 00 0 207 0 0
492 ns 1 0 1 0 0 00 10 0 300 0 0
502 ns 1 0 0 1 0 00 01 0 301 0 0
512 ns 1 0 0 1 1 00 11 0 302 0 0
522 ns 1 1 1 1 1 00 00 0 303 0 0
532 ns 1 1 1 1 1 00 00 0 304 0 0
542 ns 1 1 1 1 1 00 00 0 305 0 0
552 ns 1 1 1 1 1 00 00 0 306 0 0
562 ns 1 1 1 1 1 00 00 0 307 0 0
572 ns 1 0 1 0 0 00 11 0 400 0 0
582 ns 1 0 0 1 0 00 10 0 401 0 0
592 ns 1 0 0 1 1 00 00 0 402 0 0
602 ns 1 1 1 1 1 00 00 0 403 0 0
612 ns 1 1 1 1 1 00 00 0 404 0 0
622 ns 1 1 1 1 1 00 00 0 405 0 0
632 ns 1 1 1 1 1 00 00 0 406 0 0
642 ns 1 1 1 1 1 00 00 0 407 0 0
652 ns 1 0 1 0 1 00 00 0 -100 0 0
662 ns 1 0 0 1 0 00 11 0 -100 0 0
672 ns 1 0 0 1 1 00 01 0 -100 0 0
682 ns 1 1 1 1 1 00 00 0 -100 0 0
692 ns 1 1 1 1 1 00 00 0 -100 0 0
702 ns 1 1 1 1 1 00 00 0 -100 0 0
712 ns 1 1 1 1 1 00 00 0 -100 0 0
722 ns 1 1 1 1 1 00 00 0 -100 0 0
732 ns 1 0 1 0 1 00 01 0 -100 0 0
742 ns 1 0 0 1 0 00 00 0 -100 0 0
752 ns 1 0 0 1 1 00 10 0 -100 0 0
762 ns 1 1 1 1 1 00 00 0 -100 0 0
772 ns 1 1 1 1 1 00 00 0 -100 0 0
782 ns 1 1 1 1 1 00 00 0 -100 0 0
792 ns 1 1 1 1 1 00 00 0 -100 0 0
802 ns 1 1 1 1 1 00 00 0 -100 0 0
812 ns 1 0 1 0 1 00 10 0 -100 0 0
822 ns 1 0 0 1 0 00 01 0 -100 0 0
832 ns 1 0 0 1 1 00 11 0 -100 0 0
842 ns 1 1 1 1 1 00 00 0 -100 0 0
852 ns 1 1 1 1 1 00 00 0 -100 0 0
862 ns 1 1 1 1 1 00 00 0 -100 0 0
872 ns 1 1 1 1 1 00 00 0 -100 0 0
882 ns 1 1 1 1 1 00 00 0 -100 0 0
892 ns 1 0 1 0 1 00 11 0 -100 0 0
902 ns 1 0 0 1 0 00 10 0 -100 0 0
912 ns 1 1 1 1 1 00 00 0 -100 0 0
922 ns 1 1 1 1 1 00 00 0 -100 0 0
932 ns 1 1 1 1 1 00 00 0 -100 0 0
942 ns 1 1 1 1 1 00 00 0 -100 0 0
952 ns 1 1 1 1 1 00 00 0 -100 0 0
962 ns 1 1 1 1 1 00 00 0 -100 0 0
972 ns 1 0 0 1 0 00 11 0 -100 0 0
982 ns 1 1 1 1 1 00 00 0 -100 0 0
992 ns 1 1 1 1 1 00 00 0 -100 0 0
1002 ns 1 0 1 1 1 00 00 0 -100 0 1
1012 ns 1 1 1 1 1 00 00 0 -100 0 0
lib/models/memory/sdram/mt48lc16m16a2/test.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
LIBRARY STD;
USE std.textio.ALL;
LIBRARY work;
USE work.mti_pkg.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE test OF tb IS
CONSTANT addr_bits : INTEGER := 13;
CONSTANT data_bits : INTEGER := 16;
CONSTANT clk_start : time := 5 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT continue_time : time := 10 ns;
COMPONENT mt48lc16m16a2
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
Load : IN STD_LOGIC := '0'; -- FOR LOADING MEMORY ARRAY
Dump : IN STD_LOGIC := '0' -- FOR DUMPING MEMORY ARRAY
);
END COMPONENT;
FOR ALL : mt48lc16m16a2 USE ENTITY work.mt48lc16m16a2 (behave);
SIGNAL pDq : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
SIGNAL pAddr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
SIGNAL pBa : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pClk : STD_LOGIC;
SIGNAL pCke : STD_LOGIC;
SIGNAL pCs : STD_LOGIC;
SIGNAL pCas : STD_LOGIC;
SIGNAL pRas : STD_LOGIC;
SIGNAL pWe : STD_LOGIC;
SIGNAL pDqm : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pLoad : STD_LOGIC;
SIGNAL pDump : STD_LOGIC;
SIGNAL stim_done : boolean := false;
SIGNAL clk_done : boolean := false;
BEGIN
u1: mt48lc16m16a2
PORT MAP(
Dq => pDq,
Addr => pAddr,
Ba => pBa,
Clk => pClk,
Cke => pCke,
Cs_n => pCs,
Ras_n => pRas,
Cas_n => pCas,
We_n => pWe,
Dqm => pDqm,
Load => pLoad,
Dump => pDump
);
stimulator : PROCESS
FILE stim_file:text IS IN "test.txt";
VARIABLE l : line;
VARIABLE time_var : TIME;
VARIABLE pCke_var : bit;
VARIABLE pCs_var : bit;
VARIABLE pRas_var : bit;
VARIABLE PCas_var : bit;
VARIABLE pWe_var : bit;
VARIABLE pDqm_var : bit_vector (1 DOWNTO 0);
VARIABLE pBa_var : bit_vector (1 DOWNTO 0);
VARIABLE pAddr_var : INTEGER;
VARIABLE pDq_var : INTEGER; -- -100 is converted to hi-Z state
VARIABLE PLoad_var : bit;
VARIABLE pDump_var : bit;
VARIABLE pMa_var_vect : STD_LOGIC_VECTOR(addr_bits - 1 DOWNTO 0);
CONSTANT HiZ : STD_LOGIC_VECTOR(data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
BEGIN
WHILE not ENDFILE(stim_file) LOOP
readline(stim_file,l);
IF l'length > 0 THEN
read(l, time_var);
read(l, pCke_var);
read(l, pCs_var);
read(l, pRas_var);
read(l, pCas_var);
read(l, pWe_var);
read(l, pDqm_var);
read(l, pBa_var);
read(l, pAddr_var);
read(l, pDq_var);
read(l, PLoad_var);
read(l, pDump_var);
IF now > time_var THEN
ASSERT false
REPORT "Detected a time in the stim file that is in the past"
SEVERITY error;
ELSE
WAIT FOR time_var-now;
pCke <= TO_StdLogic(pCke_var);
pCs <= TO_StdLogic(pCs_var);
pRas <= TO_StdLogic(pRas_var);
pCas <= TO_StdLogic(pCas_var);
pWe <= TO_StdLogic(pWe_var);
pDqm <= TO_StdLogicVector(pDqm_var);
pBa <= TO_StdLogicVector(pBa_var);
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
pLoad <= TO_StdLogic(PLoad_var);
pDump <= TO_StdLogic(pDump_var);
END IF;
END IF;
END LOOP;
ASSERT false
REPORT "End of Stimulation File Detected!"
SEVERITY note;
stim_done <= true;
WAIT;
END PROCESS;
clock : PROCESS
VARIABLE done_time : time;
BEGIN
pclk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
done_time := now+continue_time;
WHILE now < done_time LOOP --one last clock to finish last command
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT false
REPORT "Suspending clock activity"
SEVERITY note;
clk_done <= true;
WAIT;
END PROCESS;
END test;
lib/models/memory/sdram/mt48lc16m16a2/vec_gen.vhd
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-------------------------------------------------------------------------------
-- --
-- This is a data generator for the testbench for Micron's Synchronous --
-- DRAM. This generator reads a text file line-by-line and generates --
-- a file of test vectors that is then read by the testbench and --
-- applied to the part. --
-- --
-- This VHDL program creates a text file of test vectors that is used by the --
-- test bench. Place your commands in a file (a copy of VEC_GEN.VHD) and run --
-- VEC_GEN.VHD in your VHDL simulator (make sure you have compiled this --
-- package prior to running the program VEC_GEN.VHD). This will produce the --
-- vectors that are required to run the included testbench. Change the name --
-- of the vector file to save your vectors in separate files. The default --
-- file name for the output vectors generated from this pacakage is --
-- "test.txt." --
-- --
-- Now compile and run the testbench program embedtb.vhd. The testbench uses --
-- the default test.txt as input vectors. --
-- --
-- --
-- Copyright 1997 Micron Technology, Inc. --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE std.textio.all;
PACKAGE generate_vectors IS
CONSTANT set_up : TIME;
CONSTANT hold : TIME;
CONSTANT cycle_start : TIME;
SIGNAL cycle : INTEGER := 0;
SIGNAL sim_time : TIME := 0 ns;
FILE output_file:TEXT IS OUT "test.txt";
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0);
first_data : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT; cs : IN BIT);
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE auto_refresh;
PROCEDURE next_cycle(SIGNAL clk : IN BIT);
PROCEDURE load_array;
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT);
PROCEDURE unload_array;
END generate_vectors;
PACKAGE BODY generate_vectors IS
CONSTANT set_up : TIME := 3 ns;
CONSTANT hold : TIME := 1 ns;
CONSTANT cycle_start : TIME := 0 ns;
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); first_data : IN INTEGER;
dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, first_data, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, row_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT; cs : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, cs, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE auto_refresh IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE next_cycle(SIGNAL clk : IN BIT) IS
BEGIN
WAIT UNTIL clk = '1';
END;
PROCEDURE load_array IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 1, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE unload_array IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 1, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, op_code, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
END generate_vectors;
lib/models/memory/sdram/mt48lc16m16a2/wave.do
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@@ -0,0 +1,33 @@
onerror {resume}
add wave -logic /tb/u1/clk
add wave -logic /tb/u1/cke
add wave -logic /tb/u1/cs_n
add wave -logic /tb/u1/ras_n
add wave -logic /tb/u1/cas_n
add wave -logic /tb/u1/we_n
add wave -literal -decimal /tb/u1/addr
add wave -literal -unsigned /tb/u1/ba
add wave -literal -decimal /tb/u1/dq
add wave -literal /tb/u1/dqm
add wave -literal /tb/u1/operation
add wave -literal -decimal /tb/u1/mode_reg
add wave -logic /tb/u1/active_enable
add wave -logic /tb/u1/aref_enable
add wave -logic /tb/u1/burst_term
add wave -logic /tb/u1/mode_reg_enable
add wave -logic /tb/u1/prech_enable
add wave -logic /tb/u1/read_enable
add wave -logic /tb/u1/write_enable
add wave -logic /tb/u1/burst_length_1
add wave -logic /tb/u1/burst_length_2
add wave -logic /tb/u1/burst_length_4
add wave -logic /tb/u1/burst_length_8
add wave -logic /tb/u1/cas_latency_2
add wave -logic /tb/u1/cas_latency_3
add wave -literal /tb/u1/pre_chk
add wave -literal /tb/u1/act_chk
add wave -literal /tb/u1/bank_chk
add wave -literal -decimal /tb/u1/row_chk
add wave -literal -decimal /tb/u1/col_chk
add wave -logic /tb/u1/dq_in_chk
add wave -logic /tb/u1/dq_out_chk