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git-svn-id: http://moon:8086/svn/vhdl/trunk@1290 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-06-10 19:27:35 +00:00
parent 8eb6b3ff9e
commit 2edaa4d7cb
217 changed files with 152127 additions and 0 deletions
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lib/models/memory/sdram/mt48lc16m16a2/dumpdata.txt
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# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)
# BA ROWS COLS DQ
# -- ------------- --------- ----------------
00 0000000000000 000000000 0000000001100100
00 0000000000000 000000001 0000000001100101
00 0000000000000 000000010 0000000001100110
00 0000000000000 000000011 0000000001100111
00 0000000000000 000000100 0000000001101000
00 0000000000000 000000101 0000000001101001
00 0000000000000 000000110 0000000001101010
00 0000000000000 000000111 0000000001101011
00 0000000000000 000001000 0011111111111110
00 0000000000000 000001001 0011111111111110
00 0000000000000 000001010 0011111111111110
01 0000000000000 000000000 0000000011001000
01 0000000000000 000000001 0000000011001001
01 0000000000000 000000010 0000000011001010
01 0000000000000 000000011 0000000011001011
01 0000000000000 000000100 0000000011001100
01 0000000000000 000000101 0000000011001101
01 0000000000000 000000110 0000000011001110
01 0000000000000 000000111 0000000011001111
01 0000000000000 000001000 0111111111111101
01 0000000000000 000001001 0111111111111101
01 0000000000000 000001010 0111111111111101
10 0000000000000 000000000 0000000100101100
10 0000000000000 000000001 0000000100101101
10 0000000000000 000000010 0000000100101110
10 0000000000000 000000011 0000000100101111
10 0000000000000 000000100 0000000100110000
10 0000000000000 000000101 0000000100110001
10 0000000000000 000000110 0000000100110010
10 0000000000000 000000111 0000000100110011
10 0000000000000 000001000 1011111111111011
10 0000000000000 000001001 1011111111111011
10 0000000000000 000001010 1011111111111011
11 0000000000000 000000000 0000000110010000
11 0000000000000 000000001 0000000110010001
11 0000000000000 000000010 0000000110010010
11 0000000000000 000000011 0000000110010011
11 0000000000000 000000100 0000000110010100
11 0000000000000 000000101 0000000110010101
11 0000000000000 000000110 0000000110010110
11 0000000000000 000000111 0000000110010111
11 0000000000000 000001000 1111111111110111
11 0000000000000 000001001 1111111111110111
11 0000000000000 000001010 1111111111110111
lib/models/memory/sdram/mt48lc16m16a2/ed_comnd.vhd
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---------------------------------------------------------------------------------
--COMMAND FORMAT --
-- --
-- write(column address(integer), bank(bit_vector), first data(integer), dqm(bit), cke(bit));--
-- read(column address(integer), bank(bit_vector), dqm(bit), cke(bit)); --
-- active(row address(integer), bank(bit_vector), data bus (integer), dqm(bit), cke(bit));--
-- precharge(bank(bit_vector), address (integer), data bus(integer), dqm(bit), cke(bit)); --
-- nop(data bus(integer), dqm(bit), cke(bit), cs(bit)); --
-- burst_term(data bus(integer), dqm(bit_vector), cke(bit)); --
-- load_array('1'); --
-- load_mode_reg(register(integer), cke(bit)); --
-- next_cycle(clk); This is used after every command(incl. nop) to clock --
-- at the correct clock frequency entered in the clock --
-- period constant below --
-- unload_array(row_start(integer), row_end(integer), bank(bit_vector)) --
-- load_mode_reg(op_code(integer)) --
-- --
---------------------------------------------------------------------------------
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.generate_vectors.all;
ENTITY vector_generate IS
END vector_generate;
ARCHITECTURE vector_generate OF vector_generate IS
SIGNAL stim_done : BOOLEAN := FALSE;
SIGNAL clk : BIT := '0';
CONSTANT clk_start : time := 15 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT Z : INTEGER := -100;
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1' AND clk'EVENT;
--------------------ENTER COMMANDS BELOW THIS LINE-----------------------------
--******************DO NOT USE -100 FOR A DQ VALUE*************************----
--*******************Z WILL PLACE HI-Z ON THE BUS**************************----
--*******USE next_cycle(clk) FOR ADVANCING TO NEXT CLOCK CYCLE*************----
nop(Z, "00", '1', '1'); --Always begin with one nop when using Micron's testbench
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
load_array;
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
precharge("00", 1024, Z, "00", '1');
FOR i IN 1 to 2 LOOP
next_cycle(clk);
nop(Z, "00", '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, "00", '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, "00", '1', '1');
END LOOP;
next_cycle(clk);
load_mode_reg(51, '1'); -- 19 / 35 / 51 -> lat=3,bl=8,mode=seq
next_cycle(clk);
nop(Z, "00", '1', '1');
-- Write Section
next_cycle(clk);
active(0, "00", Z, "00", '1'); -- Activate Bank 0
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk); -- Write Bank 0
write(0, "00", 100, "00", '1');
next_cycle(clk);
nop(101, "00", '1', '1');
next_cycle(clk);
active(0, "01", 102, "00", '1'); -- Activate Bank 1
next_cycle(clk);
nop(103, "00", '1', '1');
next_cycle(clk);
nop(104, "00", '1', '1');
next_cycle(clk);
nop(105, "00", '1', '1');
next_cycle(clk);
nop(106, "00", '1', '1');
next_cycle(clk);
nop(107, "00", '1', '1');
next_cycle(clk);
write(0, "01", 200, "00", '1'); -- Write Bank 1
next_cycle(clk);
precharge("00", 0, 201, "00", '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", 202, "00", '1'); -- Activate Bank 2
next_cycle(clk);
nop(203, "00", '1', '1');
next_cycle(clk);
nop(204, "00", '1', '1');
next_cycle(clk);
nop(205, "00", '1', '1');
next_cycle(clk);
nop(206, "00", '1', '1');
next_cycle(clk);
nop(207, "00", '1', '1');
next_cycle(clk);
write(0, "10", 300, "00", '1'); -- Write Bank 2
next_cycle(clk);
precharge("01", 0, 301, "00", '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", 302, "00", '1'); -- Activate Bank 3
next_cycle(clk);
nop(303, "00", '1', '1');
next_cycle(clk);
nop(304, "00", '1', '1');
next_cycle(clk);
nop(305, "00", '1', '1');
next_cycle(clk);
nop(306, "00", '1', '1');
next_cycle(clk);
nop(307, "00", '1', '1');
next_cycle(clk);
write(0, "11", 400, "00", '1'); -- Write Bank 3
next_cycle(clk);
precharge("10", 0, 401, "00", '1'); -- Precharge Bank 2
next_cycle(clk);
active(0, "00", 402, "00", '1'); -- Activate Bank 0
next_cycle(clk);
nop(403, "00", '1', '1');
next_cycle(clk);
nop(404, "00", '1', '1');
next_cycle(clk);
nop(405, "00", '1', '1');
next_cycle(clk);
nop(406, "00", '1', '1');
next_cycle(clk);
nop(407, "00", '1', '1');
-- Read Section
next_cycle(clk);
read(0, "00", "00", '1'); -- Read Bank 0
next_cycle(clk);
precharge("11", 0, Z, "00", '1'); -- Precharge Bank 3
next_cycle(clk);
active(0, "01", Z, "00", '1'); -- Activate Bank 1
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
read(0, "01", "00", '1'); -- Read Bank 1
next_cycle(clk);
precharge("00", 0, Z, "00", '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", Z, "00", '1'); -- Activate Bank 2
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
read(0, "10", "00", '1'); -- Read Bank 2
next_cycle(clk);
precharge("01", 0, Z, "00", '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", Z, "00", '1'); -- Activate Bank 3
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
read(0, "11", "00", '1'); -- Read Bank 3
next_cycle(clk);
precharge("10", 0, Z, "00", '1'); -- Precharge Bank 2
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
precharge("11", 0, Z, "00", '1'); -- Precharge Bank 3
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
unload_array;
next_cycle(clk);
nop(Z, "00", '1', '1');
stim_done <= TRUE; --always include this line at the end of your stimulus
-------------------------------------------------------------------------------
--*************************************************************************----
END PROCESS;
clock:
PROCESS
VARIABLE done_time : time;
VARIABLE cycle_var : integer := 0;
BEGIN
cycle <= 0;
clk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
clk <= '1';
cycle <= cycle_var;
WAIT for clk_period/2;
cycle_var := cycle_var + 1;
clk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT (FALSE)
REPORT "Test Vectors Generated"
SEVERITY note;
WAIT;
END PROCESS;
END;
lib/models/memory/sdram/mt48lc16m16a2/loaddata.txt
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# Micron Technology, Inc. (FILE LOAD / MEMORY INITIALIZE)
# BA ROWS COLS DQ
# -- ------------- --------- ----------------
00 0000000000000 000000000 0011111111111110
00 0000000000000 000000001 0011111111111110
00 0000000000000 000000010 0011111111111110
00 0000000000000 000000011 0011111111111110
00 0000000000000 000000100 0011111111111110
00 0000000000000 000000101 0011111111111110
00 0000000000000 000000110 0011111111111110
00 0000000000000 000000111 0011111111111110
00 0000000000000 000001000 0011111111111110
00 0000000000000 000001001 0011111111111110
00 0000000000000 000001010 0011111111111110
01 0000000000000 000000000 0111111111111101
01 0000000000000 000000001 0111111111111101
01 0000000000000 000000010 0111111111111101
01 0000000000000 000000011 0111111111111101
01 0000000000000 000000100 0111111111111101
01 0000000000000 000000101 0111111111111101
01 0000000000000 000000110 0111111111111101
01 0000000000000 000000111 0111111111111101
01 0000000000000 000001000 0111111111111101
01 0000000000000 000001001 0111111111111101
01 0000000000000 000001010 0111111111111101
10 0000000000000 000000000 1011111111111011
10 0000000000000 000000001 1011111111111011
10 0000000000000 000000010 1011111111111011
10 0000000000000 000000011 1011111111111011
10 0000000000000 000000100 1011111111111011
10 0000000000000 000000101 1011111111111011
10 0000000000000 000000110 1011111111111011
10 0000000000000 000000111 1011111111111011
10 0000000000000 000001000 1011111111111011
10 0000000000000 000001001 1011111111111011
10 0000000000000 000001010 1011111111111011
11 0000000000000 000000000 1111111111110111
11 0000000000000 000000001 1111111111110111
11 0000000000000 000000010 1111111111110111
11 0000000000000 000000011 1111111111110111
11 0000000000000 000000100 1111111111110111
11 0000000000000 000000101 1111111111110111
11 0000000000000 000000110 1111111111110111
11 0000000000000 000000111 1111111111110111
11 0000000000000 000001000 1111111111110111
11 0000000000000 000001001 1111111111110111
11 0000000000000 000001010 1111111111110111
lib/models/memory/sdram/mt48lc16m16a2/mt48lc16m16a2.vhd
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lib/models/memory/sdram/mt48lc16m16a2/mti_pkg.vhd
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--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE mti_pkg IS
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to STD_LOGIC
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
BEGIN
CASE s IS
WHEN '0' => RETURN ('0');
WHEN '1' => RETURN ('1');
WHEN OTHERS => RETURN ('0');
END CASE;
END;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver INTEGER to BIT_VECTOR
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN
outputlen := 32;
offset := output'LENGTH - 32;
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0';
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1';
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH;
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0';
ELSE
output(output'HIGH-j-offset) := '1';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0';
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1';
ELSE
output(output'HIGH-j-offset) := '0';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1';
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
lib/models/memory/sdram/mt48lc16m16a2/test.do
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# Macro for running Micron SDRAM VHDL model
#
# Compile Package Library (Require)
vcom mti_pkg.vhd
# Compile Micron Test Vector Generator (optional or use your own test)
vcom vec_gen.vhd
vcom ed_comnd.vhd
vsim vector_generate
run -all
# Compile Micron SDRAM
vcom mt48lc16m16a2.vhd
# Compile Micron Testbench (optional or use your own test bench)
vcom test.vhd
# Simulate Test
vsim tb
# Display waveform
onerror {resume}
add wave -logic /tb/u1/clk
add wave -logic /tb/u1/cke
add wave -logic /tb/u1/cs_n
add wave -logic /tb/u1/ras_n
add wave -logic /tb/u1/cas_n
add wave -logic /tb/u1/we_n
add wave -literal -decimal /tb/u1/addr
add wave -literal -unsigned /tb/u1/ba
add wave -literal -decimal /tb/u1/dq
add wave -literal /tb/u1/dqm
add wave -literal /tb/u1/operation
add wave -literal -decimal /tb/u1/mode_reg
add wave -logic /tb/u1/active_enable
add wave -logic /tb/u1/aref_enable
add wave -logic /tb/u1/burst_term
add wave -logic /tb/u1/mode_reg_enable
add wave -logic /tb/u1/prech_enable
add wave -logic /tb/u1/read_enable
add wave -logic /tb/u1/write_enable
add wave -logic /tb/u1/burst_length_1
add wave -logic /tb/u1/burst_length_2
add wave -logic /tb/u1/burst_length_4
add wave -logic /tb/u1/burst_length_8
add wave -logic /tb/u1/cas_latency_2
add wave -logic /tb/u1/cas_latency_3
add wave -literal /tb/u1/pre_chk
add wave -literal /tb/u1/act_chk
add wave -literal /tb/u1/bank_chk
add wave -literal -decimal /tb/u1/row_chk
add wave -literal -decimal /tb/u1/col_chk
add wave -logic /tb/u1/dq_in_chk
add wave -logic /tb/u1/dq_out_chk
# Run all test
run -all
lib/models/memory/sdram/mt48lc16m16a2/test.txt
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0 ns 1 1 1 1 1 00 00 0 -100 0 0
22 ns 1 1 1 1 1 00 00 0 -100 0 0
32 ns 1 0 1 1 1 00 00 0 -100 1 0
42 ns 1 1 1 1 1 00 00 0 -100 0 0
52 ns 1 1 1 1 1 00 00 0 -100 0 0
62 ns 1 1 1 1 1 00 00 0 -100 0 0
72 ns 1 1 1 1 1 00 00 0 -100 0 0
82 ns 1 0 0 1 0 00 00 1024 -100 0 0
92 ns 1 1 1 1 1 00 00 0 -100 0 0
102 ns 1 1 1 1 1 00 00 0 -100 0 0
112 ns 1 0 0 0 1 00 00 0 -100 0 0
122 ns 1 1 1 1 1 00 00 0 -100 0 0
132 ns 1 1 1 1 1 00 00 0 -100 0 0
142 ns 1 1 1 1 1 00 00 0 -100 0 0
152 ns 1 1 1 1 1 00 00 0 -100 0 0
162 ns 1 1 1 1 1 00 00 0 -100 0 0
172 ns 1 1 1 1 1 00 00 0 -100 0 0
182 ns 1 1 1 1 1 00 00 0 -100 0 0
192 ns 1 1 1 1 1 00 00 0 -100 0 0
202 ns 1 0 0 0 1 00 00 0 -100 0 0
212 ns 1 1 1 1 1 00 00 0 -100 0 0
222 ns 1 1 1 1 1 00 00 0 -100 0 0
232 ns 1 1 1 1 1 00 00 0 -100 0 0
242 ns 1 1 1 1 1 00 00 0 -100 0 0
252 ns 1 1 1 1 1 00 00 0 -100 0 0
262 ns 1 1 1 1 1 00 00 0 -100 0 0
272 ns 1 1 1 1 1 00 00 0 -100 0 0
282 ns 1 1 1 1 1 00 00 0 -100 0 0
292 ns 1 0 0 0 0 00 00 51 -100 0 0
302 ns 1 1 1 1 1 00 00 0 -100 0 0
312 ns 1 0 0 1 1 00 00 0 -100 0 0
322 ns 1 1 1 1 1 00 00 0 -100 0 0
332 ns 1 0 1 0 0 00 00 0 100 0 0
342 ns 1 1 1 1 1 00 00 0 101 0 0
352 ns 1 0 0 1 1 00 01 0 102 0 0
362 ns 1 1 1 1 1 00 00 0 103 0 0
372 ns 1 1 1 1 1 00 00 0 104 0 0
382 ns 1 1 1 1 1 00 00 0 105 0 0
392 ns 1 1 1 1 1 00 00 0 106 0 0
402 ns 1 1 1 1 1 00 00 0 107 0 0
412 ns 1 0 1 0 0 00 01 0 200 0 0
422 ns 1 0 0 1 0 00 00 0 201 0 0
432 ns 1 0 0 1 1 00 10 0 202 0 0
442 ns 1 1 1 1 1 00 00 0 203 0 0
452 ns 1 1 1 1 1 00 00 0 204 0 0
462 ns 1 1 1 1 1 00 00 0 205 0 0
472 ns 1 1 1 1 1 00 00 0 206 0 0
482 ns 1 1 1 1 1 00 00 0 207 0 0
492 ns 1 0 1 0 0 00 10 0 300 0 0
502 ns 1 0 0 1 0 00 01 0 301 0 0
512 ns 1 0 0 1 1 00 11 0 302 0 0
522 ns 1 1 1 1 1 00 00 0 303 0 0
532 ns 1 1 1 1 1 00 00 0 304 0 0
542 ns 1 1 1 1 1 00 00 0 305 0 0
552 ns 1 1 1 1 1 00 00 0 306 0 0
562 ns 1 1 1 1 1 00 00 0 307 0 0
572 ns 1 0 1 0 0 00 11 0 400 0 0
582 ns 1 0 0 1 0 00 10 0 401 0 0
592 ns 1 0 0 1 1 00 00 0 402 0 0
602 ns 1 1 1 1 1 00 00 0 403 0 0
612 ns 1 1 1 1 1 00 00 0 404 0 0
622 ns 1 1 1 1 1 00 00 0 405 0 0
632 ns 1 1 1 1 1 00 00 0 406 0 0
642 ns 1 1 1 1 1 00 00 0 407 0 0
652 ns 1 0 1 0 1 00 00 0 -100 0 0
662 ns 1 0 0 1 0 00 11 0 -100 0 0
672 ns 1 0 0 1 1 00 01 0 -100 0 0
682 ns 1 1 1 1 1 00 00 0 -100 0 0
692 ns 1 1 1 1 1 00 00 0 -100 0 0
702 ns 1 1 1 1 1 00 00 0 -100 0 0
712 ns 1 1 1 1 1 00 00 0 -100 0 0
722 ns 1 1 1 1 1 00 00 0 -100 0 0
732 ns 1 0 1 0 1 00 01 0 -100 0 0
742 ns 1 0 0 1 0 00 00 0 -100 0 0
752 ns 1 0 0 1 1 00 10 0 -100 0 0
762 ns 1 1 1 1 1 00 00 0 -100 0 0
772 ns 1 1 1 1 1 00 00 0 -100 0 0
782 ns 1 1 1 1 1 00 00 0 -100 0 0
792 ns 1 1 1 1 1 00 00 0 -100 0 0
802 ns 1 1 1 1 1 00 00 0 -100 0 0
812 ns 1 0 1 0 1 00 10 0 -100 0 0
822 ns 1 0 0 1 0 00 01 0 -100 0 0
832 ns 1 0 0 1 1 00 11 0 -100 0 0
842 ns 1 1 1 1 1 00 00 0 -100 0 0
852 ns 1 1 1 1 1 00 00 0 -100 0 0
862 ns 1 1 1 1 1 00 00 0 -100 0 0
872 ns 1 1 1 1 1 00 00 0 -100 0 0
882 ns 1 1 1 1 1 00 00 0 -100 0 0
892 ns 1 0 1 0 1 00 11 0 -100 0 0
902 ns 1 0 0 1 0 00 10 0 -100 0 0
912 ns 1 1 1 1 1 00 00 0 -100 0 0
922 ns 1 1 1 1 1 00 00 0 -100 0 0
932 ns 1 1 1 1 1 00 00 0 -100 0 0
942 ns 1 1 1 1 1 00 00 0 -100 0 0
952 ns 1 1 1 1 1 00 00 0 -100 0 0
962 ns 1 1 1 1 1 00 00 0 -100 0 0
972 ns 1 0 0 1 0 00 11 0 -100 0 0
982 ns 1 1 1 1 1 00 00 0 -100 0 0
992 ns 1 1 1 1 1 00 00 0 -100 0 0
1002 ns 1 0 1 1 1 00 00 0 -100 0 1
1012 ns 1 1 1 1 1 00 00 0 -100 0 0
lib/models/memory/sdram/mt48lc16m16a2/test.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
LIBRARY STD;
USE std.textio.ALL;
LIBRARY work;
USE work.mti_pkg.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE test OF tb IS
CONSTANT addr_bits : INTEGER := 13;
CONSTANT data_bits : INTEGER := 16;
CONSTANT clk_start : time := 5 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT continue_time : time := 10 ns;
COMPONENT mt48lc16m16a2
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
Load : IN STD_LOGIC := '0'; -- FOR LOADING MEMORY ARRAY
Dump : IN STD_LOGIC := '0' -- FOR DUMPING MEMORY ARRAY
);
END COMPONENT;
FOR ALL : mt48lc16m16a2 USE ENTITY work.mt48lc16m16a2 (behave);
SIGNAL pDq : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
SIGNAL pAddr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
SIGNAL pBa : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pClk : STD_LOGIC;
SIGNAL pCke : STD_LOGIC;
SIGNAL pCs : STD_LOGIC;
SIGNAL pCas : STD_LOGIC;
SIGNAL pRas : STD_LOGIC;
SIGNAL pWe : STD_LOGIC;
SIGNAL pDqm : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pLoad : STD_LOGIC;
SIGNAL pDump : STD_LOGIC;
SIGNAL stim_done : boolean := false;
SIGNAL clk_done : boolean := false;
BEGIN
u1: mt48lc16m16a2
PORT MAP(
Dq => pDq,
Addr => pAddr,
Ba => pBa,
Clk => pClk,
Cke => pCke,
Cs_n => pCs,
Ras_n => pRas,
Cas_n => pCas,
We_n => pWe,
Dqm => pDqm,
Load => pLoad,
Dump => pDump
);
stimulator : PROCESS
FILE stim_file:text IS IN "test.txt";
VARIABLE l : line;
VARIABLE time_var : TIME;
VARIABLE pCke_var : bit;
VARIABLE pCs_var : bit;
VARIABLE pRas_var : bit;
VARIABLE PCas_var : bit;
VARIABLE pWe_var : bit;
VARIABLE pDqm_var : bit_vector (1 DOWNTO 0);
VARIABLE pBa_var : bit_vector (1 DOWNTO 0);
VARIABLE pAddr_var : INTEGER;
VARIABLE pDq_var : INTEGER; -- -100 is converted to hi-Z state
VARIABLE PLoad_var : bit;
VARIABLE pDump_var : bit;
VARIABLE pMa_var_vect : STD_LOGIC_VECTOR(addr_bits - 1 DOWNTO 0);
CONSTANT HiZ : STD_LOGIC_VECTOR(data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
BEGIN
WHILE not ENDFILE(stim_file) LOOP
readline(stim_file,l);
IF l'length > 0 THEN
read(l, time_var);
read(l, pCke_var);
read(l, pCs_var);
read(l, pRas_var);
read(l, pCas_var);
read(l, pWe_var);
read(l, pDqm_var);
read(l, pBa_var);
read(l, pAddr_var);
read(l, pDq_var);
read(l, PLoad_var);
read(l, pDump_var);
IF now > time_var THEN
ASSERT false
REPORT "Detected a time in the stim file that is in the past"
SEVERITY error;
ELSE
WAIT FOR time_var-now;
pCke <= TO_StdLogic(pCke_var);
pCs <= TO_StdLogic(pCs_var);
pRas <= TO_StdLogic(pRas_var);
pCas <= TO_StdLogic(pCas_var);
pWe <= TO_StdLogic(pWe_var);
pDqm <= TO_StdLogicVector(pDqm_var);
pBa <= TO_StdLogicVector(pBa_var);
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
pLoad <= TO_StdLogic(PLoad_var);
pDump <= TO_StdLogic(pDump_var);
END IF;
END IF;
END LOOP;
ASSERT false
REPORT "End of Stimulation File Detected!"
SEVERITY note;
stim_done <= true;
WAIT;
END PROCESS;
clock : PROCESS
VARIABLE done_time : time;
BEGIN
pclk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
done_time := now+continue_time;
WHILE now < done_time LOOP --one last clock to finish last command
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT false
REPORT "Suspending clock activity"
SEVERITY note;
clk_done <= true;
WAIT;
END PROCESS;
END test;
lib/models/memory/sdram/mt48lc16m16a2/vec_gen.vhd
+353
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@@ -0,0 +1,353 @@
-------------------------------------------------------------------------------
-- --
-- This is a data generator for the testbench for Micron's Synchronous --
-- DRAM. This generator reads a text file line-by-line and generates --
-- a file of test vectors that is then read by the testbench and --
-- applied to the part. --
-- --
-- This VHDL program creates a text file of test vectors that is used by the --
-- test bench. Place your commands in a file (a copy of VEC_GEN.VHD) and run --
-- VEC_GEN.VHD in your VHDL simulator (make sure you have compiled this --
-- package prior to running the program VEC_GEN.VHD). This will produce the --
-- vectors that are required to run the included testbench. Change the name --
-- of the vector file to save your vectors in separate files. The default --
-- file name for the output vectors generated from this pacakage is --
-- "test.txt." --
-- --
-- Now compile and run the testbench program embedtb.vhd. The testbench uses --
-- the default test.txt as input vectors. --
-- --
-- --
-- Copyright 1997 Micron Technology, Inc. --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE std.textio.all;
PACKAGE generate_vectors IS
CONSTANT set_up : TIME;
CONSTANT hold : TIME;
CONSTANT cycle_start : TIME;
SIGNAL cycle : INTEGER := 0;
SIGNAL sim_time : TIME := 0 ns;
FILE output_file:TEXT IS OUT "test.txt";
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0);
first_data : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT; cs : IN BIT);
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE auto_refresh;
PROCEDURE next_cycle(SIGNAL clk : IN BIT);
PROCEDURE load_array;
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT);
PROCEDURE unload_array;
END generate_vectors;
PACKAGE BODY generate_vectors IS
CONSTANT set_up : TIME := 3 ns;
CONSTANT hold : TIME := 1 ns;
CONSTANT cycle_start : TIME := 0 ns;
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); first_data : IN INTEGER;
dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, first_data, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, row_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT; cs : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, cs, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE auto_refresh IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE next_cycle(SIGNAL clk : IN BIT) IS
BEGIN
WAIT UNTIL clk = '1';
END;
PROCEDURE load_array IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 1, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE unload_array IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 1, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, op_code, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
writeline(output_file,l); --write vector to file
END;
END generate_vectors;
lib/models/memory/sdram/mt48lc16m16a2/wave.do
+33
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@@ -0,0 +1,33 @@
onerror {resume}
add wave -logic /tb/u1/clk
add wave -logic /tb/u1/cke
add wave -logic /tb/u1/cs_n
add wave -logic /tb/u1/ras_n
add wave -logic /tb/u1/cas_n
add wave -logic /tb/u1/we_n
add wave -literal -decimal /tb/u1/addr
add wave -literal -unsigned /tb/u1/ba
add wave -literal -decimal /tb/u1/dq
add wave -literal /tb/u1/dqm
add wave -literal /tb/u1/operation
add wave -literal -decimal /tb/u1/mode_reg
add wave -logic /tb/u1/active_enable
add wave -logic /tb/u1/aref_enable
add wave -logic /tb/u1/burst_term
add wave -logic /tb/u1/mode_reg_enable
add wave -logic /tb/u1/prech_enable
add wave -logic /tb/u1/read_enable
add wave -logic /tb/u1/write_enable
add wave -logic /tb/u1/burst_length_1
add wave -logic /tb/u1/burst_length_2
add wave -logic /tb/u1/burst_length_4
add wave -logic /tb/u1/burst_length_8
add wave -logic /tb/u1/cas_latency_2
add wave -logic /tb/u1/cas_latency_3
add wave -literal /tb/u1/pre_chk
add wave -literal /tb/u1/act_chk
add wave -literal /tb/u1/bank_chk
add wave -literal -decimal /tb/u1/row_chk
add wave -literal -decimal /tb/u1/col_chk
add wave -logic /tb/u1/dq_in_chk
add wave -logic /tb/u1/dq_out_chk
lib/models/memory/sdram/mt48lc16m8a2/mt48lc16m8a2.vhd
+1069
View File
File diff suppressed because it is too large Load Diff
lib/models/memory/sdram/mt48lc16m8a2/test.do
+5
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@@ -0,0 +1,5 @@
vcom mt48lc16m8a2.vhd
vcom test.vhd
vsim -t ps tb
do wave.do
run 800 ns
lib/models/memory/sdram/mt48lc16m8a2/test.vhd
+313
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@@ -0,0 +1,313 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE test OF tb IS
COMPONENT mt48lc16m8a2
GENERIC (
tCK : TIME := 10 ns;
addr_bits : INTEGER := 12;
data_bits : INTEGER := 8
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '0';
Cs_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '0';
Ras_n : IN STD_LOGIC := '0';
We_n : IN STD_LOGIC := '0';
Dqm : IN STD_LOGIC := '0'
);
END COMPONENT;
FOR ALL : mt48lc16m8a2 USE ENTITY work.mt48lc16m8a2 (behave);
CONSTANT tCK : TIME := 10 ns;
CONSTANT addr_bits : INTEGER := 12;
CONSTANT data_bits : INTEGER := 8;
SIGNAL pDq : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
SIGNAL pAddr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
SIGNAL pBa : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pClk : STD_LOGIC;
SIGNAL pCke : STD_LOGIC;
SIGNAL pCs_n : STD_LOGIC;
SIGNAL pCas_n : STD_LOGIC;
SIGNAL pRas_n : STD_LOGIC;
SIGNAL pWe_n : STD_LOGIC;
SIGNAL pDqm : STD_LOGIC;
SIGNAL stim_done : boolean := false;
SIGNAL clk_done : boolean := false;
BEGIN
u1: mt48lc16m8a2
PORT MAP(
Dq => pDq,
Addr => pAddr,
Ba => pBa,
Clk => pClk,
Cke => pCke,
Cs_n => pCs_n,
Ras_n => pRas_n,
Cas_n => pCas_n,
We_n => pWe_n,
Dqm => pDqm
);
stimulator : PROCESS
PROCEDURE ACTIVE (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '0';
pCas_n <= '1';
pWe_n <= '1';
pDqm <= '0';
pBa <= Ba_in;
pAddr <= Addr_in;
pDq <= Dq_in;
WAIT FOR tCK;
END;
PROCEDURE AUTO_REFRESH IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '0';
pCas_n <= '0';
pWe_n <= '1';
pDqm <= '0';
--pBa <= "00";
--pAddr <= (OTHERS => '0');
pDq <= (OTHERS => 'Z');
WAIT FOR tCK;
END;
PROCEDURE BURST_TERM IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '1';
pCas_n <= '1';
pWe_n <= '0';
pDqm <= '0';
--pBa <= "00";
--pAddr <= (OTHERS => '0');
pDq <= (OTHERS => 'Z');
WAIT FOR tCK;
END;
PROCEDURE LOAD_MODE_REG (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '0';
pCas_n <= '0';
pWe_n <= '0';
pDqm <= '0';
pBa <= Ba_in;
pAddr <= Addr_in;
pDq <= (OTHERS => 'Z');
WAIT FOR tCK;
END;
PROCEDURE NOP (Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '1';
pCas_n <= '1';
pWe_n <= '1';
pDqm <= '0';
--pBa <= "00";
--pAddr <= (OTHERS => '0');
pDq <= Dq_in;
WAIT FOR tCK;
END;
PROCEDURE PRECHARGE (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '0';
pCas_n <= '1';
pWe_n <= '0';
pDqm <= '0';
pBa <= Ba_in;
pAddr <= Addr_in;
pDq <= Dq_in;
WAIT FOR tCK;
END;
PROCEDURE READ (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '1';
pCas_n <= '0';
pWe_n <= '1';
pDqm <= '0';
pBa <= Ba_in;
pAddr <= Addr_in;
pDq <= Dq_in;
WAIT FOR tCK;
END;
-- Write
PROCEDURE WRITE (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '1';
pCas_n <= '0';
pWe_n <= '0';
pDqm <= '0';
pBa <= Ba_in;
pAddr <= Addr_in;
pDq <= Dq_in;
WAIT FOR tCK;
END;
BEGIN
-- COMMAND BA ADDR DQ
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
-- We need 100 us power up sequence. I use 10 NOPs here as a required example.
PRECHARGE ("00", "010000000000", "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
AUTO_REFRESH;
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
AUTO_REFRESH;
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
LOAD_MODE_REG ("00", "000000100010");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
ACTIVE ("00", "000000000000", "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
ACTIVE ("01", "000000000000", "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
ACTIVE ("10", "000000000000", "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
ACTIVE ("11", "000000000000", "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
WRITE ("00", "000000000000", "00000000");
NOP ( "00000001");
NOP ( "00000010");
NOP ( "00000011");
WRITE ("01", "000000000000", "00000100");
NOP ( "00000101");
NOP ( "00000110");
NOP ( "00000111");
WRITE ("10", "000000000000", "00001000");
NOP ( "00001001");
NOP ( "00001010");
NOP ( "00001011");
WRITE ("11", "000000000000", "00001100");
NOP ( "00001101");
NOP ( "00001110");
NOP ( "00001111");
READ ("00", "000000000000", "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
READ ("01", "000000000000", "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
READ ("10", "000000000000", "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
READ ("11", "000000000000", "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
NOP ( "ZZZZZZZZ");
ASSERT false
REPORT "End of Stimulation Detected!"
SEVERITY note;
stim_done <= true;
WAIT;
END PROCESS;
clock : PROCESS
VARIABLE done_time : time;
BEGIN
pclk <= '0';
WAIT for tCK/2;
WHILE not stim_done loop
pclk <= '1';
WAIT for tCK/2;
pclk <= '0';
WAIT for tCK/2;
END LOOP;
done_time := now + tCK;
WHILE now < done_time LOOP -- one last clock to finish last command
pclk <= '1';
WAIT for tCK/2;
pclk <= '0';
WAIT for tCK/2;
END LOOP;
ASSERT false
REPORT "Suspending clock activity"
SEVERITY note;
clk_done <= true;
WAIT;
END PROCESS;
END test;
lib/models/memory/sdram/mt48lc16m8a2/wave.do
+39
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb/u1/clk
add wave -noupdate -format Logic /tb/u1/cke
add wave -noupdate -format Logic /tb/u1/cs_n
add wave -noupdate -format Logic /tb/u1/ras_n
add wave -noupdate -format Logic /tb/u1/cas_n
add wave -noupdate -format Logic /tb/u1/we_n
add wave -noupdate -format Literal -radix decimal /tb/u1/addr
add wave -noupdate -format Literal -radix unsigned /tb/u1/ba
add wave -noupdate -format Literal -radix decimal /tb/u1/dq
add wave -noupdate -format Logic /tb/u1/dqm
add wave -noupdate -format Literal -radix decimal /tb/u1/operation
add wave -noupdate -format Literal -radix decimal /tb/u1/mode_reg
add wave -noupdate -format Logic /tb/u1/active_enable
add wave -noupdate -format Logic /tb/u1/aref_enable
add wave -noupdate -format Logic /tb/u1/burst_term
add wave -noupdate -format Logic /tb/u1/mode_reg_enable
add wave -noupdate -format Logic /tb/u1/prech_enable
add wave -noupdate -format Logic /tb/u1/read_enable
add wave -noupdate -format Logic /tb/u1/write_enable
add wave -noupdate -format Logic /tb/u1/burst_length_1
add wave -noupdate -format Logic /tb/u1/burst_length_2
add wave -noupdate -format Logic /tb/u1/burst_length_4
add wave -noupdate -format Logic /tb/u1/burst_length_8
add wave -noupdate -format Logic /tb/u1/cas_latency_2
add wave -noupdate -format Logic /tb/u1/cas_latency_3
add wave -noupdate -format Literal /tb/u1/act_chk
add wave -noupdate -format Logic /tb/u1/din_chk
add wave -noupdate -format Logic /tb/u1/dout_chk
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {320 ns}
WaveRestoreZoom {139586 ps} {454431 ps}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
lib/models/memory/sdram/mt48lc1m16a1/ed_comnd.vhd
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---------------------------------------------------------------------------------
--COMMAND FORMAT --
-- --
-- write(column address(integer), bank(bit), first data(integer), dqm(bit), cke(bit));--
-- read(column address(integer), bank(bit), dqm(bit), cke(bit)); --
-- active(row address(integer), bank(bit), data bus (integer), dqm(bit), cke(bit));--
-- precharge(bank(bit), data bus(integer), dqm(bit), cke(bit)); --
-- nop(data bus(integer), dqm(bit), cke(bit), cs(bit)); --
-- burst_term(data bus(integer), dqm(bit_vector), cke(bit)); --
-- load_array('1'); --
-- load_mode_reg(register(integer), cke(bit)); --
-- next_cycle(clk); This is used after every command(incl. nop) to clock --
-- at the correct clock frequency entered in the clock --
-- period constant below --
-- unload_array(row_start(integer), row_end(integer), bank(bit)) --
-- load_mode_reg(op_code(integer)) --
-- --
---------------------------------------------------------------------------------
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.generate_vectors.all;
ENTITY vector_generate IS
END vector_generate;
ARCHITECTURE vector_generate OF vector_generate IS
SIGNAL stim_done : BOOLEAN := FALSE;
SIGNAL clk : BIT := '0';
CONSTANT clk_start : time := 15 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT Z : INTEGER := -100;
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1' AND clk'EVENT;
--------------------ENTER COMMANDS BELOW THIS LINE-----------------------------
--******************DO NOT USE -100 FOR A DQ VALUE*************************----
--*******************Z WILL PLACE HI-Z ON THE BUS**************************----
--*******USE next_cycle(clk) FOR ADVANCING TO NEXT CLOCK CYCLE*************----
nop(Z, "00", '1', '1'); -- Always begin with one nop when using Micron's testbench
FOR i IN 1 to 5 LOOP -- You will need 100 us for powerup.
next_cycle(clk); -- I used 5 here just for an example.
nop(Z, "00", '1', '1');
END LOOP;
next_cycle(clk);
precharge('0', 1024, Z, "00", '1'); -- Precharge all banks
FOR i IN 1 to 2 LOOP
next_cycle(clk);
nop(Z, "00", '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh; -- First auto refresh
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, "00", '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh; -- Second auto refresh
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, "00", '1', '1');
END LOOP;
next_cycle(clk);
load_mode_reg(51, '1'); -- Load mode register (lat=3, bl=8, mode=seq)
FOR i IN 1 TO 2 LOOP
next_cycle(clk);
nop(Z, "00", '1', '1');
END LOOP;
-- Alternate bank write access
next_cycle(clk);
active(0, '0', Z, "00", '1'); -- Activate Bank 0, Row 0
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
write(1024, '0', 100, "00", '1'); -- Write Bank 0, Col 0, Data 100 (auto precharge)
next_cycle(clk);
nop (101, "00", '1', '1');
next_cycle(clk);
nop (102, "00", '1', '1');
next_cycle(clk);
nop (103, "00", '1', '1');
next_cycle(clk);
nop (104, "00", '1', '1');
next_cycle(clk);
active(0, '1', 105, "00", '1'); -- Activate Bank 1, Row 0
next_cycle(clk);
nop (106, "00", '1', '1');
next_cycle(clk);
nop (107, "00", '1', '1');
next_cycle(clk);
write(1024, '1', 200, "00", '1'); -- Write Bank 1, Col 0, Data 200 (auto precharge)
next_cycle(clk);
nop (201, "00", '1', '1');
next_cycle(clk);
nop (202, "00", '1', '1');
next_cycle(clk);
nop (203, "00", '1', '1');
next_cycle(clk);
nop (204, "00", '1', '1');
next_cycle(clk);
active(0, '0', 205, "00", '1'); -- Activate Bank 0, Row 0
next_cycle(clk);
nop (206, "00", '1', '1');
next_cycle(clk);
nop (207, "00", '1', '1');
-- Alternate bank read access
next_cycle(clk);
read(1024, '0', "00", '1'); -- Read Bank 0, Col 0 (auto precharge)
next_cycle(clk);
nop (Z, "00", '1', '1');
next_cycle(clk);
nop (Z, "00", '1', '1');
next_cycle(clk);
nop (Z, "00", '1', '1');
next_cycle(clk);
nop (Z, "00", '1', '1');
next_cycle(clk);
active(0, '1', Z, "00", '1'); -- Activate Bank 1, Row 0
next_cycle(clk);
nop (Z, "00", '1', '1');
next_cycle(clk);
nop (Z, "00", '1', '1');
next_cycle(clk);
read(1024, '1', "00", '1'); -- Read Bank 1, Col 0 (auto precharge)
next_cycle(clk);
nop (Z, "00", '1', '1');
next_cycle(clk);
nop (Z, "00", '1', '1');
next_cycle(clk);
nop (Z, "00", '1', '1');
next_cycle(clk);
nop (Z, "00", '1', '1');
next_cycle(clk);
nop (Z, "00", '1', '1');
next_cycle(clk);
nop (Z, "00", '1', '1');
next_cycle(clk);
nop (Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
stim_done <= TRUE; --always include this line at the end of your stimulus
-------------------------------------------------------------------------------
--*************************************************************************----
END PROCESS;
clock:
PROCESS
VARIABLE done_time : time;
VARIABLE cycle_var : integer := 0;
BEGIN
cycle <= 0;
clk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
clk <= '1';
cycle <= cycle_var;
WAIT for clk_period/2;
cycle_var := cycle_var + 1;
clk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT (FALSE)
REPORT "Test Vectors Generated"
SEVERITY note;
WAIT;
END PROCESS;
END;
lib/models/memory/sdram/mt48lc1m16a1/io_utils.vhd
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LIBRARY ieee;
USE std.textio.ALL;
USE ieee.std_logic_1164.ALL;
PACKAGE io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0);
TYPE radix IS (binary, octal, decimal, hex);
-- read a number from the line
-- use this if you have hex numbers that are not in VHDL pound-sign format
PROCEDURE read(l : INOUT line; value : OUT integer; radix : IN positive);
-- read a number that might be in VHDL pound-sign format
PROCEDURE read_based(l : INOUT line; value : OUT integer);
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
END io_utils;
PACKAGE BODY io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0)
IS
BEGIN
write(l, value, justified, field);
END;
PROCEDURE shrink_line(l : INOUT line; pos : integer) IS
VARIABLE tmpl : line;
BEGIN
tmpl := l;
l := NEW string'(tmpl(pos TO tmpl'high));
deallocate(tmpl);
END;
PROCEDURE read(l : INOUT line;
value : OUT integer;
radix : IN positive)
IS
CONSTANT not_digit : integer := -999;
-- convert a character to a value from 0 to 15
FUNCTION digit_value(c : character) RETURN integer IS
BEGIN
IF (c >= '0') AND (c <= '9') THEN
RETURN (character'pos(c) - character'pos('0'));
ELSIF (c >= 'a') AND (c <= 'f') THEN
RETURN (character'pos(c) - character'pos('a') + 10);
ELSIF (c >= 'A') AND (c <= 'F') THEN
RETURN (character'pos(c) - character'pos('A') + 10);
ELSE
RETURN not_digit;
END IF;
END;
-- skip leading white space in the line
PROCEDURE skip_white(VARIABLE l : IN line; pos : OUT integer) IS
BEGIN
pos := l'low;
FOR i IN l'low TO l'high LOOP
CASE l(i) IS
WHEN ' ' | ht =>
pos := i + 1;
WHEN OTHERS =>
EXIT;
END CASE;
END LOOP;
END;
VARIABLE digit : integer;
VARIABLE result : integer := 0;
VARIABLE pos : integer;
BEGIN
-- skip white space
skip_white(l, pos);
-- calculate the value
FOR i IN pos TO l'right LOOP
digit := digit_value(l(i));
EXIT WHEN (digit = not_digit) OR (digit >= radix);
result := result * radix + digit;
pos := i + 1;
END LOOP;
value := result;
-- remove the "used" characters from the line
shrink_line(l, pos);
END;
PROCEDURE read_based(l : INOUT line; value : OUT integer) IS
VARIABLE digit : integer;
VARIABLE num : integer;
VARIABLE base : integer;
BEGIN
read(l, num, 10);
IF (l'length > 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
base := num;
read(l, num, base);
IF (l'length >= 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
END IF;
END IF;
value := num;
END;
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_int(bv : std_logic_vector) RETURN integer
IS
VARIABLE result : integer := 0;
BEGIN
FOR i IN bv'RANGE LOOP
result := result * 2;
IF (bv(i) = '1') THEN
result := result + 1;
END IF;
END LOOP;
RETURN result;
END;
TYPE array_of_widths IS ARRAY(radix) OF natural;
CONSTANT nibble_widths : array_of_widths := (
binary => 1,
octal => 3,
hex => 4,
decimal=> 32);
CONSTANT hex_digit : string(1 TO 16) := "0123456789ABCDEF";
ALIAS input_val : std_logic_vector(value'length DOWNTO 1) IS value;
CONSTANT nibble_width : natural := nibble_widths(base);
CONSTANT result_width : natural := (value'length + nibble_width - 1)/nibble_width;
VARIABLE result : string(1 TO result_width); -- longest possible value
VARIABLE result_pos : positive := 1;
VARIABLE nibble_val : integer;
VARIABLE bitcnt : integer;
BEGIN
IF base = decimal THEN
write(l, to_int(value), justified, field, base, use_pound);
RETURN;
END IF;
bitcnt := value'length MOD nibble_width;
IF (bitcnt = 0) THEN
bitcnt := nibble_width;
END IF;
FOR i IN input_val'RANGE LOOP
nibble_val := nibble_val * 2;
IF (input_val(i) = '1') THEN
nibble_val := nibble_val + 1;
END IF;
bitcnt := bitcnt - 1;
IF (bitcnt = 0) THEN
result(result_pos) := hex_digit(nibble_val + 1);
result_pos := result_pos + 1;
nibble_val := 0;
bitcnt := nibble_width;
END IF;
END LOOP;
write(l, result, justified, field);
END;
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_bv(int : integer) RETURN std_logic_vector
IS
VARIABLE bv : std_logic_vector(32 DOWNTO 1) := (OTHERS => '0');
VARIABLE pos : integer := 0;
VARIABLE tmpval : integer := int;
BEGIN
FOR i IN 1 TO 32 LOOP
pos := pos + 1;
IF (tmpval MOD 2) = 1 THEN
bv(i) := '1';
END IF;
tmpval := tmpval / 2;
EXIT WHEN tmpval = 0;
END LOOP;
RETURN bv(pos DOWNTO 1);
END;
VARIABLE tmp : line;
BEGIN
IF (base = decimal) THEN
IF (use_pound) THEN
write_string(tmp, "10#");
END IF;
write(tmp, value);
IF (use_pound) THEN
write_string(tmp, "#");
END IF;
write(l, tmp.ALL, justified, field);
deallocate(tmp);
ELSE
write(l, to_bv(value), justified, field, base, use_pound);
END IF;
END;
END io_utils;
-- test the hex number reader
--ENTITY test IS END;
--USE std.textio.ALL;
--USE work.io_utils.ALL;
--ARCHITECTURE hex_test OF test IS
--BEGIN
-- PROCESS
-- VARIABLE val : integer;
-- FILE myfile : text IS IN "values";
-- VARIABLE inline : line;
-- VARIABLE outline : line;
-- BEGIN
-- WHILE NOT endfile(myfile) LOOP
-- readline(myfile, inline);
-- write(outline, inline.ALL);
--
-- read_based(inline, val);
-- write_string(outline, " binary: ");
-- write(outline, val, base => binary);
-- write_string(outline, " octal: ");
-- write(outline, val, base => octal);
-- write_string(outline, " decimal: ");
-- write(outline, val, base => decimal);
-- write_string(outline, " hex: ");
-- write(outline, val, base => hex);
-- writeline(output, outline);
-- END LOOP;
-- WAIT;
-- END PROCESS;
--END;
lib/models/memory/sdram/mt48lc1m16a1/mt48lc1m16a1.vhd
+907
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-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC1M18A1.VHD
-- Version: 0.0c
-- Date: April 20th, 1999
-- Model: Behavioral
-- Simulator: Model Technology VLOG (PC version 5.2e PE)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: sphuynh@micron.com
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC1M16A1 (512k x 16 x 2 Banks)
--
-- Description: Micron 16Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0c Son P. Huynh 208-368-3825 04/20/1999 Fix precharge to different bank
-- Micron Technology Inc. terminate current bank
--
-- 0.0b Son P. Huynh 208-368-3825 12/09/1998 Fix some timing check problem
-- Micron Technology Inc. - Improve model functionality
--
-- 0.0a Son P. Huynh 208-368-3825 08/10/1998 First Release
-- Micron Technology Inc. - Simple testbench included
-----------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.mti_pkg.ALL;
ENTITY mt48lc1m16a1 IS
GENERIC (
tAC : TIME := 6.0 ns; -- Timing parameter for -10 device
tAH : TIME := 1.0 ns;
tAS : TIME := 3.0 ns;
tCH : TIME := 3.5 ns;
tCL : TIME := 3.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 1.0 ns;
tDS : TIME := 3.0 ns;
tCKH : TIME := 1.0 ns;
tCKS : TIME := 3.0 ns;
tCMH : TIME := 1.0 ns;
tCMS : TIME := 3.0 ns;
tOH : TIME := 2.5 ns;
tHZ : TIME := 6.0 ns;
tMRD : INTEGER := 2;
tRAS : TIME := 60.0 ns;
tRC : TIME := 90.0 ns;
tRCD : TIME := 30.0 ns;
tRP : TIME := 30.0 ns;
tRRD : TIME := 20.0 ns;
tWR : INTEGER := 1;
addr_bits : INTEGER := 11;
data_bits : INTEGER := 16;
col_bits : INTEGER := 8
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC := '0';
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '0';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '0';
Cas_n : IN STD_LOGIC := '0';
We_n : IN STD_LOGIC := '0';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt48lc1m16a1;
ARCHITECTURE behave OF mt48lc1m16a1 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A);
TYPE Array2xI IS ARRAY (1 DOWNTO 0) OF INTEGER;
TYPE Array2xB IS ARRAY (1 DOWNTO 0) OF BIT;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array2x2BV IS ARRAY (1 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array4xCBV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (3 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_1, Cas_latency_2, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Write_burst_mode : BIT := '0';
SIGNAL Sys_clk, CkeZ : BIT := '0';
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Act_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
SIGNAL Bank_chk : BIT := '0';
SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_1 <= NOT(Mode_reg(6)) AND NOT(Mode_reg(5)) AND Mode_reg(4);
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN
CkeZ <= TO_BIT(Cke, '1');
END IF;
Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
END PROCESS;
state_register : PROCESS
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits - 1 DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : BIT_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCBV;
VARIABLE Bank_addr : Array4xB;
VARIABLE Dqm_reg : Array2x2BV;
VARIABLE Bank, Previous_bank : BIT := '0';
VARIABLE B0_row_addr, B1_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE A10_precharge, Bank_precharge : Array4xB;
VARIABLE Auto_precharge, Read_precharge, Write_precharge : Array2xB;
VARIABLE Count_precharge : Array2xI;
VARIABLE RW_interrupt_write : BIT := '0';
VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1 : BIT := '0';
VARIABLE Act_b0, Act_b1 : BIT := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1 : TIME := 0 ns;
VARIABLE RP_chk, RP_chk0, RP_chk1 : TIME := 0 ns;
VARIABLE WR_chk : Array2xI := (0 & 0);
-- Initialize empty rows
PROCEDURE Init_mem (Bank : BIT; Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = '0' THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = '1' THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
-- Burst Counter
PROCEDURE Burst_decode IS
VARIABLE Col_int : INTEGER := 0;
VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance Burst Counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Col_int := TO_INTEGER(Col);
Col_int := Col_int + 1;
TO_BITVECTOR (Col_int, Col_temp);
ELSIF Mode_reg (3) = '1' THEN
TO_BITVECTOR (Burst_counter, Col_vec);
Col_temp (2) := Col_vec (2) XOR Col_brst (2);
Col_temp (1) := Col_vec (1) XOR Col_brst (1);
Col_temp (0) := Col_vec (0) XOR Col_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Col (0) := Col_temp (0);
ELSIF Burst_length_4 = '1' THEN
Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
ELSE
Col := Col_temp;
END IF;
-- Burst Read Single Write
IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Data counter
IF Burst_length_1 = '1' THEN
IF Burst_counter >= 1 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_2 = '1' THEN
IF Burst_counter >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF Burst_counter >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF Burst_counter >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk;
IF Sys_clk = '1' THEN
-- Internal Command Pipeline
Command(0) := Command(1);
Command(1) := Command(2);
Command(2) := Command(3);
Command(3) := NOP;
Col_addr(0) := Col_addr(1);
Col_addr(1) := Col_addr(2);
Col_addr(2) := Col_addr(3);
Col_addr(3) := (OTHERS => '0');
Bank_addr(0) := Bank_addr(1);
Bank_addr(1) := Bank_addr(2);
Bank_addr(2) := Bank_addr(3);
Bank_addr(3) := '0';
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := '0';
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := '0';
-- Operation Decode
IF Active_enable = '1' THEN
Operation <= ACT;
ELSIF Aref_enable = '1' THEN
Operation <= A_REF;
ELSIF Burst_term = '1' THEN
Operation <= BST;
ELSIF Mode_reg_enable = '1' THEN
Operation <= LMR;
ELSIF Prech_enable = '1' THEN
Operation <= PRECH;
ELSIF Read_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= READ;
ELSE
Operation <= READ_A;
END IF;
ELSIF Write_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= WRITE;
ELSE
Operation <= WRITE_A;
END IF;
ELSE
Operation <= NOP;
END IF;
-- Dqm pipeline for Read
Dqm_reg(0) := Dqm_reg(1);
Dqm_reg(1) := TO_BITVECTOR(Dqm);
-- Read or Write with Auto Precharge Counter
IF Auto_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Auto_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
-- tMRD Counter
MRD_chk := MRD_chk + 1;
-- tWR Counter
WR_chk(0) := WR_chk(0) + 1;
WR_chk(1) := WR_chk(1) + 1;
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (NOW - RP_chk >= tRP)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- Banks must be idle before Refresh
IF Pc_b1 = '0' OR Pc_b0 = '0' THEN
ASSERT (FALSE)
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
END IF;
-- Record current tRC time
RC_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
Mode_reg <= TO_BITVECTOR (Addr);
IF (Pc_b0 /= '1' OR Pc_b1 /= '1') THEN
ASSERT (FALSE)
REPORT "All bank must be Precharge before Load Mode Register"
SEVERITY WARNING;
END IF;
-- REF to LMR
ASSERT (RC_chk >= tRC)
REPORT "tRC violation during Load Mode Register"
SEVERITY WARNING;
-- LMR to LMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := 0;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
IF Ba = '0' AND Pc_b0 = '1' THEN
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := TO_BITVECTOR (Addr);
RCD_chk0 := NOW;
RAS_chk0 := NOW;
-- Precharge to Active Bank 0
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
ELSIF Ba = '1' AND Pc_b1 = '1' THEN
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := TO_BITVECTOR (Addr);
RCD_chk1 := NOW;
RAS_chk1 := NOW;
-- Precharge to Active Bank 1
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
ELSIF Ba = '0' AND Pc_b0 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 0 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = '1' AND Pc_b1 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 1 is not Precharged"
SEVERITY WARNING;
END IF;
-- Active Bank A to Active Bank B
IF (Previous_bank /= TO_BIT(Ba)) AND (NOW - RRD_chk < tRRD) THEN
ASSERT (FALSE)
REPORT "tRRD violation during activate"
SEVERITY WARNING;
END IF;
-- LMR to ACT
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Activate"
SEVERITY WARNING;
-- AutoRefresh to Activate
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Activate"
SEVERITY WARNING;
-- Record current Bank and RRD_chk
Previous_bank := TO_BIT(Ba);
RRD_chk := NOW;
END IF;
-- Precharge Block
IF Prech_enable = '1' THEN
IF Addr(10) = '1' THEN
Pc_b0 := '1';
Pc_b1 := '1';
Act_b0 := '0';
Act_b1 := '0';
RP_chk0 := NOW;
RP_chk1 := NOW;
-- Activate to Precharge all banks
ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
REPORT "tRAS violation during Precharge all banks"
SEVERITY WARNING;
-- tWR violation check for Write
IF ((WR_chk(0) < tWR) AND (WR_chk(1) < tWR)) THEN
ASSERT (FALSE)
REPORT "tWR violation during Precharge all banks"
SEVERITY WARNING;
END IF;
ELSIF Addr(10) = '0' THEN
IF Ba = '0' THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge bank 0"
SEVERITY WARNING;
ELSIF Ba = '1' THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
-- Activate to Precharge bank 1
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge bank 1"
SEVERITY WARNING;
END IF;
-- tWR violation check for Write
IF (WR_chk(TO_INTEGER(Ba)) < tWR) THEN
ASSERT (FALSE)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
END IF;
-- Terminate a Write Immediately (if same bank or all banks)
IF (Data_in_enable = '1' AND (Bank = TO_BIT(Ba) OR Addr(10) = '1')) THEN
Data_in_enable := '0';
END IF;
-- Precharge Command Pipeline for READ
IF CAS_latency_3 = '1' THEN
Command(2) := PRECH;
Bank_precharge(2) := TO_BIT (Ba);
A10_precharge(2) := TO_BIT (Addr(10));
ELSIF CAS_latency_2 = '1' THEN
Command(1) := PRECH;
Bank_precharge(1) := TO_BIT (Ba);
A10_precharge(1) := TO_BIT (Addr(10));
ELSIF CAS_latency_1 = '1' THEN
Command(0) := PRECH;
Bank_precharge(0) := TO_BIT (Ba);
A10_precharge(0) := TO_BIT (Addr(10));
END IF;
-- Record Precharge Bank and Current tRP time
RP_chk := NOW;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
IF CAS_latency_3 = '1' THEN
Command(2) := BST;
ELSIF CAS_latency_2 = '1' THEN
Command(1) := BST;
ELSIF CAS_latency_1 = '1' THEN
Command(0) := BST;
END IF;
END IF;
-- Read, Write, Column Latch
IF Read_enable = '1' OR Write_enable = '1' THEN
-- Check to see if bank is open (ACT) for Read or Write
IF ((Ba = '0' AND Pc_b0 = '1') OR (Ba = '1' AND Pc_b1 = '1')) THEN
ASSERT (FALSE)
REPORT "Cannot Read or Write - Bank is not Activated"
SEVERITY WARNING;
END IF;
-- Activate to Read or Write
IF Ba = '0' THEN
ASSERT (NOW - RCD_chk0 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 0"
SEVERITY WARNING;
ELSIF Ba = '1' THEN
ASSERT (NOW - RCD_chk1 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 1"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- Read Terminate a Write Immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
RW_interrupt_write := '1';
END IF;
-- CAS Latency Pipeline
IF Cas_latency_3 = '1' THEN
IF Addr(10) = '1' THEN
Command(2) := READ_A;
ELSE
Command(2) := READ;
END IF;
Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (2) := TO_BIT (Ba);
ELSIF Cas_latency_2 = '1' THEN
IF Addr(10) = '1' THEN
Command(1) := READ_A;
ELSE
Command(1) := READ;
END IF;
Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (1) := TO_BIT (Ba);
ELSIF Cas_latency_1 = '1' THEN
IF Addr(10) = '1' THEN
Command(0) := READ_A;
ELSE
Command(0) := READ;
END IF;
Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (0) := TO_BIT (Ba);
END IF;
-- Write Command
ELSIF Write_enable = '1' THEN
IF Addr(10) = '1' THEN
Command(0) := WRITE_A;
ELSE
Command(0) := WRITE;
END IF;
Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (0) := TO_BIT (Ba);
IF Data_in_enable = '1' THEN
RW_interrupt_write := '1';
END IF;
END IF;
-- Read or Write with Auto Precharge
IF Addr(10) = '1' THEN
Auto_precharge (TO_INTEGER(Ba)) := '1';
Count_precharge (TO_INTEGER(Ba)) := 0;
IF Read_enable = '1' THEN
Read_precharge (TO_INTEGER(Ba)) := '1';
ELSIF Write_enable = '1' THEN
Write_precharge (TO_INTEGER(Ba)) := '1';
END IF;
END IF;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. BL/2 cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
((Read_enable = '1' OR Write_enable = '1') AND Count_precharge(0) >= 1)) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Auto_precharge(0) := '0';
Read_precharge(0) := '0';
Write_precharge(0) := '0';
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
((Read_enable = '1' OR Write_enable = '1') AND Count_precharge(1) >= 1)) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Auto_precharge(1) := '0';
Read_precharge(1) := '0';
Write_precharge(1) := '0';
END IF;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. tWR cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
(RW_interrupt_write = '1' AND WR_chk(0) >= 1)) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Auto_precharge(0) := '0';
Read_precharge(0) := '0';
Write_precharge(0) := '0';
RW_interrupt_write := '0';
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
(RW_interrupt_write = '1' AND WR_chk(1) >= 1)) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Auto_precharge(1) := '0';
Read_precharge(1) := '0';
Write_precharge(1) := '0';
RW_interrupt_write := '0';
END IF;
END IF;
-- Internal Precharge or Bst
IF Command(0) = PRECH THEN
IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Command(0) = BST THEN
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
IF Data_out_enable = '0' THEN
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
END IF;
-- Detect Read or Write Command
IF Command(0) = READ OR Command(0) = READ_A THEN
Bank := Bank_addr (0);
Col := Col_addr (0);
Col_brst := Col_addr (0);
IF Bank_addr (0) = '0' THEN
Row := B0_row_addr;
ELSE
Row := B1_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '0';
Data_out_enable := '1';
ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
Bank := Bank_addr(0);
Col := Col_addr(0);
Col_brst := Col_addr(0);
IF Bank_addr (0) = '0' THEN
Row := B0_row_addr;
ELSE
Row := B1_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '1';
Data_out_enable := '0';
END IF;
-- DQ (Driver / Receiver)
Row_index := TO_INTEGER (Row);
Col_index := TO_INTEGER (Col);
IF Data_in_enable = '1' THEN
IF Dqm /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = '0' THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank0 (Row_index) (Col_index) := Dq_temp;
ELSIF Bank = '1' THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank1 (Row_index) (Col_index) := Dq_temp;
END IF;
WR_chk(TO_INTEGER(Bank)) := 0;
END IF;
Burst_decode;
ELSIF Data_out_enable = '1' THEN
Init_mem (Bank, Row_index);
IF Bank = '0' THEN
Dq_temp (15 DOWNTO 0) := Bank0 (Row_index) (Col_index);
IF Dqm_reg(0) = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg(0) = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg(0) = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
ELSE
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
END IF;
ELSIF Bank = '1' THEN
Dq_temp (15 DOWNTO 0) := Bank1 (Row_index) (Col_index);
IF Dqm_reg(0) = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg(0) = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg(0) = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
ELSE
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
END IF;
END IF;
Burst_decode;
END IF;
-- Checking internal wires
Pre_chk (0) <= Pc_b0;
Pre_chk (1) <= Pc_b1;
Act_chk (0) <= Act_b0;
Act_chk (1) <= Act_b1;
Dq_in_chk <= Data_in_enable;
Dq_out_chk <= Data_out_enable;
Bank_chk <= Bank;
Row_chk <= Row;
Col_chk <= Col;
END IF;
END PROCESS;
-- Clock timing checks
Clock_check : PROCESS
VARIABLE Clk_low, Clk_high : TIME := 0 ns;
BEGIN
WAIT ON Clk;
IF (Clk = '1' AND NOW >= 10 ns) THEN
ASSERT (NOW - Clk_low >= tCL)
REPORT "tCL violation"
SEVERITY WARNING;
ASSERT (NOW - Clk_high >= tCK)
REPORT "tCK violation"
SEVERITY WARNING;
Clk_high := NOW;
ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
ASSERT (NOW - Clk_high >= tCH)
REPORT "tCH violation"
SEVERITY WARNING;
Clk_low := NOW;
END IF;
END PROCESS;
-- Setup timing checks
Setup_check : PROCESS
BEGIN
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tCKS)
REPORT "CKE Setup time violation -- tCKS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tCMS)
REPORT "CS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tCMS)
REPORT "CAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tCMS)
REPORT "RAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tCMS)
REPORT "WE# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT >= tCMS)
REPORT "Dqm Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tAS)
REPORT "ADDR Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tAS)
REPORT "BA Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Dq'LAST_EVENT >= tDS)
REPORT "Dq Setup time violation -- tDS"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Hold timing checks
Hold_check : PROCESS
BEGIN
WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
IF Clk'DELAYED (tCKH) = '1' THEN
ASSERT(Cke'LAST_EVENT > tCKH)
REPORT "CKE Hold time violation -- tCKH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tCMH) = '1' THEN
ASSERT(Cs_n'LAST_EVENT > tCMH)
REPORT "CS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT > tCMH)
REPORT "CAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT > tCMH)
REPORT "RAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT > tCMH)
REPORT "WE# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT > tCMH)
REPORT "Dqm Hold time violation -- tCMH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tAH) = '1' THEN
ASSERT(Addr'LAST_EVENT > tAH)
REPORT "ADDR Hold time violation -- tAH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT > tAH)
REPORT "BA Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tDH) = '1' THEN
ASSERT(Dq'LAST_EVENT > tDH)
REPORT "DQ Hold time violation -- tDH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
lib/models/memory/sdram/mt48lc1m16a1/mti_pkg.vhd
+143
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@@ -0,0 +1,143 @@
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE mti_pkg IS
FUNCTION TO_INTEGER (input : BIT) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to INTEGER
FUNCTION TO_INTEGER (input : BIT) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver integer to bit_vector
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN
outputlen := 32;
offset := output'LENGTH - 32;
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0';
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1';
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH;
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0';
ELSE
output(output'HIGH-j-offset) := '1';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0';
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1';
ELSE
output(output'HIGH-j-offset) := '0';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1';
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
lib/models/memory/sdram/mt48lc1m16a1/readme.txt
+14
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@@ -0,0 +1,14 @@
To operate the test bench for the Micron SDRAM VHDL model, follow the directions
given below:
1. Be sure all supporting files for the SDRAM are compiled into your library:
util1164.vhd
stdlogar.vhd
io_utils.vhd
mti_pkg.vhd
2. Next, compile the mt48lc1m16a1.vhd file and the test.vhd file.
3. Simulate the "tb" architecture. This is the testbench for the SDRAM.
lib/models/memory/sdram/mt48lc1m16a1/stdlogar.vhd
+2247
View File
File diff suppressed because it is too large Load Diff
lib/models/memory/sdram/mt48lc1m16a1/test.txt
+69
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@@ -0,0 +1,69 @@
0 ns 1 1 1 1 1 00 0 0 -100
22 ns 1 1 1 1 1 00 0 0 -100
32 ns 1 1 1 1 1 00 0 0 -100
42 ns 1 1 1 1 1 00 0 0 -100
52 ns 1 1 1 1 1 00 0 0 -100
62 ns 1 1 1 1 1 00 0 0 -100
72 ns 1 0 0 1 0 00 0 1024 -100
82 ns 1 1 1 1 1 00 0 0 -100
92 ns 1 1 1 1 1 00 0 0 -100
102 ns 1 0 0 0 1 00 0 0 -100
112 ns 1 1 1 1 1 00 0 0 -100
122 ns 1 1 1 1 1 00 0 0 -100
132 ns 1 1 1 1 1 00 0 0 -100
142 ns 1 1 1 1 1 00 0 0 -100
152 ns 1 1 1 1 1 00 0 0 -100
162 ns 1 1 1 1 1 00 0 0 -100
172 ns 1 1 1 1 1 00 0 0 -100
182 ns 1 1 1 1 1 00 0 0 -100
192 ns 1 0 0 0 1 00 0 0 -100
202 ns 1 1 1 1 1 00 0 0 -100
212 ns 1 1 1 1 1 00 0 0 -100
222 ns 1 1 1 1 1 00 0 0 -100
232 ns 1 1 1 1 1 00 0 0 -100
242 ns 1 1 1 1 1 00 0 0 -100
252 ns 1 1 1 1 1 00 0 0 -100
262 ns 1 1 1 1 1 00 0 0 -100
272 ns 1 1 1 1 1 00 0 0 -100
282 ns 1 0 0 0 0 00 0 51 -100
292 ns 1 1 1 1 1 00 0 0 -100
302 ns 1 1 1 1 1 00 0 0 -100
312 ns 1 0 0 1 1 00 0 0 -100
322 ns 1 1 1 1 1 00 0 0 -100
332 ns 1 1 1 1 1 00 0 0 -100
342 ns 1 0 1 0 0 00 0 1024 100
352 ns 1 1 1 1 1 00 0 0 101
362 ns 1 1 1 1 1 00 0 0 102
372 ns 1 1 1 1 1 00 0 0 103
382 ns 1 1 1 1 1 00 0 0 104
392 ns 1 0 0 1 1 00 1 0 105
402 ns 1 1 1 1 1 00 0 0 106
412 ns 1 1 1 1 1 00 0 0 107
422 ns 1 0 1 0 0 00 1 1024 200
432 ns 1 1 1 1 1 00 0 0 201
442 ns 1 1 1 1 1 00 0 0 202
452 ns 1 1 1 1 1 00 0 0 203
462 ns 1 1 1 1 1 00 0 0 204
472 ns 1 0 0 1 1 00 0 0 205
482 ns 1 1 1 1 1 00 0 0 206
492 ns 1 1 1 1 1 00 0 0 207
502 ns 1 0 1 0 1 00 0 1024 -100
512 ns 1 1 1 1 1 00 0 0 -100
522 ns 1 1 1 1 1 00 0 0 -100
532 ns 1 1 1 1 1 00 0 0 -100
542 ns 1 1 1 1 1 00 0 0 -100
552 ns 1 0 0 1 1 00 1 0 -100
562 ns 1 1 1 1 1 00 0 0 -100
572 ns 1 1 1 1 1 00 0 0 -100
582 ns 1 0 1 0 1 00 1 1024 -100
592 ns 1 1 1 1 1 00 0 0 -100
602 ns 1 1 1 1 1 00 0 0 -100
612 ns 1 1 1 1 1 00 0 0 -100
622 ns 1 1 1 1 1 00 0 0 -100
632 ns 1 1 1 1 1 00 0 0 -100
642 ns 1 1 1 1 1 00 0 0 -100
652 ns 1 1 1 1 1 00 0 0 -100
662 ns 1 1 1 1 1 00 0 0 -100
672 ns 1 1 1 1 1 00 0 0 -100
682 ns 1 1 1 1 1 00 0 0 -100
692 ns 1 1 1 1 1 00 0 0 -100
lib/models/memory/sdram/mt48lc1m16a1/test.vhd
+168
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LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.ALL;
USE work.std_logic_arith.ALL;
USE work.util_1164.ALL;
USE std.textio.ALL;
USE work.mti_pkg.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE test OF tb IS
CONSTANT addr_bits : INTEGER := 11;
CONSTANT clk_start : time := 5 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT continue_time : time := 10 ns;
CONSTANT data_bits : INTEGER := 16;
COMPONENT mt48lc1m16a1
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC := '0';
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '0';
Cs_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '0';
Ras_n : IN STD_LOGIC := '0';
We_n : IN STD_LOGIC := '0';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END COMPONENT;
FOR ALL : mt48lc1m16a1 USE ENTITY work.mt48lc1m16a1 (behave);
SIGNAL pDq : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
SIGNAL pAddr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
SIGNAL pBa : STD_LOGIC;
SIGNAL pClk : STD_LOGIC;
SIGNAL pCke : STD_LOGIC;
SIGNAL pCs : STD_LOGIC;
SIGNAL pCas : STD_LOGIC;
SIGNAL pRas : STD_LOGIC;
SIGNAL pWe : STD_LOGIC;
SIGNAL pDqm : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL stim_done : boolean := false;
SIGNAL clk_done : boolean := false;
BEGIN
u1: mt48lc1m16a1
PORT MAP(
Dq => pDq,
Addr => pAddr,
Ba => pBa,
Clk => pClk,
Cke => pCke,
Cs_n => pCs,
Ras_n => pRas,
Cas_n => pCas,
We_n => pWe,
Dqm => pDqm
);
stimulator : PROCESS
FILE stim_file:text IS IN "test.txt";
VARIABLE l : line;
VARIABLE time_var : TIME;
VARIABLE pCke_var : STD_LOGIC;
VARIABLE pCs_var : STD_LOGIC;
VARIABLE pRas_var : STD_LOGIC;
VARIABLE PCas_var : STD_LOGIC;
VARIABLE pWe_var : STD_LOGIC;
VARIABLE pDqm_var : STD_LOGIC_VECTOR (1 DOWNTO 0);
VARIABLE pBa_var : STD_LOGIC;
VARIABLE pAddr_var : INTEGER;
VARIABLE pDq_var : INTEGER; -- -100 is converted to hi-Z state
VARIABLE pMa_var_vect : STD_LOGIC_VECTOR(addr_bits - 1 DOWNTO 0);
CONSTANT HiZ : STD_LOGIC_VECTOR(data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
BEGIN
WHILE not ENDFILE(stim_file) LOOP
readline(stim_file,l);
IF l'length > 0 THEN
read(l, time_var);
read(l, pCke_var);
read(l, pCs_var);
read(l, pRas_var);
read(l, pCas_var);
read(l, pWe_var);
read(l, pDqm_var);
read(l, pBa_var);
read(l, pAddr_var);
read(l, pDq_var);
IF now > time_var THEN
ASSERT false
REPORT "Detected a time in the stim file that is in the past"
SEVERITY error;
ELSE
WAIT FOR time_var-now;
IF pWe_var='1' THEN
pCke <= pCke_var;
pCs <= pCs_var;
pRas <= pRas_var;
pCas <= pCas_var;
pWe <= pWe_var;
pDqm <= pDqm_var;
pBa <= pBa_var;
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
ELSE
pCke <= pCke_var;
pCs <= pCs_var;
pRas <= pRas_var;
pCas <= pCas_var;
pWe <= pWe_var;
pDqm <= pDqm_var;
pBa <= pBa_var;
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
END IF;
END IF;
END IF;
END LOOP;
ASSERT false
REPORT "End of Stimulation File Detected!"
SEVERITY note;
stim_done <= true;
WAIT;
END PROCESS;
clock : PROCESS
VARIABLE done_time : time;
BEGIN
pclk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
done_time := now+continue_time;
WHILE now < done_time LOOP --one last clock to finish last command
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT false
REPORT "Suspending clock activity"
SEVERITY note;
clk_done <= true;
WAIT;
END PROCESS;
END test;
lib/models/memory/sdram/mt48lc1m16a1/util1164.vhd
+124
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@@ -0,0 +1,124 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE STD.textio.ALL;
PACKAGE util_1164 IS
PROCEDURE read(l: INOUT line; value: OUT std_logic);
PROCEDURE read(l: INOUT line; value: OUT std_logic_vector);
PROCEDURE write(l: INOUT line; value: IN std_logic_vector;
JUSTIFIED: IN SIDE := right;
FIELD: IN WIDTH := 0);
PROCEDURE Grow_line(L : inout LINE; incr : in integer);
END util_1164;
PACKAGE BODY util_1164 IS
FUNCTION white_space(value:character) RETURN boolean IS
VARIABLE result:boolean;
BEGIN
IF (value = ' ') OR (value = HT) THEN
RETURN true;
ELSE
RETURN false;
END IF;
END white_space;
PROCEDURE read(l: INOUT line; value: OUT std_logic) IS
VARIABLE char_var: character:= ' ';
BEGIN
WHILE l'LENGTH > 0 LOOP
read(l,char_var);
IF NOT white_space(char_var) THEN
EXIT;
END IF;
END LOOP;
IF white_space(char_var) THEN
ASSERT false REPORT "No std_logic value found in file"
SEVERITY error;
value := 'X';
RETURN;
END IF;
CASE char_var IS
WHEN 'U'|'u' => value := 'U';
WHEN '0' => value := '0';
WHEN '1' => value := '1';
WHEN 'X'|'x' => value := 'X';
WHEN 'L'|'l' => value := 'L';
WHEN 'H'|'h' => value := 'H';
WHEN 'W'|'w' => value := 'W';
WHEN 'Z'|'z' => value := 'Z';
WHEN '-' => value := '-';
WHEN OTHERS =>
ASSERT false REPORT "Unrecognized value read for std_logic"
SEVERITY error;
value := 'X';
END CASE;
END read;
PROCEDURE read(l: INOUT line; value: OUT std_logic_vector) IS
BEGIN
FOR i IN value'HIGH DOWNTO value'LOW LOOP
IF l'LENGTH > 0 THEN
read(l,value(i));
ELSE
ASSERT false REPORT "Not enough values for std_logic_vector in file"
SEVERITY error;
RETURN;
END IF;
END LOOP;
END read;
procedure Grow_line(L : inout LINE; incr : in integer)
is
variable old_L : LINE := L;
variable bfp: integer; -- Blank fill pointer.
begin
assert incr > 0
report "Textio: Grow_line called with zero increment."
severity error;
if L = null then
bfp := 0;
L := new string(1 to incr);
else
bfp := old_L'high;
L := new string(old_L'low to old_L'high + incr);
L(old_L'low to old_L'high) := old_L.all;
Deallocate(old_L);
end if;
for i in 1 to incr loop
L(bfp + i) := ' ';
end loop;
end;
PROCEDURE write(l: INOUT line; value: IN std_logic_vector;
JUSTIFIED: IN SIDE := right;
FIELD: IN WIDTH := 0) IS
variable fw: integer := VALUE'length;
variable bp: integer;
variable offset: integer := 0;
alias normal : std_logic_vector(0 to value'length - 1) is value;
begin
if L /= null then
bp := L'high + 1;
else bp := 1;
end if;
if FIELD > VALUE'length then
fw := FIELD;
if JUSTIFIED = right then
offset := fw - VALUE'length;
end if;
end if;
Grow_line(L, fw);
for i in normal'range loop
L(bp + i + offset) := character'val(
std_logic'pos(normal(i)) + character'pos('0'));
end loop;
end;
END util_1164;
lib/models/memory/sdram/mt48lc1m16a1/vec_gen.vhd
+369
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@@ -0,0 +1,369 @@
-------------------------------------------------------------------------------
-- --
-- This is a data generator for the testbench for Micron's Synchronous --
-- DRAM. This generator reads a text file line-by-line and generates --
-- a file of test vectors that is then read by the testbench and --
-- applied to the part. --
-- --
-- This VHDL program creates a text file of test vectors that is used by the --
-- test bench. Place your commands in a file (a copy of VEC_GEN.VHD) and run --
-- VEC_GEN.VHD in your VHDL simulator (make sure you have compiled this --
-- package prior to running the program VEC_GEN.VHD). This will produce the --
-- vectors that are required to run the included testbench. Change the name --
-- of the vector file to save your vectors in separate files. The default --
-- file name for the output vectors generated from this pacakage is --
-- "test.txt." --
-- --
-- Now compile and run the testbench program embedtb.vhd. The testbench uses --
-- the default test.txt as input vectors. --
-- --
-- --
-- Copyright 1997 Micron Technology, Inc. --
-- --
-------------------------------------------------------------------------------
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.io_utils.all;
PACKAGE generate_vectors IS
CONSTANT set_up : TIME;
CONSTANT hold : TIME;
CONSTANT cycle_start : TIME;
SIGNAL cycle : INTEGER := 0;
SIGNAL sim_time : TIME := 0 ns;
FILE output_file:TEXT IS OUT "test.txt";
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT;
first_data : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT; data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE precharge(bank : IN BIT; address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT; cs : IN BIT);
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE auto_refresh;
PROCEDURE next_cycle(SIGNAL clk : IN BIT);
PROCEDURE load_array(load : IN BIT);
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT);
PROCEDURE unload_array(row_start : IN INTEGER; row_end : IN INTEGER; bank : IN BIT);
END generate_vectors;
PACKAGE BODY generate_vectors IS
CONSTANT set_up : TIME := 3 ns;
CONSTANT hold : TIME := 1 ns;
CONSTANT cycle_start : TIME := 0 ns;
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT; first_data : IN INTEGER;
dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, first_data, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT; data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, row_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE precharge(bank : IN BIT; address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT; cs : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT := '0';
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, cs, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, 0, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE auto_refresh IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, 0, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE next_cycle(SIGNAL clk : IN BIT) IS
BEGIN
WAIT UNTIL clk = '1';
END;
PROCEDURE load_array(load : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, 0, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 1, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE unload_array(row_start : IN INTEGER; row_end : IN INTEGER; bank : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 1, right, 4); --unload
--write(l, row_start, right, 6); --row_address_start
--write(l, row_end, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, 0, right, 4); --Ba
write(l, op_code, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
END generate_vectors;
lib/models/memory/sdram/mt48lc32m4a2/base.do
+5
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@@ -0,0 +1,5 @@
vcom util1164.vhd
vcom stdlogar.vhd
vcom io_utils.vhd
vcom mti_pkg.vhd
lib/models/memory/sdram/mt48lc32m4a2/ed_comnd.vhd
+345
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@@ -0,0 +1,345 @@
---------------------------------------------------------------------------------
--COMMAND FORMAT --
-- --
-- write(column address(integer), bank(bit_vector), first data(integer), dqm(bit), cke(bit));--
-- read(column address(integer), bank(bit_vector), dqm(bit), cke(bit)); --
-- active(row address(integer), bank(bit_vector), data bus (integer), dqm(bit), cke(bit));--
-- precharge(bank(bit_vector), address (integer), data bus(integer), dqm(bit), cke(bit)); --
-- nop(data bus(integer), dqm(bit), cke(bit), cs(bit)); --
-- burst_term(data bus(integer), dqm(bit), cke(bit)); --
-- load_array('1'); --
-- load_mode_reg(register(integer), cke(bit)); --
-- next_cycle(clk); This is used after every command(incl. nop) to clock --
-- at the correct clock frequency entered in the clock --
-- period constant below --
-- unload_array(row_start(integer), row_end(integer), bank(bit_vector)) --
-- load_mode_reg(op_code(integer)) --
-- --
---------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.generate_vectors.all;
ENTITY vector_generate IS
END vector_generate;
ARCHITECTURE vector_generate OF vector_generate IS
SIGNAL stim_done : BOOLEAN := FALSE;
SIGNAL clk : BIT := '0';
CONSTANT clk_start : time := 15 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT Z : INTEGER := -100;
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1' AND clk'EVENT;
--------------------ENTER COMMANDS BELOW THIS LINE-----------------------------
--******************DO NOT USE -100 FOR A DQ VALUE*************************----
--*******************Z WILL PLACE HI-Z ON THE BUS**************************----
--*******USE next_cycle(clk) FOR ADVANCING TO NEXT CLOCK CYCLE*************----
nop(Z, '0', '1', '1'); --Always begin with one nop when using Micron's testbench
--next_cycle(clk);
--load_array('1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
precharge("00", 1024, Z, '0', '1');
FOR i IN 1 to 2 LOOP
next_cycle(clk);
nop(Z, '0', '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, '0', '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, '0', '1', '1');
END LOOP;
next_cycle(clk);
load_mode_reg(51, '1'); -- 19 / 35 / 51 -> lat=3,bl=8,mode=seq
next_cycle(clk);
nop(Z, '0', '1', '1');
-- Write Section
next_cycle(clk);
active(0, "00", Z, '0', '1'); -- Activate Bank 0
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk); -- Write Bank 0
write(10, "00", 0, '0', '1');
next_cycle(clk);
nop(1, '0', '1', '1');
next_cycle(clk);
active(0, "01", 2, '0', '1'); -- Activate Bank 1
next_cycle(clk);
nop(3, '0', '1', '1');
next_cycle(clk);
nop(4, '0', '1', '1');
next_cycle(clk);
nop(5, '0', '1', '1');
next_cycle(clk);
nop(6, '0', '1', '1');
next_cycle(clk);
nop(7, '0', '1', '1');
next_cycle(clk);
write(20, "01", 8, '0', '1'); -- Write Bank 1
next_cycle(clk);
precharge("00", 0, 9, '0', '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", 10, '0', '1'); -- Activate Bank 2
next_cycle(clk);
nop(11, '0', '1', '1');
next_cycle(clk);
nop(12, '0', '1', '1');
next_cycle(clk);
nop(13, '0', '1', '1');
next_cycle(clk);
nop(14, '0', '1', '1');
next_cycle(clk);
nop(15, '0', '1', '1');
next_cycle(clk);
write(30, "10", 0, '0', '1'); -- Write Bank 2
next_cycle(clk);
precharge("01", 0, 1, '0', '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", 2, '0', '1'); -- Activate Bank 3
next_cycle(clk);
nop(3, '0', '1', '1');
next_cycle(clk);
nop(4, '0', '1', '1');
next_cycle(clk);
nop(5, '0', '1', '1');
next_cycle(clk);
nop(6, '0', '1', '1');
next_cycle(clk);
nop(7, '0', '1', '1');
next_cycle(clk);
write(40, "11", 8, '0', '1'); -- Write Bank 3
next_cycle(clk);
precharge("10", 0, 9, '0', '1'); -- Precharge Bank 2
next_cycle(clk);
active(0, "00", 10, '0', '1'); -- Activate Bank 0
next_cycle(clk);
nop(11, '0', '1', '1');
next_cycle(clk);
nop(12, '0', '1', '1');
next_cycle(clk);
nop(13, '0', '1', '1');
next_cycle(clk);
nop(14, '0', '1', '1');
next_cycle(clk);
nop(15, '0', '1', '1');
-- Read Section
next_cycle(clk);
read(10, "00", '0', '1'); -- Read Bank 0
next_cycle(clk);
precharge("11", 0, Z, '0', '1'); -- Precharge Bank 3
next_cycle(clk);
active(0, "01", Z, '0', '1'); -- Activate Bank 1
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
read(20, "01", '0', '1'); -- Read Bank 1
next_cycle(clk);
precharge("00", 0, Z, '0', '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", Z, '0', '1'); -- Activate Bank 2
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
read(30, "10", '0', '1'); -- Read Bank 2
next_cycle(clk);
precharge("01", 0, Z, '0', '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", Z, '0', '1'); -- Activate Bank 3
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
read(40, "11", '0', '1'); -- Read Bank 3
next_cycle(clk);
precharge("10", 0, Z, '0', '1'); -- Precharge Bank 2
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
precharge("11", 0, Z, '0', '1'); -- Precharge Bank 3
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
--next_cycle(clk);
--unload_array(0, 0, '0');
next_cycle(clk);
nop(Z, '0', '1', '1');
stim_done <= TRUE; --always include this line at the end of your stimulus
-------------------------------------------------------------------------------
--*************************************************************************----
END PROCESS;
clock:
PROCESS
VARIABLE done_time : time;
VARIABLE cycle_var : integer := 0;
BEGIN
cycle <= 0;
clk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
clk <= '1';
cycle <= cycle_var;
WAIT for clk_period/2;
cycle_var := cycle_var + 1;
clk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT (FALSE)
REPORT "Test Vectors Generated"
SEVERITY note;
WAIT;
END PROCESS;
END;
lib/models/memory/sdram/mt48lc32m4a2/io_utils.vhd
+266
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@@ -0,0 +1,266 @@
LIBRARY ieee;
USE std.textio.ALL;
USE ieee.std_logic_1164.ALL;
PACKAGE io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0);
TYPE radix IS (binary, octal, decimal, hex);
-- read a number from the line
-- use this if you have hex numbers that are not in VHDL pound-sign format
PROCEDURE read(l : INOUT line; value : OUT integer; radix : IN positive);
-- read a number that might be in VHDL pound-sign format
PROCEDURE read_based(l : INOUT line; value : OUT integer);
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
END io_utils;
PACKAGE BODY io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0)
IS
BEGIN
write(l, value, justified, field);
END;
PROCEDURE shrink_line(l : INOUT line; pos : integer) IS
VARIABLE tmpl : line;
BEGIN
tmpl := l;
l := NEW string'(tmpl(pos TO tmpl'high));
deallocate(tmpl);
END;
PROCEDURE read(l : INOUT line;
value : OUT integer;
radix : IN positive)
IS
CONSTANT not_digit : integer := -999;
-- convert a character to a value from 0 to 15
FUNCTION digit_value(c : character) RETURN integer IS
BEGIN
IF (c >= '0') AND (c <= '9') THEN
RETURN (character'pos(c) - character'pos('0'));
ELSIF (c >= 'a') AND (c <= 'f') THEN
RETURN (character'pos(c) - character'pos('a') + 10);
ELSIF (c >= 'A') AND (c <= 'F') THEN
RETURN (character'pos(c) - character'pos('A') + 10);
ELSE
RETURN not_digit;
END IF;
END;
-- skip leading white space in the line
PROCEDURE skip_white(VARIABLE l : IN line; pos : OUT integer) IS
BEGIN
pos := l'low;
FOR i IN l'low TO l'high LOOP
CASE l(i) IS
WHEN ' ' | ht =>
pos := i + 1;
WHEN OTHERS =>
EXIT;
END CASE;
END LOOP;
END;
VARIABLE digit : integer;
VARIABLE result : integer := 0;
VARIABLE pos : integer;
BEGIN
-- skip white space
skip_white(l, pos);
-- calculate the value
FOR i IN pos TO l'right LOOP
digit := digit_value(l(i));
EXIT WHEN (digit = not_digit) OR (digit >= radix);
result := result * radix + digit;
pos := i + 1;
END LOOP;
value := result;
-- remove the "used" characters from the line
shrink_line(l, pos);
END;
PROCEDURE read_based(l : INOUT line; value : OUT integer) IS
VARIABLE digit : integer;
VARIABLE num : integer;
VARIABLE base : integer;
BEGIN
read(l, num, 10);
IF (l'length > 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
base := num;
read(l, num, base);
IF (l'length >= 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
END IF;
END IF;
value := num;
END;
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_int(bv : std_logic_vector) RETURN integer
IS
VARIABLE result : integer := 0;
BEGIN
FOR i IN bv'RANGE LOOP
result := result * 2;
IF (bv(i) = '1') THEN
result := result + 1;
END IF;
END LOOP;
RETURN result;
END;
TYPE array_of_widths IS ARRAY(radix) OF natural;
CONSTANT nibble_widths : array_of_widths := (
binary => 1,
octal => 3,
hex => 4,
decimal=> 32);
CONSTANT hex_digit : string(1 TO 16) := "0123456789ABCDEF";
ALIAS input_val : std_logic_vector(value'length DOWNTO 1) IS value;
CONSTANT nibble_width : natural := nibble_widths(base);
CONSTANT result_width : natural := (value'length + nibble_width - 1)/nibble_width;
VARIABLE result : string(1 TO result_width); -- longest possible value
VARIABLE result_pos : positive := 1;
VARIABLE nibble_val : integer;
VARIABLE bitcnt : integer;
BEGIN
IF base = decimal THEN
write(l, to_int(value), justified, field, base, use_pound);
RETURN;
END IF;
bitcnt := value'length MOD nibble_width;
IF (bitcnt = 0) THEN
bitcnt := nibble_width;
END IF;
FOR i IN input_val'RANGE LOOP
nibble_val := nibble_val * 2;
IF (input_val(i) = '1') THEN
nibble_val := nibble_val + 1;
END IF;
bitcnt := bitcnt - 1;
IF (bitcnt = 0) THEN
result(result_pos) := hex_digit(nibble_val + 1);
result_pos := result_pos + 1;
nibble_val := 0;
bitcnt := nibble_width;
END IF;
END LOOP;
write(l, result, justified, field);
END;
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_bv(int : integer) RETURN std_logic_vector
IS
VARIABLE bv : std_logic_vector(32 DOWNTO 1) := (OTHERS => '0');
VARIABLE pos : integer := 0;
VARIABLE tmpval : integer := int;
BEGIN
FOR i IN 1 TO 32 LOOP
pos := pos + 1;
IF (tmpval MOD 2) = 1 THEN
bv(i) := '1';
END IF;
tmpval := tmpval / 2;
EXIT WHEN tmpval = 0;
END LOOP;
RETURN bv(pos DOWNTO 1);
END;
VARIABLE tmp : line;
BEGIN
IF (base = decimal) THEN
IF (use_pound) THEN
write_string(tmp, "10#");
END IF;
write(tmp, value);
IF (use_pound) THEN
write_string(tmp, "#");
END IF;
write(l, tmp.ALL, justified, field);
deallocate(tmp);
ELSE
write(l, to_bv(value), justified, field, base, use_pound);
END IF;
END;
END io_utils;
-- test the hex number reader
--ENTITY test IS END;
--USE std.textio.ALL;
--USE work.io_utils.ALL;
--ARCHITECTURE hex_test OF test IS
--BEGIN
-- PROCESS
-- VARIABLE val : integer;
-- FILE myfile : text IS IN "values";
-- VARIABLE inline : line;
-- VARIABLE outline : line;
-- BEGIN
-- WHILE NOT endfile(myfile) LOOP
-- readline(myfile, inline);
-- write(outline, inline.ALL);
--
-- read_based(inline, val);
-- write_string(outline, " binary: ");
-- write(outline, val, base => binary);
-- write_string(outline, " octal: ");
-- write(outline, val, base => octal);
-- write_string(outline, " decimal: ");
-- write(outline, val, base => decimal);
-- write_string(outline, " hex: ");
-- write(outline, val, base => hex);
-- writeline(output, outline);
-- END LOOP;
-- WAIT;
-- END PROCESS;
--END;
lib/models/memory/sdram/mt48lc32m4a2/mt48lc32m4a2.vhd
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lib/models/memory/sdram/mt48lc32m4a2/mti_pkg.vhd
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--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE mti_pkg IS
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver integer to bit_vector
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN
outputlen := 32;
offset := output'LENGTH - 32;
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0';
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1';
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH;
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0';
ELSE
output(output'HIGH-j-offset) := '1';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0';
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1';
ELSE
output(output'HIGH-j-offset) := '0';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1';
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
lib/models/memory/sdram/mt48lc32m4a2/readme.txt
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To operate the test bench for the Micron SDRAM VHDL model, follow the directions
given below:
1. Be sure all supporting files for the SDRAM are compiled into your library:
util1164.vhd
stdlogar.vhd
io_utils.vhd
mti_pkg.vhd
2. Next, compile the mt48lc32m4a2.vhd file and the test.vhd file.
3. Simulate the "tb" architecture. This is the testbench for the 128Mb SDRAM.
lib/models/memory/sdram/mt48lc32m4a2/stdlogar.vhd
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lib/models/memory/sdram/mt48lc32m4a2/test.do
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vcom mt48lc32m4a2.vhd
vcom test.vhd
vsim tb
do wave.do
run -all
lib/models/memory/sdram/mt48lc32m4a2/test.txt
+98
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@@ -0,0 +1,98 @@
0 ns 1 1 1 1 1 0 00 0 -100
22 ns 1 1 1 1 1 0 00 0 -100
32 ns 1 1 1 1 1 0 00 0 -100
42 ns 1 1 1 1 1 0 00 0 -100
52 ns 1 1 1 1 1 0 00 0 -100
62 ns 1 0 0 1 0 0 00 1024 -100
72 ns 1 1 1 1 1 0 00 0 -100
82 ns 1 1 1 1 1 0 00 0 -100
92 ns 1 0 0 0 1 0 00 0 -100
102 ns 1 1 1 1 1 0 00 0 -100
112 ns 1 1 1 1 1 0 00 0 -100
122 ns 1 1 1 1 1 0 00 0 -100
132 ns 1 1 1 1 1 0 00 0 -100
142 ns 1 1 1 1 1 0 00 0 -100
152 ns 1 1 1 1 1 0 00 0 -100
162 ns 1 1 1 1 1 0 00 0 -100
172 ns 1 1 1 1 1 0 00 0 -100
182 ns 1 0 0 0 1 0 00 0 -100
192 ns 1 1 1 1 1 0 00 0 -100
202 ns 1 1 1 1 1 0 00 0 -100
212 ns 1 1 1 1 1 0 00 0 -100
222 ns 1 1 1 1 1 0 00 0 -100
232 ns 1 1 1 1 1 0 00 0 -100
242 ns 1 1 1 1 1 0 00 0 -100
252 ns 1 1 1 1 1 0 00 0 -100
262 ns 1 1 1 1 1 0 00 0 -100
272 ns 1 0 0 0 0 0 00 51 -100
282 ns 1 1 1 1 1 0 00 0 -100
292 ns 1 0 0 1 1 0 00 0 -100
302 ns 1 1 1 1 1 0 00 0 -100
312 ns 1 0 1 0 0 0 00 10 0
322 ns 1 1 1 1 1 0 00 0 1
332 ns 1 0 0 1 1 0 01 0 2
342 ns 1 1 1 1 1 0 00 0 3
352 ns 1 1 1 1 1 0 00 0 4
362 ns 1 1 1 1 1 0 00 0 5
372 ns 1 1 1 1 1 0 00 0 6
382 ns 1 1 1 1 1 0 00 0 7
392 ns 1 0 1 0 0 0 01 20 8
402 ns 1 0 0 1 0 0 00 0 9
412 ns 1 0 0 1 1 0 10 0 10
422 ns 1 1 1 1 1 0 00 0 11
432 ns 1 1 1 1 1 0 00 0 12
442 ns 1 1 1 1 1 0 00 0 13
452 ns 1 1 1 1 1 0 00 0 14
462 ns 1 1 1 1 1 0 00 0 15
472 ns 1 0 1 0 0 0 10 30 0
482 ns 1 0 0 1 0 0 01 0 1
492 ns 1 0 0 1 1 0 11 0 2
502 ns 1 1 1 1 1 0 00 0 3
512 ns 1 1 1 1 1 0 00 0 4
522 ns 1 1 1 1 1 0 00 0 5
532 ns 1 1 1 1 1 0 00 0 6
542 ns 1 1 1 1 1 0 00 0 7
552 ns 1 0 1 0 0 0 11 40 8
562 ns 1 0 0 1 0 0 10 0 9
572 ns 1 0 0 1 1 0 00 0 10
582 ns 1 1 1 1 1 0 00 0 11
592 ns 1 1 1 1 1 0 00 0 12
602 ns 1 1 1 1 1 0 00 0 13
612 ns 1 1 1 1 1 0 00 0 14
622 ns 1 1 1 1 1 0 00 0 15
632 ns 1 0 1 0 1 0 00 10 -100
642 ns 1 0 0 1 0 0 11 0 -100
652 ns 1 0 0 1 1 0 01 0 -100
662 ns 1 1 1 1 1 0 00 0 -100
672 ns 1 1 1 1 1 0 00 0 -100
682 ns 1 1 1 1 1 0 00 0 -100
692 ns 1 1 1 1 1 0 00 0 -100
702 ns 1 1 1 1 1 0 00 0 -100
712 ns 1 0 1 0 1 0 01 20 -100
722 ns 1 0 0 1 0 0 00 0 -100
732 ns 1 0 0 1 1 0 10 0 -100
742 ns 1 1 1 1 1 0 00 0 -100
752 ns 1 1 1 1 1 0 00 0 -100
762 ns 1 1 1 1 1 0 00 0 -100
772 ns 1 1 1 1 1 0 00 0 -100
782 ns 1 1 1 1 1 0 00 0 -100
792 ns 1 0 1 0 1 0 10 30 -100
802 ns 1 0 0 1 0 0 01 0 -100
812 ns 1 0 0 1 1 0 11 0 -100
822 ns 1 1 1 1 1 0 00 0 -100
832 ns 1 1 1 1 1 0 00 0 -100
842 ns 1 1 1 1 1 0 00 0 -100
852 ns 1 1 1 1 1 0 00 0 -100
862 ns 1 1 1 1 1 0 00 0 -100
872 ns 1 0 1 0 1 0 11 40 -100
882 ns 1 0 0 1 0 0 10 0 -100
892 ns 1 1 1 1 1 0 00 0 -100
902 ns 1 1 1 1 1 0 00 0 -100
912 ns 1 1 1 1 1 0 00 0 -100
922 ns 1 1 1 1 1 0 00 0 -100
932 ns 1 1 1 1 1 0 00 0 -100
942 ns 1 1 1 1 1 0 00 0 -100
952 ns 1 0 0 1 0 0 11 0 -100
962 ns 1 1 1 1 1 0 00 0 -100
972 ns 1 1 1 1 1 0 00 0 -100
982 ns 1 1 1 1 1 0 00 0 -100
lib/models/memory/sdram/mt48lc32m4a2/test.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.ALL;
USE work.std_logic_arith.ALL;
USE work.util_1164.ALL;
USE work.mti_pkg.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE test OF tb IS
CONSTANT addr_bits : INTEGER := 12;
CONSTANT data_bits : INTEGER := 4;
CONSTANT clk_start : time := 5 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT continue_time : time := 10 ns;
COMPONENT mt48lc32m4a2
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC := '0'
);
END COMPONENT;
FOR ALL : mt48lc32m4a2 USE ENTITY work.mt48lc32m4a2 (behave);
SIGNAL pDq : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
SIGNAL pAddr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
SIGNAL pBa : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pClk : STD_LOGIC;
SIGNAL pCke : STD_LOGIC;
SIGNAL pCs : STD_LOGIC;
SIGNAL pCas : STD_LOGIC;
SIGNAL pRas : STD_LOGIC;
SIGNAL pWe : STD_LOGIC;
SIGNAL pDqm : STD_LOGIC;
SIGNAL stim_done : boolean := false;
SIGNAL clk_done : boolean := false;
BEGIN
u1: mt48lc32m4a2
PORT MAP(
Dq => pDq,
Addr => pAddr,
Ba => pBa,
Clk => pClk,
Cke => pCke,
Cs_n => pCs,
Ras_n => pRas,
Cas_n => pCas,
We_n => pWe,
Dqm => pDqm
);
stimulator : PROCESS
FILE stim_file:text IS IN "test.txt";
--FILE stim_file:text IS IN "test1.txt";
VARIABLE l : line;
VARIABLE time_var : TIME;
VARIABLE pCke_var : STD_LOGIC;
VARIABLE pCs_var : STD_LOGIC;
VARIABLE pRas_var : STD_LOGIC;
VARIABLE PCas_var : STD_LOGIC;
VARIABLE pWe_var : STD_LOGIC;
VARIABLE pDqm_var : STD_LOGIC;
VARIABLE pBa_var : STD_LOGIC_VECTOR (1 DOWNTO 0);
VARIABLE pAddr_var : INTEGER;
VARIABLE pDq_var : INTEGER; -- -100 is converted to hi-Z state
VARIABLE pMa_var_vect : STD_LOGIC_VECTOR(addr_bits - 1 DOWNTO 0);
CONSTANT HiZ : STD_LOGIC_VECTOR(data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
BEGIN
WHILE not ENDFILE(stim_file) LOOP
readline(stim_file,l);
IF l'length > 0 THEN
read(l, time_var);
read(l, pCke_var);
read(l, pCs_var);
read(l, pRas_var);
read(l, pCas_var);
read(l, pWe_var);
read(l, pDqm_var);
read(l, pBa_var);
read(l, pAddr_var);
read(l, pDq_var);
IF now > time_var THEN
ASSERT false
REPORT "Detected a time in the stim file that is in the past"
SEVERITY error;
ELSE
WAIT FOR time_var-now;
IF pWe_var='1' THEN
pCke <= pCke_var;
pCs <= pCs_var;
pRas <= pRas_var;
pCas <= pCas_var;
pWe <= pWe_var;
pDqm <= pDqm_var;
pBa <= pBa_var;
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
ELSE
pCke <= pCke_var;
pCs <= pCs_var;
pRas <= pRas_var;
pCas <= pCas_var;
pWe <= pWe_var;
pDqm <= pDqm_var;
pBa <= pBa_var;
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
END IF;
END IF;
END IF;
END LOOP;
ASSERT false
REPORT "End of Stimulation File Detected!"
SEVERITY note;
stim_done <= true;
WAIT;
END PROCESS;
clock : PROCESS
VARIABLE done_time : time;
BEGIN
pclk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
done_time := now+continue_time;
WHILE now < done_time LOOP --one last clock to finish last command
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT false
REPORT "Suspending clock activity"
SEVERITY note;
clk_done <= true;
WAIT;
END PROCESS;
END test;
lib/models/memory/sdram/mt48lc32m4a2/util1164.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE STD.textio.ALL;
PACKAGE util_1164 IS
PROCEDURE read(l: INOUT line; value: OUT std_logic);
PROCEDURE read(l: INOUT line; value: OUT std_logic_vector);
PROCEDURE write(l: INOUT line; value: IN std_logic_vector;
JUSTIFIED: IN SIDE := right;
FIELD: IN WIDTH := 0);
PROCEDURE Grow_line(L : inout LINE; incr : in integer);
END util_1164;
PACKAGE BODY util_1164 IS
FUNCTION white_space(value:character) RETURN boolean IS
VARIABLE result:boolean;
BEGIN
IF (value = ' ') OR (value = HT) THEN
RETURN true;
ELSE
RETURN false;
END IF;
END white_space;
PROCEDURE read(l: INOUT line; value: OUT std_logic) IS
VARIABLE char_var: character:= ' ';
BEGIN
WHILE l'LENGTH > 0 LOOP
read(l,char_var);
IF NOT white_space(char_var) THEN
EXIT;
END IF;
END LOOP;
IF white_space(char_var) THEN
ASSERT false REPORT "No std_logic value found in file"
SEVERITY error;
value := 'X';
RETURN;
END IF;
CASE char_var IS
WHEN 'U'|'u' => value := 'U';
WHEN '0' => value := '0';
WHEN '1' => value := '1';
WHEN 'X'|'x' => value := 'X';
WHEN 'L'|'l' => value := 'L';
WHEN 'H'|'h' => value := 'H';
WHEN 'W'|'w' => value := 'W';
WHEN 'Z'|'z' => value := 'Z';
WHEN '-' => value := '-';
WHEN OTHERS =>
ASSERT false REPORT "Unrecognized value read for std_logic"
SEVERITY error;
value := 'X';
END CASE;
END read;
PROCEDURE read(l: INOUT line; value: OUT std_logic_vector) IS
BEGIN
FOR i IN value'HIGH DOWNTO value'LOW LOOP
IF l'LENGTH > 0 THEN
read(l,value(i));
ELSE
ASSERT false REPORT "Not enough values for std_logic_vector in file"
SEVERITY error;
RETURN;
END IF;
END LOOP;
END read;
procedure Grow_line(L : inout LINE; incr : in integer)
is
variable old_L : LINE := L;
variable bfp: integer; -- Blank fill pointer.
begin
assert incr > 0
report "Textio: Grow_line called with zero increment."
severity error;
if L = null then
bfp := 0;
L := new string(1 to incr);
else
bfp := old_L'high;
L := new string(old_L'low to old_L'high + incr);
L(old_L'low to old_L'high) := old_L.all;
Deallocate(old_L);
end if;
for i in 1 to incr loop
L(bfp + i) := ' ';
end loop;
end;
PROCEDURE write(l: INOUT line; value: IN std_logic_vector;
JUSTIFIED: IN SIDE := right;
FIELD: IN WIDTH := 0) IS
variable fw: integer := VALUE'length;
variable bp: integer;
variable offset: integer := 0;
alias normal : std_logic_vector(0 to value'length - 1) is value;
begin
if L /= null then
bp := L'high + 1;
else bp := 1;
end if;
if FIELD > VALUE'length then
fw := FIELD;
if JUSTIFIED = right then
offset := fw - VALUE'length;
end if;
end if;
Grow_line(L, fw);
for i in normal'range loop
L(bp + i + offset) := character'val(
std_logic'pos(normal(i)) + character'pos('0'));
end loop;
end;
END util_1164;
lib/models/memory/sdram/mt48lc32m4a2/vec_gen.vhd
+372
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-------------------------------------------------------------------------------
-- --
-- This is a data generator for the testbench for Micron's Synchronous --
-- DRAM. This generator reads a text file line-by-line and generates --
-- a file of test vectors that is then read by the testbench and --
-- applied to the part. --
-- --
-- This VHDL program creates a text file of test vectors that is used by the --
-- test bench. Place your commands in a file (a copy of VEC_GEN.VHD) and run --
-- VEC_GEN.VHD in your VHDL simulator (make sure you have compiled this --
-- package prior to running the program VEC_GEN.VHD). This will produce the --
-- vectors that are required to run the included testbench. Change the name --
-- of the vector file to save your vectors in separate files. The default --
-- file name for the output vectors generated from this pacakage is --
-- "test.txt." --
-- --
-- Now compile and run the testbench program embedtb.vhd. The testbench uses --
-- the default test.txt as input vectors. --
-- --
-- --
-- Copyright 1997 Micron Technology, Inc. --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.io_utils.all;
PACKAGE generate_vectors IS
CONSTANT set_up : TIME;
CONSTANT hold : TIME;
CONSTANT cycle_start : TIME;
SIGNAL cycle : INTEGER := 0;
SIGNAL sim_time : TIME := 0 ns;
FILE output_file:TEXT IS OUT "test.txt";
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0);
first_data : IN INTEGER; dqm : IN BIT; cke : IN BIT);
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT; cke : IN BIT);
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT);
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT; cke : IN BIT);
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT; cs : IN BIT);
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT);
PROCEDURE auto_refresh;
PROCEDURE next_cycle(SIGNAL clk : IN BIT);
PROCEDURE load_array(load : IN BIT);
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT);
PROCEDURE unload_array(row_start : IN INTEGER; row_end : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0));
END generate_vectors;
PACKAGE BODY generate_vectors IS
CONSTANT set_up : TIME := 3 ns;
CONSTANT hold : TIME := 1 ns;
CONSTANT cycle_start : TIME := 0 ns;
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); first_data : IN INTEGER;
dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, first_data, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, row_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT; cs : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, cs, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE auto_refresh IS
VARIABLE l : LINE;
VARIABLE dqm : BIT := '0';
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE next_cycle(SIGNAL clk : IN BIT) IS
BEGIN
WAIT UNTIL clk = '1';
END;
PROCEDURE load_array(load : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT := '0';
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 1, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE unload_array(row_start : IN INTEGER; row_end : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0)) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT := '0';
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 1, right, 4); --unload
--write(l, row_start, right, 6); --row_address_start
--write(l, row_end, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT := '0';
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, op_code, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
END generate_vectors;
lib/models/memory/sdram/mt48lc32m4a2/vector.do
+4
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@@ -0,0 +1,4 @@
vcom vec_gen.vhd
vcom ed_comnd.vhd
vsim vector_generate
run -all
lib/models/memory/sdram/mt48lc32m4a2/wave.do
+31
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@@ -0,0 +1,31 @@
onerror {resume}
add wave -logic -height 20 /tb/u1/clk
add wave -logic -height 20 /tb/u1/cke
add wave -logic -height 20 /tb/u1/cs_n
add wave -logic -height 20 /tb/u1/ras_n
add wave -logic -height 20 /tb/u1/cas_n
add wave -logic -height 20 /tb/u1/we_n
add wave -logic -unsigned -height 20 /tb/u1/addr
add wave -logic -height 20 /tb/u1/ba
add wave -logic -unsigned -height 20 /tb/u1/dq
add wave -logic -height 20 /tb/u1/dqm
add wave -literal -ascii -height 20 /tb/u1/operation
add wave -logic -unsigned -height 20 /tb/u1/mode_reg
add wave -logic -height 20 /tb/u1/active_enable
add wave -logic -height 20 /tb/u1/aref_enable
add wave -logic -height 20 /tb/u1/burst_term
add wave -logic -height 20 /tb/u1/mode_reg_enable
add wave -logic -height 20 /tb/u1/prech_enable
add wave -logic -height 20 /tb/u1/read_enable
add wave -logic -height 20 /tb/u1/write_enable
add wave -logic -height 20 /tb/u1/burst_length_1
add wave -logic -height 20 /tb/u1/burst_length_2
add wave -logic -height 20 /tb/u1/burst_length_4
add wave -logic -height 20 /tb/u1/burst_length_8
add wave -logic -height 20 /tb/u1/cas_latency_2
add wave -logic -height 20 /tb/u1/cas_latency_3
add wave -logic -height 20 /tb/u1/pre_chk
add wave -logic -height 20 /tb/u1/act_chk
add wave -logic -height 20 /tb/u1/bank_chk
add wave -logic -unsigned -height 20 /tb/u1/row_chk
add wave -logic -unsigned -height 20 /tb/u1/col_chk
lib/models/memory/sdram/mt48lc4m16a2/base.do
+5
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@@ -0,0 +1,5 @@
vcom util1164.vhd
vcom stdlogar.vhd
vcom io_utils.vhd
vcom mti_pkg.vhd
lib/models/memory/sdram/mt48lc4m16a2/ed_comnd.vhd
+357
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@@ -0,0 +1,357 @@
---------------------------------------------------------------------------------
--COMMAND FORMAT --
-- --
-- write(column address(integer), bank(bit_vector), first data(integer), dqm(bit), cke(bit));--
-- read(column address(integer), bank(bit_vector), dqm(bit), cke(bit)); --
-- active(row address(integer), bank(bit_vector), data bus (integer), dqm(bit), cke(bit));--
-- precharge(bank(bit_vector), address (integer), data bus(integer), dqm(bit), cke(bit)); --
-- nop(data bus(integer), dqm(bit), cke(bit)); --
-- burst_term(data bus(integer), dqm(bit_vector), cke(bit)); --
-- load_array('1'); --
-- load_mode_reg(register(integer), cke(bit)); --
-- next_cycle(clk); This is used after every command(incl. nop) to clock --
-- at the correct clock frequency entered in the clock --
-- period constant below --
-- unload_array(row_start(integer), row_end(integer), bank(bit_vector)) --
-- load_mode_reg(op_code(integer)) --
-- --
---------------------------------------------------------------------------------
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.generate_vectors.all;
ENTITY vector_generate IS
END vector_generate;
ARCHITECTURE vector_generate OF vector_generate IS
SIGNAL stim_done : BOOLEAN := FALSE;
SIGNAL clk : BIT := '0';
CONSTANT clk_start : time := 15 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT Z : INTEGER := -100;
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1' AND clk'EVENT;
--------------------ENTER COMMANDS BELOW THIS LINE-----------------------------
--******************DO NOT USE -100 FOR A DQ VALUE*************************----
--*******************Z WILL PLACE HI-Z ON THE BUS**************************----
--*******USE next_cycle(clk) FOR ADVANCING TO NEXT CLOCK CYCLE*************----
nop(Z, "00", '1'); -- Always begin with one nop when using Micron's testbench
next_cycle(clk); -- Load Memory Array
load_array('1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk); -- Precharge All Banks
precharge("00", 1024, Z, "00", '1');
FOR i IN 1 to 2 LOOP
next_cycle(clk);
nop(Z, "00", '1');
END LOOP;
next_cycle(clk); -- First Auto Refresh
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, "00", '1');
END LOOP;
next_cycle(clk); -- Second Auto Refresh
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, "00", '1');
END LOOP;
next_cycle(clk); -- Load Mode Register (CAS Latency = 3, Burst Length = 8)
load_mode_reg(51, '1');
next_cycle(clk);
nop(Z, "00", '1');
-- Write Section
next_cycle(clk);
active(0, "00", Z, "00", '1'); -- Activate Bank 0
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk); -- Write Bank 0
write(0, "00", 10, "00", '1');
next_cycle(clk);
nop(11, "00", '1');
next_cycle(clk);
active(0, "01", 12, "00", '1'); -- Activate Bank 1
next_cycle(clk);
nop(13, "00", '1');
next_cycle(clk);
nop(14, "00", '1');
next_cycle(clk);
nop(15, "00", '1');
next_cycle(clk);
nop(16, "00", '1');
next_cycle(clk);
nop(17, "00", '1');
next_cycle(clk);
write(0, "01", 20, "00", '1'); -- Write Bank 1
next_cycle(clk);
precharge("00", 0, 21, "00", '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", 22, "00", '1'); -- Activate Bank 2
next_cycle(clk);
nop(23, "00", '1');
next_cycle(clk);
nop(24, "00", '1');
next_cycle(clk);
nop(25, "00", '1');
next_cycle(clk);
nop(26, "00", '1');
next_cycle(clk);
nop(27, "00", '1');
next_cycle(clk);
write(0, "10", 30, "00", '1'); -- Write Bank 2
next_cycle(clk);
precharge("01", 0, 31, "00", '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", 32, "00", '1'); -- Activate Bank 3
next_cycle(clk);
nop(33, "00", '1');
next_cycle(clk);
nop(34, "00", '1');
next_cycle(clk);
nop(35, "00", '1');
next_cycle(clk);
nop(36, "00", '1');
next_cycle(clk);
nop(37, "00", '1');
next_cycle(clk);
write(0, "11", 40, "00", '1'); -- Write Bank 3
next_cycle(clk);
precharge("10", 0, 41, "00", '1'); -- Precharge Bank 2
next_cycle(clk);
active(0, "00", 42, "00", '1'); -- Activate Bank 0
next_cycle(clk);
nop(43, "00", '1');
next_cycle(clk);
nop(44, "00", '1');
next_cycle(clk);
nop(45, "00", '1');
next_cycle(clk);
nop(46, "00", '1');
next_cycle(clk);
nop(47, "00", '1');
-- Read Section
next_cycle(clk);
read(0, "00", "00", '1'); -- Read Bank 0
next_cycle(clk);
precharge("11", 0, Z, "00", '1'); -- Precharge Bank 3
next_cycle(clk);
active(0, "01", Z, "00", '1'); -- Activate Bank 1
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
read(0, "01", "00", '1'); -- Read Bank 1
next_cycle(clk);
precharge("00", 0, Z, "00", '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", Z, "00", '1'); -- Activate Bank 2
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
read(0, "10", "00", '1'); -- Read Bank 2
next_cycle(clk);
precharge("01", 0, Z, "00", '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", Z, "00", '1'); -- Activate Bank 3
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
read(0, "11", "00", '1'); -- Read Bank 3
next_cycle(clk);
precharge("10", 0, Z, "00", '1'); -- Precharge Bank 2
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
precharge("11", 0, Z, "00", '1'); -- Precharge Bank 3
next_cycle(clk);
nop(Z, "00", '1');
next_cycle(clk);
nop(Z, "00", '1');
--next_cycle(clk); -- Unload Bank 0 Memory Array
--unload_array(0, 3, "00");
--next_cycle(clk); -- Unload Bank 1 Memory Array
--unload_array(0, 3, "01");
--next_cycle(clk); -- Unload Bank 2 Memory Array
--unload_array(0, 3, "10");
--next_cycle(clk); -- Unload Bank 3 Memory Array
--unload_array(0, 3, "11");
next_cycle(clk);
nop(Z, "00", '1');
stim_done <= TRUE; --always include this line at the end of your stimulus
-------------------------------------------------------------------------------
--*************************************************************************----
END PROCESS;
clock:
PROCESS
VARIABLE done_time : time;
VARIABLE cycle_var : integer := 0;
BEGIN
cycle <= 0;
clk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
clk <= '1';
cycle <= cycle_var;
WAIT for clk_period/2;
cycle_var := cycle_var + 1;
clk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT (FALSE)
REPORT "Test Vectors Generated"
SEVERITY note;
WAIT;
END PROCESS;
END;
lib/models/memory/sdram/mt48lc4m16a2/io_utils.vhd
+266
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@@ -0,0 +1,266 @@
LIBRARY ieee;
USE std.textio.ALL;
USE ieee.std_logic_1164.ALL;
PACKAGE io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0);
TYPE radix IS (binary, octal, decimal, hex);
-- read a number from the line
-- use this if you have hex numbers that are not in VHDL pound-sign format
PROCEDURE read(l : INOUT line; value : OUT integer; radix : IN positive);
-- read a number that might be in VHDL pound-sign format
PROCEDURE read_based(l : INOUT line; value : OUT integer);
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
END io_utils;
PACKAGE BODY io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0)
IS
BEGIN
write(l, value, justified, field);
END;
PROCEDURE shrink_line(l : INOUT line; pos : integer) IS
VARIABLE tmpl : line;
BEGIN
tmpl := l;
l := NEW string'(tmpl(pos TO tmpl'high));
deallocate(tmpl);
END;
PROCEDURE read(l : INOUT line;
value : OUT integer;
radix : IN positive)
IS
CONSTANT not_digit : integer := -999;
-- convert a character to a value from 0 to 15
FUNCTION digit_value(c : character) RETURN integer IS
BEGIN
IF (c >= '0') AND (c <= '9') THEN
RETURN (character'pos(c) - character'pos('0'));
ELSIF (c >= 'a') AND (c <= 'f') THEN
RETURN (character'pos(c) - character'pos('a') + 10);
ELSIF (c >= 'A') AND (c <= 'F') THEN
RETURN (character'pos(c) - character'pos('A') + 10);
ELSE
RETURN not_digit;
END IF;
END;
-- skip leading white space in the line
PROCEDURE skip_white(VARIABLE l : IN line; pos : OUT integer) IS
BEGIN
pos := l'low;
FOR i IN l'low TO l'high LOOP
CASE l(i) IS
WHEN ' ' | ht =>
pos := i + 1;
WHEN OTHERS =>
EXIT;
END CASE;
END LOOP;
END;
VARIABLE digit : integer;
VARIABLE result : integer := 0;
VARIABLE pos : integer;
BEGIN
-- skip white space
skip_white(l, pos);
-- calculate the value
FOR i IN pos TO l'right LOOP
digit := digit_value(l(i));
EXIT WHEN (digit = not_digit) OR (digit >= radix);
result := result * radix + digit;
pos := i + 1;
END LOOP;
value := result;
-- remove the "used" characters from the line
shrink_line(l, pos);
END;
PROCEDURE read_based(l : INOUT line; value : OUT integer) IS
VARIABLE digit : integer;
VARIABLE num : integer;
VARIABLE base : integer;
BEGIN
read(l, num, 10);
IF (l'length > 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
base := num;
read(l, num, base);
IF (l'length >= 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
END IF;
END IF;
value := num;
END;
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_int(bv : std_logic_vector) RETURN integer
IS
VARIABLE result : integer := 0;
BEGIN
FOR i IN bv'RANGE LOOP
result := result * 2;
IF (bv(i) = '1') THEN
result := result + 1;
END IF;
END LOOP;
RETURN result;
END;
TYPE array_of_widths IS ARRAY(radix) OF natural;
CONSTANT nibble_widths : array_of_widths := (
binary => 1,
octal => 3,
hex => 4,
decimal=> 32);
CONSTANT hex_digit : string(1 TO 16) := "0123456789ABCDEF";
ALIAS input_val : std_logic_vector(value'length DOWNTO 1) IS value;
CONSTANT nibble_width : natural := nibble_widths(base);
CONSTANT result_width : natural := (value'length + nibble_width - 1)/nibble_width;
VARIABLE result : string(1 TO result_width); -- longest possible value
VARIABLE result_pos : positive := 1;
VARIABLE nibble_val : integer;
VARIABLE bitcnt : integer;
BEGIN
IF base = decimal THEN
write(l, to_int(value), justified, field, base, use_pound);
RETURN;
END IF;
bitcnt := value'length MOD nibble_width;
IF (bitcnt = 0) THEN
bitcnt := nibble_width;
END IF;
FOR i IN input_val'RANGE LOOP
nibble_val := nibble_val * 2;
IF (input_val(i) = '1') THEN
nibble_val := nibble_val + 1;
END IF;
bitcnt := bitcnt - 1;
IF (bitcnt = 0) THEN
result(result_pos) := hex_digit(nibble_val + 1);
result_pos := result_pos + 1;
nibble_val := 0;
bitcnt := nibble_width;
END IF;
END LOOP;
write(l, result, justified, field);
END;
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_bv(int : integer) RETURN std_logic_vector
IS
VARIABLE bv : std_logic_vector(32 DOWNTO 1) := (OTHERS => '0');
VARIABLE pos : integer := 0;
VARIABLE tmpval : integer := int;
BEGIN
FOR i IN 1 TO 32 LOOP
pos := pos + 1;
IF (tmpval MOD 2) = 1 THEN
bv(i) := '1';
END IF;
tmpval := tmpval / 2;
EXIT WHEN tmpval = 0;
END LOOP;
RETURN bv(pos DOWNTO 1);
END;
VARIABLE tmp : line;
BEGIN
IF (base = decimal) THEN
IF (use_pound) THEN
write_string(tmp, "10#");
END IF;
write(tmp, value);
IF (use_pound) THEN
write_string(tmp, "#");
END IF;
write(l, tmp.ALL, justified, field);
deallocate(tmp);
ELSE
write(l, to_bv(value), justified, field, base, use_pound);
END IF;
END;
END io_utils;
-- test the hex number reader
--ENTITY test IS END;
--USE std.textio.ALL;
--USE work.io_utils.ALL;
--ARCHITECTURE hex_test OF test IS
--BEGIN
-- PROCESS
-- VARIABLE val : integer;
-- FILE myfile : text IS IN "values";
-- VARIABLE inline : line;
-- VARIABLE outline : line;
-- BEGIN
-- WHILE NOT endfile(myfile) LOOP
-- readline(myfile, inline);
-- write(outline, inline.ALL);
--
-- read_based(inline, val);
-- write_string(outline, " binary: ");
-- write(outline, val, base => binary);
-- write_string(outline, " octal: ");
-- write(outline, val, base => octal);
-- write_string(outline, " decimal: ");
-- write(outline, val, base => decimal);
-- write_string(outline, " hex: ");
-- write(outline, val, base => hex);
-- writeline(output, outline);
-- END LOOP;
-- WAIT;
-- END PROCESS;
--END;
lib/models/memory/sdram/mt48lc4m16a2/loaddata.txt
+40
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@@ -0,0 +1,40 @@
0 0 00 0 -- ROW (HEX), COL (HEX), BANK (BIN), DATA (HEX)
0 1 00 1
0 2 00 2
0 3 00 3
0 4 00 4
0 5 00 5
0 6 00 6
0 7 00 7
0 8 00 8
0 9 00 9
0 0 01 10
0 1 01 11
0 2 01 12
0 3 01 13
0 4 01 14
0 5 01 15
0 6 01 16
0 7 01 17
0 8 01 18
0 9 01 19
0 0 10 20
0 1 10 21
0 2 10 22
0 3 10 23
0 4 10 24
0 5 10 25
0 6 10 26
0 7 10 27
0 8 10 28
0 9 10 29
0 0 11 30
0 1 11 31
0 2 11 32
0 3 11 33
0 4 11 34
0 5 11 35
0 6 11 36
0 7 11 37
0 8 11 38
0 9 11 39
lib/models/memory/sdram/mt48lc4m16a2/mt48lc4m16a2.vhd
+1356
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File diff suppressed because it is too large Load Diff
lib/models/memory/sdram/mt48lc4m16a2/mti_pkg.vhd
+128
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@@ -0,0 +1,128 @@
-- ----------------------------------------------------------------------------
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
-- ----------------------------------------------------------------------------
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE mti_pkg IS
FUNCTION TO_INTEGER (input : BIT) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
FUNCTION TO_INTEGER (input : BIT) RETURN INTEGER IS
BEGIN
CASE input IS
WHEN '0' => RETURN 0;
WHEN '1' => RETURN 1;
WHEN OTHERS => RETURN 0;
END CASE;
END TO_INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
BEGIN
CASE input IS
WHEN '0' | 'L' => RETURN 0;
WHEN '1' | 'H' => RETURN 1;
WHEN OTHERS => RETURN 0;
END CASE;
END TO_INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' OR input(i) = 'H' THEN
result := result + weight;
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN
outputlen := 32;
offset := output'LENGTH - 32;
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0';
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1';
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH;
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0';
ELSE
output(output'HIGH-j-offset) := '1';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0';
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1';
ELSE
output(output'HIGH-j-offset) := '0';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1';
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
lib/models/memory/sdram/mt48lc4m16a2/outdata0.txt
View File
lib/models/memory/sdram/mt48lc4m16a2/outdata1.txt
View File
lib/models/memory/sdram/mt48lc4m16a2/outdata2.txt
View File
lib/models/memory/sdram/mt48lc4m16a2/outdata3.txt
View File
lib/models/memory/sdram/mt48lc4m16a2/readme.txt
+14
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@@ -0,0 +1,14 @@
To operate the test bench for the Micron SDRAM VHDL model, follow the directions
given below:
1. Be sure all supporting files for the SDRAM are compiled into your library:
util1164.vhd
stdlogar.vhd
io_utils.vhd
mti_pkg.vhd
2. Next, compile the mt48lc4m16a2.vhd file and the test.vhd file.
3. Simulate the "tb" architecture. This is the testbench for the 64Mb SDRAM.
lib/models/memory/sdram/mt48lc4m16a2/runall.do
+42
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@@ -0,0 +1,42 @@
vcom util1164.vhd
vcom stdlogar.vhd
vcom io_utils.vhd
vcom mti_pkg.vhd
vcom vec_gen.vhd
vcom ed_comnd.vhd
vsim vector_generate
run -all
vcom mt48lc4m16a2.vhd
vcom test.vhd
vsim tb
add wave -logic /u1/clk
add wave -logic /u1/cke
add wave -logic /u1/cs_n
add wave -logic /u1/ras_n
add wave -logic /u1/cas_n
add wave -logic /u1/we_n
add wave -literal -dec /u1/addr
add wave -literal -dec /u1/ba
add wave -literal -dec /u1/dq
add wave -literal /u1/dqm
add wave -literal /u1/operation
add wave -literal -dec /u1/mode_reg
add wave -logic /u1/active_enable
add wave -logic /u1/aref_enable
add wave -logic /u1/burst_term
add wave -logic /u1/mode_reg_enable
add wave -logic /u1/prech_enable
add wave -logic /u1/read_enable
add wave -logic /u1/write_enable
add wave -logic /u1/burst_length_1
add wave -logic /u1/burst_length_2
add wave -logic /u1/burst_length_4
add wave -logic /u1/burst_length_8
add wave -logic /u1/cas_latency_2
add wave -logic /u1/cas_latency_3
add wave -literal /u1/pre_chk
add wave -literal /u1/act_chk
add wave -literal /u1/bank_chk
add wave -literal -dec /u1/row_chk
add wave -literal -dec /u1/col_chk
run -all
lib/models/memory/sdram/mt48lc4m16a2/stdlogar.vhd
+2247
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File diff suppressed because it is too large Load Diff
lib/models/memory/sdram/mt48lc4m16a2/test.do
+5
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@@ -0,0 +1,5 @@
vcom mt48lc4m16a2.vhd
vcom test.vhd
vsim tb
do wave.do
run -all
lib/models/memory/sdram/mt48lc4m16a2/test.txt
+99
View File
@@ -0,0 +1,99 @@
0 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
22 ns 1 1 1 1 1 00 00 0 -100 1 0 0 0
32 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
42 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
52 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
62 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
72 ns 1 0 0 1 0 00 00 1024 -100 0 0 0 0
82 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
92 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
102 ns 1 0 0 0 1 00 00 0 -100 0 0 0 0
112 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
122 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
132 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
142 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
152 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
162 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
172 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
182 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
192 ns 1 0 0 0 1 00 00 0 -100 0 0 0 0
202 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
212 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
222 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
232 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
242 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
252 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
262 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
272 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
282 ns 1 0 0 0 0 00 00 51 -100 0 0 0 0
292 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
302 ns 1 0 0 1 1 00 00 0 -100 0 0 0 0
312 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
322 ns 1 0 1 0 0 00 00 0 10 0 0 0 0
332 ns 1 1 1 1 1 00 00 0 11 0 0 0 0
342 ns 1 0 0 1 1 00 01 0 12 0 0 0 0
352 ns 1 1 1 1 1 00 00 0 13 0 0 0 0
362 ns 1 1 1 1 1 00 00 0 14 0 0 0 0
372 ns 1 1 1 1 1 00 00 0 15 0 0 0 0
382 ns 1 1 1 1 1 00 00 0 16 0 0 0 0
392 ns 1 1 1 1 1 00 00 0 17 0 0 0 0
402 ns 1 0 1 0 0 00 01 0 20 0 0 0 0
412 ns 1 0 0 1 0 00 00 0 21 0 0 0 0
422 ns 1 0 0 1 1 00 10 0 22 0 0 0 0
432 ns 1 1 1 1 1 00 00 0 23 0 0 0 0
442 ns 1 1 1 1 1 00 00 0 24 0 0 0 0
452 ns 1 1 1 1 1 00 00 0 25 0 0 0 0
462 ns 1 1 1 1 1 00 00 0 26 0 0 0 0
472 ns 1 1 1 1 1 00 00 0 27 0 0 0 0
482 ns 1 0 1 0 0 00 10 0 30 0 0 0 0
492 ns 1 0 0 1 0 00 01 0 31 0 0 0 0
502 ns 1 0 0 1 1 00 11 0 32 0 0 0 0
512 ns 1 1 1 1 1 00 00 0 33 0 0 0 0
522 ns 1 1 1 1 1 00 00 0 34 0 0 0 0
532 ns 1 1 1 1 1 00 00 0 35 0 0 0 0
542 ns 1 1 1 1 1 00 00 0 36 0 0 0 0
552 ns 1 1 1 1 1 00 00 0 37 0 0 0 0
562 ns 1 0 1 0 0 00 11 0 40 0 0 0 0
572 ns 1 0 0 1 0 00 10 0 41 0 0 0 0
582 ns 1 0 0 1 1 00 00 0 42 0 0 0 0
592 ns 1 1 1 1 1 00 00 0 43 0 0 0 0
602 ns 1 1 1 1 1 00 00 0 44 0 0 0 0
612 ns 1 1 1 1 1 00 00 0 45 0 0 0 0
622 ns 1 1 1 1 1 00 00 0 46 0 0 0 0
632 ns 1 1 1 1 1 00 00 0 47 0 0 0 0
642 ns 1 0 1 0 1 00 00 0 -100 0 0 0 0
652 ns 1 0 0 1 0 00 11 0 -100 0 0 0 0
662 ns 1 0 0 1 1 00 01 0 -100 0 0 0 0
672 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
682 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
692 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
702 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
712 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
722 ns 1 0 1 0 1 00 01 0 -100 0 0 0 0
732 ns 1 0 0 1 0 00 00 0 -100 0 0 0 0
742 ns 1 0 0 1 1 00 10 0 -100 0 0 0 0
752 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
762 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
772 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
782 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
792 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
802 ns 1 0 1 0 1 00 10 0 -100 0 0 0 0
812 ns 1 0 0 1 0 00 01 0 -100 0 0 0 0
822 ns 1 0 0 1 1 00 11 0 -100 0 0 0 0
832 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
842 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
852 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
862 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
872 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
882 ns 1 0 1 0 1 00 11 0 -100 0 0 0 0
892 ns 1 0 0 1 0 00 10 0 -100 0 0 0 0
902 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
912 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
922 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
932 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
942 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
952 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
962 ns 1 0 0 1 0 00 11 0 -100 0 0 0 0
972 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
982 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
992 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
lib/models/memory/sdram/mt48lc4m16a2/test.vhd
+196
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@@ -0,0 +1,196 @@
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.ALL;
USE work.std_logic_arith.ALL;
USE work.util_1164.ALL;
USE std.textio.ALL;
USE work.mti_pkg.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE test OF tb IS
CONSTANT addr_bits : INTEGER := 12;
CONSTANT data_bits : INTEGER := 16;
CONSTANT clk_start : time := 5 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT continue_time : time := 10 ns;
COMPONENT mt48lc4m16a2
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
Load : IN STD_LOGIC := '0';
Unload : IN STD_LOGIC := '0';
Row_start : IN INTEGER := 0;
Row_end : IN INTEGER := 0
);
END COMPONENT;
FOR ALL : mt48lc4m16a2 USE ENTITY work.mt48lc4m16a2 (behave);
SIGNAL pDq : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
SIGNAL pAddr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
SIGNAL pBa : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pClk : STD_LOGIC;
SIGNAL pCke : STD_LOGIC;
SIGNAL pCs : STD_LOGIC;
SIGNAL pCas : STD_LOGIC;
SIGNAL pRas : STD_LOGIC;
SIGNAL pWe : STD_LOGIC;
SIGNAL pDqm : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL PLoad : STD_LOGIC;
SIGNAL PUnload : STD_LOGIC;
SIGNAL PRow_start : INTEGER;
SIGNAL PRow_end : INTEGER;
SIGNAL stim_done : boolean := false;
SIGNAL clk_done : boolean := false;
BEGIN
u1: mt48lc4m16a2
PORT MAP(
Dq => pDq,
Addr => pAddr,
Ba => pBa,
Clk => pClk,
Cke => pCke,
Cs_n => pCs,
Ras_n => pRas,
Cas_n => pCas,
We_n => pWe,
Dqm => pDqm,
Load => pLoad,
Unload => pUnload,
Row_start => PRow_start,
Row_end => PRow_end
);
stimulator : PROCESS
FILE stim_file:text IS IN "test.txt";
VARIABLE l : line;
VARIABLE time_var : TIME;
VARIABLE pCke_var : STD_LOGIC;
VARIABLE pCs_var : STD_LOGIC;
VARIABLE pRas_var : STD_LOGIC;
VARIABLE PCas_var : STD_LOGIC;
VARIABLE pWe_var : STD_LOGIC;
VARIABLE pDqm_var : STD_LOGIC_VECTOR (1 DOWNTO 0);
VARIABLE pBa_var : STD_LOGIC_VECTOR (1 DOWNTO 0);
VARIABLE pAddr_var : INTEGER;
VARIABLE pDq_var : INTEGER; -- -100 is converted to hi-Z state
VARIABLE pLoad_var : STD_LOGIC;
VARIABLE pUnload_var : STD_LOGIC;
VARIABLE pRow_start_var : INTEGER;
VARIABLE pRow_end_var : INTEGER;
VARIABLE pMa_var_vect : STD_LOGIC_VECTOR(addr_bits - 1 DOWNTO 0);
CONSTANT HiZ : STD_LOGIC_VECTOR(data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
BEGIN
WHILE not ENDFILE(stim_file) LOOP
readline(stim_file,l);
IF l'length > 0 THEN
read (l, time_var);
read (l, pCke_var);
read (l, pCs_var);
read (l, pRas_var);
read (l, pCas_var);
read (l, pWe_var);
read (l, pDqm_var);
read (l, pBa_var);
read (l, pAddr_var);
read (l, pDq_var);
read (l, pLoad_var);
read (l, pUnload_var);
read (l, pRow_start_var);
read (l, pRow_end_var);
IF now > time_var THEN
ASSERT false
REPORT "Detected a time in the stim file that is in the past"
SEVERITY error;
ELSE
WAIT FOR time_var-now;
IF pWe_var='1' THEN
pCke <= pCke_var;
pCs <= pCs_var;
pRas <= pRas_var;
pCas <= pCas_var;
pWe <= pWe_var;
pDqm <= pDqm_var;
pBa <= pBa_var;
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
pLoad <= pLoad_var;
pUnload <= pUnload_var;
pRow_start <= pRow_start_var;
pRow_end <= pRow_end_var;
ELSE
pCke <= pCke_var;
pCs <= pCs_var;
pRas <= pRas_var;
pCas <= pCas_var;
pWe <= pWe_var;
pDqm <= pDqm_var;
pBa <= pBa_var;
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
pLoad <= pLoad_var;
pUnload <= pUnload_var;
pRow_start <= pRow_start_var;
pRow_end <= pRow_end_var;
END IF;
END IF;
END IF;
END LOOP;
ASSERT false
REPORT "End of Stimulation File Detected!"
SEVERITY note;
stim_done <= true;
WAIT;
END PROCESS;
clock : PROCESS
VARIABLE done_time : time;
BEGIN
pclk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
done_time := now+continue_time;
WHILE now < done_time LOOP --one last clock to finish last command
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT false
REPORT "Suspending clock activity"
SEVERITY note;
clk_done <= true;
WAIT;
END PROCESS;
END test;
lib/models/memory/sdram/mt48lc4m16a2/util1164.vhd
+124
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE STD.textio.ALL;
PACKAGE util_1164 IS
PROCEDURE read(l: INOUT line; value: OUT std_logic);
PROCEDURE read(l: INOUT line; value: OUT std_logic_vector);
PROCEDURE write(l: INOUT line; value: IN std_logic_vector;
JUSTIFIED: IN SIDE := right;
FIELD: IN WIDTH := 0);
PROCEDURE Grow_line(L : inout LINE; incr : in integer);
END util_1164;
PACKAGE BODY util_1164 IS
FUNCTION white_space(value:character) RETURN boolean IS
VARIABLE result:boolean;
BEGIN
IF (value = ' ') OR (value = HT) THEN
RETURN true;
ELSE
RETURN false;
END IF;
END white_space;
PROCEDURE read(l: INOUT line; value: OUT std_logic) IS
VARIABLE char_var: character:= ' ';
BEGIN
WHILE l'LENGTH > 0 LOOP
read(l,char_var);
IF NOT white_space(char_var) THEN
EXIT;
END IF;
END LOOP;
IF white_space(char_var) THEN
ASSERT false REPORT "No std_logic value found in file"
SEVERITY error;
value := 'X';
RETURN;
END IF;
CASE char_var IS
WHEN 'U'|'u' => value := 'U';
WHEN '0' => value := '0';
WHEN '1' => value := '1';
WHEN 'X'|'x' => value := 'X';
WHEN 'L'|'l' => value := 'L';
WHEN 'H'|'h' => value := 'H';
WHEN 'W'|'w' => value := 'W';
WHEN 'Z'|'z' => value := 'Z';
WHEN '-' => value := '-';
WHEN OTHERS =>
ASSERT false REPORT "Unrecognized value read for std_logic"
SEVERITY error;
value := 'X';
END CASE;
END read;
PROCEDURE read(l: INOUT line; value: OUT std_logic_vector) IS
BEGIN
FOR i IN value'HIGH DOWNTO value'LOW LOOP
IF l'LENGTH > 0 THEN
read(l,value(i));
ELSE
ASSERT false REPORT "Not enough values for std_logic_vector in file"
SEVERITY error;
RETURN;
END IF;
END LOOP;
END read;
procedure Grow_line(L : inout LINE; incr : in integer)
is
variable old_L : LINE := L;
variable bfp: integer; -- Blank fill pointer.
begin
assert incr > 0
report "Textio: Grow_line called with zero increment."
severity error;
if L = null then
bfp := 0;
L := new string(1 to incr);
else
bfp := old_L'high;
L := new string(old_L'low to old_L'high + incr);
L(old_L'low to old_L'high) := old_L.all;
Deallocate(old_L);
end if;
for i in 1 to incr loop
L(bfp + i) := ' ';
end loop;
end;
PROCEDURE write(l: INOUT line; value: IN std_logic_vector;
JUSTIFIED: IN SIDE := right;
FIELD: IN WIDTH := 0) IS
variable fw: integer := VALUE'length;
variable bp: integer;
variable offset: integer := 0;
alias normal : std_logic_vector(0 to value'length - 1) is value;
begin
if L /= null then
bp := L'high + 1;
else bp := 1;
end if;
if FIELD > VALUE'length then
fw := FIELD;
if JUSTIFIED = right then
offset := fw - VALUE'length;
end if;
end if;
Grow_line(L, fw);
for i in normal'range loop
L(bp + i + offset) := character'val(
std_logic'pos(normal(i)) + character'pos('0'));
end loop;
end;
END util_1164;
lib/models/memory/sdram/mt48lc4m16a2/vec_gen.vhd
+373
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-------------------------------------------------------------------------------
-- --
-- This is a data generator for the testbench for Micron's Synchronous --
-- DRAM. This generator reads a text file line-by-line and generates --
-- a file of test vectors that is then read by the testbench and --
-- applied to the part. --
-- --
-- This VHDL program creates a text file of test vectors that is used by the --
-- test bench. Place your commands in a file (a copy of VEC_GEN.VHD) and run --
-- VEC_GEN.VHD in your VHDL simulator (make sure you have compiled this --
-- package prior to running the program VEC_GEN.VHD). This will produce the --
-- vectors that are required to run the included testbench. Change the name --
-- of the vector file to save your vectors in separate files. The default --
-- file name for the output vectors generated from this pacakage is --
-- "test.txt." --
-- --
-- Now compile and run the testbench program embedtb.vhd. The testbench uses --
-- the default test.txt as input vectors. --
-- --
-- --
-- Copyright 1997 Micron Technology, Inc. --
-- --
-------------------------------------------------------------------------------
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.io_utils.all;
PACKAGE generate_vectors IS
CONSTANT set_up : TIME;
CONSTANT hold : TIME;
CONSTANT cycle_start : TIME;
SIGNAL cycle : INTEGER := 0;
SIGNAL sim_time : TIME := 0 ns;
FILE output_file:TEXT IS OUT "test.txt";
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0);
first_data : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE auto_refresh;
PROCEDURE next_cycle(SIGNAL clk : IN BIT);
PROCEDURE load_array(load : IN BIT);
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT);
PROCEDURE unload_array(row_start : IN INTEGER; row_end : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0));
END generate_vectors;
PACKAGE BODY generate_vectors IS
CONSTANT set_up : TIME := 3 ns;
CONSTANT hold : TIME := 1 ns;
CONSTANT cycle_start : TIME := 0 ns;
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); first_data : IN INTEGER;
dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, first_data, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, row_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 1, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE auto_refresh IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE next_cycle(SIGNAL clk : IN BIT) IS
BEGIN
WAIT UNTIL clk = '1';
END;
PROCEDURE load_array(load : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 1, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 1, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE unload_array(row_start : IN INTEGER; row_end : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0)) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 1, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 1, right, 4); --unload
write(l, row_start, right, 6); --row_address_start
write(l, row_end, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, op_code, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
END generate_vectors;
lib/models/memory/sdram/mt48lc4m16a2/vector.do
+4
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@@ -0,0 +1,4 @@
vcom vec_gen.vhd
vcom ed_comnd.vhd
vsim vector_generate
run -all
lib/models/memory/sdram/mt48lc4m16a2/wave.do
+34
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@@ -0,0 +1,34 @@
onerror {resume}
add wave -logic /tb/u1/clk
add wave -logic /tb/u1/cke
add wave -logic /tb/u1/cs_n
add wave -logic /tb/u1/ras_n
add wave -logic /tb/u1/cas_n
add wave -logic /tb/u1/we_n
add wave -literal -decimal /tb/u1/addr
add wave -literal -binary /tb/u1/ba
add wave -literal -hexadecimal /tb/u1/dq
add wave -literal /tb/u1/dqm
add wave -literal /tb/u1/operation
add wave -literal -decimal /tb/u1/mode_reg
add wave -logic /tb/u1/active_enable
add wave -logic /tb/u1/aref_enable
add wave -logic /tb/u1/burst_term
add wave -logic /tb/u1/mode_reg_enable
add wave -logic /tb/u1/prech_enable
add wave -logic /tb/u1/read_enable
add wave -logic /tb/u1/write_enable
add wave -logic /tb/u1/burst_length_1
add wave -logic /tb/u1/burst_length_2
add wave -logic /tb/u1/burst_length_4
add wave -logic /tb/u1/burst_length_8
add wave -logic /tb/u1/cas_latency_2
add wave -logic /tb/u1/cas_latency_3
add wave -literal /tb/u1/pre_chk
add wave -literal /tb/u1/act_chk
add wave -literal /tb/u1/bank_chk
add wave -literal -decimal /tb/u1/row_chk
add wave -literal -decimal /tb/u1/col_chk
add wave -logic /tb/u1/dq_in_chk
add wave -logic /tb/u1/dq_out_chk
add wave -literal -decimal /tb/u1/rw_bank_chk
lib/models/memory/sdram/mt48lc4m32b2/mt48lc4m32b2.vhd
+1148
View File
File diff suppressed because it is too large Load Diff
lib/models/memory/sdram/mt48lc4m32b2/test.do
+5
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@@ -0,0 +1,5 @@
vcom mt48lc4m32b2.vhd
vcom test.vhd
vsim -t ps tb
do wave.do
run -all
lib/models/memory/sdram/mt48lc4m32b2/test.vhd
+309
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@@ -0,0 +1,309 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE test OF tb IS
COMPONENT mt48lc4m32b2
GENERIC ( -- Timing for -7 CL2
tCK : TIME := 7.500 ns;
addr_bits : INTEGER := 12;
data_bits : INTEGER := 32
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000"
);
END COMPONENT;
FOR ALL : mt48lc4m32b2 USE ENTITY work.mt48lc4m32b2 (behave);
CONSTANT tCK : TIME := 7.500 ns;
CONSTANT addr_bits : INTEGER := 12;
CONSTANT data_bits : INTEGER := 32;
SIGNAL pDq : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
SIGNAL pAddr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
SIGNAL pBa : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pClk : STD_LOGIC;
SIGNAL pCke : STD_LOGIC;
SIGNAL pCs_n : STD_LOGIC;
SIGNAL pCas_n : STD_LOGIC;
SIGNAL pRas_n : STD_LOGIC;
SIGNAL pWe_n : STD_LOGIC;
SIGNAL pDqm : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL stim_done : boolean := false;
SIGNAL clk_done : boolean := false;
BEGIN
u1: mt48lc4m32b2
PORT MAP(
Dq => pDq,
Addr => pAddr,
Ba => pBa,
Clk => pClk,
Cke => pCke,
Cs_n => pCs_n,
Ras_n => pRas_n,
Cas_n => pCas_n,
We_n => pWe_n,
Dqm => pDqm
);
stimulator : PROCESS
PROCEDURE ACTIVE (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '0';
pCas_n <= '1';
pWe_n <= '1';
pDqm <= "0000";
pBa <= Ba_in;
pAddr <= Addr_in;
pDq <= Dq_in;
WAIT FOR tCK;
END;
PROCEDURE AUTO_REFRESH IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '0';
pCas_n <= '0';
pWe_n <= '1';
pDqm <= "0000";
--pBa <= "00";
--pAddr <= (OTHERS => '0');
pDq <= (OTHERS => 'Z');
WAIT FOR tCK;
END;
PROCEDURE BURST_TERM IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '1';
pCas_n <= '1';
pWe_n <= '0';
pDqm <= "0000";
--pBa <= "00";
--pAddr <= (OTHERS => '0');
pDq <= (OTHERS => 'Z');
WAIT FOR tCK;
END;
PROCEDURE LOAD_MODE_REG (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '0';
pCas_n <= '0';
pWe_n <= '0';
pDqm <= "0000";
pBa <= Ba_in;
pAddr <= Addr_in;
pDq <= (OTHERS => 'Z');
WAIT FOR tCK;
END;
PROCEDURE NOP (Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '1';
pCas_n <= '1';
pWe_n <= '1';
pDqm <= "0000";
--pBa <= "00";
--pAddr <= (OTHERS => '0');
pDq <= Dq_in;
WAIT FOR tCK;
END;
PROCEDURE PRECHARGE (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '0';
pCas_n <= '1';
pWe_n <= '0';
pDqm <= "0000";
pBa <= Ba_in;
pAddr <= Addr_in;
pDq <= Dq_in;
WAIT FOR tCK;
END;
PROCEDURE READ (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '1';
pCas_n <= '0';
pWe_n <= '1';
pDqm <= "0000";
pBa <= Ba_in;
pAddr <= Addr_in;
pDq <= Dq_in;
WAIT FOR tCK;
END;
-- Write
PROCEDURE WRITE (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1';
pCs_n <= '0';
pRas_n <= '1';
pCas_n <= '0';
pWe_n <= '0';
pDqm <= "0000";
pBa <= Ba_in;
pAddr <= Addr_in;
pDq <= Dq_in;
WAIT FOR tCK;
END;
BEGIN
-- COMMAND BA ADDR DQ
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
-- We need 100 us power up sequence. I use 10 NOPs here as a required example.
PRECHARGE ("00", "010000000000", "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
AUTO_REFRESH;
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
AUTO_REFRESH;
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
LOAD_MODE_REG ("00", "000000100010");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
ACTIVE ("00", "000000000000", "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
ACTIVE ("01", "000000000000", "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
ACTIVE ("10", "000000000000", "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
ACTIVE ("11", "000000000000", "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
WRITE ("00", "000000000000", "00000000000000000000000000000000");
NOP ( "00000000000000000000000000000001");
NOP ( "00000000000000000000000000000010");
NOP ( "00000000000000000000000000000011");
WRITE ("01", "000000000000", "00000000000000000000000000000100");
NOP ( "00000000000000000000000000000101");
NOP ( "00000000000000000000000000000110");
NOP ( "00000000000000000000000000000111");
WRITE ("10", "000000000000", "00000000000000000000000000001000");
NOP ( "00000000000000000000000000001001");
NOP ( "00000000000000000000000000001010");
NOP ( "00000000000000000000000000001011");
WRITE ("11", "000000000000", "00000000000000000000000000001100");
NOP ( "00000000000000000000000000001101");
NOP ( "00000000000000000000000000001110");
NOP ( "00000000000000000000000000001111");
READ ("00", "000000000000", "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
READ ("01", "000000000000", "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
READ ("10", "000000000000", "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
READ ("11", "000000000000", "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
NOP ( "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
ASSERT false
REPORT "End of Stimulation File Detected!"
SEVERITY note;
stim_done <= true;
WAIT;
END PROCESS;
clock : PROCESS
VARIABLE done_time : time;
BEGIN
pclk <= '0';
WAIT for tCK/2;
WHILE not stim_done loop
pclk <= '1';
WAIT for tCK/2;
pclk <= '0';
WAIT for tCK/2;
END LOOP;
done_time := now + tCK;
WHILE now < done_time LOOP -- one last clock to finish last command
pclk <= '1';
WAIT for tCK/2;
pclk <= '0';
WAIT for tCK/2;
END LOOP;
ASSERT false
REPORT "Suspending clock activity"
SEVERITY note;
clk_done <= true;
WAIT;
END PROCESS;
END test;
lib/models/memory/sdram/mt48lc4m32b2/wave.do
+26
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add wave -noupdate -radix default -format Logic /tb/u1/clk
add wave -noupdate -radix default -format Logic /tb/u1/cke
add wave -noupdate -radix default -format Logic /tb/u1/cs_n
add wave -noupdate -radix default -format Logic /tb/u1/ras_n
add wave -noupdate -radix default -format Logic /tb/u1/cas_n
add wave -noupdate -radix default -format Logic /tb/u1/we_n
add wave -noupdate -radix decimal /tb/u1/addr
add wave -noupdate -radix unsigned /tb/u1/ba
add wave -noupdate -radix decimal /tb/u1/dq
add wave -noupdate -radix default -format Logic /tb/u1/dqm
add wave -noupdate -radix decimal /tb/u1/operation
add wave -noupdate -radix decimal /tb/u1/mode_reg
add wave -noupdate -radix default -format Logic /tb/u1/active_enable
add wave -noupdate -radix default -format Logic /tb/u1/aref_enable
add wave -noupdate -radix default -format Logic /tb/u1/burst_term
add wave -noupdate -radix default -format Logic /tb/u1/mode_reg_enable
add wave -noupdate -radix default -format Logic /tb/u1/prech_enable
add wave -noupdate -radix default -format Logic /tb/u1/read_enable
add wave -noupdate -radix default -format Logic /tb/u1/write_enable
add wave -noupdate -radix default -format Logic /tb/u1/burst_length_1
add wave -noupdate -radix default -format Logic /tb/u1/burst_length_2
add wave -noupdate -radix default -format Logic /tb/u1/burst_length_4
add wave -noupdate -radix default -format Logic /tb/u1/burst_length_8
add wave -noupdate -radix default -format Logic /tb/u1/cas_latency_2
add wave -noupdate -radix default -format Logic /tb/u1/cas_latency_3
lib/models/memory/sdram/mt48lc64m4a2/base.do
+5
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@@ -0,0 +1,5 @@
vcom util1164.vhd
vcom stdlogar.vhd
vcom io_utils.vhd
vcom mti_pkg.vhd
lib/models/memory/sdram/mt48lc64m4a2/ed_comnd.vhd
+345
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@@ -0,0 +1,345 @@
---------------------------------------------------------------------------------
--COMMAND FORMAT --
-- --
-- write(column address(integer), bank(bit_vector), first data(integer), dqm(bit), cke(bit));--
-- read(column address(integer), bank(bit_vector), dqm(bit), cke(bit)); --
-- active(row address(integer), bank(bit_vector), data bus (integer), dqm(bit), cke(bit));--
-- precharge(bank(bit_vector), address (integer), data bus(integer), dqm(bit), cke(bit)); --
-- nop(data bus(integer), dqm(bit), cke(bit), cs(bit)); --
-- burst_term(data bus(integer), dqm(bit), cke(bit)); --
-- load_array('1'); --
-- load_mode_reg(register(integer), cke(bit)); --
-- next_cycle(clk); This is used after every command(incl. nop) to clock --
-- at the correct clock frequency entered in the clock --
-- period constant below --
-- unload_array(row_start(integer), row_end(integer), bank(bit_vector)) --
-- load_mode_reg(op_code(integer)) --
-- --
---------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.generate_vectors.all;
ENTITY vector_generate IS
END vector_generate;
ARCHITECTURE vector_generate OF vector_generate IS
SIGNAL stim_done : BOOLEAN := FALSE;
SIGNAL clk : BIT := '0';
CONSTANT clk_start : time := 15 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT Z : INTEGER := -100;
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1' AND clk'EVENT;
--------------------ENTER COMMANDS BELOW THIS LINE-----------------------------
--******************DO NOT USE -100 FOR A DQ VALUE*************************----
--*******************Z WILL PLACE HI-Z ON THE BUS**************************----
--*******USE next_cycle(clk) FOR ADVANCING TO NEXT CLOCK CYCLE*************----
nop(Z, '0', '1', '1'); --Always begin with one nop when using Micron's testbench
--next_cycle(clk);
--load_array('1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
precharge("00", 1024, Z, '0', '1');
FOR i IN 1 to 2 LOOP
next_cycle(clk);
nop(Z, '0', '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, '0', '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, '0', '1', '1');
END LOOP;
next_cycle(clk);
load_mode_reg(51, '1'); -- 19 / 35 / 51 -> lat=3,bl=8,mode=seq
next_cycle(clk);
nop(Z, '0', '1', '1');
-- Write Section
next_cycle(clk);
active(0, "00", Z, '0', '1'); -- Activate Bank 0
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk); -- Write Bank 0
write(10, "00", 0, '0', '1');
next_cycle(clk);
nop(1, '0', '1', '1');
next_cycle(clk);
active(0, "01", 2, '0', '1'); -- Activate Bank 1
next_cycle(clk);
nop(3, '0', '1', '1');
next_cycle(clk);
nop(4, '0', '1', '1');
next_cycle(clk);
nop(5, '0', '1', '1');
next_cycle(clk);
nop(6, '0', '1', '1');
next_cycle(clk);
nop(7, '0', '1', '1');
next_cycle(clk);
write(20, "01", 8, '0', '1'); -- Write Bank 1
next_cycle(clk);
precharge("00", 0, 9, '0', '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", 10, '0', '1'); -- Activate Bank 2
next_cycle(clk);
nop(11, '0', '1', '1');
next_cycle(clk);
nop(12, '0', '1', '1');
next_cycle(clk);
nop(13, '0', '1', '1');
next_cycle(clk);
nop(14, '0', '1', '1');
next_cycle(clk);
nop(15, '0', '1', '1');
next_cycle(clk);
write(30, "10", 0, '0', '1'); -- Write Bank 2
next_cycle(clk);
precharge("01", 0, 1, '0', '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", 2, '0', '1'); -- Activate Bank 3
next_cycle(clk);
nop(3, '0', '1', '1');
next_cycle(clk);
nop(4, '0', '1', '1');
next_cycle(clk);
nop(5, '0', '1', '1');
next_cycle(clk);
nop(6, '0', '1', '1');
next_cycle(clk);
nop(7, '0', '1', '1');
next_cycle(clk);
write(40, "11", 8, '0', '1'); -- Write Bank 3
next_cycle(clk);
precharge("10", 0, 9, '0', '1'); -- Precharge Bank 2
next_cycle(clk);
active(0, "00", 10, '0', '1'); -- Activate Bank 0
next_cycle(clk);
nop(11, '0', '1', '1');
next_cycle(clk);
nop(12, '0', '1', '1');
next_cycle(clk);
nop(13, '0', '1', '1');
next_cycle(clk);
nop(14, '0', '1', '1');
next_cycle(clk);
nop(15, '0', '1', '1');
-- Read Section
next_cycle(clk);
read(10, "00", '0', '1'); -- Read Bank 0
next_cycle(clk);
precharge("11", 0, Z, '0', '1'); -- Precharge Bank 3
next_cycle(clk);
active(0, "01", Z, '0', '1'); -- Activate Bank 1
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
read(20, "01", '0', '1'); -- Read Bank 1
next_cycle(clk);
precharge("00", 0, Z, '0', '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", Z, '0', '1'); -- Activate Bank 2
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
read(30, "10", '0', '1'); -- Read Bank 2
next_cycle(clk);
precharge("01", 0, Z, '0', '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", Z, '0', '1'); -- Activate Bank 3
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
read(40, "11", '0', '1'); -- Read Bank 3
next_cycle(clk);
precharge("10", 0, Z, '0', '1'); -- Precharge Bank 2
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
precharge("11", 0, Z, '0', '1'); -- Precharge Bank 3
next_cycle(clk);
nop(Z, '0', '1', '1');
next_cycle(clk);
nop(Z, '0', '1', '1');
--next_cycle(clk);
--unload_array(0, 0, '0');
next_cycle(clk);
nop(Z, '0', '1', '1');
stim_done <= TRUE; --always include this line at the end of your stimulus
-------------------------------------------------------------------------------
--*************************************************************************----
END PROCESS;
clock:
PROCESS
VARIABLE done_time : time;
VARIABLE cycle_var : integer := 0;
BEGIN
cycle <= 0;
clk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
clk <= '1';
cycle <= cycle_var;
WAIT for clk_period/2;
cycle_var := cycle_var + 1;
clk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT (FALSE)
REPORT "Test Vectors Generated"
SEVERITY note;
WAIT;
END PROCESS;
END;
lib/models/memory/sdram/mt48lc64m4a2/io_utils.vhd
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LIBRARY ieee;
USE std.textio.ALL;
USE ieee.std_logic_1164.ALL;
PACKAGE io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0);
TYPE radix IS (binary, octal, decimal, hex);
-- read a number from the line
-- use this if you have hex numbers that are not in VHDL pound-sign format
PROCEDURE read(l : INOUT line; value : OUT integer; radix : IN positive);
-- read a number that might be in VHDL pound-sign format
PROCEDURE read_based(l : INOUT line; value : OUT integer);
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
END io_utils;
PACKAGE BODY io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0)
IS
BEGIN
write(l, value, justified, field);
END;
PROCEDURE shrink_line(l : INOUT line; pos : integer) IS
VARIABLE tmpl : line;
BEGIN
tmpl := l;
l := NEW string'(tmpl(pos TO tmpl'high));
deallocate(tmpl);
END;
PROCEDURE read(l : INOUT line;
value : OUT integer;
radix : IN positive)
IS
CONSTANT not_digit : integer := -999;
-- convert a character to a value from 0 to 15
FUNCTION digit_value(c : character) RETURN integer IS
BEGIN
IF (c >= '0') AND (c <= '9') THEN
RETURN (character'pos(c) - character'pos('0'));
ELSIF (c >= 'a') AND (c <= 'f') THEN
RETURN (character'pos(c) - character'pos('a') + 10);
ELSIF (c >= 'A') AND (c <= 'F') THEN
RETURN (character'pos(c) - character'pos('A') + 10);
ELSE
RETURN not_digit;
END IF;
END;
-- skip leading white space in the line
PROCEDURE skip_white(VARIABLE l : IN line; pos : OUT integer) IS
BEGIN
pos := l'low;
FOR i IN l'low TO l'high LOOP
CASE l(i) IS
WHEN ' ' | ht =>
pos := i + 1;
WHEN OTHERS =>
EXIT;
END CASE;
END LOOP;
END;
VARIABLE digit : integer;
VARIABLE result : integer := 0;
VARIABLE pos : integer;
BEGIN
-- skip white space
skip_white(l, pos);
-- calculate the value
FOR i IN pos TO l'right LOOP
digit := digit_value(l(i));
EXIT WHEN (digit = not_digit) OR (digit >= radix);
result := result * radix + digit;
pos := i + 1;
END LOOP;
value := result;
-- remove the "used" characters from the line
shrink_line(l, pos);
END;
PROCEDURE read_based(l : INOUT line; value : OUT integer) IS
VARIABLE digit : integer;
VARIABLE num : integer;
VARIABLE base : integer;
BEGIN
read(l, num, 10);
IF (l'length > 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
base := num;
read(l, num, base);
IF (l'length >= 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
END IF;
END IF;
value := num;
END;
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_int(bv : std_logic_vector) RETURN integer
IS
VARIABLE result : integer := 0;
BEGIN
FOR i IN bv'RANGE LOOP
result := result * 2;
IF (bv(i) = '1') THEN
result := result + 1;
END IF;
END LOOP;
RETURN result;
END;
TYPE array_of_widths IS ARRAY(radix) OF natural;
CONSTANT nibble_widths : array_of_widths := (
binary => 1,
octal => 3,
hex => 4,
decimal=> 32);
CONSTANT hex_digit : string(1 TO 16) := "0123456789ABCDEF";
ALIAS input_val : std_logic_vector(value'length DOWNTO 1) IS value;
CONSTANT nibble_width : natural := nibble_widths(base);
CONSTANT result_width : natural := (value'length + nibble_width - 1)/nibble_width;
VARIABLE result : string(1 TO result_width); -- longest possible value
VARIABLE result_pos : positive := 1;
VARIABLE nibble_val : integer;
VARIABLE bitcnt : integer;
BEGIN
IF base = decimal THEN
write(l, to_int(value), justified, field, base, use_pound);
RETURN;
END IF;
bitcnt := value'length MOD nibble_width;
IF (bitcnt = 0) THEN
bitcnt := nibble_width;
END IF;
FOR i IN input_val'RANGE LOOP
nibble_val := nibble_val * 2;
IF (input_val(i) = '1') THEN
nibble_val := nibble_val + 1;
END IF;
bitcnt := bitcnt - 1;
IF (bitcnt = 0) THEN
result(result_pos) := hex_digit(nibble_val + 1);
result_pos := result_pos + 1;
nibble_val := 0;
bitcnt := nibble_width;
END IF;
END LOOP;
write(l, result, justified, field);
END;
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_bv(int : integer) RETURN std_logic_vector
IS
VARIABLE bv : std_logic_vector(32 DOWNTO 1) := (OTHERS => '0');
VARIABLE pos : integer := 0;
VARIABLE tmpval : integer := int;
BEGIN
FOR i IN 1 TO 32 LOOP
pos := pos + 1;
IF (tmpval MOD 2) = 1 THEN
bv(i) := '1';
END IF;
tmpval := tmpval / 2;
EXIT WHEN tmpval = 0;
END LOOP;
RETURN bv(pos DOWNTO 1);
END;
VARIABLE tmp : line;
BEGIN
IF (base = decimal) THEN
IF (use_pound) THEN
write_string(tmp, "10#");
END IF;
write(tmp, value);
IF (use_pound) THEN
write_string(tmp, "#");
END IF;
write(l, tmp.ALL, justified, field);
deallocate(tmp);
ELSE
write(l, to_bv(value), justified, field, base, use_pound);
END IF;
END;
END io_utils;
-- test the hex number reader
--ENTITY test IS END;
--USE std.textio.ALL;
--USE work.io_utils.ALL;
--ARCHITECTURE hex_test OF test IS
--BEGIN
-- PROCESS
-- VARIABLE val : integer;
-- FILE myfile : text IS IN "values";
-- VARIABLE inline : line;
-- VARIABLE outline : line;
-- BEGIN
-- WHILE NOT endfile(myfile) LOOP
-- readline(myfile, inline);
-- write(outline, inline.ALL);
--
-- read_based(inline, val);
-- write_string(outline, " binary: ");
-- write(outline, val, base => binary);
-- write_string(outline, " octal: ");
-- write(outline, val, base => octal);
-- write_string(outline, " decimal: ");
-- write(outline, val, base => decimal);
-- write_string(outline, " hex: ");
-- write(outline, val, base => hex);
-- writeline(output, outline);
-- END LOOP;
-- WAIT;
-- END PROCESS;
--END;
lib/models/memory/sdram/mt48lc64m4a2/mt48lc64m4a2.vhd
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lib/models/memory/sdram/mt48lc64m4a2/mti_pkg.vhd
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--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE mti_pkg IS
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver integer to bit_vector
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN
outputlen := 32;
offset := output'LENGTH - 32;
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0';
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1';
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH;
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0';
ELSE
output(output'HIGH-j-offset) := '1';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0';
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1';
ELSE
output(output'HIGH-j-offset) := '0';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1';
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
lib/models/memory/sdram/mt48lc64m4a2/readme.txt
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To operate the test bench for the Micron SDRAM VHDL model, follow the directions
given below:
1. Be sure all supporting files for the SDRAM are compiled into your library:
util1164.vhd
stdlogar.vhd
io_utils.vhd
mti_pkg.vhd
2. Next, compile the mt48lc64m4a2.vhd file and the test.vhd file.
3. Simulate the "tb" architecture. This is the testbench for the 256Mb SDRAM.
lib/models/memory/sdram/mt48lc64m4a2/stdlogar.vhd
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lib/models/memory/sdram/mt48lc64m4a2/test.do
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vcom mt48lc64m4a2.vhd
vcom test.vhd
vsim tb
do wave.do
run -all
lib/models/memory/sdram/mt48lc64m4a2/test.txt
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0 ns 1 1 1 1 1 0 00 0 -100
22 ns 1 1 1 1 1 0 00 0 -100
32 ns 1 1 1 1 1 0 00 0 -100
42 ns 1 1 1 1 1 0 00 0 -100
52 ns 1 1 1 1 1 0 00 0 -100
62 ns 1 0 0 1 0 0 00 1024 -100
72 ns 1 1 1 1 1 0 00 0 -100
82 ns 1 1 1 1 1 0 00 0 -100
92 ns 1 0 0 0 1 0 00 0 -100
102 ns 1 1 1 1 1 0 00 0 -100
112 ns 1 1 1 1 1 0 00 0 -100
122 ns 1 1 1 1 1 0 00 0 -100
132 ns 1 1 1 1 1 0 00 0 -100
142 ns 1 1 1 1 1 0 00 0 -100
152 ns 1 1 1 1 1 0 00 0 -100
162 ns 1 1 1 1 1 0 00 0 -100
172 ns 1 1 1 1 1 0 00 0 -100
182 ns 1 0 0 0 1 0 00 0 -100
192 ns 1 1 1 1 1 0 00 0 -100
202 ns 1 1 1 1 1 0 00 0 -100
212 ns 1 1 1 1 1 0 00 0 -100
222 ns 1 1 1 1 1 0 00 0 -100
232 ns 1 1 1 1 1 0 00 0 -100
242 ns 1 1 1 1 1 0 00 0 -100
252 ns 1 1 1 1 1 0 00 0 -100
262 ns 1 1 1 1 1 0 00 0 -100
272 ns 1 0 0 0 0 0 00 51 -100
282 ns 1 1 1 1 1 0 00 0 -100
292 ns 1 0 0 1 1 0 00 0 -100
302 ns 1 1 1 1 1 0 00 0 -100
312 ns 1 0 1 0 0 0 00 10 0
322 ns 1 1 1 1 1 0 00 0 1
332 ns 1 0 0 1 1 0 01 0 2
342 ns 1 1 1 1 1 0 00 0 3
352 ns 1 1 1 1 1 0 00 0 4
362 ns 1 1 1 1 1 0 00 0 5
372 ns 1 1 1 1 1 0 00 0 6
382 ns 1 1 1 1 1 0 00 0 7
392 ns 1 0 1 0 0 0 01 20 8
402 ns 1 0 0 1 0 0 00 0 9
412 ns 1 0 0 1 1 0 10 0 10
422 ns 1 1 1 1 1 0 00 0 11
432 ns 1 1 1 1 1 0 00 0 12
442 ns 1 1 1 1 1 0 00 0 13
452 ns 1 1 1 1 1 0 00 0 14
462 ns 1 1 1 1 1 0 00 0 15
472 ns 1 0 1 0 0 0 10 30 0
482 ns 1 0 0 1 0 0 01 0 1
492 ns 1 0 0 1 1 0 11 0 2
502 ns 1 1 1 1 1 0 00 0 3
512 ns 1 1 1 1 1 0 00 0 4
522 ns 1 1 1 1 1 0 00 0 5
532 ns 1 1 1 1 1 0 00 0 6
542 ns 1 1 1 1 1 0 00 0 7
552 ns 1 0 1 0 0 0 11 40 8
562 ns 1 0 0 1 0 0 10 0 9
572 ns 1 0 0 1 1 0 00 0 10
582 ns 1 1 1 1 1 0 00 0 11
592 ns 1 1 1 1 1 0 00 0 12
602 ns 1 1 1 1 1 0 00 0 13
612 ns 1 1 1 1 1 0 00 0 14
622 ns 1 1 1 1 1 0 00 0 15
632 ns 1 0 1 0 1 0 00 10 -100
642 ns 1 0 0 1 0 0 11 0 -100
652 ns 1 0 0 1 1 0 01 0 -100
662 ns 1 1 1 1 1 0 00 0 -100
672 ns 1 1 1 1 1 0 00 0 -100
682 ns 1 1 1 1 1 0 00 0 -100
692 ns 1 1 1 1 1 0 00 0 -100
702 ns 1 1 1 1 1 0 00 0 -100
712 ns 1 0 1 0 1 0 01 20 -100
722 ns 1 0 0 1 0 0 00 0 -100
732 ns 1 0 0 1 1 0 10 0 -100
742 ns 1 1 1 1 1 0 00 0 -100
752 ns 1 1 1 1 1 0 00 0 -100
762 ns 1 1 1 1 1 0 00 0 -100
772 ns 1 1 1 1 1 0 00 0 -100
782 ns 1 1 1 1 1 0 00 0 -100
792 ns 1 0 1 0 1 0 10 30 -100
802 ns 1 0 0 1 0 0 01 0 -100
812 ns 1 0 0 1 1 0 11 0 -100
822 ns 1 1 1 1 1 0 00 0 -100
832 ns 1 1 1 1 1 0 00 0 -100
842 ns 1 1 1 1 1 0 00 0 -100
852 ns 1 1 1 1 1 0 00 0 -100
862 ns 1 1 1 1 1 0 00 0 -100
872 ns 1 0 1 0 1 0 11 40 -100
882 ns 1 0 0 1 0 0 10 0 -100
892 ns 1 1 1 1 1 0 00 0 -100
902 ns 1 1 1 1 1 0 00 0 -100
912 ns 1 1 1 1 1 0 00 0 -100
922 ns 1 1 1 1 1 0 00 0 -100
932 ns 1 1 1 1 1 0 00 0 -100
942 ns 1 1 1 1 1 0 00 0 -100
952 ns 1 0 0 1 0 0 11 0 -100
962 ns 1 1 1 1 1 0 00 0 -100
972 ns 1 1 1 1 1 0 00 0 -100
982 ns 1 1 1 1 1 0 00 0 -100
lib/models/memory/sdram/mt48lc64m4a2/test.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.ALL;
USE work.std_logic_arith.ALL;
USE work.util_1164.ALL;
USE work.mti_pkg.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE test OF tb IS
CONSTANT addr_bits : INTEGER := 13;
CONSTANT data_bits : INTEGER := 4;
CONSTANT clk_start : time := 5 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT continue_time : time := 10 ns;
COMPONENT mt48lc64m4a2
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC := '0'
);
END COMPONENT;
FOR ALL : mt48lc64m4a2 USE ENTITY work.mt48lc64m4a2 (behave);
SIGNAL pDq : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
SIGNAL pAddr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
SIGNAL pBa : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pClk : STD_LOGIC;
SIGNAL pCke : STD_LOGIC;
SIGNAL pCs : STD_LOGIC;
SIGNAL pCas : STD_LOGIC;
SIGNAL pRas : STD_LOGIC;
SIGNAL pWe : STD_LOGIC;
SIGNAL pDqm : STD_LOGIC;
SIGNAL stim_done : boolean := false;
SIGNAL clk_done : boolean := false;
BEGIN
u1: mt48lc64m4a2
PORT MAP(
Dq => pDq,
Addr => pAddr,
Ba => pBa,
Clk => pClk,
Cke => pCke,
Cs_n => pCs,
Ras_n => pRas,
Cas_n => pCas,
We_n => pWe,
Dqm => pDqm
);
stimulator : PROCESS
FILE stim_file:text IS IN "test.txt";
VARIABLE l : line;
VARIABLE time_var : TIME;
VARIABLE pCke_var : STD_LOGIC;
VARIABLE pCs_var : STD_LOGIC;
VARIABLE pRas_var : STD_LOGIC;
VARIABLE PCas_var : STD_LOGIC;
VARIABLE pWe_var : STD_LOGIC;
VARIABLE pDqm_var : STD_LOGIC;
VARIABLE pBa_var : STD_LOGIC_VECTOR (1 DOWNTO 0);
VARIABLE pAddr_var : INTEGER;
VARIABLE pDq_var : INTEGER; -- -100 is converted to hi-Z state
VARIABLE pMa_var_vect : STD_LOGIC_VECTOR(addr_bits - 1 DOWNTO 0);
CONSTANT HiZ : STD_LOGIC_VECTOR(data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
BEGIN
WHILE not ENDFILE(stim_file) LOOP
readline(stim_file,l);
IF l'length > 0 THEN
read(l, time_var);
read(l, pCke_var);
read(l, pCs_var);
read(l, pRas_var);
read(l, pCas_var);
read(l, pWe_var);
read(l, pDqm_var);
read(l, pBa_var);
read(l, pAddr_var);
read(l, pDq_var);
IF now > time_var THEN
ASSERT false
REPORT "Detected a time in the stim file that is in the past"
SEVERITY error;
ELSE
WAIT FOR time_var-now;
IF pWe_var='1' THEN
pCke <= pCke_var;
pCs <= pCs_var;
pRas <= pRas_var;
pCas <= pCas_var;
pWe <= pWe_var;
pDqm <= pDqm_var;
pBa <= pBa_var;
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
ELSE
pCke <= pCke_var;
pCs <= pCs_var;
pRas <= pRas_var;
pCas <= pCas_var;
pWe <= pWe_var;
pDqm <= pDqm_var;
pBa <= pBa_var;
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
END IF;
END IF;
END IF;
END LOOP;
ASSERT false
REPORT "End of Stimulation File Detected!"
SEVERITY note;
stim_done <= true;
WAIT;
END PROCESS;
clock : PROCESS
VARIABLE done_time : time;
BEGIN
pclk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
done_time := now+continue_time;
WHILE now < done_time LOOP --one last clock to finish last command
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT false
REPORT "Suspending clock activity"
SEVERITY note;
clk_done <= true;
WAIT;
END PROCESS;
END test;
lib/models/memory/sdram/mt48lc64m4a2/util1164.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE STD.textio.ALL;
PACKAGE util_1164 IS
PROCEDURE read(l: INOUT line; value: OUT std_logic);
PROCEDURE read(l: INOUT line; value: OUT std_logic_vector);
PROCEDURE write(l: INOUT line; value: IN std_logic_vector;
JUSTIFIED: IN SIDE := right;
FIELD: IN WIDTH := 0);
PROCEDURE Grow_line(L : inout LINE; incr : in integer);
END util_1164;
PACKAGE BODY util_1164 IS
FUNCTION white_space(value:character) RETURN boolean IS
VARIABLE result:boolean;
BEGIN
IF (value = ' ') OR (value = HT) THEN
RETURN true;
ELSE
RETURN false;
END IF;
END white_space;
PROCEDURE read(l: INOUT line; value: OUT std_logic) IS
VARIABLE char_var: character:= ' ';
BEGIN
WHILE l'LENGTH > 0 LOOP
read(l,char_var);
IF NOT white_space(char_var) THEN
EXIT;
END IF;
END LOOP;
IF white_space(char_var) THEN
ASSERT false REPORT "No std_logic value found in file"
SEVERITY error;
value := 'X';
RETURN;
END IF;
CASE char_var IS
WHEN 'U'|'u' => value := 'U';
WHEN '0' => value := '0';
WHEN '1' => value := '1';
WHEN 'X'|'x' => value := 'X';
WHEN 'L'|'l' => value := 'L';
WHEN 'H'|'h' => value := 'H';
WHEN 'W'|'w' => value := 'W';
WHEN 'Z'|'z' => value := 'Z';
WHEN '-' => value := '-';
WHEN OTHERS =>
ASSERT false REPORT "Unrecognized value read for std_logic"
SEVERITY error;
value := 'X';
END CASE;
END read;
PROCEDURE read(l: INOUT line; value: OUT std_logic_vector) IS
BEGIN
FOR i IN value'HIGH DOWNTO value'LOW LOOP
IF l'LENGTH > 0 THEN
read(l,value(i));
ELSE
ASSERT false REPORT "Not enough values for std_logic_vector in file"
SEVERITY error;
RETURN;
END IF;
END LOOP;
END read;
procedure Grow_line(L : inout LINE; incr : in integer)
is
variable old_L : LINE := L;
variable bfp: integer; -- Blank fill pointer.
begin
assert incr > 0
report "Textio: Grow_line called with zero increment."
severity error;
if L = null then
bfp := 0;
L := new string(1 to incr);
else
bfp := old_L'high;
L := new string(old_L'low to old_L'high + incr);
L(old_L'low to old_L'high) := old_L.all;
Deallocate(old_L);
end if;
for i in 1 to incr loop
L(bfp + i) := ' ';
end loop;
end;
PROCEDURE write(l: INOUT line; value: IN std_logic_vector;
JUSTIFIED: IN SIDE := right;
FIELD: IN WIDTH := 0) IS
variable fw: integer := VALUE'length;
variable bp: integer;
variable offset: integer := 0;
alias normal : std_logic_vector(0 to value'length - 1) is value;
begin
if L /= null then
bp := L'high + 1;
else bp := 1;
end if;
if FIELD > VALUE'length then
fw := FIELD;
if JUSTIFIED = right then
offset := fw - VALUE'length;
end if;
end if;
Grow_line(L, fw);
for i in normal'range loop
L(bp + i + offset) := character'val(
std_logic'pos(normal(i)) + character'pos('0'));
end loop;
end;
END util_1164;
lib/models/memory/sdram/mt48lc64m4a2/vec_gen.vhd
+372
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-------------------------------------------------------------------------------
-- --
-- This is a data generator for the testbench for Micron's Synchronous --
-- DRAM. This generator reads a text file line-by-line and generates --
-- a file of test vectors that is then read by the testbench and --
-- applied to the part. --
-- --
-- This VHDL program creates a text file of test vectors that is used by the --
-- test bench. Place your commands in a file (a copy of VEC_GEN.VHD) and run --
-- VEC_GEN.VHD in your VHDL simulator (make sure you have compiled this --
-- package prior to running the program VEC_GEN.VHD). This will produce the --
-- vectors that are required to run the included testbench. Change the name --
-- of the vector file to save your vectors in separate files. The default --
-- file name for the output vectors generated from this pacakage is --
-- "test.txt." --
-- --
-- Now compile and run the testbench program embedtb.vhd. The testbench uses --
-- the default test.txt as input vectors. --
-- --
-- --
-- Copyright 1997 Micron Technology, Inc. --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.io_utils.all;
PACKAGE generate_vectors IS
CONSTANT set_up : TIME;
CONSTANT hold : TIME;
CONSTANT cycle_start : TIME;
SIGNAL cycle : INTEGER := 0;
SIGNAL sim_time : TIME := 0 ns;
FILE output_file:TEXT IS OUT "test.txt";
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0);
first_data : IN INTEGER; dqm : IN BIT; cke : IN BIT);
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT; cke : IN BIT);
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT);
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT; cke : IN BIT);
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT; cs : IN BIT);
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT);
PROCEDURE auto_refresh;
PROCEDURE next_cycle(SIGNAL clk : IN BIT);
PROCEDURE load_array(load : IN BIT);
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT);
PROCEDURE unload_array(row_start : IN INTEGER; row_end : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0));
END generate_vectors;
PACKAGE BODY generate_vectors IS
CONSTANT set_up : TIME := 3 ns;
CONSTANT hold : TIME := 1 ns;
CONSTANT cycle_start : TIME := 0 ns;
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); first_data : IN INTEGER;
dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, first_data, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, row_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT; cs : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, cs, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT; cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE auto_refresh IS
VARIABLE l : LINE;
VARIABLE dqm : BIT := '0';
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE next_cycle(SIGNAL clk : IN BIT) IS
BEGIN
WAIT UNTIL clk = '1';
END;
PROCEDURE load_array(load : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT := '0';
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 1, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE unload_array(row_start : IN INTEGER; row_end : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0)) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT := '0';
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 1, right, 4); --unload
--write(l, row_start, right, 6); --row_address_start
--write(l, row_end, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT := '0';
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, op_code, right, 6); --address
write(l, -100, right, 6); --first data location
--write(l, 0, right, 4); --load
--write(l, 0, right, 4); --unload
--write(l, 0, right, 6); --row_address_start
--write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
END generate_vectors;
lib/models/memory/sdram/mt48lc64m4a2/vector.do
+4
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@@ -0,0 +1,4 @@
vcom vec_gen.vhd
vcom ed_comnd.vhd
vsim vector_generate
run -all
lib/models/memory/sdram/mt48lc64m4a2/wave.do
+31
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@@ -0,0 +1,31 @@
onerror {resume}
add wave -logic -height 20 /tb/u1/clk
add wave -logic -height 20 /tb/u1/cke
add wave -logic -height 20 /tb/u1/cs_n
add wave -logic -height 20 /tb/u1/ras_n
add wave -logic -height 20 /tb/u1/cas_n
add wave -logic -height 20 /tb/u1/we_n
add wave -logic -unsigned -height 20 /tb/u1/addr
add wave -logic -height 20 /tb/u1/ba
add wave -logic -unsigned -height 20 /tb/u1/dq
add wave -logic -height 20 /tb/u1/dqm
add wave -literal -ascii -height 20 /tb/u1/operation
add wave -logic -unsigned -height 20 /tb/u1/mode_reg
add wave -logic -height 20 /tb/u1/active_enable
add wave -logic -height 20 /tb/u1/aref_enable
add wave -logic -height 20 /tb/u1/burst_term
add wave -logic -height 20 /tb/u1/mode_reg_enable
add wave -logic -height 20 /tb/u1/prech_enable
add wave -logic -height 20 /tb/u1/read_enable
add wave -logic -height 20 /tb/u1/write_enable
add wave -logic -height 20 /tb/u1/burst_length_1
add wave -logic -height 20 /tb/u1/burst_length_2
add wave -logic -height 20 /tb/u1/burst_length_4
add wave -logic -height 20 /tb/u1/burst_length_8
add wave -logic -height 20 /tb/u1/cas_latency_2
add wave -logic -height 20 /tb/u1/cas_latency_3
add wave -logic -height 20 /tb/u1/pre_chk
add wave -logic -height 20 /tb/u1/act_chk
add wave -logic -height 20 /tb/u1/bank_chk
add wave -logic -unsigned -height 20 /tb/u1/row_chk
add wave -logic -unsigned -height 20 /tb/u1/col_chk
lib/models/memory/sdram/mt48lc8m16a2/base.do
+5
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@@ -0,0 +1,5 @@
vcom util1164.vhd
vcom stdlogar.vhd
vcom io_utils.vhd
vcom mti_pkg.vhd
lib/models/memory/sdram/mt48lc8m16a2/ed_comnd.vhd
+349
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@@ -0,0 +1,349 @@
---------------------------------------------------------------------------------
--COMMAND FORMAT --
-- --
-- write(column address(integer), bank(bit_vector), first data(integer), dqm(bit), cke(bit));--
-- read(column address(integer), bank(bit_vector), dqm(bit), cke(bit)); --
-- active(row address(integer), bank(bit_vector), data bus (integer), dqm(bit), cke(bit));--
-- precharge(bank(bit_vector), address (integer), data bus(integer), dqm(bit), cke(bit)); --
-- nop(data bus(integer), dqm(bit), cke(bit), cs(bit)); --
-- burst_term(data bus(integer), dqm(bit_vector), cke(bit)); --
-- load_array('1'); --
-- load_mode_reg(register(integer), cke(bit)); --
-- next_cycle(clk); This is used after every command(incl. nop) to clock --
-- at the correct clock frequency entered in the clock --
-- period constant below --
-- unload_array(row_start(integer), row_end(integer), bank(bit_vector)) --
-- load_mode_reg(op_code(integer)) --
-- --
---------------------------------------------------------------------------------
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.generate_vectors.all;
ENTITY vector_generate IS
END vector_generate;
ARCHITECTURE vector_generate OF vector_generate IS
SIGNAL stim_done : BOOLEAN := FALSE;
SIGNAL clk : BIT := '0';
CONSTANT clk_start : time := 15 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT Z : INTEGER := -100;
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1' AND clk'EVENT;
--------------------ENTER COMMANDS BELOW THIS LINE-----------------------------
--******************DO NOT USE -100 FOR A DQ VALUE*************************----
--*******************Z WILL PLACE HI-Z ON THE BUS**************************----
--*******USE next_cycle(clk) FOR ADVANCING TO NEXT CLOCK CYCLE*************----
nop(Z, "00", '1', '1'); --Always begin with one nop when using Micron's testbench
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
load_array('1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
precharge("00", 1024, Z, "00", '1');
FOR i IN 1 to 2 LOOP
next_cycle(clk);
nop(Z, "00", '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, "00", '1', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, "00", '1', '1');
END LOOP;
next_cycle(clk);
load_mode_reg(51, '1'); -- 19 / 35 / 51 -> lat=3,bl=8,mode=seq
next_cycle(clk);
nop(Z, "00", '1', '1');
-- Write Section
next_cycle(clk);
active(0, "00", Z, "00", '1'); -- Activate Bank 0
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk); -- Write Bank 0
write(0, "00", 100, "00", '1');
next_cycle(clk);
nop(101, "00", '1', '1');
next_cycle(clk);
active(0, "01", 102, "00", '1'); -- Activate Bank 1
next_cycle(clk);
nop(103, "00", '1', '1');
next_cycle(clk);
nop(104, "00", '1', '1');
next_cycle(clk);
nop(105, "00", '1', '1');
next_cycle(clk);
nop(106, "00", '1', '1');
next_cycle(clk);
nop(107, "00", '1', '1');
next_cycle(clk);
write(0, "01", 200, "00", '1'); -- Write Bank 1
next_cycle(clk);
precharge("00", 0, 201, "00", '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", 202, "00", '1'); -- Activate Bank 2
next_cycle(clk);
nop(203, "00", '1', '1');
next_cycle(clk);
nop(204, "00", '1', '1');
next_cycle(clk);
nop(205, "00", '1', '1');
next_cycle(clk);
nop(206, "00", '1', '1');
next_cycle(clk);
nop(207, "00", '1', '1');
next_cycle(clk);
write(0, "10", 300, "00", '1'); -- Write Bank 2
next_cycle(clk);
precharge("01", 0, 301, "00", '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", 302, "00", '1'); -- Activate Bank 3
next_cycle(clk);
nop(303, "00", '1', '1');
next_cycle(clk);
nop(304, "00", '1', '1');
next_cycle(clk);
nop(305, "00", '1', '1');
next_cycle(clk);
nop(306, "00", '1', '1');
next_cycle(clk);
nop(307, "00", '1', '1');
next_cycle(clk);
write(0, "11", 400, "00", '1'); -- Write Bank 3
next_cycle(clk);
precharge("10", 0, 401, "00", '1'); -- Precharge Bank 2
next_cycle(clk);
active(0, "00", 402, "00", '1'); -- Activate Bank 0
next_cycle(clk);
nop(403, "00", '1', '1');
next_cycle(clk);
nop(404, "00", '1', '1');
next_cycle(clk);
nop(405, "00", '1', '1');
next_cycle(clk);
nop(406, "00", '1', '1');
next_cycle(clk);
nop(407, "00", '1', '1');
-- Read Section
next_cycle(clk);
read(0, "00", "00", '1'); -- Read Bank 0
next_cycle(clk);
precharge("11", 0, Z, "00", '1'); -- Precharge Bank 3
next_cycle(clk);
active(0, "01", Z, "00", '1'); -- Activate Bank 1
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
read(0, "01", "00", '1'); -- Read Bank 1
next_cycle(clk);
precharge("00", 0, Z, "00", '1'); -- Precharge Bank 0
next_cycle(clk);
active(0, "10", Z, "00", '1'); -- Activate Bank 2
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
read(0, "10", "00", '1'); -- Read Bank 2
next_cycle(clk);
precharge("01", 0, Z, "00", '1'); -- Precharge Bank 1
next_cycle(clk);
active(0, "11", Z, "00", '1'); -- Activate Bank 3
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
read(0, "11", "00", '1'); -- Read Bank 3
next_cycle(clk);
precharge("10", 0, Z, "00", '1'); -- Precharge Bank 2
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
precharge("11", 0, Z, "00", '1'); -- Precharge Bank 3
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
nop(Z, "00", '1', '1');
next_cycle(clk);
unload_array(0, 0, "00");
next_cycle(clk);
nop(Z, "00", '1', '1');
stim_done <= TRUE; --always include this line at the end of your stimulus
-------------------------------------------------------------------------------
--*************************************************************************----
END PROCESS;
clock:
PROCESS
VARIABLE done_time : time;
VARIABLE cycle_var : integer := 0;
BEGIN
cycle <= 0;
clk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
clk <= '1';
cycle <= cycle_var;
WAIT for clk_period/2;
cycle_var := cycle_var + 1;
clk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT (FALSE)
REPORT "Test Vectors Generated"
SEVERITY note;
WAIT;
END PROCESS;
END;
lib/models/memory/sdram/mt48lc8m16a2/io_utils.vhd
+266
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LIBRARY ieee;
USE std.textio.ALL;
USE ieee.std_logic_1164.ALL;
PACKAGE io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0);
TYPE radix IS (binary, octal, decimal, hex);
-- read a number from the line
-- use this if you have hex numbers that are not in VHDL pound-sign format
PROCEDURE read(l : INOUT line; value : OUT integer; radix : IN positive);
-- read a number that might be in VHDL pound-sign format
PROCEDURE read_based(l : INOUT line; value : OUT integer);
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
END io_utils;
PACKAGE BODY io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0)
IS
BEGIN
write(l, value, justified, field);
END;
PROCEDURE shrink_line(l : INOUT line; pos : integer) IS
VARIABLE tmpl : line;
BEGIN
tmpl := l;
l := NEW string'(tmpl(pos TO tmpl'high));
deallocate(tmpl);
END;
PROCEDURE read(l : INOUT line;
value : OUT integer;
radix : IN positive)
IS
CONSTANT not_digit : integer := -999;
-- convert a character to a value from 0 to 15
FUNCTION digit_value(c : character) RETURN integer IS
BEGIN
IF (c >= '0') AND (c <= '9') THEN
RETURN (character'pos(c) - character'pos('0'));
ELSIF (c >= 'a') AND (c <= 'f') THEN
RETURN (character'pos(c) - character'pos('a') + 10);
ELSIF (c >= 'A') AND (c <= 'F') THEN
RETURN (character'pos(c) - character'pos('A') + 10);
ELSE
RETURN not_digit;
END IF;
END;
-- skip leading white space in the line
PROCEDURE skip_white(VARIABLE l : IN line; pos : OUT integer) IS
BEGIN
pos := l'low;
FOR i IN l'low TO l'high LOOP
CASE l(i) IS
WHEN ' ' | ht =>
pos := i + 1;
WHEN OTHERS =>
EXIT;
END CASE;
END LOOP;
END;
VARIABLE digit : integer;
VARIABLE result : integer := 0;
VARIABLE pos : integer;
BEGIN
-- skip white space
skip_white(l, pos);
-- calculate the value
FOR i IN pos TO l'right LOOP
digit := digit_value(l(i));
EXIT WHEN (digit = not_digit) OR (digit >= radix);
result := result * radix + digit;
pos := i + 1;
END LOOP;
value := result;
-- remove the "used" characters from the line
shrink_line(l, pos);
END;
PROCEDURE read_based(l : INOUT line; value : OUT integer) IS
VARIABLE digit : integer;
VARIABLE num : integer;
VARIABLE base : integer;
BEGIN
read(l, num, 10);
IF (l'length > 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
base := num;
read(l, num, base);
IF (l'length >= 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
END IF;
END IF;
value := num;
END;
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_int(bv : std_logic_vector) RETURN integer
IS
VARIABLE result : integer := 0;
BEGIN
FOR i IN bv'RANGE LOOP
result := result * 2;
IF (bv(i) = '1') THEN
result := result + 1;
END IF;
END LOOP;
RETURN result;
END;
TYPE array_of_widths IS ARRAY(radix) OF natural;
CONSTANT nibble_widths : array_of_widths := (
binary => 1,
octal => 3,
hex => 4,
decimal=> 32);
CONSTANT hex_digit : string(1 TO 16) := "0123456789ABCDEF";
ALIAS input_val : std_logic_vector(value'length DOWNTO 1) IS value;
CONSTANT nibble_width : natural := nibble_widths(base);
CONSTANT result_width : natural := (value'length + nibble_width - 1)/nibble_width;
VARIABLE result : string(1 TO result_width); -- longest possible value
VARIABLE result_pos : positive := 1;
VARIABLE nibble_val : integer;
VARIABLE bitcnt : integer;
BEGIN
IF base = decimal THEN
write(l, to_int(value), justified, field, base, use_pound);
RETURN;
END IF;
bitcnt := value'length MOD nibble_width;
IF (bitcnt = 0) THEN
bitcnt := nibble_width;
END IF;
FOR i IN input_val'RANGE LOOP
nibble_val := nibble_val * 2;
IF (input_val(i) = '1') THEN
nibble_val := nibble_val + 1;
END IF;
bitcnt := bitcnt - 1;
IF (bitcnt = 0) THEN
result(result_pos) := hex_digit(nibble_val + 1);
result_pos := result_pos + 1;
nibble_val := 0;
bitcnt := nibble_width;
END IF;
END LOOP;
write(l, result, justified, field);
END;
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_bv(int : integer) RETURN std_logic_vector
IS
VARIABLE bv : std_logic_vector(32 DOWNTO 1) := (OTHERS => '0');
VARIABLE pos : integer := 0;
VARIABLE tmpval : integer := int;
BEGIN
FOR i IN 1 TO 32 LOOP
pos := pos + 1;
IF (tmpval MOD 2) = 1 THEN
bv(i) := '1';
END IF;
tmpval := tmpval / 2;
EXIT WHEN tmpval = 0;
END LOOP;
RETURN bv(pos DOWNTO 1);
END;
VARIABLE tmp : line;
BEGIN
IF (base = decimal) THEN
IF (use_pound) THEN
write_string(tmp, "10#");
END IF;
write(tmp, value);
IF (use_pound) THEN
write_string(tmp, "#");
END IF;
write(l, tmp.ALL, justified, field);
deallocate(tmp);
ELSE
write(l, to_bv(value), justified, field, base, use_pound);
END IF;
END;
END io_utils;
-- test the hex number reader
--ENTITY test IS END;
--USE std.textio.ALL;
--USE work.io_utils.ALL;
--ARCHITECTURE hex_test OF test IS
--BEGIN
-- PROCESS
-- VARIABLE val : integer;
-- FILE myfile : text IS IN "values";
-- VARIABLE inline : line;
-- VARIABLE outline : line;
-- BEGIN
-- WHILE NOT endfile(myfile) LOOP
-- readline(myfile, inline);
-- write(outline, inline.ALL);
--
-- read_based(inline, val);
-- write_string(outline, " binary: ");
-- write(outline, val, base => binary);
-- write_string(outline, " octal: ");
-- write(outline, val, base => octal);
-- write_string(outline, " decimal: ");
-- write(outline, val, base => decimal);
-- write_string(outline, " hex: ");
-- write(outline, val, base => hex);
-- writeline(output, outline);
-- END LOOP;
-- WAIT;
-- END PROCESS;
--END;
lib/models/memory/sdram/mt48lc8m16a2/loaddata.txt
+40
View File
@@ -0,0 +1,40 @@
0 0 00 0 -- ROW (HEX), COL (HEX), BANK (BIN), DATA (HEX)
0 1 00 1
0 2 00 2
0 3 00 3
0 4 00 4
0 5 00 5
0 6 00 6
0 7 00 7
0 8 00 8
0 9 00 9
0 0 01 10
0 1 01 11
0 2 01 12
0 3 01 13
0 4 01 14
0 5 01 15
0 6 01 16
0 7 01 17
0 8 01 18
0 9 01 19
0 0 10 20
0 1 10 21
0 2 10 22
0 3 10 23
0 4 10 24
0 5 10 25
0 6 10 26
0 7 10 27
0 8 10 28
0 9 10 29
0 0 11 30
0 1 11 31
0 2 11 32
0 3 11 33
0 4 11 34
0 5 11 35
0 6 11 36
0 7 11 37
0 8 11 38
0 9 11 39
lib/models/memory/sdram/mt48lc8m16a2/mt48lc8m16a2.vhd
+1426
View File
File diff suppressed because it is too large Load Diff
lib/models/memory/sdram/mt48lc8m16a2/mti_pkg.vhd
+129
View File
@@ -0,0 +1,129 @@
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE mti_pkg IS
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver integer to bit_vector
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN
outputlen := 32;
offset := output'LENGTH - 32;
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0';
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1';
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH;
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0';
ELSE
output(output'HIGH-j-offset) := '1';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0';
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1';
ELSE
output(output'HIGH-j-offset) := '0';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1';
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
lib/models/memory/sdram/mt48lc8m16a2/outdata0.txt
+33
View File
@@ -0,0 +1,33 @@
Micron Technology Inc. - Unload Data Array - Bank 0 Row 0
0 : 0 : 0064 0065 0066 0067 0068 0069 006A 006B 0074 0075 006E 006F 0070 0071 0072 0073
0 : 10 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 20 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 30 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 40 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 50 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 60 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 70 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 80 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 90 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : A0 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : B0 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : C0 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : D0 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : E0 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : F0 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 100 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 110 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 120 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 130 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 140 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 150 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 160 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 170 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 180 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 190 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 1A0 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 1B0 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 1C0 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 1D0 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 1E0 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0 : 1F0 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
lib/models/memory/sdram/mt48lc8m16a2/outdata1.txt
View File
lib/models/memory/sdram/mt48lc8m16a2/outdata2.txt
View File
lib/models/memory/sdram/mt48lc8m16a2/outdata3.txt
View File
lib/models/memory/sdram/mt48lc8m16a2/readme.txt
+14
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@@ -0,0 +1,14 @@
To operate the test bench for the Micron SDRAM VHDL model, follow the directions
given below:
1. Be sure all supporting files for the SDRAM are compiled into your library:
util1164.vhd
stdlogar.vhd
io_utils.vhd
mti_pkg.vhd
2. Next, compile the mt48lc8m16a2.vhd file and the test.vhd file.
3. Simulate the "tb" architecture. This is the testbench for the 128Mb SDRAM.
lib/models/memory/sdram/mt48lc8m16a2/runall.do
+49
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@@ -0,0 +1,49 @@
# Compile base libraries
vcom util1164.vhd
vcom stdlogar.vhd
vcom io_utils.vhd
vcom mti_pkg.vhd
# Compile test vectors
vcom vec_gen.vhd
vcom ed_comnd.vhd
vsim vector_generate
run -all
# Compile Micron SDRAM model and testbench
vcom mt48lc8m16a2.vhd
vcom test.vhd
vsim -t ps tb
# Add waveform
add wave -logic /tb/u1/clk
add wave -logic /tb/u1/cke
add wave -logic /tb/u1/cs_n
add wave -logic /tb/u1/ras_n
add wave -logic /tb/u1/cas_n
add wave -logic /tb/u1/we_n
add wave -literal -decimal /tb/u1/addr
add wave -literal -unsigned /tb/u1/ba
add wave -literal -decimal /tb/u1/dq
add wave -literal /tb/u1/dqm
add wave -literal /tb/u1/operation
add wave -literal -decimal /tb/u1/mode_reg
add wave -logic /tb/u1/active_enable
add wave -logic /tb/u1/aref_enable
add wave -logic /tb/u1/burst_term
add wave -logic /tb/u1/mode_reg_enable
add wave -logic /tb/u1/prech_enable
add wave -logic /tb/u1/read_enable
add wave -logic /tb/u1/write_enable
add wave -logic /tb/u1/burst_length_1
add wave -logic /tb/u1/burst_length_2
add wave -logic /tb/u1/burst_length_4
add wave -logic /tb/u1/burst_length_8
add wave -logic /tb/u1/cas_latency_2
add wave -logic /tb/u1/cas_latency_3
add wave -literal /tb/u1/pre_chk
add wave -literal /tb/u1/act_chk
add wave -literal /tb/u1/bank_chk
add wave -literal -decimal /tb/u1/row_chk
add wave -literal -decimal /tb/u1/col_chk
add wave -logic /tb/u1/dq_in_chk
add wave -logic /tb/u1/dq_out_chk
# run all test vectors
run -all
lib/models/memory/sdram/mt48lc8m16a2/stdlogar.vhd
+2247
View File
File diff suppressed because it is too large Load Diff
lib/models/memory/sdram/mt48lc8m16a2/test.do
+5
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@@ -0,0 +1,5 @@
vcom mt48lc8m16a2.vhd
vcom test.vhd
vsim tb
do wave.do
run -all
lib/models/memory/sdram/mt48lc8m16a2/test.txt
+115
View File
@@ -0,0 +1,115 @@
0 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
22 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
32 ns 1 0 1 1 1 00 00 0 -100 1 0 0 0
42 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
52 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
62 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
72 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
82 ns 1 0 0 1 0 00 00 1024 -100 0 0 0 0
92 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
102 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
112 ns 1 0 0 0 1 00 00 0 -100 0 0 0 0
122 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
132 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
142 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
152 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
162 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
172 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
182 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
192 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
202 ns 1 0 0 0 1 00 00 0 -100 0 0 0 0
212 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
222 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
232 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
242 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
252 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
262 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
272 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
282 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
292 ns 1 0 0 0 0 00 00 51 -100 0 0 0 0
302 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
312 ns 1 0 0 1 1 00 00 0 -100 0 0 0 0
322 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
332 ns 1 0 1 0 0 00 00 0 100 0 0 0 0
342 ns 1 1 1 1 1 00 00 0 101 0 0 0 0
352 ns 1 0 0 1 1 00 01 0 102 0 0 0 0
362 ns 1 1 1 1 1 00 00 0 103 0 0 0 0
372 ns 1 1 1 1 1 00 00 0 104 0 0 0 0
382 ns 1 1 1 1 1 00 00 0 105 0 0 0 0
392 ns 1 1 1 1 1 00 00 0 106 0 0 0 0
402 ns 1 1 1 1 1 00 00 0 107 0 0 0 0
412 ns 1 0 1 0 0 00 01 0 200 0 0 0 0
422 ns 1 0 0 1 0 00 00 0 201 0 0 0 0
432 ns 1 0 0 1 1 00 10 0 202 0 0 0 0
442 ns 1 1 1 1 1 00 00 0 203 0 0 0 0
452 ns 1 1 1 1 1 00 00 0 204 0 0 0 0
462 ns 1 1 1 1 1 00 00 0 205 0 0 0 0
472 ns 1 1 1 1 1 00 00 0 206 0 0 0 0
482 ns 1 1 1 1 1 00 00 0 207 0 0 0 0
492 ns 1 0 1 0 0 00 10 0 300 0 0 0 0
502 ns 1 0 0 1 0 00 01 0 301 0 0 0 0
512 ns 1 0 0 1 1 00 11 0 302 0 0 0 0
522 ns 1 1 1 1 1 00 00 0 303 0 0 0 0
532 ns 1 1 1 1 1 00 00 0 304 0 0 0 0
542 ns 1 1 1 1 1 00 00 0 305 0 0 0 0
552 ns 1 1 1 1 1 00 00 0 306 0 0 0 0
562 ns 1 1 1 1 1 00 00 0 307 0 0 0 0
572 ns 1 0 1 0 0 00 11 0 400 0 0 0 0
582 ns 1 0 0 1 0 00 10 0 401 0 0 0 0
592 ns 1 0 0 1 1 00 00 0 402 0 0 0 0
602 ns 1 1 1 1 1 00 00 0 403 0 0 0 0
612 ns 1 1 1 1 1 00 00 0 404 0 0 0 0
622 ns 1 1 1 1 1 00 00 0 405 0 0 0 0
632 ns 1 1 1 1 1 00 00 0 406 0 0 0 0
642 ns 1 1 1 1 1 00 00 0 407 0 0 0 0
652 ns 1 0 1 0 1 00 00 0 -100 0 0 0 0
662 ns 1 0 0 1 0 00 11 0 -100 0 0 0 0
672 ns 1 0 0 1 1 00 01 0 -100 0 0 0 0
682 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
692 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
702 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
712 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
722 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
732 ns 1 0 1 0 1 00 01 0 -100 0 0 0 0
742 ns 1 0 0 1 0 00 00 0 -100 0 0 0 0
752 ns 1 0 0 1 1 00 10 0 -100 0 0 0 0
762 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
772 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
782 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
792 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
802 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
812 ns 1 0 1 0 1 00 10 0 -100 0 0 0 0
822 ns 1 0 0 1 0 00 01 0 -100 0 0 0 0
832 ns 1 0 0 1 1 00 11 0 -100 0 0 0 0
842 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
852 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
862 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
872 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
882 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
892 ns 1 0 1 0 1 00 11 0 -100 0 0 0 0
902 ns 1 0 0 1 0 00 10 0 -100 0 0 0 0
912 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
922 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
932 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
942 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
952 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
962 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
972 ns 1 0 0 1 0 00 11 0 -100 0 0 0 0
982 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
992 ns 1 0 0 1 1 00 00 0 -100 0 0 0 0
1002 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
1012 ns 1 0 1 0 0 00 00 1034 110 0 0 0 0
1022 ns 1 1 1 1 1 00 00 0 111 0 0 0 0
1032 ns 1 1 1 1 1 00 00 0 112 0 0 0 0
1042 ns 1 1 1 1 1 00 00 0 113 0 0 0 0
1052 ns 1 1 1 1 1 00 00 0 114 0 0 0 0
1062 ns 1 1 1 1 1 00 00 0 115 0 0 0 0
1072 ns 1 1 1 1 1 00 00 0 116 0 0 0 0
1082 ns 1 1 1 1 1 00 00 0 117 0 0 0 0
1092 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
1102 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
1112 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
1122 ns 1 0 0 1 1 00 00 0 -100 0 0 0 0
1132 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
1142 ns 1 0 1 1 1 00 00 0 -100 0 1 0 0
1152 ns 1 1 1 1 1 00 00 0 -100 0 0 0 0
lib/models/memory/sdram/mt48lc8m16a2/test.vhd
+197
View File
@@ -0,0 +1,197 @@
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.ALL;
USE work.std_logic_arith.ALL;
USE work.util_1164.ALL;
USE std.textio.ALL;
USE work.mti_pkg.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE test OF tb IS
CONSTANT addr_bits : INTEGER := 12;
CONSTANT data_bits : INTEGER := 16;
CONSTANT clk_start : time := 5 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT continue_time : time := 10 ns;
COMPONENT mt48lc8m16a2
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
Load : IN STD_LOGIC := '0';
Unload : IN STD_LOGIC := '0';
Row_start : IN INTEGER := 0;
Row_end : IN INTEGER := 0
);
END COMPONENT;
FOR ALL : mt48lc8m16a2 USE ENTITY work.mt48lc8m16a2 (behave);
SIGNAL pDq : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
SIGNAL pAddr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
SIGNAL pBa : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL pClk : STD_LOGIC;
SIGNAL pCke : STD_LOGIC;
SIGNAL pCs : STD_LOGIC;
SIGNAL pCas : STD_LOGIC;
SIGNAL pRas : STD_LOGIC;
SIGNAL pWe : STD_LOGIC;
SIGNAL pDqm : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL PLoad : STD_LOGIC;
SIGNAL PUnload : STD_LOGIC;
SIGNAL PRow_start : INTEGER;
SIGNAL PRow_end : INTEGER;
SIGNAL stim_done : boolean := false;
SIGNAL clk_done : boolean := false;
BEGIN
u1: mt48lc8m16a2
PORT MAP(
Dq => pDq,
Addr => pAddr,
Ba => pBa,
Clk => pClk,
Cke => pCke,
Cs_n => pCs,
Ras_n => pRas,
Cas_n => pCas,
We_n => pWe,
Dqm => pDqm,
Load => pLoad,
Unload => pUnload,
Row_start => PRow_start,
Row_end => PRow_end
);
stimulator : PROCESS
FILE stim_file:text IS IN "test.txt";
VARIABLE l : line;
VARIABLE time_var : TIME;
VARIABLE pCke_var : STD_LOGIC;
VARIABLE pCs_var : STD_LOGIC;
VARIABLE pRas_var : STD_LOGIC;
VARIABLE PCas_var : STD_LOGIC;
VARIABLE pWe_var : STD_LOGIC;
VARIABLE pDqm_var : STD_LOGIC_VECTOR (1 DOWNTO 0);
VARIABLE pBa_var : STD_LOGIC_VECTOR (1 DOWNTO 0);
VARIABLE pAddr_var : INTEGER;
VARIABLE pDq_var : INTEGER; -- -100 is converted to hi-Z state
VARIABLE pLoad_var : STD_LOGIC;
VARIABLE pUnload_var : STD_LOGIC;
VARIABLE pRow_start_var : INTEGER;
VARIABLE pRow_end_var : INTEGER;
VARIABLE pMa_var_vect : STD_LOGIC_VECTOR(addr_bits - 1 DOWNTO 0);
CONSTANT HiZ : STD_LOGIC_VECTOR(data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
BEGIN
WHILE not ENDFILE(stim_file) LOOP
readline(stim_file,l);
IF l'length > 0 THEN
read(l, time_var);
read(l, pCke_var);
read(l, pCs_var);
read(l, pRas_var);
read(l, pCas_var);
read(l, pWe_var);
read(l, pDqm_var);
read(l, pBa_var);
read(l, pAddr_var);
read(l, pDq_var);
read (l, pLoad_var);
read (l, pUnload_var);
read (l, pRow_start_var);
read (l, pRow_end_var);
IF now > time_var THEN
ASSERT false
REPORT "Detected a time in the stim file that is in the past"
SEVERITY error;
ELSE
WAIT FOR time_var-now;
IF pWe_var='1' THEN
pCke <= pCke_var;
pCs <= pCs_var;
pRas <= pRas_var;
pCas <= pCas_var;
pWe <= pWe_var;
pDqm <= pDqm_var;
pBa <= pBa_var;
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
pLoad <= pLoad_var;
pUnload <= pUnload_var;
pRow_start <= pRow_start_var;
pRow_end <= pRow_end_var;
ELSE
pCke <= pCke_var;
pCs <= pCs_var;
pRas <= pRas_var;
pCas <= pCas_var;
pWe <= pWe_var;
pDqm <= pDqm_var;
pBa <= pBa_var;
pMa_var_vect := CONV_STD_LOGIC_VECTOR(pAddr_var, addr_bits);
pAddr <= pMa_var_vect;
IF pDq_var = -100 THEN
pDq <= HiZ;
ELSE
pDq <= CONV_STD_LOGIC_VECTOR(pDq_var, data_bits);
END IF;
pLoad <= pLoad_var;
pUnload <= pUnload_var;
pRow_start <= pRow_start_var;
pRow_end <= pRow_end_var;
END IF;
END IF;
END IF;
END LOOP;
ASSERT false
REPORT "End of Stimulation File Detected!"
SEVERITY note;
stim_done <= true;
WAIT;
END PROCESS;
clock : PROCESS
VARIABLE done_time : time;
BEGIN
pclk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
done_time := now+continue_time;
WHILE now < done_time LOOP --one last clock to finish last command
pclk <= '1';
WAIT for clk_period/2;
pclk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT false
REPORT "Suspending clock activity"
SEVERITY note;
clk_done <= true;
WAIT;
END PROCESS;
END test;
lib/models/memory/sdram/mt48lc8m16a2/util1164.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE STD.textio.ALL;
PACKAGE util_1164 IS
PROCEDURE read(l: INOUT line; value: OUT std_logic);
PROCEDURE read(l: INOUT line; value: OUT std_logic_vector);
PROCEDURE write(l: INOUT line; value: IN std_logic_vector;
JUSTIFIED: IN SIDE := right;
FIELD: IN WIDTH := 0);
PROCEDURE Grow_line(L : inout LINE; incr : in integer);
END util_1164;
PACKAGE BODY util_1164 IS
FUNCTION white_space(value:character) RETURN boolean IS
VARIABLE result:boolean;
BEGIN
IF (value = ' ') OR (value = HT) THEN
RETURN true;
ELSE
RETURN false;
END IF;
END white_space;
PROCEDURE read(l: INOUT line; value: OUT std_logic) IS
VARIABLE char_var: character:= ' ';
BEGIN
WHILE l'LENGTH > 0 LOOP
read(l,char_var);
IF NOT white_space(char_var) THEN
EXIT;
END IF;
END LOOP;
IF white_space(char_var) THEN
ASSERT false REPORT "No std_logic value found in file"
SEVERITY error;
value := 'X';
RETURN;
END IF;
CASE char_var IS
WHEN 'U'|'u' => value := 'U';
WHEN '0' => value := '0';
WHEN '1' => value := '1';
WHEN 'X'|'x' => value := 'X';
WHEN 'L'|'l' => value := 'L';
WHEN 'H'|'h' => value := 'H';
WHEN 'W'|'w' => value := 'W';
WHEN 'Z'|'z' => value := 'Z';
WHEN '-' => value := '-';
WHEN OTHERS =>
ASSERT false REPORT "Unrecognized value read for std_logic"
SEVERITY error;
value := 'X';
END CASE;
END read;
PROCEDURE read(l: INOUT line; value: OUT std_logic_vector) IS
BEGIN
FOR i IN value'HIGH DOWNTO value'LOW LOOP
IF l'LENGTH > 0 THEN
read(l,value(i));
ELSE
ASSERT false REPORT "Not enough values for std_logic_vector in file"
SEVERITY error;
RETURN;
END IF;
END LOOP;
END read;
procedure Grow_line(L : inout LINE; incr : in integer)
is
variable old_L : LINE := L;
variable bfp: integer; -- Blank fill pointer.
begin
assert incr > 0
report "Textio: Grow_line called with zero increment."
severity error;
if L = null then
bfp := 0;
L := new string(1 to incr);
else
bfp := old_L'high;
L := new string(old_L'low to old_L'high + incr);
L(old_L'low to old_L'high) := old_L.all;
Deallocate(old_L);
end if;
for i in 1 to incr loop
L(bfp + i) := ' ';
end loop;
end;
PROCEDURE write(l: INOUT line; value: IN std_logic_vector;
JUSTIFIED: IN SIDE := right;
FIELD: IN WIDTH := 0) IS
variable fw: integer := VALUE'length;
variable bp: integer;
variable offset: integer := 0;
alias normal : std_logic_vector(0 to value'length - 1) is value;
begin
if L /= null then
bp := L'high + 1;
else bp := 1;
end if;
if FIELD > VALUE'length then
fw := FIELD;
if JUSTIFIED = right then
offset := fw - VALUE'length;
end if;
end if;
Grow_line(L, fw);
for i in normal'range loop
L(bp + i + offset) := character'val(
std_logic'pos(normal(i)) + character'pos('0'));
end loop;
end;
END util_1164;
lib/models/memory/sdram/mt48lc8m16a2/vec_gen.vhd
+364
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-------------------------------------------------------------------------------
-- --
-- This is a data generator for the testbench for Micron's Synchronous --
-- DRAM. This generator reads a text file line-by-line and generates --
-- a file of test vectors that is then read by the testbench and --
-- applied to the part. --
-- --
-- This VHDL program creates a text file of test vectors that is used by the --
-- test bench. Place your commands in a file (a copy of VEC_GEN.VHD) and run --
-- VEC_GEN.VHD in your VHDL simulator (make sure you have compiled this --
-- package prior to running the program VEC_GEN.VHD). This will produce the --
-- vectors that are required to run the included testbench. Change the name --
-- of the vector file to save your vectors in separate files. The default --
-- file name for the output vectors generated from this pacakage is --
-- "test.txt." --
-- --
-- Now compile and run the testbench program embedtb.vhd. The testbench uses --
-- the default test.txt as input vectors. --
-- --
-- --
-- Copyright 1997 Micron Technology, Inc. --
-- --
-------------------------------------------------------------------------------
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.io_utils.all;
PACKAGE generate_vectors IS
CONSTANT set_up : TIME;
CONSTANT hold : TIME;
CONSTANT cycle_start : TIME;
SIGNAL cycle : INTEGER := 0;
SIGNAL sim_time : TIME := 0 ns;
FILE output_file:TEXT IS OUT "test.txt";
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0);
first_data : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT; cs : IN BIT);
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT);
PROCEDURE auto_refresh;
PROCEDURE next_cycle(SIGNAL clk : IN BIT);
PROCEDURE load_array(load : IN BIT);
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT);
PROCEDURE unload_array(row_start : IN INTEGER; row_end : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0));
END generate_vectors;
PACKAGE BODY generate_vectors IS
CONSTANT set_up : TIME := 3 ns;
CONSTANT hold : TIME := 1 ns;
CONSTANT cycle_start : TIME := 0 ns;
PROCEDURE write(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); first_data : IN INTEGER;
dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, first_data, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE read(col_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE active(row_address : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0); data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, row_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE precharge(bank : IN BIT_VECTOR(1 DOWNTO 0); address : IN INTEGER; data_bus: IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, Cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE nop(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT; cs : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, cs, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE burst_term(data_bus : IN INTEGER; dqm : IN BIT_VECTOR(1 DOWNTO 0); cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE col_address : INTEGER := 0;
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, col_address, right, 6); --address
write(l, data_bus, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE auto_refresh IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE next_cycle(SIGNAL clk : IN BIT) IS
BEGIN
WAIT UNTIL clk = '1';
END;
PROCEDURE load_array(load : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 1, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE unload_array(row_start : IN INTEGER; row_end : IN INTEGER; bank : IN BIT_VECTOR(1 DOWNTO 0)) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, 1, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 1, right, 4); --Ras
write(l, 1, right, 4); --Cas
write(l, 1, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, 0, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 1, right, 4); --unload
write(l, row_start, right, 6); --row_address_start
write(l, row_end, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
PROCEDURE load_mode_reg(op_code : IN INTEGER; cke : IN BIT) IS
VARIABLE l : LINE;
VARIABLE dqm : BIT_VECTOR(1 DOWNTO 0) := "00";
VARIABLE bank : BIT_VECTOR(1 DOWNTO 0) := "00";
BEGIN
IF cycle = 0 THEN
write(l, cycle_start, left, 4, ns);
ELSE
write(l, now-set_up, left, 4, ns);
END IF;
write(l, cke, right, 4); --Cke
write(l, 0, right, 4); --Cs
write(l, 0, right, 4); --Ras
write(l, 0, right, 4); --Cas
write(l, 0, right, 4); --We
write(l, dqm, right, 4); --Dqm
write(l, bank, right, 4); --Ba
write(l, op_code, right, 6); --address
write(l, -100, right, 6); --first data location
write(l, 0, right, 4); --load
write(l, 0, right, 4); --unload
write(l, 0, right, 6); --row_address_start
write(l, 0, right, 6); --row_address_end
writeline(output_file,l); --write vector to file
END;
END generate_vectors;
lib/models/memory/sdram/mt48lc8m16a2/vector.do
+4
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vcom vec_gen.vhd
vcom ed_comnd.vhd
vsim vector_generate
run -all
lib/models/memory/sdram/mt48lc8m16a2/wave.do
+33
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@@ -0,0 +1,33 @@
onerror {resume}
add wave -logic /tb/u1/clk
add wave -logic /tb/u1/cke
add wave -logic /tb/u1/cs_n
add wave -logic /tb/u1/ras_n
add wave -logic /tb/u1/cas_n
add wave -logic /tb/u1/we_n
add wave -literal -decimal /tb/u1/addr
add wave -literal -unsigned /tb/u1/ba
add wave -literal -decimal /tb/u1/dq
add wave -literal /tb/u1/dqm
add wave -literal /tb/u1/operation
add wave -literal -decimal /tb/u1/mode_reg
add wave -logic /tb/u1/active_enable
add wave -logic /tb/u1/aref_enable
add wave -logic /tb/u1/burst_term
add wave -logic /tb/u1/mode_reg_enable
add wave -logic /tb/u1/prech_enable
add wave -logic /tb/u1/read_enable
add wave -logic /tb/u1/write_enable
add wave -logic /tb/u1/burst_length_1
add wave -logic /tb/u1/burst_length_2
add wave -logic /tb/u1/burst_length_4
add wave -logic /tb/u1/burst_length_8
add wave -logic /tb/u1/cas_latency_2
add wave -logic /tb/u1/cas_latency_3
add wave -literal /tb/u1/pre_chk
add wave -literal /tb/u1/act_chk
add wave -literal /tb/u1/bank_chk
add wave -literal -decimal /tb/u1/row_chk
add wave -literal -decimal /tb/u1/col_chk
add wave -logic /tb/u1/dq_in_chk
add wave -logic /tb/u1/dq_out_chk
lib/models/memory/sdram/mt48lc8m8a2/base.do
+5
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@@ -0,0 +1,5 @@
vcom util1164.vhd
vcom stdlogar.vhd
vcom io_utils.vhd
vcom mti_pkg.vhd
lib/models/memory/sdram/mt48lc8m8a2/ed_comnd.vhd
+370
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@@ -0,0 +1,370 @@
--------------------------------------------------------------------------------------------------
-- COMMAND FORMAT --
-- --
-- write(column address(integer), bank(bit_vector), first data(integer), dqm(bit), cke(bit)); --
-- read(column address(integer), bank(bit_vector), dqm(bit), cke(bit)); --
-- active(row address(integer), bank(bit_vector), data bus (integer), dqm(bit), cke(bit)); --
-- precharge(bank(bit_vector), address (integer), data bus(integer), dqm(bit), cke(bit)); --
-- nop(data bus(integer), dqm(bit), cke(bit)); --
-- burst_term(data bus(integer), dqm(bit), cke(bit)); --
-- load_array('1'); --
-- load_mode_reg(register(integer), cke(bit)); --
-- next_cycle(clk); This is used after every command(incl. nop) to clock --
-- at the correct clock frequency entered in the clock --
-- period constant below --
-- unload_array(row_start(integer), row_end(integer), bank(bit_vector)) --
-- load_mode_reg(op_code(integer)) --
-- --
--------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
USE work.generate_vectors.all;
ENTITY vector_generate IS
END vector_generate;
ARCHITECTURE vector_generate OF vector_generate IS
SIGNAL stim_done : BOOLEAN := FALSE;
SIGNAL clk : BIT := '0';
CONSTANT clk_start : time := 15 ns;
CONSTANT clk_period : time := 10 ns;
CONSTANT Z : INTEGER := -100;
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1' AND clk'EVENT;
--------------------ENTER COMMANDS BELOW THIS LINE-----------------------------
--******************DO NOT USE -100 FOR A DQ VALUE*************************----
--*******************Z WILL PLACE HI-Z ON THE BUS**************************----
--*******USE next_cycle(clk) FOR ADVANCING TO NEXT CLOCK CYCLE*************----
nop(Z, '0', '1'); --Always begin with one nop when using Micron's testbench
next_cycle(clk);
load_array;
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
precharge("00", 1024, Z, '0', '1');
FOR i IN 1 to 2 LOOP
next_cycle(clk);
nop(Z, '0', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, '0', '1');
END LOOP;
next_cycle(clk);
auto_refresh;
FOR i IN 1 TO 8 LOOP
next_cycle(clk);
nop(Z, '0', '1');
END LOOP;
next_cycle(clk);
load_mode_reg(49, '1'); -- 19 / 35 / 51 -> lat=3,bl=8,mode=seq
next_cycle(clk);
nop(Z, '0', '1');
-- Write Section
next_cycle(clk);
active(0, "00", Z, '0', '1'); -- Activate Bank 0
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
--write(0, "00", 10, '0', '1'); -- Write Bank 0
write(1024, "00", 10, '0', '1'); -- Write Bank 0 Auto Precharge
next_cycle(clk);
nop(11, '0', '1');
next_cycle(clk);
active(0, "01", 12, '0', '1'); -- Activate Bank 1
next_cycle(clk);
nop(13, '0', '1');
next_cycle(clk);
nop(14, '0', '1');
next_cycle(clk);
nop(15, '0', '1');
next_cycle(clk);
nop(16, '0', '1');
next_cycle(clk);
nop(17, '0', '1');
next_cycle(clk);
--write(0, "01", 20, '0', '1'); -- Write Bank 1
write(1024, "01", 20, '0', '1'); -- Write Bank 1 Auto Precharge
next_cycle(clk);
--precharge("00", 0, 21, '0', '1'); -- Precharge Bank 0
nop(21, '0', '1');
next_cycle(clk);
active(0, "10", 22, '0', '1'); -- Activate Bank 2
next_cycle(clk);
nop(23, '0', '1');
next_cycle(clk);
nop(24, '0', '1');
next_cycle(clk);
nop(25, '0', '1');
next_cycle(clk);
nop(26, '0', '1');
next_cycle(clk);
nop(27, '0', '1');
next_cycle(clk);
--write(0, "10", 30, '0', '1'); -- Write Bank 2
write(1024, "10", 30, '0', '1'); -- Write Bank 2 Auto Precharge
next_cycle(clk);
--precharge("01", 0, 31, '0', '1'); -- Precharge Bank 1
nop(31, '0', '1');
next_cycle(clk);
active(0, "11", 32, '0', '1'); -- Activate Bank 3
next_cycle(clk);
nop(33, '0', '1');
next_cycle(clk);
nop(34, '0', '1');
next_cycle(clk);
nop(35, '0', '1');
next_cycle(clk);
nop(36, '0', '1');
next_cycle(clk);
nop(37, '0', '1');
next_cycle(clk);
--write(0, "11", 40, '0', '1'); -- Write Bank 3
write(1024, "11", 40, '0', '1'); -- Write Bank 3 Auto Precharge
next_cycle(clk);
--precharge("10", 0, 41, '0', '1'); -- Precharge Bank 2
nop(41, '0', '1');
next_cycle(clk);
active(0, "00", 42, '0', '1'); -- Activate Bank 0
next_cycle(clk);
nop(43, '0', '1');
next_cycle(clk);
nop(44, '0', '1');
next_cycle(clk);
nop(45, '0', '1');
next_cycle(clk);
nop(46, '0', '1');
next_cycle(clk);
nop(47, '0', '1');
-- Read Section
next_cycle(clk);
--read(0, "00", '0', '1'); -- Read Bank 0
read(1024, "00", '0', '1'); -- Read Bank 0 Auto Precharge
next_cycle(clk);
--precharge("11", 0, Z, '0', '1'); -- Precharge Bank 3
nop(Z, '0', '1');
next_cycle(clk);
active(0, "01", Z, '0', '1'); -- Activate Bank 1
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
--read(0, "01", '0', '1'); -- Read Bank 1
read(1024, "01", '0', '1'); -- Read Bank 1 Auto Precharge
next_cycle(clk);
--precharge("00", 0, Z, '0', '1'); -- Precharge Bank 0
nop(Z, '0', '1');
next_cycle(clk);
active(0, "10", Z, '0', '1'); -- Activate Bank 2
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
--read(0, "10", '0', '1'); -- Read Bank 2
read(1024, "10", '0', '1'); -- Read Bank 2 Auto Precharge
next_cycle(clk);
--precharge("01", 0, Z, '0', '1'); -- Precharge Bank 1
nop(Z, '0', '1');
next_cycle(clk);
active(0, "11", Z, '0', '1'); -- Activate Bank 3
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
--read(0, "11", '0', '1'); -- Read Bank 3
read(1024, "11", '0', '1'); -- Read Bank 3 Auto Precharge
next_cycle(clk);
--precharge("10", 0, Z, '0', '1'); -- Precharge Bank 2
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
--precharge("11", 0, Z, '0', '1'); -- Precharge Bank 3
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
nop(Z, '0', '1');
next_cycle(clk);
unload_array(0, 1, "00"); -- Unload From Row 0-1, Bank 00
next_cycle(clk);
unload_array(0, 1, "01"); -- Unload From Row 0-1, Bank 10
next_cycle(clk);
unload_array(0, 1, "10"); -- Unload From Row 0-1, Bank 01
next_cycle(clk);
unload_array(0, 1, "11"); -- Unload From Row 0-1, Bank 11
next_cycle(clk);
nop(Z, '0', '1');
stim_done <= TRUE; --always include this line at the end of your stimulus
-------------------------------------------------------------------------------
--*************************************************************************----
END PROCESS;
clock:
PROCESS
VARIABLE done_time : time;
VARIABLE cycle_var : integer := 0;
BEGIN
cycle <= 0;
clk <= '0';
WAIT for clk_start;
WHILE not stim_done loop
clk <= '1';
cycle <= cycle_var;
WAIT for clk_period/2;
cycle_var := cycle_var + 1;
clk <= '0';
WAIT for clk_period/2;
END LOOP;
ASSERT (FALSE)
REPORT "Test Vectors Generated"
SEVERITY note;
WAIT;
END PROCESS;
END;
lib/models/memory/sdram/mt48lc8m8a2/io_utils.vhd
+266
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LIBRARY ieee;
USE std.textio.ALL;
USE ieee.std_logic_1164.ALL;
PACKAGE io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0);
TYPE radix IS (binary, octal, decimal, hex);
-- read a number from the line
-- use this if you have hex numbers that are not in VHDL pound-sign format
PROCEDURE read(l : INOUT line; value : OUT integer; radix : IN positive);
-- read a number that might be in VHDL pound-sign format
PROCEDURE read_based(l : INOUT line; value : OUT integer);
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
END io_utils;
PACKAGE BODY io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0)
IS
BEGIN
write(l, value, justified, field);
END;
PROCEDURE shrink_line(l : INOUT line; pos : integer) IS
VARIABLE tmpl : line;
BEGIN
tmpl := l;
l := NEW string'(tmpl(pos TO tmpl'high));
deallocate(tmpl);
END;
PROCEDURE read(l : INOUT line;
value : OUT integer;
radix : IN positive)
IS
CONSTANT not_digit : integer := -999;
-- convert a character to a value from 0 to 15
FUNCTION digit_value(c : character) RETURN integer IS
BEGIN
IF (c >= '0') AND (c <= '9') THEN
RETURN (character'pos(c) - character'pos('0'));
ELSIF (c >= 'a') AND (c <= 'f') THEN
RETURN (character'pos(c) - character'pos('a') + 10);
ELSIF (c >= 'A') AND (c <= 'F') THEN
RETURN (character'pos(c) - character'pos('A') + 10);
ELSE
RETURN not_digit;
END IF;
END;
-- skip leading white space in the line
PROCEDURE skip_white(VARIABLE l : IN line; pos : OUT integer) IS
BEGIN
pos := l'low;
FOR i IN l'low TO l'high LOOP
CASE l(i) IS
WHEN ' ' | ht =>
pos := i + 1;
WHEN OTHERS =>
EXIT;
END CASE;
END LOOP;
END;
VARIABLE digit : integer;
VARIABLE result : integer := 0;
VARIABLE pos : integer;
BEGIN
-- skip white space
skip_white(l, pos);
-- calculate the value
FOR i IN pos TO l'right LOOP
digit := digit_value(l(i));
EXIT WHEN (digit = not_digit) OR (digit >= radix);
result := result * radix + digit;
pos := i + 1;
END LOOP;
value := result;
-- remove the "used" characters from the line
shrink_line(l, pos);
END;
PROCEDURE read_based(l : INOUT line; value : OUT integer) IS
VARIABLE digit : integer;
VARIABLE num : integer;
VARIABLE base : integer;
BEGIN
read(l, num, 10);
IF (l'length > 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
base := num;
read(l, num, base);
IF (l'length >= 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
END IF;
END IF;
value := num;
END;
PROCEDURE write(l : INOUT line;
value : IN std_logic_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_int(bv : std_logic_vector) RETURN integer
IS
VARIABLE result : integer := 0;
BEGIN
FOR i IN bv'RANGE LOOP
result := result * 2;
IF (bv(i) = '1') THEN
result := result + 1;
END IF;
END LOOP;
RETURN result;
END;
TYPE array_of_widths IS ARRAY(radix) OF natural;
CONSTANT nibble_widths : array_of_widths := (
binary => 1,
octal => 3,
hex => 4,
decimal=> 32);
CONSTANT hex_digit : string(1 TO 16) := "0123456789ABCDEF";
ALIAS input_val : std_logic_vector(value'length DOWNTO 1) IS value;
CONSTANT nibble_width : natural := nibble_widths(base);
CONSTANT result_width : natural := (value'length + nibble_width - 1)/nibble_width;
VARIABLE result : string(1 TO result_width); -- longest possible value
VARIABLE result_pos : positive := 1;
VARIABLE nibble_val : integer;
VARIABLE bitcnt : integer;
BEGIN
IF base = decimal THEN
write(l, to_int(value), justified, field, base, use_pound);
RETURN;
END IF;
bitcnt := value'length MOD nibble_width;
IF (bitcnt = 0) THEN
bitcnt := nibble_width;
END IF;
FOR i IN input_val'RANGE LOOP
nibble_val := nibble_val * 2;
IF (input_val(i) = '1') THEN
nibble_val := nibble_val + 1;
END IF;
bitcnt := bitcnt - 1;
IF (bitcnt = 0) THEN
result(result_pos) := hex_digit(nibble_val + 1);
result_pos := result_pos + 1;
nibble_val := 0;
bitcnt := nibble_width;
END IF;
END LOOP;
write(l, result, justified, field);
END;
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_bv(int : integer) RETURN std_logic_vector
IS
VARIABLE bv : std_logic_vector(32 DOWNTO 1) := (OTHERS => '0');
VARIABLE pos : integer := 0;
VARIABLE tmpval : integer := int;
BEGIN
FOR i IN 1 TO 32 LOOP
pos := pos + 1;
IF (tmpval MOD 2) = 1 THEN
bv(i) := '1';
END IF;
tmpval := tmpval / 2;
EXIT WHEN tmpval = 0;
END LOOP;
RETURN bv(pos DOWNTO 1);
END;
VARIABLE tmp : line;
BEGIN
IF (base = decimal) THEN
IF (use_pound) THEN
write_string(tmp, "10#");
END IF;
write(tmp, value);
IF (use_pound) THEN
write_string(tmp, "#");
END IF;
write(l, tmp.ALL, justified, field);
deallocate(tmp);
ELSE
write(l, to_bv(value), justified, field, base, use_pound);
END IF;
END;
END io_utils;
-- test the hex number reader
--ENTITY test IS END;
--USE std.textio.ALL;
--USE work.io_utils.ALL;
--ARCHITECTURE hex_test OF test IS
--BEGIN
-- PROCESS
-- VARIABLE val : integer;
-- FILE myfile : text IS IN "values";
-- VARIABLE inline : line;
-- VARIABLE outline : line;
-- BEGIN
-- WHILE NOT endfile(myfile) LOOP
-- readline(myfile, inline);
-- write(outline, inline.ALL);
--
-- read_based(inline, val);
-- write_string(outline, " binary: ");
-- write(outline, val, base => binary);
-- write_string(outline, " octal: ");
-- write(outline, val, base => octal);
-- write_string(outline, " decimal: ");
-- write(outline, val, base => decimal);
-- write_string(outline, " hex: ");
-- write(outline, val, base => hex);
-- writeline(output, outline);
-- END LOOP;
-- WAIT;
-- END PROCESS;
--END;
lib/models/memory/sdram/mt48lc8m8a2/loaddata.txt
+41
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@@ -0,0 +1,41 @@
0 0 00 0 -- ROW (HEX), COL (HEX), BANK (BIN), DATA (HEX)
0 1 00 1
0 2 00 2
0 3 00 3
0 4 00 4
0 5 00 5
0 6 00 6
0 7 00 7
0 8 00 8
0 9 00 9
0 0 01 10
0 1 01 11
0 2 01 12
0 3 01 13
0 4 01 14
0 5 01 15
0 6 01 16
0 7 01 17
0 8 01 18
0 9 01 19
0 0 10 20
0 1 10 21
0 2 10 22
0 3 10 23
0 4 10 24
0 5 10 25
0 6 10 26
0 7 10 27
0 8 10 28
0 9 10 29
0 0 11 30
0 1 11 31
0 2 11 32
0 3 11 33
0 4 11 34
0 5 11 35
0 6 11 36
0 7 11 37
0 8 11 38
0 9 11 39

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