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git-svn-id: http://moon:8086/svn/vhdl/trunk@1290 cc03376c-175c-47c8-b038-4cd826a8556b
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2015-06-10 19:27:35 +00:00
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commit 2edaa4d7cb
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lib/models/memory/flash/serial/S25fl512s/model/model_release_history.txt
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##########################################
Date (DD/MM/YYYY) - 16.11.2009
Model name - S25FL256S
Vendor - Spansion (www.spansion.com)
Publication ID - S25FL128 256 512 01GS MRS Rev0 98
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
##########################################
##########################################
INITIAL RELEASE
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2009-11-16-1.tar.gz
# Release Date (DD/MM/YYYY) => 16/11/2009
# Release Version => 1.0
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2009-11-19-2.tar.gz
# Release Date (DD/MM/YYYY) => 19/11/2009
# Release Version => 1.1
# Corrections:
# 1.Negative tests which show how model behaves when reset pulse
# width is less than specified and when write and erase operations are interrupted .
# with reset signal are interrupted with reset signal are added.
# 2.Implementation of Continuous Read Mode
# 3.After 8 clock cycles for instruction, first address bit is latched on the next
# rising edge of clock.
# Files modified
-s25fl512s.vhd
-testbench_s25fl512s_vhdl.vhd
-spansion_tc_pkg.vhd
-s25fl512s.ftm
-s25fl512s_vhdl.sdf
-s25fl512s.v
-testbench_s25fl512s_verilog.vhd
-s25fl512s.ftmv
-s25fl512s_verilog.sdf
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-03-04-1.tar.gz
# Release Date (DD/MM/YYYY) => 04/03/2010
# Release Version => 1.2
# Corrections:
# 1.Array variable WByte in sensitivity list is replaced with signal WB_flag to enable
# compilation in NCSim
# 2.addr_cnt for second read in high performance read continuous mode can change its
# value only when CSNeg = '0'
# Files modified
-s25fl512s.v
-s25fl512s.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-04-15-1.tar.gz
# Release Date (DD/MM/YYYY) => 15/04/2010
# Release Version => 1.3
# Corrections:
# 1.HOLD mode corrected
# 2.Condition for PP operation corrected
# Files modified
-s25fl512s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-05-21-1.tar.gz
# Release Date (DD/MM/YYYY) => 21/05/2010
# Release Version => 1.4
# Corrections:
# 1.SRWD bit assignment is corrected
# 2.Condition for WRR command in write_cycle_decode section is corrected
# 3.Blocking assignments for signals WSTART and PSTART are replaced with
# nonblocking assignments
# 4.Conditions in Page Program section are fixed
#
# Files modified
-s25fl512s.v
-s25fl512s.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-05-25-1.tar.gz
# Release Date (DD/MM/YYYY) => 25/05/2010
# Release Version => 1.5
# Corrections:
# 1. Timing control sections for Program and Erase operation are changed
# 2. Conditions in Page Program section are fixed
#
# Files modified
-s25fl512s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-06-03-2.tar.gz
# Release Date (DD/MM/YYYY) => 03/06/2010
# Release Version => 1.6
# Corrections:
# 1. bus_cycle_state section for PGSP command is fixed
#
# Files modified
-s25fl512s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-07-28-1.tar.gz
# Release Date (DD/MM/YYYY) => 28/07/2010
# Release Version => 1.7
# Corrections:
# 1. During the QUAD mode HOLD# input is not monitored for its normal function
# 2. Internal pull-up resistors for HOLD# and WP# inputs are implemented
# Files modified
-s25fl512s.v
-s25fl512s.vhd
##########################################
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-08-24-1.tar.gz
# Release Date (DD/MM/YYYY) => 24/08/2010
# Release Version => 1.8
# Corrections:
# 1. All redundant signals are removed from BusCycle process
# Files modified
-s25fl512s.v
-s25fl512s.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-10-14-1.tar.gz
# Release Date (DD/MM/YYYY) => 14/10/2010
# Release Version => 1.9
# Corrections:
# 1. Latest datasheet aligned (VERILOG files only)
# Files modified
-spansion_tc_pkg.vhd
-s25fl512s.v
-testbench_s25fl512s_verilog.vhd
-s25fl512s.ftmv
-s25fl512s_verilog.sdf
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-10-20-1.tar.gz
# Release Date (DD/MM/YYYY) => 20/10/2010
# Release Version => 2.0
# Corrections:
# 1. Latest datasheet aligned (VHDL files added)
# Files modified
-s25fl512s.vhd
-testbench_s25fl512s_vhdl.vhd
-s25fl512s.ftm
-s25fl512s_vhdl.sdf
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-10-22-2.tar.gz
# Release Date (DD/MM/YYYY) => 22/10/2010
# Release Version => 2.1
# Corrections:
# 1. Latest datasheet aligned (VHDL files added)
# Files modified
-s25fl512s.vhd
-testbench_s25fl512s_vhdl.vhd
-s25fl512s.ftm
-s25fl512s_verilog.sdf
-s25fl512s.v
-s25fl512s.sv
-testbench_s25fl512s_verilog.vhd
-s25fl512s.ftmv
-s25fl512s_vhdl.sdf
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-11-05-1.tar.gz
# Release Date (DD/MM/YYYY) => 05/11/2010
# Release Version => 2.2
# Corrections:
# 1. Latest datasheet aligned
# Files modified
-spansion_tc_pkg.vhd
-s25fl512s.vhd
-testbench_s25fl512s_vhdl.vhd
-s25fl512s.v
-s25fl512s.sv
-testbench_s25fl512s_verilog.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
Hana Dimitrijevic
h-dimitrijevic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-11-15-1.tar.gz
# Release Date (DD/MM/YYYY) => 15/11/2010
# Release Version => 2.3
# Corrections:
# 1. QUAD Program operation during Erase Suspend is added
# 2. Warning for Resume to Suspend time is added
# 3. During Erase Suspend, after Program operation is completed, WEL bit is cleared
# 4. Implementation of Software Reset is Changed
# 5. ADDRHILO_PG procedure corrected
# Files modified
-spansion_tc_pkg.vhd
-s25fl512s.v
-s25fl512s.vhd
##########################################
##########################################
VITAL model author - Snezana Petrovic
s-petrovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2011-04-18-1.tar.gz
# Release Date (DD/MM/YYYY) => 18/04/2011
# Release Version => 2.4
# Corrections:
- corrected timing for internal signal rising_edge_CSNeg_ipd
# Files modified
-s25fl512s.v
-s25fl512s.sv
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2011-07-11-1.tar.gz
# Release Date (DD/MM/YYYY) => 11/07/2011
# Release Version => 2.5
# Corrections:
- Latest Datasheet Aligned
# Files modified
-s25fl512s.v
-s25fl512s.vhd
-testbench_s25fl512s_verilog.vhd
-testbench_s25fl512s_vhdl.vhd
-spansion_tc_pkg.vhd
-s25fl512s.ftmv
-s25fl512s.ftm
-s25fl512s_verilog.sdf
-s25fl512s_vhdl.sdf
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2011-07-15-2.tar.gz
# Release Date (DD/MM/YYYY) => 15/07/2011
# Release Version => 2.6
# Corrections:
- Optimization issue is fixed
- Timingmodel is corrected
# Files modified
-s25fl512s.v
-s25fl512s.sv
-testbench_s25fl512s_vhdl.vhd
-testbench_s25fl512s_verilog.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2011-07-22-1.tar.gz
# Release Date (DD/MM/YYYY) => 22/07/2011
# Release Version => 2.7
# Corrections:
- Timing check issue is fixed
- Correction for P4E and P4E4 instructions
# Files modified
-s25fl512s.v
-s25fl512s.sv
-s25fl512s.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2011-11-18-1.tar.gz
# Release Date (DD/MM/YYYY) => 18/11/2011
# Release Version => 2.8
# Corrections:
- Time tHO is changed to 1 ns (customer's request)
- Setting of Device protection mode is modified (customer's request)
- BRWR instruction is corrected
# Files modified
-s25fl512s.v
-s25fl512s.vhd
-testbench_s25fl512s_verilog.vhd
-testbench_s25fl512s_vhdl.vhd
-s25fl512s.ftmv
-s25fl512s.ftm
-s25fl512s_verilog.sdf
-s25fl512s_vhdl.sdf
##########################################
##########################################
VITAL model author - Snezana Petrovic
s-petrovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2012-06-02-1.tar.gz
# Release Date (DD/MM/YYYY) => 02/06/2012
# Release Version => 2.9
# Corrections:
- OPP instruction is allowed in previously programmed page
# Files modified
-s25fl512s.v
-s25fl512s.sv
-s25fl512s.vhd
-testbench_s25fl512s_verilog.vhd
-testbench_s25fl512s_vhdl.vhd
-spansion_tc_pkg.vhd
##########################################
lib/models/memory/flash/serial/S25fl512s/model/s25fl512s.sv
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lib/models/memory/flash/serial/S25fl512s/model/s25fl512s.v
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lib/models/memory/flash/serial/S25fl512s/model/s25fl512s.vhd
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lib/models/memory/flash/serial/S25fl512s/model/s25fl512s_ver.ftm
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<!DOCTYPE FTML SYSTEM "ftml.dtd">
<FTML><HEAD><TITLE>FMF Timing for s25fl512s Parts</TITLE>
<BODY>
<REVISION.HISTORY>
version: | author: | mod date: | changes made:
V1.0 R. Prokopovic 09 Nov 27 Initial release
V1.1 V.Mancev 10 Oct 20 Latest datasheet aligned
V1.2 B.Colakovic 11 July 11 Latest datasheet aligned
V1.3 V.Mancev 11 Nov 17 Time tHO is changed to 1 ns
</REVISION.HISTORY>
<TIMESCALE>1ns</TIMESCALE>
<MODEL>s25fl512s
<FMFTIME>
S25FL512SAGMFI010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for VIO=VCC=2.7V to 3.6V, CL=30pF </COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (3))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (2))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (4.8))
(WIDTH (COND dual_rd (negedge SCK)) (4.8))
(WIDTH (COND fast_rd (negedge SCK)) (3.75))
(WIDTH (COND fast_rd (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SAGMFI010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR11_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR11_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI210_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI213_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI310_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI313_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV210_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV213_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV310_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV313_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=30pF </COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (3))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (2))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (4.8))
(WIDTH (COND dual_rd (negedge SCK)) (4.8))
(WIDTH (COND fast_rd (negedge SCK)) (3.75))
(WIDTH (COND fast_rd (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SAGMFI010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR11_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR11_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI210_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI213_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI310_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI313_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV210_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV213_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV310_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV313_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=15pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (3))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (2))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (4.8))
(WIDTH (COND dual_rd (negedge SCK)) (4.8))
(WIDTH (COND fast_rd (negedge SCK)) (3.75))
(WIDTH (COND fast_rd (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SDPMFIR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for Vcc range VCC=2.7V to 3.6V, CL=30pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (5))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (5))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (4))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (5))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (7.5))
(WIDTH (COND dual_rd (negedge SCK)) (7.5))
(WIDTH (COND fast_rd (negedge SCK)) (7.5))
(WIDTH (COND fast_rd (posedge SCK)) (7.5))
(WIDTH (COND quadpg (posedge SCK)) (7.5))
(WIDTH (COND quadpg (negedge SCK)) (7.5))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (15))
(PERIOD (COND dual_rd SCK) (15))
(PERIOD (COND quadpg SCK) (15))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SDPMFIR10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR11_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI210_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI213_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI310_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI313_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for Vcc range VCC=2.7V to 3.6V, CL=15pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (5))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (5))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (4))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (5))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (7.5))
(WIDTH (COND dual_rd (negedge SCK)) (7.5))
(WIDTH (COND fast_rd (negedge SCK)) (7.5))
(WIDTH (COND fast_rd (posedge SCK)) (7.5))
(WIDTH (COND quadpg (posedge SCK)) (7.5))
(WIDTH (COND quadpg (negedge SCK)) (7.5))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (15))
(PERIOD (COND dual_rd SCK) (15))
(PERIOD (COND quadpg SCK) (15))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
lib/models/memory/flash/serial/S25fl512s/model/s25fl512s_vhd.ftm
+547
View File
@@ -0,0 +1,547 @@
<!DOCTYPE FTML SYSTEM "ftml.dtd">
<FTML><HEAD><TITLE>FMF Timing for s25fl512s Parts</TITLE>
<BODY>
<REVISION.HISTORY>
version: | author: | mod date: | changes made:
V1.0 V.Mancev 09 Nov 26 Initial release
V1.1 V.Mancev 11 July 11 Latest datasheet aligned
V1.2 V.Mancev 11 Nov 17 Time tHO is changed to 1 ns
</REVISION.HISTORY>
<TIMESCALE>1ns</TIMESCALE>
<MODEL>s25fl512s
<FMFTIME>
S25FL512SAGMFI010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for VCC=2.7V to 3.6V, CL=30pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (3))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (3))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (2))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (3))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (4.8))
(WIDTH (COND dual (negedge SCK)) (4.8))
(WIDTH (COND fast (negedge SCK)) (3.75))
(WIDTH (COND fast (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP) (DELAY (ABSOLUTE (DEVICE(200e3:340e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(100e3:150e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE) (DELAY (ABSOLUTE (DEVICE(200e6:400e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:103e9:460e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SAGMFI010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR11_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR11_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI210_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI213_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI310_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI313_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV210_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV213_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV310_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV313_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=30pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (3))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (3))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (2))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (3))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (4.8))
(WIDTH (COND dual (negedge SCK)) (4.8))
(WIDTH (COND fast (negedge SCK)) (3.75))
(WIDTH (COND fast (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP) (DELAY (ABSOLUTE (DEVICE(200e3:340e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(100e3:150e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE) (DELAY (ABSOLUTE (DEVICE(200e6:400e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:103e9:460e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SAGMFI010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR11_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR11_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI210_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI213_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI310_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI313_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV210_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV213_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV310_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV313_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=15pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (3))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (3))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (2))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (3))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (4.8))
(WIDTH (COND dual (negedge SCK)) (4.8))
(WIDTH (COND fast (negedge SCK)) (3.75))
(WIDTH (COND fast (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP) (DELAY (ABSOLUTE (DEVICE(200e3:340e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(100e3:150e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE) (DELAY (ABSOLUTE (DEVICE(200e6:400e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:103e9:460e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SDPMFIR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=30pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (10:12:14) (10:12:14) (10:12:14) (10:12:14))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (5))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (5))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (4))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (5))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (7.5))
(WIDTH (COND dual (negedge SCK)) (7.5))
(WIDTH (COND fast (negedge SCK)) (7.5))
(WIDTH (COND fast (posedge SCK)) (7.5))
(WIDTH (COND quadpg (posedge SCK)) (7.5))
(WIDTH (COND quadpg (negedge SCK)) (7.5))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (15))
(PERIOD (COND dual_rd SCK) (15))
(PERIOD (COND quadpg SCK) (15))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP) (DELAY (ABSOLUTE (DEVICE(200e3:340e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(100e3:150e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE) (DELAY (ABSOLUTE (DEVICE(200e6:400e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:103e9:460e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SDPMFIR10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR11_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI210_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI213_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI310_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI313_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=15pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (10:12:14) (10:12:14) (10:12:14) (10:12:14))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (5))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (5))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (4))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (5))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (7.5))
(WIDTH (COND dual (negedge SCK)) (7.5))
(WIDTH (COND fast (negedge SCK)) (7.5))
(WIDTH (COND fast (posedge SCK)) (7.5))
(WIDTH (COND quadpg (posedge SCK)) (7.5))
(WIDTH (COND quadpg (negedge SCK)) (7.5))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (15))
(PERIOD (COND dual_rd SCK) (15))
(PERIOD (COND quadpg SCK) (15))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP) (DELAY (ABSOLUTE (DEVICE(200e3:340e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(100e3:150e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE) (DELAY (ABSOLUTE (DEVICE(200e6:400e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:103e9:460e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>