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git-svn-id: http://moon:8086/svn/vhdl/trunk@1290 cc03376c-175c-47c8-b038-4cd826a8556b
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2015-06-10 19:27:35 +00:00
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lib/models/memory/flash/serial/S25fl512s/Model_Manual_English.pdf
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##########################################
Date (DD/MM/YYYY) - 16.11.2009
Model name - S25FL256S
Vendor - Spansion (www.spansion.com)
Publication ID - S25FL128 256 512 01GS MRS Rev0 98
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
##########################################
##########################################
INITIAL RELEASE
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2009-11-16-1.tar.gz
# Release Date (DD/MM/YYYY) => 16/11/2009
# Release Version => 1.0
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2009-11-19-2.tar.gz
# Release Date (DD/MM/YYYY) => 19/11/2009
# Release Version => 1.1
# Corrections:
# 1.Negative tests which show how model behaves when reset pulse
# width is less than specified and when write and erase operations are interrupted .
# with reset signal are interrupted with reset signal are added.
# 2.Implementation of Continuous Read Mode
# 3.After 8 clock cycles for instruction, first address bit is latched on the next
# rising edge of clock.
# Files modified
-s25fl512s.vhd
-testbench_s25fl512s_vhdl.vhd
-spansion_tc_pkg.vhd
-s25fl512s.ftm
-s25fl512s_vhdl.sdf
-s25fl512s.v
-testbench_s25fl512s_verilog.vhd
-s25fl512s.ftmv
-s25fl512s_verilog.sdf
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-03-04-1.tar.gz
# Release Date (DD/MM/YYYY) => 04/03/2010
# Release Version => 1.2
# Corrections:
# 1.Array variable WByte in sensitivity list is replaced with signal WB_flag to enable
# compilation in NCSim
# 2.addr_cnt for second read in high performance read continuous mode can change its
# value only when CSNeg = '0'
# Files modified
-s25fl512s.v
-s25fl512s.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-04-15-1.tar.gz
# Release Date (DD/MM/YYYY) => 15/04/2010
# Release Version => 1.3
# Corrections:
# 1.HOLD mode corrected
# 2.Condition for PP operation corrected
# Files modified
-s25fl512s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-05-21-1.tar.gz
# Release Date (DD/MM/YYYY) => 21/05/2010
# Release Version => 1.4
# Corrections:
# 1.SRWD bit assignment is corrected
# 2.Condition for WRR command in write_cycle_decode section is corrected
# 3.Blocking assignments for signals WSTART and PSTART are replaced with
# nonblocking assignments
# 4.Conditions in Page Program section are fixed
#
# Files modified
-s25fl512s.v
-s25fl512s.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-05-25-1.tar.gz
# Release Date (DD/MM/YYYY) => 25/05/2010
# Release Version => 1.5
# Corrections:
# 1. Timing control sections for Program and Erase operation are changed
# 2. Conditions in Page Program section are fixed
#
# Files modified
-s25fl512s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-06-03-2.tar.gz
# Release Date (DD/MM/YYYY) => 03/06/2010
# Release Version => 1.6
# Corrections:
# 1. bus_cycle_state section for PGSP command is fixed
#
# Files modified
-s25fl512s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-07-28-1.tar.gz
# Release Date (DD/MM/YYYY) => 28/07/2010
# Release Version => 1.7
# Corrections:
# 1. During the QUAD mode HOLD# input is not monitored for its normal function
# 2. Internal pull-up resistors for HOLD# and WP# inputs are implemented
# Files modified
-s25fl512s.v
-s25fl512s.vhd
##########################################
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-08-24-1.tar.gz
# Release Date (DD/MM/YYYY) => 24/08/2010
# Release Version => 1.8
# Corrections:
# 1. All redundant signals are removed from BusCycle process
# Files modified
-s25fl512s.v
-s25fl512s.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-10-14-1.tar.gz
# Release Date (DD/MM/YYYY) => 14/10/2010
# Release Version => 1.9
# Corrections:
# 1. Latest datasheet aligned (VERILOG files only)
# Files modified
-spansion_tc_pkg.vhd
-s25fl512s.v
-testbench_s25fl512s_verilog.vhd
-s25fl512s.ftmv
-s25fl512s_verilog.sdf
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-10-20-1.tar.gz
# Release Date (DD/MM/YYYY) => 20/10/2010
# Release Version => 2.0
# Corrections:
# 1. Latest datasheet aligned (VHDL files added)
# Files modified
-s25fl512s.vhd
-testbench_s25fl512s_vhdl.vhd
-s25fl512s.ftm
-s25fl512s_vhdl.sdf
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-10-22-2.tar.gz
# Release Date (DD/MM/YYYY) => 22/10/2010
# Release Version => 2.1
# Corrections:
# 1. Latest datasheet aligned (VHDL files added)
# Files modified
-s25fl512s.vhd
-testbench_s25fl512s_vhdl.vhd
-s25fl512s.ftm
-s25fl512s_verilog.sdf
-s25fl512s.v
-s25fl512s.sv
-testbench_s25fl512s_verilog.vhd
-s25fl512s.ftmv
-s25fl512s_vhdl.sdf
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-11-05-1.tar.gz
# Release Date (DD/MM/YYYY) => 05/11/2010
# Release Version => 2.2
# Corrections:
# 1. Latest datasheet aligned
# Files modified
-spansion_tc_pkg.vhd
-s25fl512s.vhd
-testbench_s25fl512s_vhdl.vhd
-s25fl512s.v
-s25fl512s.sv
-testbench_s25fl512s_verilog.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
Hana Dimitrijevic
h-dimitrijevic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2010-11-15-1.tar.gz
# Release Date (DD/MM/YYYY) => 15/11/2010
# Release Version => 2.3
# Corrections:
# 1. QUAD Program operation during Erase Suspend is added
# 2. Warning for Resume to Suspend time is added
# 3. During Erase Suspend, after Program operation is completed, WEL bit is cleared
# 4. Implementation of Software Reset is Changed
# 5. ADDRHILO_PG procedure corrected
# Files modified
-spansion_tc_pkg.vhd
-s25fl512s.v
-s25fl512s.vhd
##########################################
##########################################
VITAL model author - Snezana Petrovic
s-petrovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2011-04-18-1.tar.gz
# Release Date (DD/MM/YYYY) => 18/04/2011
# Release Version => 2.4
# Corrections:
- corrected timing for internal signal rising_edge_CSNeg_ipd
# Files modified
-s25fl512s.v
-s25fl512s.sv
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2011-07-11-1.tar.gz
# Release Date (DD/MM/YYYY) => 11/07/2011
# Release Version => 2.5
# Corrections:
- Latest Datasheet Aligned
# Files modified
-s25fl512s.v
-s25fl512s.vhd
-testbench_s25fl512s_verilog.vhd
-testbench_s25fl512s_vhdl.vhd
-spansion_tc_pkg.vhd
-s25fl512s.ftmv
-s25fl512s.ftm
-s25fl512s_verilog.sdf
-s25fl512s_vhdl.sdf
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2011-07-15-2.tar.gz
# Release Date (DD/MM/YYYY) => 15/07/2011
# Release Version => 2.6
# Corrections:
- Optimization issue is fixed
- Timingmodel is corrected
# Files modified
-s25fl512s.v
-s25fl512s.sv
-testbench_s25fl512s_vhdl.vhd
-testbench_s25fl512s_verilog.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2011-07-22-1.tar.gz
# Release Date (DD/MM/YYYY) => 22/07/2011
# Release Version => 2.7
# Corrections:
- Timing check issue is fixed
- Correction for P4E and P4E4 instructions
# Files modified
-s25fl512s.v
-s25fl512s.sv
-s25fl512s.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2011-11-18-1.tar.gz
# Release Date (DD/MM/YYYY) => 18/11/2011
# Release Version => 2.8
# Corrections:
- Time tHO is changed to 1 ns (customer's request)
- Setting of Device protection mode is modified (customer's request)
- BRWR instruction is corrected
# Files modified
-s25fl512s.v
-s25fl512s.vhd
-testbench_s25fl512s_verilog.vhd
-testbench_s25fl512s_vhdl.vhd
-s25fl512s.ftmv
-s25fl512s.ftm
-s25fl512s_verilog.sdf
-s25fl512s_vhdl.sdf
##########################################
##########################################
VITAL model author - Snezana Petrovic
s-petrovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl512s-2012-06-02-1.tar.gz
# Release Date (DD/MM/YYYY) => 02/06/2012
# Release Version => 2.9
# Corrections:
- OPP instruction is allowed in previously programmed page
# Files modified
-s25fl512s.v
-s25fl512s.sv
-s25fl512s.vhd
-testbench_s25fl512s_verilog.vhd
-testbench_s25fl512s_vhdl.vhd
-spansion_tc_pkg.vhd
##########################################
lib/models/memory/flash/serial/S25fl512s/model/s25fl512s.sv
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<!DOCTYPE FTML SYSTEM "ftml.dtd">
<FTML><HEAD><TITLE>FMF Timing for s25fl512s Parts</TITLE>
<BODY>
<REVISION.HISTORY>
version: | author: | mod date: | changes made:
V1.0 R. Prokopovic 09 Nov 27 Initial release
V1.1 V.Mancev 10 Oct 20 Latest datasheet aligned
V1.2 B.Colakovic 11 July 11 Latest datasheet aligned
V1.3 V.Mancev 11 Nov 17 Time tHO is changed to 1 ns
</REVISION.HISTORY>
<TIMESCALE>1ns</TIMESCALE>
<MODEL>s25fl512s
<FMFTIME>
S25FL512SAGMFI010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for VIO=VCC=2.7V to 3.6V, CL=30pF </COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (3))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (2))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (4.8))
(WIDTH (COND dual_rd (negedge SCK)) (4.8))
(WIDTH (COND fast_rd (negedge SCK)) (3.75))
(WIDTH (COND fast_rd (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SAGMFI010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR11_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR11_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI210_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI213_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI310_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI313_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV210_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV213_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV310_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV313_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=30pF </COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (3))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (2))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (4.8))
(WIDTH (COND dual_rd (negedge SCK)) (4.8))
(WIDTH (COND fast_rd (negedge SCK)) (3.75))
(WIDTH (COND fast_rd (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SAGMFI010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR11_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR11_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI210_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI213_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI310_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI313_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV210_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV213_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV310_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV313_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=15pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (3))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (2))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (4.8))
(WIDTH (COND dual_rd (negedge SCK)) (4.8))
(WIDTH (COND fast_rd (negedge SCK)) (3.75))
(WIDTH (COND fast_rd (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SDPMFIR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for Vcc range VCC=2.7V to 3.6V, CL=30pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (5))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (5))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (4))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (5))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (7.5))
(WIDTH (COND dual_rd (negedge SCK)) (7.5))
(WIDTH (COND fast_rd (negedge SCK)) (7.5))
(WIDTH (COND fast_rd (posedge SCK)) (7.5))
(WIDTH (COND quadpg (posedge SCK)) (7.5))
(WIDTH (COND quadpg (negedge SCK)) (7.5))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (15))
(PERIOD (COND dual_rd SCK) (15))
(PERIOD (COND quadpg SCK) (15))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SDPMFIR10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR11_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI210_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI213_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI310_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI313_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for Vcc range VCC=2.7V to 3.6V, CL=15pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (5))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (5))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (4))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (5))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (7.5))
(WIDTH (COND dual_rd (negedge SCK)) (7.5))
(WIDTH (COND fast_rd (negedge SCK)) (7.5))
(WIDTH (COND fast_rd (posedge SCK)) (7.5))
(WIDTH (COND quadpg (posedge SCK)) (7.5))
(WIDTH (COND quadpg (negedge SCK)) (7.5))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (15))
(PERIOD (COND dual_rd SCK) (15))
(PERIOD (COND quadpg SCK) (15))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
lib/models/memory/flash/serial/S25fl512s/model/s25fl512s_vhd.ftm
+547
View File
@@ -0,0 +1,547 @@
<!DOCTYPE FTML SYSTEM "ftml.dtd">
<FTML><HEAD><TITLE>FMF Timing for s25fl512s Parts</TITLE>
<BODY>
<REVISION.HISTORY>
version: | author: | mod date: | changes made:
V1.0 V.Mancev 09 Nov 26 Initial release
V1.1 V.Mancev 11 July 11 Latest datasheet aligned
V1.2 V.Mancev 11 Nov 17 Time tHO is changed to 1 ns
</REVISION.HISTORY>
<TIMESCALE>1ns</TIMESCALE>
<MODEL>s25fl512s
<FMFTIME>
S25FL512SAGMFI010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for VCC=2.7V to 3.6V, CL=30pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (3))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (3))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (2))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (3))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (4.8))
(WIDTH (COND dual (negedge SCK)) (4.8))
(WIDTH (COND fast (negedge SCK)) (3.75))
(WIDTH (COND fast (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP) (DELAY (ABSOLUTE (DEVICE(200e3:340e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(100e3:150e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE) (DELAY (ABSOLUTE (DEVICE(200e6:400e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:103e9:460e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SAGMFI010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR11_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR11_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI210_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI213_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI310_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI313_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV210_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV213_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV310_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV313_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=30pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (3))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (3))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (2))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (3))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (4.8))
(WIDTH (COND dual (negedge SCK)) (4.8))
(WIDTH (COND fast (negedge SCK)) (3.75))
(WIDTH (COND fast (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP) (DELAY (ABSOLUTE (DEVICE(200e3:340e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(100e3:150e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE) (DELAY (ABSOLUTE (DEVICE(200e6:400e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:103e9:460e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SAGMFI010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFI013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR11_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFIR13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFV013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR11_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGMFVR13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI210_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI213_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI310_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHI313_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIA13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIB13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIC13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHID13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV210_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV213_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV310_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHV313_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVA13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVB13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVC13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHVD13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIY13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIZ13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIS13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIT13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIK13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SAGBHIL13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=15pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (3))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (3))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (2))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (3))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (4.8))
(WIDTH (COND dual (negedge SCK)) (4.8))
(WIDTH (COND fast (negedge SCK)) (3.75))
(WIDTH (COND fast (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP) (DELAY (ABSOLUTE (DEVICE(200e3:340e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(100e3:150e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE) (DELAY (ABSOLUTE (DEVICE(200e6:400e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:103e9:460e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SDPMFIR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=30pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (10:12:14) (10:12:14) (10:12:14) (10:12:14))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (5))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (5))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (4))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (5))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (7.5))
(WIDTH (COND dual (negedge SCK)) (7.5))
(WIDTH (COND fast (negedge SCK)) (7.5))
(WIDTH (COND fast (posedge SCK)) (7.5))
(WIDTH (COND quadpg (posedge SCK)) (7.5))
(WIDTH (COND quadpg (negedge SCK)) (7.5))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (15))
(PERIOD (COND dual_rd SCK) (15))
(PERIOD (COND quadpg SCK) (15))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP) (DELAY (ABSOLUTE (DEVICE(200e3:340e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(100e3:150e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE) (DELAY (ABSOLUTE (DEVICE(200e6:400e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:103e9:460e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL512SDPMFIR10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR11_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPMFIR13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI210_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI213_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI310_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHI313_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHIC13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL512SDPBHID13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=15pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (10:12:14) (10:12:14) (10:12:14) (10:12:14))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (5))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (5))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (4))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (5))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (7.5))
(WIDTH (COND dual (negedge SCK)) (7.5))
(WIDTH (COND fast (negedge SCK)) (7.5))
(WIDTH (COND fast (posedge SCK)) (7.5))
(WIDTH (COND quadpg (posedge SCK)) (7.5))
(WIDTH (COND quadpg (negedge SCK)) (7.5))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (15))
(PERIOD (COND dual_rd SCK) (15))
(PERIOD (COND quadpg SCK) (15))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP) (DELAY (ABSOLUTE (DEVICE(200e3:340e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(100e3:150e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE) (DELAY (ABSOLUTE (DEVICE(200e6:400e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:103e9:460e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
lib/models/memory/flash/serial/S25fl512s/utilities/CreateSDF/mk_sdf.cmd
+10
View File
@@ -0,0 +1,10 @@
SET sdffile_suffix .sdf
SET use_global_timing_dir false
SET timingfile_dir /user/USERNAME/CreateSDF
SET timingfile_suffix .ftm
SET time_scale 1ns
SET local_path .
SET vendor MODELSIM_HOME
SET diagnostics on
SET vhdl_file testbench.vhd
SET lwb false
lib/models/memory/flash/serial/S25fl512s/utilities/CreateSDF/mk_sdf_204.pl
+462
View File
@@ -0,0 +1,462 @@
#!/usr/local/bin/perl
#
# mk_sdf : Perl replacement for C mk_sdf
#
# Copyright (C) 2000, 1999 Free Model Foundry; http:/vhdl.org/fmf/
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License version 2 as
# published by the Free Software Foundation.
#
# Author : R. Munden
# Date : 20001115
# Version : 2.0.4
#
# Revision history:
# 2.0: 19990702
# o Intial release of perl version
# 2.0.1: 19990722
# o fixed problem with . in path for TimingModels
# 2.0.2: 20000616
# o changed instance search to work with Mentor
# 2.0.3: 20001115
# o changed to parse ":" without leading space
# o fixed problem with . in path for TimingModels again
# 2.0.4: 20030405
# o chaged SDF version to 3.0
#
#################################################################
#
# command line arguments:
# ARGV[0] - name of VHDL netlist
# global variables:
# %component_list - list of instance names by component name
# %instance_isin - list architectures by instances contained therein
# %instance_comp - list of component names by instance name
# %comp_lib - library each component (by name) is configured to
# @instance_list - array of all instance names in design in order found
$version = "2.0.4";
$design_name = '';
$timing_dir = '';
$diags = "off";
%keywords = (architecture => 1,
component => 1,
timingmodel => 1);
# INPUT files
$CMD = "mk_sdf.cmd";
$VHD = ''; # name of VHDL netlist
# OUTPUT files
$RFV = "/tmp/short.vhd"; # reformatted VHDL
$sdf_file = ''; # name of SDF file
&read_cmd_file;
&get_names;
&reformat;
open INPUT, $RFV;
@lines = <INPUT>;
close INPUT;
$current_architecture = "";
foreach $line (@lines)
{
@words = split / /, $line;
foreach $word (@words)
{
$keywords{$word} == "1" and do { &$word(@words);};
if ($component_list{$word})
{
$line =~ /(.+) : $word/ and do {
if ($1 !~ /for/) { # instantiation found
$component_list{$word} = $component_list{$word} . $1;
push (@instance_list, $1);
$instance_name = $1;
}
};
$instance_comp{$1} = $word;
$instance_isin{$1} = $current_architecture;
if ( $diags ne off ) {
print "reading instance $instance_name: $word in $current_architecture\n";
}
$line =~ /for all : $word use entity (.+)/ and do
{
@config = split(/\./, $1);
$comp_lib{$word} = $config[0];};
}
}
}
if ( $diags ne off ) {
print "finished with netlist\n\n";
}
&begin_sdf;
&build_paths;
&close_sdf;
`rm $RFV`;
print "$time\n";
sub architecture
{
$current_architecture = $_[3];
push (@architectures, $current_architecture);
}
sub component
{
if ($_[0] ne "end")
{
$name = $_[1];
$arch_list{$current_architecture} =
$arch_list{$current_architecture} . " " . $name;
unless ($component_list{$name}) { $component_list{$name} = " ";}
}
}
sub timingmodel
{
$line =~ /timingmodel => \"(.+)\"/ and do {
$model = $1;
$model_name{$instance_name} = $model;
};
}
sub begin_sdf
{
if ( $diags ne off ) {
print "writing SDF boilerplate\n";
}
$time = localtime;
if (open(SDF, ">$sdf_file") !=1) { die "can't open $sdf_file\n";}
print "Opening $sdf_file\n";
print SDF "(DELAYFILE\n";
print SDF " (SDFVERSION \"3.0\")\n";
print SDF " (DESIGN \"$design_name\")\n";
print SDF " (DATE \"$time\")\n";
print SDF " (VENDOR \"Free Model Foundry\")\n";
print SDF " (PROGRAM \"SDF timing utility(tm)\")\n";
print SDF " (VERSION \"$version\")\n";
print SDF " (DIVIDER /)\n";
print SDF " (VOLTAGE)\n";
print SDF " (PROCESS)\n";
print SDF " (TEMPERATURE)\n";
print SDF " (TIMESCALE 1ns)\n";
}
sub build_paths
{
foreach $instance_list (@instance_list)
{
@instance = $instance_list;
foreach $instance (@instance)
{
if ( $diags ne off ) {
print "working on $instance\n";
}
if ($gtd =~ /true/i) {
$path = "$lib_path{$comp_lib{$instance_comp{$instance}}}/$timing_dir";
# $path = "$lib_path{$comp_lib{$instance_comp{$instance}}}./$timing_dir";
} else {
$path = "$lib_path{$comp_lib{$instance_comp{$instance}}}/$timing_dir";
}
$timing_file = "$path/$instance_comp{$instance}_vhd.ftm";
$timing_file =~ s/\s//;
if ( $diags ne off ) {
print "$instance should be in $timing_file\n";
}
if (-e $timing_file) {
if ($model_name{$instance} ne "") {
print SDF " (CELL\n";
print SDF " (CELLTYPE \"$instance_comp{$instance}\")\n";
$inst = $instance;
$full_inst = $instance;
while ($component_list{$instance_isin{$inst}}) {
$full_inst = "$component_list{$instance_isin{$inst}}/$full_inst";
$full_inst =~ s/\s+//;
$inst = $component_list{$instance_isin{$inst}};
$inst =~ s/\s+//;
# print SDF " (INSTANCE $component_list{$instance_isin{$instance}}/$instance)\n";
}
print SDF " (INSTANCE $full_inst)\n";
&add_timing;
}
} else {
if ( $diags ne off ) {
print "$timing_file not found!\n";
}
}
}
}
}
sub add_timing
{
$timing_found = "false";
$part_found = "false";
# unless ($lib_path{$comp_lib{$instance_comp{$instance}}})
unless ($timing_file)
{
print "path to $timing_file not found\n";
exit;
}
if ($gtd =~ /true/i) {
$path = "$lib_path{$comp_lib{$instance_comp{$instance}}}/$timing_dir";
# $path = "$lib_path{$comp_lib{$instance_comp{$instance}}}./$timing_dir";
} else {
$path = "$lib_path{$comp_lib{$instance_comp{$instance}}}/$timing_dir";
}
$timing_file = "$path/$instance_comp{$instance}_vhd.ftm";
if (open(TF, "<$timing_file") !=1) { warn "can't open $timing_file\n"; }
if ( $diags ne off ) {
print "reading $timing_file\n";
}
$section_found = "false";
while (<TF>)
{
next unless (/$model_name{$instance}/i || ($part_found eq "true"));
$part_found = "true";
if ( $diags ne off ) {
print "found entry for $model_name{$instance}\n";
}
next unless (/<timing>/i || ($timing_found eq "true"));
$timing_found = "true";
next if (/<timing>/i);
if (/<\/timing>/i)
{
print SDF " )\n";
$timing_found = "false";
$part_found = "false";
$section_found = "true";
last;
} else {
if (/%LABEL%/)
{
if ($component_list{$instance_isin{$instance}})
{
$_ =~ s/%LABEL%/$component_list{$instance_isin{$instance}}\/$instance/;
} else {
$_ =~ s/%LABEL%/$instance/;
}
}
print SDF $_;
}
}
unless ($section_found eq "true") {
print "$model_name not found\n";
}
}
sub close_sdf
{
print SDF ")\n";
print "closing $sdf_file\n";
close(SDF);
}
# read mk_sdf.cmd
sub read_cmd_file {
if (open(CMD, $CMD) !=1) { die "can't open $CMD\n"; }
while (<CMD>) {
chop;
@fields = '';
@fields = split;
unless ($fields[0] =~ /#/) {
if ($fields[0] =~ /SET/) {
if ($fields[1] =~ /vhdl_file/) {$VHD = $fields[2]}
if ($fields[1] =~ /sdffile_suffix/) {$suffix = $fields[2]}
if ($fields[1] =~ /use_global_timing_dir/) {$gtd = $fields[2]}
if ($fields[1] =~ /timingfile_dir/) {$timing_dir = $fields[2]}
if ($fields[1] =~ /vendor/) {$vendor = $fields[2]}
if ($fields[1] =~ /diagnostics/) {$diags = $fields[2]}
}
}
}
if ( $diags ne off ) {
print "\nmk_sdf diagnostics on\n\n";
print "vhdl_file $VHD\n";
print "sdffile_suffix $suffix\n";
print "use_global_timing_dir $gtd\n";
print "timingfile_dir $timing_dir\n";
print "vendor $vendor\n\n";
}
}
#
# get name of netlist
sub get_names
{
if ($ARGV[0] ne "") { $VHD = "$ARGV[0]"; }
if ($ARGV[1] eq "")
{
@name = split(/\./,$VHD);
$design_name = $name[0];
} else {
$design_name = "$ARGV[1]";
}
$sdf_file = $design_name . $suffix;
if ($gtd =~ /false/i)
{
if ($vendor =~ /modeltech/i) { &read_mti; }
if ($vendor =~ /cadence/i) { &read_cds; }
}
if ( $diags ne off ) {
print "design name is $design_name\n\n";
}
}
#
################################################################
#
# reformat netlist
sub reformat
{
$entfound = false;
if (open(VHD, $VHD) !=1) { die "can't open $VHD\n"; }
if (open(OUT, ">$RFV") !=1) { die "can't open $OUT\n"; }
while (<VHD>) {
if (/^--|library|package/i) { next }
if (/--/) { # strip embeded comments
@line = split("--");
$_ = $line[0];
}
s/:/ : /g;
s/;/ ;/g;
s/\s+/ /g; # reduces spaces and tabs
s/^\s//g; # no leading spaces
if (/entity/i) {
$entfound = "true";
}
chomp;
if ( $entfound eq true ) {
print OUT lc($_);
if (/;|is|begin/i) { print OUT "\n"; }
}
}
close OUT;
if ( $diags ne off ) {
print "reformatted netlist written to $RFV\n\n";
}
}
# read ModelTech's modelsim.ini file
sub read_mti
{
$lib_found = "false";
if ($ENV{MODELPATH})
{
$ini_file = "$ENV{MODELPATH}/../modelsim.ini";
if (open(INI, "$ini_file") !=1) { die "can't open $ini_file\n";}
if ( $diags ne off ) {
print "reading $ini_file\n\n";
}
while (<INI>)
{
if ($lib_found eq "true")
{
chomp;
if (/\[.+\]/) { last; }
s/\s+//;
@lib_line = split(/=/);
$lib_line[1] =~ s/\/work//;
$lib_path{$lib_line[0]} = $lib_line[1];
} elsif (/\[Library\]/i)
{
$lib_found = "true";
next;
}
}
} else {
print "\$MODELPATH environment variable not found\n";
}
$lib_found = "false";
if (-e "modelsim.ini")
{
$ini_file = "modelsim.ini";
if (open(INI, "$ini_file") !=1) { die "can't open $ini_file\n";}
if ( $diags ne off ) {
print "reading $ini_file\n\n";
}
while (<INI>)
{
if ($lib_found eq "true")
{
chomp;
if (/\[.+\]/) { last; }
s/\s+//;
@lib_line = split(/=/);
$lib_line[1] =~ s/\/work//;
$lib_path{$lib_line[0]} = $lib_line[1];
} elsif (/\[Library\]/i)
{
$lib_found = "true";
next;
}
}
} else {
print "local modelsim.ini file not found, may not be needed\n";
}
}
# read Cadence's cds.lib file
sub read_cds
{
if ($ENV{CDS_VHDL})
{
$ini_file = "$ENV{CDS_VHDL}/files/cds.lib";
if (open(INI, "$ini_file") !=1) { die "can't open $ini_file\n";}
if ( $diags ne off ) {
print "reading $ini_file\n\n";
}
while (<INI>)
{
chomp;
s/\s+/ /;
if (/define/i)
{
@lib_line = split;
$lib_path{$lib_line[1]} = $lib_line[2];
}
}
} else {
print "\$CDS_VHDL environment variable not found\n";
}
if (-e "cds.lib")
{
$ini_file = "cds.lib";
if (open(INI, "$ini_file") !=1) { die "can't open $ini_file\n";}
if ( $diags ne off ) {
print "reading $ini_file\n\n";
}
while (<INI>)
{
chomp;
s/\s+/ /;
if (/define/i)
{
@lib_line = split;
$lib_path{$lib_line[1]} = $lib_line[2];
}
}
} else {
print "local cds.lib file not found, may not be needed\n";
}
}
lib/models/memory/flash/serial/S25fl512s/utilities/CreateSDF/my_mem_vhd.ftm
+205
View File
@@ -0,0 +1,205 @@
<!DOCTYPE FTML SYSTEM "ftml.dtd">
<FTML><HEAD><TITLE>FMF Timing for testbench Parts</TITLE>
<BODY>
<REVISION.HISTORY>
version: | author: | mod date: | changes made:
V1.0 VHD2FTM 03 July 11 Initial release
</REVISION.HISTORY>
<TIMESCALE>1ns</TIMESCALE>
<MODEL>am29lv640m
<FMFTIME>
MY_MEM<SOURCE></SOURCE>
AM29LV640MH90R<SOURCE></SOURCE>
AM29LV640ML90R<SOURCE></SOURCE>
<COMMENT></COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(IOPATH A0 DQ0 (90:90:90) (90:90:90))
(IOPATH A0 DQ1 (25:25:25) (25:25:25))
(IOPATH CENeg DQ0 (85:85:85) (85:85:85) (11:11:11) (85:85:85) (11:11:11) (85:85:85))
(IOPATH OENeg DQ0 (20:20:20) (20:20:20) (11:11:11) (20:20:20) (11:11:11) (20:20:20))
(IOPATH RESETNeg DQ0 () () (0:0:0) () (0:0:0) ())
(IOPATH CENeg RY (0) (90))
(IOPATH WENeg RY (0) (90))
))
(TIMINGCHECK
(SETUP A0 CENeg (0:0:0))
(SETUP A0 OENeg (15:15:15))
(SETUP DQ0 CENeg (45:45:45))
(HOLD CENeg RESETNeg (50:50:50))
(HOLD OENeg WENeg (0:0:0))
(HOLD A0 CENeg (45:45:45))
(HOLD A0 OENeg (0:0:0))
(HOLD DQ0 CENeg (0:0:0))
(HOLD WENeg OENeg (0:0:0))
(WIDTH (negedge RESETNeg) (500:500:500))
(WIDTH (posedge OENeg) (20:20:20))
(WIDTH (negedge WENeg) (35:35:35))
(WIDTH (posedge WENeg) (30:30:30))
(WIDTH (negedge CENeg) (45:45:45))
(WIDTH (posedge CENeg) (30:30:30))
(WIDTH (negedge A0) (90:90:90))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/WBPB) (DELAY (ABSOLUTE (DEVICE(11000:11000:11000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/POB) (DELAY (ABSOLUTE (DEVICE(100000:100000:100000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/SEO) (DELAY (ABSOLUTE (DEVICE(500000000:500000000:500000000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/HANG) (DELAY (ABSOLUTE (DEVICE(400000000:400000000:400000000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/START_T1) (DELAY (ABSOLUTE (DEVICE(5000:5000:20000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/CTMOUT) (DELAY (ABSOLUTE (DEVICE(50000:50000:50000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/READY) (DELAY (ABSOLUTE (DEVICE(20000:20000:20000) ) ) )
</TIMING></FMFTIME>
<FMFTIME>
AM29LV640MH101<SOURCE></SOURCE>
AM29LV640ML101<SOURCE></SOURCE>
AM29LV640MH101R<SOURCE></SOURCE>
AM29LV640ML101R<SOURCE></SOURCE>
<COMMENT></COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(IOPATH A0 DQ0 (100:100:100) (100:100:100))
(IOPATH A0 DQ1 (30:30:30) (30:30:30))
(IOPATH CENeg DQ0 (95:95:95) (95:95:95) (11:11:11) (95:95:95) (11:11:11) (95:95:95))
(IOPATH OENeg DQ0 (25:25:25) (25:25:25) (11:11:11) (25:25:25) (11:11:11) (25:25:25))
(IOPATH RESETNeg DQ0 () () (0:0:0) () (0:0:0) ())
(IOPATH CENeg RY (0) (100))
(IOPATH WENeg RY (0) (100))
))
(TIMINGCHECK
(SETUP A0 CENeg (0:0:0))
(SETUP A0 OENeg (15:15:15))
(SETUP DQ0 CENeg (45:45:45))
(HOLD CENeg RESETNeg (50:50:50))
(HOLD OENeg WENeg (0:0:0))
(HOLD A0 CENeg (45:45:45))
(HOLD A0 OENeg (0:0:0))
(HOLD DQ0 CENeg (0:0:0))
(HOLD WENeg OENeg (0:0:0))
(WIDTH (negedge RESETNeg) (500:500:500))
(WIDTH (posedge OENeg) (20:20:20))
(WIDTH (negedge WENeg) (35:35:35))
(WIDTH (posedge WENeg) (30:30:30))
(WIDTH (negedge CENeg) (45:45:45))
(WIDTH (posedge CENeg) (30:30:30))
(WIDTH (negedge A0) (100:100:100))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/WBPB) (DELAY (ABSOLUTE (DEVICE(11000:11000:11000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/POB) (DELAY (ABSOLUTE (DEVICE(100000:100000:100000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/SEO) (DELAY (ABSOLUTE (DEVICE(500000000:500000000:500000000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/HANG) (DELAY (ABSOLUTE (DEVICE(400000000:400000000:400000000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/START_T1) (DELAY (ABSOLUTE (DEVICE(5000:5000:20000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/CTMOUT) (DELAY (ABSOLUTE (DEVICE(50000:50000:50000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/READY) (DELAY (ABSOLUTE (DEVICE(20000:20000:20000) ) ) )
</TIMING></FMFTIME>
<FMFTIME>
AM29LV640MH112<SOURCE></SOURCE>
AM29LV640ML112<SOURCE></SOURCE>
AM29LV640MH112R<SOURCE></SOURCE>
AM29LV640ML112R<SOURCE></SOURCE>
<COMMENT></COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(IOPATH A0 DQ0 (110:110:110) (110:110:110))
(IOPATH A0 DQ1 (40:40:40) (40:40:40))
(IOPATH CENeg DQ0 (105:105:105) (105:105:105) (11:11:11) (105:105:105) (11:11:11) (105:105:105))
(IOPATH OENeg DQ0 (35:35:35) (35:35:35) (11:11:11) (35:35:35) (11:11:11) (35:35:35))
(IOPATH RESETNeg DQ0 () () (0:0:0) () (0:0:0) ())
(IOPATH CENeg RY (0) (110))
(IOPATH WENeg RY (0) (110))
))
(TIMINGCHECK
(SETUP A0 CENeg (0:0:0))
(SETUP A0 OENeg (15:15:15))
(SETUP DQ0 CENeg (45:45:45))
(HOLD CENeg RESETNeg (50:50:50))
(HOLD OENeg WENeg (0:0:0))
(HOLD A0 CENeg (45:45:45))
(HOLD A0 OENeg (0:0:0))
(HOLD DQ0 CENeg (0:0:0))
(HOLD WENeg OENeg (0:0:0))
(WIDTH (negedge RESETNeg) (500:500:500))
(WIDTH (posedge OENeg) (20:20:20))
(WIDTH (negedge WENeg) (35:35:35))
(WIDTH (posedge WENeg) (30:30:30))
(WIDTH (negedge CENeg) (45:45:45))
(WIDTH (posedge CENeg) (30:30:30))
(WIDTH (negedge A0) (110:110:110))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/WBPB) (DELAY (ABSOLUTE (DEVICE(11000:11000:11000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/POB) (DELAY (ABSOLUTE (DEVICE(100000:100000:100000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/SEO) (DELAY (ABSOLUTE (DEVICE(500000000:500000000:500000000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/HANG) (DELAY (ABSOLUTE (DEVICE(400000000:400000000:400000000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/START_T1) (DELAY (ABSOLUTE (DEVICE(5000:5000:20000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/CTMOUT) (DELAY (ABSOLUTE (DEVICE(50000:50000:50000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/READY) (DELAY (ABSOLUTE (DEVICE(20000:20000:20000) ) ) )
</TIMING></FMFTIME>
<FMFTIME>
AM29LV640MH120<SOURCE></SOURCE>
AM29LV640ML120<SOURCE></SOURCE>
AM29LV640MH120R<SOURCE></SOURCE>
AM29LV640ML120R<SOURCE></SOURCE>
<COMMENT></COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(IOPATH A0 DQ0 (120:120:120) (120:120:120))
(IOPATH A0 DQ1 (40:40:40) (40:40:40))
(IOPATH CENeg DQ0 (115:115:115) (115:115:115) (11:11:11) (115:115:115) (11:11:11) (115:115:115))
(IOPATH OENeg DQ0 (35:35:35) (35:35:35) (11:11:11) (35:35:35) (11:11:11) (35:35:35))
(IOPATH RESETNeg DQ0 () () (0:0:0) () (0:0:0) ())
(IOPATH CENeg RY (0) (120))
(IOPATH WENeg RY (0) (120))
))
(TIMINGCHECK
(SETUP A0 CENeg (0:0:0))
(SETUP A0 OENeg (15:15:15))
(SETUP DQ0 CENeg (45:45:45))
(HOLD CENeg RESETNeg (50:50:50))
(HOLD OENeg WENeg (0:0:0))
(HOLD A0 CENeg (45:45:45))
(HOLD A0 OENeg (0:0:0))
(HOLD DQ0 CENeg (0:0:0))
(HOLD WENeg OENeg (0:0:0))
(WIDTH (negedge RESETNeg) (500:500:500))
(WIDTH (posedge OENeg) (20:20:20))
(WIDTH (negedge WENeg) (35:35:35))
(WIDTH (posedge WENeg) (30:30:30))
(WIDTH (negedge CENeg) (45:45:45))
(WIDTH (posedge CENeg) (30:30:30))
(WIDTH (negedge A0) (120:120:120))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/WBPB) (DELAY (ABSOLUTE (DEVICE(11000:11000:11000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/POB) (DELAY (ABSOLUTE (DEVICE(100000:100000:100000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/SEO) (DELAY (ABSOLUTE (DEVICE(500000000:500000000:500000000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/HANG) (DELAY (ABSOLUTE (DEVICE(400000000:400000000:400000000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/START_T1) (DELAY (ABSOLUTE (DEVICE(5000:5000:20000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/CTMOUT) (DELAY (ABSOLUTE (DEVICE(50000:50000:50000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/READY) (DELAY (ABSOLUTE (DEVICE(20000:20000:20000) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
lib/models/memory/flash/serial/S25fl512s/utilities/CreateSDF/testbench.sdf
+58
View File
@@ -0,0 +1,58 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "testbench")
(DATE "Wed Jan 28 15:15:41 2004")
(VENDOR "Free Model Foundry")
(PROGRAM "SDF timing utility(tm)")
(VERSION "2.0.4")
(DIVIDER /)
(VOLTAGE)
(PROCESS)
(TEMPERATURE)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "my_mem")
(INSTANCE dut)
(DELAY (ABSOLUTE
(IOPATH A0 DQ0 (90:90:90) (90:90:90))
(IOPATH A0 DQ1 (25:25:25) (25:25:25))
(IOPATH CENeg DQ0 (85:85:85) (85:85:85) (11:11:11) (85:85:85) (11:11:11) (85:85:85))
(IOPATH OENeg DQ0 (20:20:20) (20:20:20) (11:11:11) (20:20:20) (11:11:11) (20:20:20))
(IOPATH RESETNeg DQ0 () () (0:0:0) () (0:0:0) ())
(IOPATH CENeg RY (0) (90))
(IOPATH WENeg RY (0) (90))
))
(TIMINGCHECK
(SETUP A0 CENeg (0:0:0))
(SETUP A0 OENeg (15:15:15))
(SETUP DQ0 CENeg (45:45:45))
(HOLD CENeg RESETNeg (50:50:50))
(HOLD OENeg WENeg (0:0:0))
(HOLD A0 CENeg (45:45:45))
(HOLD A0 OENeg (0:0:0))
(HOLD DQ0 CENeg (0:0:0))
(HOLD WENeg OENeg (0:0:0))
(WIDTH (negedge RESETNeg) (500:500:500))
(WIDTH (posedge OENeg) (20:20:20))
(WIDTH (negedge WENeg) (35:35:35))
(WIDTH (posedge WENeg) (30:30:30))
(WIDTH (negedge CENeg) (45:45:45))
(WIDTH (posedge CENeg) (30:30:30))
(WIDTH (negedge A0) (90:90:90))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/WBPB) (DELAY (ABSOLUTE (DEVICE(11000:11000:11000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/POB) (DELAY (ABSOLUTE (DEVICE(100000:100000:100000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/SEO) (DELAY (ABSOLUTE (DEVICE(500000000:500000000:500000000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/HANG) (DELAY (ABSOLUTE (DEVICE(400000000:400000000:400000000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/START_T1) (DELAY (ABSOLUTE (DEVICE(5000:5000:20000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/CTMOUT) (DELAY (ABSOLUTE (DEVICE(50000:50000:50000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE dut/READY) (DELAY (ABSOLUTE (DEVICE(20000:20000:20000) ) ) )
)
)
lib/models/memory/flash/serial/S25fl512s/utilities/CreateSDF/testbench.vhd
+1606
View File
File diff suppressed because it is too large Load Diff
lib/models/memory/flash/serial/S25fl512s/utilities/conversions.vhd
+1035
View File
File diff suppressed because it is too large Load Diff
lib/models/memory/flash/serial/S25fl512s/utilities/gen_utils.vhd
+144
View File
@@ -0,0 +1,144 @@
--------------------------------------------------------------------------------
-- File name: gen_utils.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1996, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Steele 96 SEP 26 Initial release
-- V1.1 REV3 97 Feb 27 Added Xon and MsgOn generics
-- V1.2 R. Steele 97 APR 16 Changed wired-or to wired-and
-- V1.3 R. Steele 97 APR 16 Added diff. receiver table
-- V1.4 R. Munden 98 APR 13 Added GenParity and CheckParity
-- V1.5 R. Munden 01 NOV 24 Added UnitDelay01ZX
--
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_Logic_1164.ALL;
USE IEEE.VITAL_primitives.ALL;
USE IEEE.VITAL_timing.ALL;
PACKAGE gen_utils IS
----------------------------------------------------------------------------
-- Result map for Wired-and output values (open collector)
----------------------------------------------------------------------------
CONSTANT STD_wired_and_rmap : VitalResultMapType := ('U','X','0','Z');
----------------------------------------------------------------------------
-- Table for computing a single signal from a differential receiver input
-- pair.
----------------------------------------------------------------------------
CONSTANT diff_rec_tab : VitalStateTableType := (
------INPUTS--|-PREV-|-OUTPUT----
-- A ANeg | Aint | Aint' --
--------------|------|-----------
( 'X', '-', '-', 'X'), -- A unknown
( '-', 'X', '-', 'X'), -- A unknown
( '1', '-', 'X', '1'), -- Recover from 'X'
( '0', '-', 'X', '0'), -- Recover from 'X'
( '/', '0', '0', '1'), -- valid diff. rising edge
( '1', '\', '0', '1'), -- valid diff. rising edge
( '\', '1', '1', '0'), -- valid diff. falling edge
( '0', '/', '1', '0'), -- valid diff. falling edge
( '-', '-', '-', 'S') -- default
); -- end of VitalStateTableType definition
----------------------------------------------------------------------------
-- Default Constants
----------------------------------------------------------------------------
CONSTANT UnitDelay : VitalDelayType := 1 ns;
CONSTANT UnitDelay01 : VitalDelayType01 := (1 ns, 1 ns);
CONSTANT UnitDelay01Z : VitalDelayType01Z := (others => 1 ns);
CONSTANT UnitDelay01ZX : VitalDelayType01ZX := (others => 1 ns);
CONSTANT DefaultInstancePath : STRING := "*";
CONSTANT DefaultTimingChecks : BOOLEAN := FALSE;
CONSTANT DefaultTimingModel : STRING := "UNIT";
CONSTANT DefaultXon : BOOLEAN := TRUE;
CONSTANT DefaultMsgOn : BOOLEAN := TRUE;
-- Older VITAL generic being phased out
CONSTANT DefaultXGeneration : BOOLEAN := TRUE;
-------------------------------------------------------------------
-- Generate Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION GenParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic_vector;
-------------------------------------------------------------------
-- Check Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION CheckParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic; -- '0' - Parity Error
END gen_utils;
PACKAGE BODY gen_utils IS
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
-------------------------------------------------------------------
-- Generate Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION GenParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic_vector
IS
VARIABLE I: NATURAL;
VARIABLE Result: std_logic_vector (Data'Length - 1 DOWNTO 0);
BEGIN
I := 0;
WHILE (I < SIZE) LOOP
Result(I+7 DOWNTO I) := Data(I+7 downto I);
Result(I+8) := XOR_REDUCE( Data(I+7 downto I) ) XOR ODDEVEN;
I := I + 9;
END LOOP;
RETURN Result;
END GenParity;
-------------------------------------------------------------------
-- Check Parity for each 8-bit in 9th bit
-------------------------------------------------------------------
FUNCTION CheckParity
(Data : in std_logic_vector; -- Data
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
SIZE : in POSITIVE) -- Bit Size
RETURN std_logic -- '0' - Parity Error
IS
VARIABLE I: NATURAL;
VARIABLE Result: std_logic;
BEGIN
I := 0; Result := '1';
WHILE (I < SIZE) LOOP
Result := Result AND
NOT (XOR_REDUCE( Data(I+8 downto I) ) XOR ODDEVEN);
I := I + 9;
END LOOP;
RETURN Result;
END CheckParity;
END gen_utils;