- added models

git-svn-id: http://moon:8086/svn/vhdl/trunk@1290 cc03376c-175c-47c8-b038-4cd826a8556b
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##########################################
Date (DD/MM/YYYY) - 11.11.2009
Model name - S25FL128S
Vendor - Spansion (www.spansion.com)
Publication ID - S25FL128 256 512 01GS MRS Rev0 98
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
Hana Dimitrijevic
h-dimitrijevic@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
##########################################
INITIAL RELEASE
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2009-11-11-3.tar.gz
# Release Date (DD/MM/YYYY) => 11/11/2009
# Release Version => 1.0
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
Hana Dimitrijevic
h-dimitrijevic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2009-11-12-1.tar.gz
# Release Date (DD/MM/YYYY) => 12/11/2009
# Release Version => 1.1
# Correction of s25fl128s.v file :
# State transition from Program Suspend to Autoboot state when
# RESET command is initiated, is delayed with additional 500 ps.
# (For compatibility with Modelsim 6.4b Version)
# Files modified
-s25fl128s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2009-11-20-1.tar.gz
# Release Date (DD/MM/YYYY) => 20/11/2009
# Release Version => 1.2
# Corrections:
# 1.Negative tests which show how model behaves when reset pulse
# width is less than specified and when write and erase operations are interrupted .
# with reset signal are interrupted with reset signal are added.
# 2.Implementation of Continuous Read Mode
# 3.After 8 clock cycles for instruction, first address bit is latched on the next
# rising edge of clock.
# Files modified
-s25fl128s.vhd
-testbench_s25fl128s_vhdl.vhd
-spansion_tc_pkg.vhd
-s25fl128s.ftm
-s25fl128s_vhdl.sdf
-s25fl128s.v
-testbench_s25fl128s_verilog.vhd
-s25fl128s.ftmv
-s25fl128s_verilog.sdf
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2009-11-23-1.tar.gz
# Release Date (DD/MM/YYYY) => 23/11/2009
# Release Version => 1.3
# Corrections:
# 1.Correction of Bulk Erase Time
#
# Files modified
-s25fl128s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2010-02-24-1.tar.gz
# Release Date (DD/MM/YYYY) => 24/02/2010
# Release Version => 1.4
# Corrections:
# 1.Array variable WByte in sensitivity list is replaced with signal WB_flag to enable
# compilation in NCSim
# 2.addr_cnt for second read in high performance read continuous mode can change its
# value only when CSNeg = '0'
# Files modified
-s25fl128s.v
-s25fl128s.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2010-04-15-1.tar.gz
# Release Date (DD/MM/YYYY) => 15/04/2010
# Release Version => 1.5
# Corrections:
# 1.HOLD mode corrected
# 2.Condition for PP operation corrected
# Files modified
-s25fl128s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2010-05-19-1.tar.gz
# Release Date (DD/MM/YYYY) => 19/05/2010
# Release Version => 1.6
# Corrections:
# 1.SRWD bit assignment is corrected
# 2.Condition for WRR command in write_cycle_decode section is corrected
# 3.Blocking assignments for signals WSTART and PSTART are replaced with
# nonblocking assignments
# 4.Conditions in Page Program section are fixed
#
# Files modified
-s25fl128s.v
-s25fl128s.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2010-05-26-1.tar.gz
# Release Date (DD/MM/YYYY) => 26/05/2010
# Release Version => 1.7
# Corrections:
# 1. Timing control sections for Program and Erase operation are changed
# 2. Conditions in Page Program section are fixed
#
# Files modified
-s25fl128s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2010-06-03-2.tar.gz
# Release Date (DD/MM/YYYY) => 03/06/2010
# Release Version => 1.8
# Corrections:
# 1. bus_cycle_state section for PGSP command is fixed
#
# Files modified
-s25fl128s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2010-07-29-1.tar.gz
# Release Date (DD/MM/YYYY) => 29/07/2010
# Release Version => 1.9
# Corrections:
# 1. During the QUAD mode HOLD# input is not monitored for its normal function
# 2. Internal pull-up resistors for HOLD# and WP# inputs are implemented
# Files modified
-s25fl128s.v
-s25fl128s.vhd
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2010-08-24-1.tar.gz
# Release Date (DD/MM/YYYY) => 24/08/2010
# Release Version => 2.0
# Corrections:
# 1. All redundant signals are removed from BusCycle process
# Files modified
-s25fl128s.v
-s25fl128s.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2010-10-19-2.tar.gz
# Release Date (DD/MM/YYYY) => 19/10/2010
# Release Version => 2.1
# Corrections:
# 1. Path delay correction: path delay is longer than clock cycle.
# 2. Write bank register: WIP bit of status register 1 is not affected by this
# instruction.
# 3. All other functionality is updated according to new datasheet version 1.5
# Files modified
-s25fl128s.v
-testbench_s25fl128s_verilog.vhd
-s25fl128s.ftmv
-s25fl128s_verilog.sdf
-spansion_tc_pkg.vhd
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2010-10-21-1.tar.gz
# Release Date (DD/MM/YYYY) => 21/10/2010
# Release Version => 2.2
# Corrections:
# 1. VHDL model, which is alligned with datasheet version 1.5, added to the release
# 2. Names of documentation files are updated
# Files modified
-s25fl128s.vhd
-testbench_s25fl128s_vhdl.vhd
-s25fl128s.ftm
-s25fl128s_vhdl.sdf
-spansion_flash_testbench_struct.pdf
-spansion_flash_test_cases_list.pdf
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2010-11-05-1.tar.gz
# Release Date (DD/MM/YYYY) => 05/11/2010
# Release Version => 2.3
# Corrections:
# 1. Hybrid configuration added
# Files modified
-s25fl128s.v
-s25fl128s.vhd
-testbench_s25fl128s_verilog.vhd
-testbench_s25fl128s_vhdl.vhd
-spansion_tc_pkg.vhd
-s25fl128s.ftmv
-s25fl128s.ftm
-s25fl128s_verilog.sdf
-s25fl128s_vhdl.sdf
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Ranko Prokopovic
r-prokopovic@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2010-11-12-1.tar.gz
# Release Date (DD/MM/YYYY) => 12/11/2010
# Release Version => 2.4
# Corrections:
# 1. QUAD Program operation during Erase Suspend is added
# 2. Warning for Resume to Suspend time is added
# 3. During Erase Suspend, after Program operation is completed, WEL bit is cleared
# 4. Implemetation of Software Reset is Changed
# Files modified
-spansion_tc_pkg.vhd
-s25fl128s.v
-s25fl128s.vhd
##########################################
##########################################
VITAL model author - Snezana Petrovic
s-petrovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2011-04-08-2.tar.gz
# Release Date (DD/MM/YYYY) => 08/04/2011
# Release Version => 2.5
# Corrections:
- corrected timing for internal signal rising_edge_CSNeg_ipd
# Files modified
-s25fl128s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2011-05-11-1.tar.gz
# Release Date (DD/MM/YYYY) => 11/05/2011
# Release Version => 2.6
# Corrections:
- Condition for CS# High Time(Program/Erase) is fixed
# Files modified
-s25fl128s.vhd
-testbench_s25fl128s_vhdl.vhd
-spansion_tc_pkg.vhd
-s25fl128s.v
-testbench_s25fl128s_verilog.vhd
-s25fl128s.ftmv
-s25fl128s_verilog.sdf
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2011-07-01-1.tar.gz
# Release Date (DD/MM/YYYY) => 01/07/2011
# Release Version => 2.7
# Corrections:
- Latest Datasheet Aligned
# Files modified
-s25fl128s.v
-s25fl128s.vhd
-testbench_s25fl128s_verilog.vhd
-testbench_s25fl128s_vhdl.vhd
-spansion_tc_pkg.vhd
-s25fl128s.ftmv
-s25fl128s.ftm
-s25fl128s_verilog.sdf
-s25fl128s_vhdl.sdf
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
Branislav Colakovic
b-colakovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2011-07-14-2.tar.gz
# Release Date (DD/MM/YYYY) => 14/07/2011
# Release Version => 2.8
# Corrections:
- Optimization issue is fixed
# Files modified
-s25fl128s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2011-07-22-1.tar.gz
# Release Date (DD/MM/YYYY) => 22/07/2011
# Release Version => 2.9
# Corrections:
- Timing check issue is fixed
# Files modified
-s25fl128s.v
##########################################
##########################################
VITAL model author - Vesna Mancev
v-mancev@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2011-11-16-1.tar.gz
# Release Date (DD/MM/YYYY) => 16/11/2011
# Release Version => 3.0
# Corrections:
- Time tHO is changed to 1 ns (customer's request)
- Setting of Device protection mode is modified (customer's request)
- BRWR instruction is corrected
# Files modified
-s25fl128s.v
-s25fl128s.vhd
-testbench_s25fl128s_verilog.vhd
-testbench_s25fl128s_vhdl.vhd
-s25fl128s.ftmv
-s25fl128s.ftm
-s25fl128s_verilog.sdf
-s25fl128s_vhdl.sdf
##########################################
##########################################
VITAL model author - Snezana Petrovic
s-petrovic@hdl-dh.com
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2012-08-28-1.tar.gz
# Release Date (DD/MM/YYYY) => 28/08/2012
# Release Version => 3.1
# Corrections:
- QPP instruction is allowed on previously programmed page
# Files modified
-s25fl128s.v
-s25fl128s.vhd
-testbench_s25fl128s_verilog.vhd
-testbench_s25fl128s_vhdl.vhd
-spansion_tc_pkg.vhd
##########################################
# Release Label => vital-amd-serial-s25fl-REL-s25fl128s-2012-08-30-1.tar.gz
# Release Date (DD/MM/YYYY) => 30/08/2012
# Release Version => 3.2
# Corrections:
- Wrong code corrected
# Files modified
-s25fl128s.v
##########################################
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,726 @@
<!DOCTYPE FTML SYSTEM "ftml.dtd">
<FTML><HEAD><TITLE>FMF Timing for s25fl128s Parts</TITLE>
<BODY>
<REVISION.HISTORY>
version: | author: | mod date: | changes made:
V1.0 R. Prokopovic 09 Nov 19 Initial release
V1.1 V.Mancev 10 Oct 07 Latest datasheet aligned
V1.2 V.Mancev 11 May 11 CS# High Time modifications
V1.3 V.Mancev 11 June 27 Latest datasheet aligned
V1.4 V.Mancev 11 Nov 16 Time tHO is changed to 1 ns
</REVISION.HISTORY>
<TIMESCALE>1ns</TIMESCALE>
<MODEL>s25fl128s
<FMFTIME>
S25FL128SAGMFI000_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI001_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI003_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR01_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV000_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV001_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV003_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR01_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI000_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI001_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI003_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV000_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV001_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV003_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI200_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI203_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI300_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI303_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV200_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV203_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV300_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV303_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for VIO=VCC=2.7V to 3.6V, CL=30pF </COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (3))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (2))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (4.8))
(WIDTH (COND dual_rd (negedge SCK)) (4.8))
(WIDTH (COND fast_rd (negedge SCK)) (3.75))
(WIDTH (COND fast_rd (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL128SAGMFI000_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI001_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI003_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR01_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR11_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV000_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV001_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV003_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR01_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR11_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI000_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI001_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI003_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV000_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV001_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV003_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI200_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI203_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI210_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI213_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI300_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI303_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI310_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI313_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV200_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV203_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV210_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV213_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV300_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV303_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV310_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV313_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=30pF </COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (3))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (2))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (4.8))
(WIDTH (COND dual_rd (negedge SCK)) (4.8))
(WIDTH (COND fast_rd (negedge SCK)) (3.75))
(WIDTH (COND fast_rd (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL128SAGMFI000_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI001_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI003_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR01_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR11_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV000_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV001_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV003_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR01_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR11_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI000_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI001_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI003_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV000_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV001_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV003_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI200_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI203_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI210_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI213_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI300_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI303_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI310_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI313_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV200_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV203_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV210_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV213_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV300_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV303_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV310_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV313_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=15pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (3))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (2))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (4.8))
(WIDTH (COND dual_rd (negedge SCK)) (4.8))
(WIDTH (COND fast_rd (negedge SCK)) (3.75))
(WIDTH (COND fast_rd (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL128SDPMFIR00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR01_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI000_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI001_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI003_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI200_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI203_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI300_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI303_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for Vcc range VCC=2.7V to 3.6V, CL=30pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (5))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (5))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (4))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (5))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (7.5))
(WIDTH (COND dual_rd (negedge SCK)) (7.5))
(WIDTH (COND fast_rd (negedge SCK)) (7.5))
(WIDTH (COND fast_rd (posedge SCK)) (7.5))
(WIDTH (COND quadpg (posedge SCK)) (7.5))
(WIDTH (COND quadpg (negedge SCK)) (7.5))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (15))
(PERIOD (COND dual_rd SCK) (15))
(PERIOD (COND quadpg SCK) (15))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL128SDPMFIR00_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR01_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR03_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR11_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI000_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI001_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI003_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI010_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI011_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI013_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI200_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI203_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI210_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI213_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI300_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI303_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI310_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI313_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC00_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC03_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID00_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID03_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for Vcc range VCC=2.7V to 3.6V, CL=15pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND ~ddr (IOPATH SCK SO (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && dual (IOPATH SCK SI (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK HOLDNeg (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND ~ddr && QUAD (IOPATH SCK WPNeg (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(COND CSNeg (IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && dual (IOPATH CSNeg SI () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND CSNeg && QUAD (IOPATH CSNeg WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ()))
(COND ~QUAD (IOPATH HOLDNeg SO () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14)))
(COND ~QUAD && dual (IOPATH HOLDNeg SI () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14)))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP CSNeg (COND sdr_rd SCK) (3))
(SETUP CSNeg (COND ddr_rd SCK) (3))
(SETUP SI (COND deg_sin(posedge SCK)) (5))
(SETUP SI (COND ddro(posedge SCK)) (2))
(SETUP SI (COND ddro(negedge SCK)) (2))
(SETUP WPNeg (COND wr_prot(negedge CSNeg)) (20))
(SETUP HOLDNeg (COND quad_rd (posedge SCK)) (5))
(SETUP RSTNeg CSNeg (50))
(HOLD CSNeg (COND sdr_rd SCK) (3))
(HOLD CSNeg (COND ddr_rd SCK) (3))
(HOLD SI (COND deg_sin (posedge SCK)) (4))
(HOLD SI (COND ddro (posedge SCK)) (2))
(HOLD SI (COND ddro (negedge SCK)) (2))
(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
(HOLD HOLDNeg (COND quad_rd (posedge SCK)) (5))
(HOLD CSNeg RSTNeg (35000))
(WIDTH (COND rd (posedge SCK)) (10))
(WIDTH (COND rd (negedge SCK)) (10))
(WIDTH (COND dual_rd (posedge SCK)) (7.5))
(WIDTH (COND dual_rd (negedge SCK)) (7.5))
(WIDTH (COND fast_rd (negedge SCK)) (7.5))
(WIDTH (COND fast_rd (posedge SCK)) (7.5))
(WIDTH (COND quadpg (posedge SCK)) (7.5))
(WIDTH (COND quadpg (negedge SCK)) (7.5))
(WIDTH (COND ddrd (posedge SCK)) (7.5))
(WIDTH (COND ddrd (negedge SCK)) (7.5))
(WIDTH (COND RD_EQU_1 (posedge CSNeg)) (10))
(WIDTH (COND RD_EQU_0 (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND rd SCK) (20))
(PERIOD (COND fast_rd SCK) (15))
(PERIOD (COND dual_rd SCK) (15))
(PERIOD (COND quadpg SCK) (15))
(PERIOD (COND ddrd SCK) (15))
)
</TIMING></FMFTIME>
</BODY></FTML>
@@ -0,0 +1,783 @@
<!DOCTYPE FTML SYSTEM "ftml.dtd">
<FTML><HEAD><TITLE>FMF Timing for s25fl128s Parts</TITLE>
<BODY>
<REVISION.HISTORY>
version: | author: | mod date: | changes made:
V1.0 V.Mancev 09 Nov 26 Initial release
V1.1 V. Mancev 10 Oct 21 New datasheet aligned
R. Prokopovic
V1.2 V.Mancev 11 June 27 Latest datasheet aligned
V1.3 V.Mancev 11 Nov 16 Time tHO is changed to 1 ns
</REVISION.HISTORY>
<TIMESCALE>1ns</TIMESCALE>
<MODEL>s25fl128s
<FMFTIME>
S25FL128SAGMFI000_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI001_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI003_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR01_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV000_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV001_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV003_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR01_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI000_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI001_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI003_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV000_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV001_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV003_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI200_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI203_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI300_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI303_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV200_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV203_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV300_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV303_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for VCC=2.7V to 3.6V, CL=30pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (3))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (3))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (2))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (3))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (4.8))
(WIDTH (COND dual (negedge SCK)) (4.8))
(WIDTH (COND fast (negedge SCK)) (3.75))
(WIDTH (COND fast (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP256) (DELAY (ABSOLUTE (DEVICE(183e3:366e3:550e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP512) (DELAY (ABSOLUTE (DEVICE(250e3:500e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(133e3:266e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE64) (DELAY (ABSOLUTE (DEVICE(217e6:434e6:650e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE256) (DELAY (ABSOLUTE (DEVICE(625e6:1250e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:110e9:165e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL128SAGMFI000_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI001_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI003_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR01_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR11_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV000_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV001_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV003_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR01_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR11_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI000_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI001_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI003_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV000_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV001_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV003_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV010_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV011_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV013_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI200_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI203_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI210_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI213_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI300_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI303_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI310_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI313_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV200_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV203_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV210_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV213_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV300_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV303_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV310_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV313_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL00_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL03_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL10_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL13_R_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=30pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (3))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (3))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (2))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (3))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (4.8))
(WIDTH (COND dual (negedge SCK)) (4.8))
(WIDTH (COND fast (negedge SCK)) (3.75))
(WIDTH (COND fast (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP256) (DELAY (ABSOLUTE (DEVICE(183e3:366e3:550e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP512) (DELAY (ABSOLUTE (DEVICE(250e3:500e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(133e3:266e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE64) (DELAY (ABSOLUTE (DEVICE(217e6:434e6:650e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE256) (DELAY (ABSOLUTE (DEVICE(625e6:1250e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:110e9:165e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL128SAGMFI000_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI001_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI003_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFI013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR01_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR11_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFIR13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV000_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV001_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV003_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFV013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR01_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR11_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGMFVR13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI000_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI001_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI003_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFI013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV000_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV001_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV003_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV010_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV011_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGNFV013_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI200_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI203_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI210_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI213_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI300_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI303_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI310_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHI313_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIA13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIB13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIC13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHID13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV200_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV203_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV210_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV213_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV300_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV303_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV310_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHV313_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVA13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVB13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVC13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHVD13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIY13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIZ13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIS13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIT13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIK13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL00_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL03_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL10_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SAGBHIL13_R_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=15pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (3))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (3))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (2))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (3))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (4.8))
(WIDTH (COND dual (negedge SCK)) (4.8))
(WIDTH (COND fast (negedge SCK)) (3.75))
(WIDTH (COND fast (posedge SCK)) (3.75))
(WIDTH (COND quadpg (posedge SCK)) (6.25))
(WIDTH (COND quadpg (negedge SCK)) (6.25))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (7.52))
(PERIOD (COND dual_rd SCK) (9.6))
(PERIOD (COND quadpg SCK) (12.5))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP256) (DELAY (ABSOLUTE (DEVICE(183e3:366e3:550e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP512) (DELAY (ABSOLUTE (DEVICE(250e3:500e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(133e3:266e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE64) (DELAY (ABSOLUTE (DEVICE(217e6:434e6:650e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE256) (DELAY (ABSOLUTE (DEVICE(625e6:1250e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:110e9:165e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL128SDPMFIR00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR01_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR11_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI000_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI001_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI003_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI010_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI011_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI013_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI200_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI203_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI210_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI213_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI300_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI303_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI310_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI313_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID00_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID03_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID10_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID13_F_30pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=30pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (10:12:14) (10:12:14) (10:12:14) (10:12:14))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (5))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (5))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (4))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (5))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (7.5))
(WIDTH (COND dual (negedge SCK)) (7.5))
(WIDTH (COND fast (negedge SCK)) (7.5))
(WIDTH (COND fast (posedge SCK)) (7.5))
(WIDTH (COND quadpg (posedge SCK)) (7.5))
(WIDTH (COND quadpg (negedge SCK)) (7.5))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (15))
(PERIOD (COND dual_rd SCK) (15))
(PERIOD (COND quadpg SCK) (15))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP256) (DELAY (ABSOLUTE (DEVICE(183e3:366e3:550e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP512) (DELAY (ABSOLUTE (DEVICE(250e3:500e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(133e3:266e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE64) (DELAY (ABSOLUTE (DEVICE(217e6:434e6:650e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE256) (DELAY (ABSOLUTE (DEVICE(625e6:1250e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:110e9:165e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>
<FMFTIME>
S25FL128SDPMFIR00_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR01_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR03_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR11_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPMFIR13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI000_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI001_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI003_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI010_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI011_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPNFI013_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI200_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI203_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI210_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI213_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI300_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI303_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI310_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHI313_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC00_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC03_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHIC13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID00_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID03_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID10_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
S25FL128SDPBHID13_F_15pF<SOURCE> Spansion, FL-S_PPD_2.0 April 1, 2011 </SOURCE>
<COMMENT>The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=15pF,
Industrial Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
(DELAY (ABSOLUTE
(COND normal (IOPATH SCK SO (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12)))
(COND DDR (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5)))
(IOPATH CSNeg SO () () (5.4:6.7:8) () (5.4:6.7:8) ())
(IOPATH HOLDNeg SO () () (10:12:14) (10:12:14) (10:12:14) (10:12:14))
(IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))
))
(TIMINGCHECK
(SETUP (COND normal CSNeg) (posedge SCK) (3))
(SETUP (COND DDR CSNeg) (posedge SCK) (3))
(SETUP (COND normal SI) (posedge SCK) (5))
(SETUP WPNeg CSNeg (20))
(SETUP HOLDNeg SCK (5))
(SETUP RSTNeg CSNeg (50))
(SETUP (COND DDR SI) (posedge SCK) (2))
(SETUP (COND DDR SI) (negedge SCK) (2))
(HOLD (COND normal CSNeg) (posedge SCK) (3))
(HOLD (COND DDR CSNeg) (posedge SCK) (3))
(HOLD (COND normal SI) (posedge SCK) (4))
(HOLD WPNeg CSNeg (100))
(HOLD HOLDNeg SCK (5))
(HOLD CSNeg RSTNeg (35000))
(HOLD (COND DDR SI) (posedge SCK) (2))
(HOLD (COND DDR SI) (negedge SCK) (2))
(WIDTH (COND serial (posedge SCK)) (10))
(WIDTH (COND serial (negedge SCK)) (10))
(WIDTH (COND dual (posedge SCK)) (7.5))
(WIDTH (COND dual (negedge SCK)) (7.5))
(WIDTH (COND fast (negedge SCK)) (7.5))
(WIDTH (COND fast (posedge SCK)) (7.5))
(WIDTH (COND quadpg (posedge SCK)) (7.5))
(WIDTH (COND quadpg (negedge SCK)) (7.5))
(WIDTH (COND DDR (posedge SCK)) (7.5))
(WIDTH (COND DDR (negedge SCK)) (7.5))
(WIDTH (COND read (posedge CSNeg)) (10))
(WIDTH (COND pgers (posedge CSNeg)) (50))
(WIDTH (negedge RSTNeg) (200))
(WIDTH (posedge RSTNeg) (50))
(PERIOD (COND serial_rd SCK) (20))
(PERIOD (COND fast_rd SCK) (15))
(PERIOD (COND dual_rd SCK) (15))
(PERIOD (COND quadpg SCK) (15))
(PERIOD (COND DDR_rd SCK) (15))
))
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP256) (DELAY (ABSOLUTE (DEVICE(183e3:366e3:550e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PP512) (DELAY (ABSOLUTE (DEVICE(250e3:500e3:750e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BP) (DELAY (ABSOLUTE (DEVICE(133e3:266e3:400e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE64) (DELAY (ABSOLUTE (DEVICE(217e6:434e6:650e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/SE256) (DELAY (ABSOLUTE (DEVICE(625e6:1250e6:1875e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/BE) (DELAY (ABSOLUTE (DEVICE(55e9:110e9:165e9) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(200e6:200e6:200e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(300e3:300e3:300e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(40e3:40e3:40e3) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PPBERASE) (DELAY (ABSOLUTE (DEVICE(15e6:15e6:15e6) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSULCK) (DELAY (ABSOLUTE (DEVICE(1000:1000:1000) ) ) ) )
(CELL (CELLTYPE "VITALbuf")
(INSTANCE %LABEL%/PASSACC) (DELAY (ABSOLUTE (DEVICE(100e3:100e3:100e3) ) ) )
</TIMING></FMFTIME>
</BODY></FTML>