- added models
git-svn-id: http://moon:8086/svn/vhdl/trunk@1290 cc03376c-175c-47c8-b038-4cd826a8556b
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##########################################
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Date (DD/MM/YYYY) - 08.10.2010
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Model name - S25FL128K
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Vendor - SPANSION (www.spansion.com)
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Publication ID - Document No. P/N: S25FL128K_00_01, July 22. 2010,
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Spansion Inc.
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VITAL model author - Ranko Prokopovic
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r-prokopovic@hdl-dh.com
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##########################################
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##########################################
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INITIAL RELEASE
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# Release Label => vital-amd-serial-s25fl-REL-s25fl128k-2010-10-08-1.tar.gz
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# Release Date (DD/MM/YYYY) => 08/10/2010
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# Release Version => 1.0
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##########################################
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Load Diff
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Load Diff
@@ -0,0 +1,65 @@
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<!DOCTYPE FTML SYSTEM "ftml.dtd">
|
||||
<FTML><HEAD><TITLE>FMF Timing for s25fl128k Parts</TITLE>
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||||
<BODY>
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||||
<REVISION.HISTORY>
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version: | author: | mod date: | changes made:
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V1.0 R. Prokopovic 10 Oct 08 Initial release
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</REVISION.HISTORY>
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<TIMESCALE>1ns</TIMESCALE>
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<MODEL>s25fl128k
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<FMFTIME>
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S25FL128KOXMFI000<SOURCE> Spansion, S25FL128K, JULY 22,2010 </SOURCE>
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S25FL128KOXMFI001<SOURCE> Spansion, S25FL128K, JULY 22,2010 </SOURCE>
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S25FL128KOXMFI003<SOURCE> Spansion, S25FL128K, JULY 22,2010 </SOURCE>
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<COMMENT>The values listed are for VCC=2.7V to 3.6V,
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Industrial Ta=-40 to +85 Celsius</COMMENT>
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<TIMING>
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(DELAY(ABSOLUTE
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(COND ~read_id (IOPATH SCK SO (5:6:7) (5:6:7) () (5:6:7) () (5:6:7)))
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(COND (~glitch || quad_read) && read_id (IOPATH SCK SO (5.5:7:8.5) (5.5:7:8.5) () (5.5:7:8.5) () (5.5:7:8.5)))
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(COND CSNeg (IOPATH CSNeg SO () () (5:6:7) () (5:6:7) ()))
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(COND ~quad_read (IOPATH HOLDNeg SO () () (8:10:12) (5:6:7) (8:10:12) (5:6:7)))
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(COND (dual_read || quad_read) && ~read_id (IOPATH SCK SI (5:6:7) (5:6:7) () (5:6:7) () (5:6:7)))
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(COND dual_read && read_id && ~glitch (IOPATH SCK SI (5.5:7:8.5) (5.5:7:8.5) () (5.5:7:8.5) () (5.5:7:8.5)))
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(COND quad_read && read_id (IOPATH SCK SI (5.5:7:8.5) (5.5:7:8.5) () (5.5:7:8.5) () (5.5:7:8.5)))
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(COND CSNeg && ~deg_sin (IOPATH CSNeg SI () () (5:6:7) () (5:6:7) ()))
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(COND ~quad_read && dual_read (IOPATH HOLDNeg SI () () (8:10:12) (5:6:7) (8:10:12) (5:6:7)))
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(COND quad_read && ~read_id (IOPATH SCK WPNeg (5:6:7) (5:6:7) () (5:6:7) () (5:6:7)))
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(COND quad_read && read_id (IOPATH SCK WPNeg (5.5:7:8.5) (5.5:7:8.5) () (5.5:7:8.5) () (5.5:7:8.5)))
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(COND quad_read && ~read_id (IOPATH SCK HOLDNeg (5:6:7) (5:6:7) () (5:6:7) () (5:6:7)))
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(COND quad_read && read_id (IOPATH SCK HOLDNeg (5.5:7:8.5) (5.5:7:8.5) () (5.5:7:8.5) () (5.5:7:8.5)))
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(COND CSNeg && QE (IOPATH CSNeg SI () () (5:6:7) () (5:6:7) ()))
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(COND CSNeg && QE (IOPATH CSNeg WPNeg () () (5:6:7) () (5:6:7) ()))
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(COND CSNeg && QE (IOPATH CSNeg HOLDNeg () () (5:6:7) () (5:6:7) ()))
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))
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(TIMINGCHECK
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(SETUP CSNeg (posedge SCK) (5))
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(SETUP SI (COND deg_sin(posedge SCK)) (2))
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(SETUP SO (COND quad_pg(posedge SCK)) (2))
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(SETUP WPNeg (COND quad_pg(posedge SCK)) (2))
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(SETUP HOLDNeg (COND quad_pg(posedge SCK)) (2))
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(SETUP HOLDNeg (COND hold_cond(posedge SCK)) (5))
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(SETUP WPNeg CSNeg (20))
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||||
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(HOLD CSNeg SCK (5))
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(HOLD SI (COND deg_sin (posedge SCK)) (5))
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(HOLD SO (COND quad_pg (posedge SCK)) (5))
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||||
(HOLD WPNeg (COND quad_pg (posedge SCK)) (5))
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(HOLD HOLDNeg (COND quad_pg (posedge SCK)) (5))
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(HOLD HOLDNeg (COND hold_cond(posedge SCK)) (5))
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(HOLD WPNeg (COND wr_prot (posedge CSNeg)) (100))
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||||
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(WIDTH (COND rd_slow (posedge SCK)) (8))
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||||
(WIDTH (COND rd_slow (negedge SCK)) (8))
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||||
(WIDTH (COND rd_fast (posedge SCK)) (4))
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||||
(WIDTH (COND rd_fast (negedge SCK)) (4))
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(WIDTH (COND quad_spi (posedge SCK)) (6))
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(WIDTH (COND quad_spi (negedge SCK)) (6))
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||||
(WIDTH (COND any_read (posedge CSNeg)) (10))
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(WIDTH (COND pg_ers (posedge CSNeg)) (50))
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(PERIOD (COND rd_slow SCK) (16))
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(PERIOD (COND rd_fast SCK) (8))
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(PERIOD (COND quad_spi SCK) (12))
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)
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</TIMING></FMFTIME>
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||||
</BODY></FTML>
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||||
@@ -0,0 +1,81 @@
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<!DOCTYPE FTML SYSTEM "ftml.dtd">
|
||||
<FTML><HEAD><TITLE>FMF Timing for s25fl128k Parts</TITLE>
|
||||
<BODY>
|
||||
<REVISION.HISTORY>
|
||||
version: | author: | mod date: | changes made:
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||||
V1.0 R. Prokopovic 10 Oct 05 Initial release
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||||
</REVISION.HISTORY>
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||||
<TIMESCALE>1ns</TIMESCALE>
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<MODEL>s25fl128k
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<FMFTIME>
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S25FL128KOXMFI000<SOURCE> Spansion, S25FL128K, JULY 22,2010 </SOURCE>
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||||
S25FL128KOXMFI001<SOURCE> Spansion, S25FL128K, JULY 22,2010 </SOURCE>
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||||
S25FL128KOXMFI003<SOURCE> Spansion, S25FL128K, JULY 22,2010 </SOURCE>
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||||
<COMMENT>The values listed are for VCC=2.7V to 3.6V,
|
||||
Industrial Ta=-40 to +85 Celsius</COMMENT>
|
||||
<TIMING>
|
||||
(DELAY(ABSOLUTE
|
||||
(COND RDID == 0 (IOPATH SCK SO (5:6:7) (5:6:7) () (5:6:7) () (5:6:7)))
|
||||
(COND RDID == 1 (IOPATH SCK SO (5.5:7:8.5) (5.5:7:8.5) () (5.5:7:8.5) () (5.5:7:8.5)))
|
||||
(IOPATH CSNeg SO () () (5:6:7) () (5:6:7) ())
|
||||
(IOPATH HOLDNeg SO () () (8:10:12) (5:6:7) (8:10:12) (5:6:7))
|
||||
))
|
||||
(TIMINGCHECK
|
||||
(SETUP CSNeg SCK (5))
|
||||
(SETUP (COND normal SI) (posedge SCK) (2))
|
||||
(SETUP HOLDNeg SCK (5))
|
||||
(SETUP WPNeg CSNeg (20))
|
||||
|
||||
(HOLD CSNeg SCK (5))
|
||||
(HOLD (COND normal SI) (posedge SCK) (5))
|
||||
(HOLD HOLDNeg SCK (5))
|
||||
(HOLD WPNeg CSNeg (100))
|
||||
|
||||
(WIDTH (COND slow (posedge SCK)) (8))
|
||||
(WIDTH (COND slow (negedge SCK)) (8))
|
||||
(WIDTH (COND fast (posedge SCK)) (4))
|
||||
(WIDTH (COND fast (negedge SCK)) (4))
|
||||
(WIDTH (COND quad (posedge SCK)) (6))
|
||||
(WIDTH (COND quad (negedge SCK)) (6))
|
||||
(WIDTH (COND read (posedge CSNeg)) (10))
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||||
(WIDTH (COND pger (posedge CSNeg)) (50))
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||||
(PERIOD (COND slow SCK) (16))
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||||
(PERIOD (COND fast SCK) (8))
|
||||
(PERIOD (COND quad SCK) (12))
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||||
))
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE %LABEL%/PP) (DELAY (ABSOLUTE (DEVICE(400000:700000:3000000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE %LABEL%/BP1) (DELAY (ABSOLUTE (DEVICE(15000:30000:50000) ) ) ) )
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||||
(CELL (CELLTYPE "VITALbuf")
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||||
(INSTANCE %LABEL%/BP2) (DELAY (ABSOLUTE (DEVICE(1000:2500:12000) ) ) ) )
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||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE %LABEL%/SE) (DELAY (ABSOLUTE (DEVICE(10000000:30000000:400000000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE %LABEL%/BE1) (DELAY (ABSOLUTE (DEVICE(5e7:12e7:8e8) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE %LABEL%/BE2) (DELAY (ABSOLUTE (DEVICE(5e7:15e7:1e9) ) ) ) )
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||||
(CELL (CELLTYPE "VITALbuf")
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||||
(INSTANCE %LABEL%/CE) (DELAY (ABSOLUTE (DEVICE(15e9:25e9:40e9) ) ) ) )
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||||
(CELL (CELLTYPE "VITALbuf")
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||||
(INSTANCE %LABEL%/PU) (DELAY (ABSOLUTE (DEVICE(10000:10000:10000) ) ) ) )
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||||
(CELL (CELLTYPE "VITALbuf")
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||||
(INSTANCE %LABEL%/DP) (DELAY (ABSOLUTE (DEVICE(3000:3000:3000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE %LABEL%/RES1) (DELAY (ABSOLUTE (DEVICE(3000:3000:3000) ) ) ) )
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||||
(CELL (CELLTYPE "VITALbuf")
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||||
(INSTANCE %LABEL%/RES2) (DELAY (ABSOLUTE (DEVICE(1800:1800:1800) ) ) ) )
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||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE %LABEL%/ERSSUSP) (DELAY (ABSOLUTE (DEVICE(20000:20000:20000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE %LABEL%/PRGSUSP) (DELAY (ABSOLUTE (DEVICE(20000:20000:20000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE %LABEL%/PRGRES) (DELAY (ABSOLUTE (DEVICE(200:200:200) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE %LABEL%/ERSRES) (DELAY (ABSOLUTE (DEVICE(200:200:200) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE %LABEL%/WRR) (DELAY (ABSOLUTE(DEVICE(15000000:15000000:15000000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE %LABEL%/SUSP_DLY) (DELAY (ABSOLUTE (DEVICE(20000:20000:20000) ) ) )
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||||
</TIMING></FMFTIME>
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||||
</BODY></FTML>
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||||
@@ -0,0 +1,10 @@
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||||
SET sdffile_suffix .sdf
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||||
SET use_global_timing_dir false
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||||
SET timingfile_dir /user/USERNAME/CreateSDF
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||||
SET timingfile_suffix .ftm
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||||
SET time_scale 1ns
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||||
SET local_path .
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||||
SET vendor MODELSIM_HOME
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||||
SET diagnostics on
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||||
SET vhdl_file testbench.vhd
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||||
SET lwb false
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||||
@@ -0,0 +1,462 @@
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#!/usr/local/bin/perl
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||||
#
|
||||
# mk_sdf : Perl replacement for C mk_sdf
|
||||
#
|
||||
# Copyright (C) 2000, 1999 Free Model Foundry; http:/vhdl.org/fmf/
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License version 2 as
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||||
# published by the Free Software Foundation.
|
||||
#
|
||||
# Author : R. Munden
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||||
# Date : 20001115
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# Version : 2.0.4
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||||
#
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||||
# Revision history:
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||||
# 2.0: 19990702
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# o Intial release of perl version
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# 2.0.1: 19990722
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# o fixed problem with . in path for TimingModels
|
||||
# 2.0.2: 20000616
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# o changed instance search to work with Mentor
|
||||
# 2.0.3: 20001115
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||||
# o changed to parse ":" without leading space
|
||||
# o fixed problem with . in path for TimingModels again
|
||||
# 2.0.4: 20030405
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||||
# o chaged SDF version to 3.0
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||||
#
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||||
#################################################################
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||||
#
|
||||
# command line arguments:
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||||
|
||||
# ARGV[0] - name of VHDL netlist
|
||||
|
||||
# global variables:
|
||||
|
||||
# %component_list - list of instance names by component name
|
||||
# %instance_isin - list architectures by instances contained therein
|
||||
# %instance_comp - list of component names by instance name
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||||
# %comp_lib - library each component (by name) is configured to
|
||||
# @instance_list - array of all instance names in design in order found
|
||||
|
||||
$version = "2.0.4";
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||||
$design_name = '';
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||||
$timing_dir = '';
|
||||
$diags = "off";
|
||||
|
||||
%keywords = (architecture => 1,
|
||||
component => 1,
|
||||
timingmodel => 1);
|
||||
|
||||
# INPUT files
|
||||
$CMD = "mk_sdf.cmd";
|
||||
$VHD = ''; # name of VHDL netlist
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||||
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||||
# OUTPUT files
|
||||
$RFV = "/tmp/short.vhd"; # reformatted VHDL
|
||||
$sdf_file = ''; # name of SDF file
|
||||
|
||||
&read_cmd_file;
|
||||
&get_names;
|
||||
&reformat;
|
||||
|
||||
open INPUT, $RFV;
|
||||
@lines = <INPUT>;
|
||||
close INPUT;
|
||||
|
||||
$current_architecture = "";
|
||||
|
||||
foreach $line (@lines)
|
||||
{
|
||||
@words = split / /, $line;
|
||||
foreach $word (@words)
|
||||
{
|
||||
$keywords{$word} == "1" and do { &$word(@words);};
|
||||
if ($component_list{$word})
|
||||
{
|
||||
$line =~ /(.+) : $word/ and do {
|
||||
if ($1 !~ /for/) { # instantiation found
|
||||
$component_list{$word} = $component_list{$word} . $1;
|
||||
push (@instance_list, $1);
|
||||
$instance_name = $1;
|
||||
}
|
||||
};
|
||||
$instance_comp{$1} = $word;
|
||||
$instance_isin{$1} = $current_architecture;
|
||||
if ( $diags ne off ) {
|
||||
print "reading instance $instance_name: $word in $current_architecture\n";
|
||||
}
|
||||
$line =~ /for all : $word use entity (.+)/ and do
|
||||
{
|
||||
@config = split(/\./, $1);
|
||||
$comp_lib{$word} = $config[0];};
|
||||
}
|
||||
}
|
||||
}
|
||||
if ( $diags ne off ) {
|
||||
print "finished with netlist\n\n";
|
||||
}
|
||||
|
||||
&begin_sdf;
|
||||
&build_paths;
|
||||
&close_sdf;
|
||||
`rm $RFV`;
|
||||
|
||||
print "$time\n";
|
||||
|
||||
sub architecture
|
||||
{
|
||||
$current_architecture = $_[3];
|
||||
push (@architectures, $current_architecture);
|
||||
}
|
||||
|
||||
sub component
|
||||
{
|
||||
if ($_[0] ne "end")
|
||||
{
|
||||
$name = $_[1];
|
||||
$arch_list{$current_architecture} =
|
||||
$arch_list{$current_architecture} . " " . $name;
|
||||
unless ($component_list{$name}) { $component_list{$name} = " ";}
|
||||
}
|
||||
}
|
||||
|
||||
sub timingmodel
|
||||
{
|
||||
$line =~ /timingmodel => \"(.+)\"/ and do {
|
||||
$model = $1;
|
||||
$model_name{$instance_name} = $model;
|
||||
};
|
||||
}
|
||||
|
||||
sub begin_sdf
|
||||
{
|
||||
if ( $diags ne off ) {
|
||||
print "writing SDF boilerplate\n";
|
||||
}
|
||||
$time = localtime;
|
||||
if (open(SDF, ">$sdf_file") !=1) { die "can't open $sdf_file\n";}
|
||||
print "Opening $sdf_file\n";
|
||||
print SDF "(DELAYFILE\n";
|
||||
print SDF " (SDFVERSION \"3.0\")\n";
|
||||
print SDF " (DESIGN \"$design_name\")\n";
|
||||
print SDF " (DATE \"$time\")\n";
|
||||
print SDF " (VENDOR \"Free Model Foundry\")\n";
|
||||
print SDF " (PROGRAM \"SDF timing utility(tm)\")\n";
|
||||
print SDF " (VERSION \"$version\")\n";
|
||||
print SDF " (DIVIDER /)\n";
|
||||
print SDF " (VOLTAGE)\n";
|
||||
print SDF " (PROCESS)\n";
|
||||
print SDF " (TEMPERATURE)\n";
|
||||
print SDF " (TIMESCALE 1ns)\n";
|
||||
}
|
||||
|
||||
sub build_paths
|
||||
{
|
||||
foreach $instance_list (@instance_list)
|
||||
{
|
||||
@instance = $instance_list;
|
||||
foreach $instance (@instance)
|
||||
{
|
||||
if ( $diags ne off ) {
|
||||
print "working on $instance\n";
|
||||
}
|
||||
if ($gtd =~ /true/i) {
|
||||
$path = "$lib_path{$comp_lib{$instance_comp{$instance}}}/$timing_dir";
|
||||
# $path = "$lib_path{$comp_lib{$instance_comp{$instance}}}./$timing_dir";
|
||||
} else {
|
||||
$path = "$lib_path{$comp_lib{$instance_comp{$instance}}}/$timing_dir";
|
||||
}
|
||||
$timing_file = "$path/$instance_comp{$instance}_vhd.ftm";
|
||||
$timing_file =~ s/\s//;
|
||||
if ( $diags ne off ) {
|
||||
print "$instance should be in $timing_file\n";
|
||||
}
|
||||
if (-e $timing_file) {
|
||||
if ($model_name{$instance} ne "") {
|
||||
print SDF " (CELL\n";
|
||||
print SDF " (CELLTYPE \"$instance_comp{$instance}\")\n";
|
||||
$inst = $instance;
|
||||
$full_inst = $instance;
|
||||
while ($component_list{$instance_isin{$inst}}) {
|
||||
$full_inst = "$component_list{$instance_isin{$inst}}/$full_inst";
|
||||
$full_inst =~ s/\s+//;
|
||||
$inst = $component_list{$instance_isin{$inst}};
|
||||
$inst =~ s/\s+//;
|
||||
# print SDF " (INSTANCE $component_list{$instance_isin{$instance}}/$instance)\n";
|
||||
}
|
||||
print SDF " (INSTANCE $full_inst)\n";
|
||||
&add_timing;
|
||||
}
|
||||
} else {
|
||||
if ( $diags ne off ) {
|
||||
print "$timing_file not found!\n";
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
sub add_timing
|
||||
{
|
||||
$timing_found = "false";
|
||||
$part_found = "false";
|
||||
# unless ($lib_path{$comp_lib{$instance_comp{$instance}}})
|
||||
unless ($timing_file)
|
||||
{
|
||||
print "path to $timing_file not found\n";
|
||||
exit;
|
||||
}
|
||||
if ($gtd =~ /true/i) {
|
||||
$path = "$lib_path{$comp_lib{$instance_comp{$instance}}}/$timing_dir";
|
||||
# $path = "$lib_path{$comp_lib{$instance_comp{$instance}}}./$timing_dir";
|
||||
} else {
|
||||
$path = "$lib_path{$comp_lib{$instance_comp{$instance}}}/$timing_dir";
|
||||
}
|
||||
$timing_file = "$path/$instance_comp{$instance}_vhd.ftm";
|
||||
if (open(TF, "<$timing_file") !=1) { warn "can't open $timing_file\n"; }
|
||||
if ( $diags ne off ) {
|
||||
print "reading $timing_file\n";
|
||||
}
|
||||
$section_found = "false";
|
||||
while (<TF>)
|
||||
{
|
||||
next unless (/$model_name{$instance}/i || ($part_found eq "true"));
|
||||
$part_found = "true";
|
||||
if ( $diags ne off ) {
|
||||
print "found entry for $model_name{$instance}\n";
|
||||
}
|
||||
next unless (/<timing>/i || ($timing_found eq "true"));
|
||||
$timing_found = "true";
|
||||
next if (/<timing>/i);
|
||||
if (/<\/timing>/i)
|
||||
{
|
||||
print SDF " )\n";
|
||||
$timing_found = "false";
|
||||
$part_found = "false";
|
||||
$section_found = "true";
|
||||
last;
|
||||
} else {
|
||||
if (/%LABEL%/)
|
||||
{
|
||||
if ($component_list{$instance_isin{$instance}})
|
||||
{
|
||||
$_ =~ s/%LABEL%/$component_list{$instance_isin{$instance}}\/$instance/;
|
||||
} else {
|
||||
$_ =~ s/%LABEL%/$instance/;
|
||||
}
|
||||
}
|
||||
print SDF $_;
|
||||
}
|
||||
}
|
||||
unless ($section_found eq "true") {
|
||||
print "$model_name not found\n";
|
||||
}
|
||||
}
|
||||
|
||||
sub close_sdf
|
||||
{
|
||||
print SDF ")\n";
|
||||
print "closing $sdf_file\n";
|
||||
close(SDF);
|
||||
}
|
||||
|
||||
# read mk_sdf.cmd
|
||||
|
||||
sub read_cmd_file {
|
||||
|
||||
if (open(CMD, $CMD) !=1) { die "can't open $CMD\n"; }
|
||||
while (<CMD>) {
|
||||
chop;
|
||||
@fields = '';
|
||||
@fields = split;
|
||||
unless ($fields[0] =~ /#/) {
|
||||
if ($fields[0] =~ /SET/) {
|
||||
if ($fields[1] =~ /vhdl_file/) {$VHD = $fields[2]}
|
||||
if ($fields[1] =~ /sdffile_suffix/) {$suffix = $fields[2]}
|
||||
if ($fields[1] =~ /use_global_timing_dir/) {$gtd = $fields[2]}
|
||||
if ($fields[1] =~ /timingfile_dir/) {$timing_dir = $fields[2]}
|
||||
if ($fields[1] =~ /vendor/) {$vendor = $fields[2]}
|
||||
if ($fields[1] =~ /diagnostics/) {$diags = $fields[2]}
|
||||
}
|
||||
}
|
||||
}
|
||||
if ( $diags ne off ) {
|
||||
print "\nmk_sdf diagnostics on\n\n";
|
||||
print "vhdl_file $VHD\n";
|
||||
print "sdffile_suffix $suffix\n";
|
||||
print "use_global_timing_dir $gtd\n";
|
||||
print "timingfile_dir $timing_dir\n";
|
||||
print "vendor $vendor\n\n";
|
||||
}
|
||||
}
|
||||
#
|
||||
|
||||
# get name of netlist
|
||||
|
||||
sub get_names
|
||||
{
|
||||
|
||||
if ($ARGV[0] ne "") { $VHD = "$ARGV[0]"; }
|
||||
|
||||
if ($ARGV[1] eq "")
|
||||
{
|
||||
@name = split(/\./,$VHD);
|
||||
$design_name = $name[0];
|
||||
} else {
|
||||
$design_name = "$ARGV[1]";
|
||||
}
|
||||
$sdf_file = $design_name . $suffix;
|
||||
if ($gtd =~ /false/i)
|
||||
{
|
||||
if ($vendor =~ /modeltech/i) { &read_mti; }
|
||||
if ($vendor =~ /cadence/i) { &read_cds; }
|
||||
}
|
||||
if ( $diags ne off ) {
|
||||
print "design name is $design_name\n\n";
|
||||
}
|
||||
}
|
||||
#
|
||||
################################################################
|
||||
#
|
||||
|
||||
# reformat netlist
|
||||
|
||||
sub reformat
|
||||
{
|
||||
$entfound = false;
|
||||
|
||||
if (open(VHD, $VHD) !=1) { die "can't open $VHD\n"; }
|
||||
if (open(OUT, ">$RFV") !=1) { die "can't open $OUT\n"; }
|
||||
|
||||
while (<VHD>) {
|
||||
if (/^--|library|package/i) { next }
|
||||
if (/--/) { # strip embeded comments
|
||||
@line = split("--");
|
||||
$_ = $line[0];
|
||||
}
|
||||
s/:/ : /g;
|
||||
s/;/ ;/g;
|
||||
s/\s+/ /g; # reduces spaces and tabs
|
||||
s/^\s//g; # no leading spaces
|
||||
if (/entity/i) {
|
||||
$entfound = "true";
|
||||
}
|
||||
chomp;
|
||||
if ( $entfound eq true ) {
|
||||
print OUT lc($_);
|
||||
if (/;|is|begin/i) { print OUT "\n"; }
|
||||
}
|
||||
}
|
||||
|
||||
close OUT;
|
||||
if ( $diags ne off ) {
|
||||
print "reformatted netlist written to $RFV\n\n";
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
# read ModelTech's modelsim.ini file
|
||||
|
||||
sub read_mti
|
||||
{
|
||||
$lib_found = "false";
|
||||
if ($ENV{MODELPATH})
|
||||
{
|
||||
$ini_file = "$ENV{MODELPATH}/../modelsim.ini";
|
||||
if (open(INI, "$ini_file") !=1) { die "can't open $ini_file\n";}
|
||||
if ( $diags ne off ) {
|
||||
print "reading $ini_file\n\n";
|
||||
}
|
||||
while (<INI>)
|
||||
{
|
||||
if ($lib_found eq "true")
|
||||
{
|
||||
chomp;
|
||||
if (/\[.+\]/) { last; }
|
||||
s/\s+//;
|
||||
@lib_line = split(/=/);
|
||||
$lib_line[1] =~ s/\/work//;
|
||||
$lib_path{$lib_line[0]} = $lib_line[1];
|
||||
} elsif (/\[Library\]/i)
|
||||
{
|
||||
$lib_found = "true";
|
||||
next;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
print "\$MODELPATH environment variable not found\n";
|
||||
}
|
||||
$lib_found = "false";
|
||||
if (-e "modelsim.ini")
|
||||
{
|
||||
$ini_file = "modelsim.ini";
|
||||
if (open(INI, "$ini_file") !=1) { die "can't open $ini_file\n";}
|
||||
if ( $diags ne off ) {
|
||||
print "reading $ini_file\n\n";
|
||||
}
|
||||
while (<INI>)
|
||||
{
|
||||
if ($lib_found eq "true")
|
||||
{
|
||||
chomp;
|
||||
if (/\[.+\]/) { last; }
|
||||
s/\s+//;
|
||||
@lib_line = split(/=/);
|
||||
$lib_line[1] =~ s/\/work//;
|
||||
$lib_path{$lib_line[0]} = $lib_line[1];
|
||||
} elsif (/\[Library\]/i)
|
||||
{
|
||||
$lib_found = "true";
|
||||
next;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
print "local modelsim.ini file not found, may not be needed\n";
|
||||
}
|
||||
}
|
||||
|
||||
# read Cadence's cds.lib file
|
||||
|
||||
sub read_cds
|
||||
{
|
||||
if ($ENV{CDS_VHDL})
|
||||
{
|
||||
$ini_file = "$ENV{CDS_VHDL}/files/cds.lib";
|
||||
if (open(INI, "$ini_file") !=1) { die "can't open $ini_file\n";}
|
||||
if ( $diags ne off ) {
|
||||
print "reading $ini_file\n\n";
|
||||
}
|
||||
while (<INI>)
|
||||
{
|
||||
chomp;
|
||||
s/\s+/ /;
|
||||
if (/define/i)
|
||||
{
|
||||
@lib_line = split;
|
||||
$lib_path{$lib_line[1]} = $lib_line[2];
|
||||
}
|
||||
}
|
||||
} else {
|
||||
print "\$CDS_VHDL environment variable not found\n";
|
||||
}
|
||||
if (-e "cds.lib")
|
||||
{
|
||||
$ini_file = "cds.lib";
|
||||
if (open(INI, "$ini_file") !=1) { die "can't open $ini_file\n";}
|
||||
if ( $diags ne off ) {
|
||||
print "reading $ini_file\n\n";
|
||||
}
|
||||
while (<INI>)
|
||||
{
|
||||
chomp;
|
||||
s/\s+/ /;
|
||||
if (/define/i)
|
||||
{
|
||||
@lib_line = split;
|
||||
$lib_path{$lib_line[1]} = $lib_line[2];
|
||||
}
|
||||
}
|
||||
} else {
|
||||
print "local cds.lib file not found, may not be needed\n";
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,205 @@
|
||||
<!DOCTYPE FTML SYSTEM "ftml.dtd">
|
||||
<FTML><HEAD><TITLE>FMF Timing for testbench Parts</TITLE>
|
||||
<BODY>
|
||||
<REVISION.HISTORY>
|
||||
version: | author: | mod date: | changes made:
|
||||
V1.0 VHD2FTM 03 July 11 Initial release
|
||||
</REVISION.HISTORY>
|
||||
<TIMESCALE>1ns</TIMESCALE>
|
||||
<MODEL>am29lv640m
|
||||
<FMFTIME>
|
||||
MY_MEM<SOURCE></SOURCE>
|
||||
AM29LV640MH90R<SOURCE></SOURCE>
|
||||
AM29LV640ML90R<SOURCE></SOURCE>
|
||||
<COMMENT></COMMENT>
|
||||
<TIMING>
|
||||
(DELAY (ABSOLUTE
|
||||
(IOPATH A0 DQ0 (90:90:90) (90:90:90))
|
||||
(IOPATH A0 DQ1 (25:25:25) (25:25:25))
|
||||
(IOPATH CENeg DQ0 (85:85:85) (85:85:85) (11:11:11) (85:85:85) (11:11:11) (85:85:85))
|
||||
(IOPATH OENeg DQ0 (20:20:20) (20:20:20) (11:11:11) (20:20:20) (11:11:11) (20:20:20))
|
||||
(IOPATH RESETNeg DQ0 () () (0:0:0) () (0:0:0) ())
|
||||
(IOPATH CENeg RY (0) (90))
|
||||
(IOPATH WENeg RY (0) (90))
|
||||
))
|
||||
(TIMINGCHECK
|
||||
(SETUP A0 CENeg (0:0:0))
|
||||
(SETUP A0 OENeg (15:15:15))
|
||||
(SETUP DQ0 CENeg (45:45:45))
|
||||
(HOLD CENeg RESETNeg (50:50:50))
|
||||
(HOLD OENeg WENeg (0:0:0))
|
||||
(HOLD A0 CENeg (45:45:45))
|
||||
(HOLD A0 OENeg (0:0:0))
|
||||
(HOLD DQ0 CENeg (0:0:0))
|
||||
(HOLD WENeg OENeg (0:0:0))
|
||||
(WIDTH (negedge RESETNeg) (500:500:500))
|
||||
(WIDTH (posedge OENeg) (20:20:20))
|
||||
(WIDTH (negedge WENeg) (35:35:35))
|
||||
(WIDTH (posedge WENeg) (30:30:30))
|
||||
(WIDTH (negedge CENeg) (45:45:45))
|
||||
(WIDTH (posedge CENeg) (30:30:30))
|
||||
(WIDTH (negedge A0) (90:90:90))
|
||||
))
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/WBPB) (DELAY (ABSOLUTE (DEVICE(11000:11000:11000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/POB) (DELAY (ABSOLUTE (DEVICE(100000:100000:100000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/SEO) (DELAY (ABSOLUTE (DEVICE(500000000:500000000:500000000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/HANG) (DELAY (ABSOLUTE (DEVICE(400000000:400000000:400000000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/START_T1) (DELAY (ABSOLUTE (DEVICE(5000:5000:20000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/CTMOUT) (DELAY (ABSOLUTE (DEVICE(50000:50000:50000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/READY) (DELAY (ABSOLUTE (DEVICE(20000:20000:20000) ) ) )
|
||||
</TIMING></FMFTIME>
|
||||
<FMFTIME>
|
||||
AM29LV640MH101<SOURCE></SOURCE>
|
||||
AM29LV640ML101<SOURCE></SOURCE>
|
||||
AM29LV640MH101R<SOURCE></SOURCE>
|
||||
AM29LV640ML101R<SOURCE></SOURCE>
|
||||
<COMMENT></COMMENT>
|
||||
<TIMING>
|
||||
(DELAY (ABSOLUTE
|
||||
(IOPATH A0 DQ0 (100:100:100) (100:100:100))
|
||||
(IOPATH A0 DQ1 (30:30:30) (30:30:30))
|
||||
(IOPATH CENeg DQ0 (95:95:95) (95:95:95) (11:11:11) (95:95:95) (11:11:11) (95:95:95))
|
||||
(IOPATH OENeg DQ0 (25:25:25) (25:25:25) (11:11:11) (25:25:25) (11:11:11) (25:25:25))
|
||||
(IOPATH RESETNeg DQ0 () () (0:0:0) () (0:0:0) ())
|
||||
(IOPATH CENeg RY (0) (100))
|
||||
(IOPATH WENeg RY (0) (100))
|
||||
))
|
||||
(TIMINGCHECK
|
||||
(SETUP A0 CENeg (0:0:0))
|
||||
(SETUP A0 OENeg (15:15:15))
|
||||
(SETUP DQ0 CENeg (45:45:45))
|
||||
(HOLD CENeg RESETNeg (50:50:50))
|
||||
(HOLD OENeg WENeg (0:0:0))
|
||||
(HOLD A0 CENeg (45:45:45))
|
||||
(HOLD A0 OENeg (0:0:0))
|
||||
(HOLD DQ0 CENeg (0:0:0))
|
||||
(HOLD WENeg OENeg (0:0:0))
|
||||
(WIDTH (negedge RESETNeg) (500:500:500))
|
||||
(WIDTH (posedge OENeg) (20:20:20))
|
||||
(WIDTH (negedge WENeg) (35:35:35))
|
||||
(WIDTH (posedge WENeg) (30:30:30))
|
||||
(WIDTH (negedge CENeg) (45:45:45))
|
||||
(WIDTH (posedge CENeg) (30:30:30))
|
||||
(WIDTH (negedge A0) (100:100:100))
|
||||
))
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/WBPB) (DELAY (ABSOLUTE (DEVICE(11000:11000:11000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/POB) (DELAY (ABSOLUTE (DEVICE(100000:100000:100000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/SEO) (DELAY (ABSOLUTE (DEVICE(500000000:500000000:500000000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/HANG) (DELAY (ABSOLUTE (DEVICE(400000000:400000000:400000000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/START_T1) (DELAY (ABSOLUTE (DEVICE(5000:5000:20000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/CTMOUT) (DELAY (ABSOLUTE (DEVICE(50000:50000:50000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/READY) (DELAY (ABSOLUTE (DEVICE(20000:20000:20000) ) ) )
|
||||
</TIMING></FMFTIME>
|
||||
<FMFTIME>
|
||||
AM29LV640MH112<SOURCE></SOURCE>
|
||||
AM29LV640ML112<SOURCE></SOURCE>
|
||||
AM29LV640MH112R<SOURCE></SOURCE>
|
||||
AM29LV640ML112R<SOURCE></SOURCE>
|
||||
<COMMENT></COMMENT>
|
||||
<TIMING>
|
||||
(DELAY (ABSOLUTE
|
||||
(IOPATH A0 DQ0 (110:110:110) (110:110:110))
|
||||
(IOPATH A0 DQ1 (40:40:40) (40:40:40))
|
||||
(IOPATH CENeg DQ0 (105:105:105) (105:105:105) (11:11:11) (105:105:105) (11:11:11) (105:105:105))
|
||||
(IOPATH OENeg DQ0 (35:35:35) (35:35:35) (11:11:11) (35:35:35) (11:11:11) (35:35:35))
|
||||
(IOPATH RESETNeg DQ0 () () (0:0:0) () (0:0:0) ())
|
||||
(IOPATH CENeg RY (0) (110))
|
||||
(IOPATH WENeg RY (0) (110))
|
||||
))
|
||||
(TIMINGCHECK
|
||||
(SETUP A0 CENeg (0:0:0))
|
||||
(SETUP A0 OENeg (15:15:15))
|
||||
(SETUP DQ0 CENeg (45:45:45))
|
||||
(HOLD CENeg RESETNeg (50:50:50))
|
||||
(HOLD OENeg WENeg (0:0:0))
|
||||
(HOLD A0 CENeg (45:45:45))
|
||||
(HOLD A0 OENeg (0:0:0))
|
||||
(HOLD DQ0 CENeg (0:0:0))
|
||||
(HOLD WENeg OENeg (0:0:0))
|
||||
(WIDTH (negedge RESETNeg) (500:500:500))
|
||||
(WIDTH (posedge OENeg) (20:20:20))
|
||||
(WIDTH (negedge WENeg) (35:35:35))
|
||||
(WIDTH (posedge WENeg) (30:30:30))
|
||||
(WIDTH (negedge CENeg) (45:45:45))
|
||||
(WIDTH (posedge CENeg) (30:30:30))
|
||||
(WIDTH (negedge A0) (110:110:110))
|
||||
))
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/WBPB) (DELAY (ABSOLUTE (DEVICE(11000:11000:11000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/POB) (DELAY (ABSOLUTE (DEVICE(100000:100000:100000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/SEO) (DELAY (ABSOLUTE (DEVICE(500000000:500000000:500000000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/HANG) (DELAY (ABSOLUTE (DEVICE(400000000:400000000:400000000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/START_T1) (DELAY (ABSOLUTE (DEVICE(5000:5000:20000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/CTMOUT) (DELAY (ABSOLUTE (DEVICE(50000:50000:50000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/READY) (DELAY (ABSOLUTE (DEVICE(20000:20000:20000) ) ) )
|
||||
</TIMING></FMFTIME>
|
||||
<FMFTIME>
|
||||
AM29LV640MH120<SOURCE></SOURCE>
|
||||
AM29LV640ML120<SOURCE></SOURCE>
|
||||
AM29LV640MH120R<SOURCE></SOURCE>
|
||||
AM29LV640ML120R<SOURCE></SOURCE>
|
||||
<COMMENT></COMMENT>
|
||||
<TIMING>
|
||||
(DELAY (ABSOLUTE
|
||||
(IOPATH A0 DQ0 (120:120:120) (120:120:120))
|
||||
(IOPATH A0 DQ1 (40:40:40) (40:40:40))
|
||||
(IOPATH CENeg DQ0 (115:115:115) (115:115:115) (11:11:11) (115:115:115) (11:11:11) (115:115:115))
|
||||
(IOPATH OENeg DQ0 (35:35:35) (35:35:35) (11:11:11) (35:35:35) (11:11:11) (35:35:35))
|
||||
(IOPATH RESETNeg DQ0 () () (0:0:0) () (0:0:0) ())
|
||||
(IOPATH CENeg RY (0) (120))
|
||||
(IOPATH WENeg RY (0) (120))
|
||||
))
|
||||
(TIMINGCHECK
|
||||
(SETUP A0 CENeg (0:0:0))
|
||||
(SETUP A0 OENeg (15:15:15))
|
||||
(SETUP DQ0 CENeg (45:45:45))
|
||||
(HOLD CENeg RESETNeg (50:50:50))
|
||||
(HOLD OENeg WENeg (0:0:0))
|
||||
(HOLD A0 CENeg (45:45:45))
|
||||
(HOLD A0 OENeg (0:0:0))
|
||||
(HOLD DQ0 CENeg (0:0:0))
|
||||
(HOLD WENeg OENeg (0:0:0))
|
||||
(WIDTH (negedge RESETNeg) (500:500:500))
|
||||
(WIDTH (posedge OENeg) (20:20:20))
|
||||
(WIDTH (negedge WENeg) (35:35:35))
|
||||
(WIDTH (posedge WENeg) (30:30:30))
|
||||
(WIDTH (negedge CENeg) (45:45:45))
|
||||
(WIDTH (posedge CENeg) (30:30:30))
|
||||
(WIDTH (negedge A0) (120:120:120))
|
||||
))
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/WBPB) (DELAY (ABSOLUTE (DEVICE(11000:11000:11000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/POB) (DELAY (ABSOLUTE (DEVICE(100000:100000:100000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/SEO) (DELAY (ABSOLUTE (DEVICE(500000000:500000000:500000000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/HANG) (DELAY (ABSOLUTE (DEVICE(400000000:400000000:400000000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/START_T1) (DELAY (ABSOLUTE (DEVICE(5000:5000:20000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/CTMOUT) (DELAY (ABSOLUTE (DEVICE(50000:50000:50000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/READY) (DELAY (ABSOLUTE (DEVICE(20000:20000:20000) ) ) )
|
||||
</TIMING></FMFTIME>
|
||||
</BODY></FTML>
|
||||
@@ -0,0 +1,58 @@
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "testbench")
|
||||
(DATE "Wed Jan 28 15:15:41 2004")
|
||||
(VENDOR "Free Model Foundry")
|
||||
(PROGRAM "SDF timing utility(tm)")
|
||||
(VERSION "2.0.4")
|
||||
(DIVIDER /)
|
||||
(VOLTAGE)
|
||||
(PROCESS)
|
||||
(TEMPERATURE)
|
||||
(TIMESCALE 1ns)
|
||||
(CELL
|
||||
(CELLTYPE "my_mem")
|
||||
(INSTANCE dut)
|
||||
(DELAY (ABSOLUTE
|
||||
(IOPATH A0 DQ0 (90:90:90) (90:90:90))
|
||||
(IOPATH A0 DQ1 (25:25:25) (25:25:25))
|
||||
(IOPATH CENeg DQ0 (85:85:85) (85:85:85) (11:11:11) (85:85:85) (11:11:11) (85:85:85))
|
||||
(IOPATH OENeg DQ0 (20:20:20) (20:20:20) (11:11:11) (20:20:20) (11:11:11) (20:20:20))
|
||||
(IOPATH RESETNeg DQ0 () () (0:0:0) () (0:0:0) ())
|
||||
(IOPATH CENeg RY (0) (90))
|
||||
(IOPATH WENeg RY (0) (90))
|
||||
))
|
||||
(TIMINGCHECK
|
||||
(SETUP A0 CENeg (0:0:0))
|
||||
(SETUP A0 OENeg (15:15:15))
|
||||
(SETUP DQ0 CENeg (45:45:45))
|
||||
(HOLD CENeg RESETNeg (50:50:50))
|
||||
(HOLD OENeg WENeg (0:0:0))
|
||||
(HOLD A0 CENeg (45:45:45))
|
||||
(HOLD A0 OENeg (0:0:0))
|
||||
(HOLD DQ0 CENeg (0:0:0))
|
||||
(HOLD WENeg OENeg (0:0:0))
|
||||
(WIDTH (negedge RESETNeg) (500:500:500))
|
||||
(WIDTH (posedge OENeg) (20:20:20))
|
||||
(WIDTH (negedge WENeg) (35:35:35))
|
||||
(WIDTH (posedge WENeg) (30:30:30))
|
||||
(WIDTH (negedge CENeg) (45:45:45))
|
||||
(WIDTH (posedge CENeg) (30:30:30))
|
||||
(WIDTH (negedge A0) (90:90:90))
|
||||
))
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/WBPB) (DELAY (ABSOLUTE (DEVICE(11000:11000:11000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/POB) (DELAY (ABSOLUTE (DEVICE(100000:100000:100000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/SEO) (DELAY (ABSOLUTE (DEVICE(500000000:500000000:500000000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/HANG) (DELAY (ABSOLUTE (DEVICE(400000000:400000000:400000000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/START_T1) (DELAY (ABSOLUTE (DEVICE(5000:5000:20000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/CTMOUT) (DELAY (ABSOLUTE (DEVICE(50000:50000:50000) ) ) ) )
|
||||
(CELL (CELLTYPE "VITALbuf")
|
||||
(INSTANCE dut/READY) (DELAY (ABSOLUTE (DEVICE(20000:20000:20000) ) ) )
|
||||
)
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,144 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- File name: gen_utils.vhd
|
||||
--------------------------------------------------------------------------------
|
||||
-- Copyright (C) 1996, 1998, 2001 Free Model Foundry; http://eda.org/fmf/
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License version 2 as
|
||||
-- published by the Free Software Foundation.
|
||||
--
|
||||
-- MODIFICATION HISTORY:
|
||||
--
|
||||
-- version: | author: | mod date: | changes made:
|
||||
-- V1.0 R. Steele 96 SEP 26 Initial release
|
||||
-- V1.1 REV3 97 Feb 27 Added Xon and MsgOn generics
|
||||
-- V1.2 R. Steele 97 APR 16 Changed wired-or to wired-and
|
||||
-- V1.3 R. Steele 97 APR 16 Added diff. receiver table
|
||||
-- V1.4 R. Munden 98 APR 13 Added GenParity and CheckParity
|
||||
-- V1.5 R. Munden 01 NOV 24 Added UnitDelay01ZX
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY IEEE; USE IEEE.std_Logic_1164.ALL;
|
||||
USE IEEE.VITAL_primitives.ALL;
|
||||
USE IEEE.VITAL_timing.ALL;
|
||||
|
||||
PACKAGE gen_utils IS
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
-- Result map for Wired-and output values (open collector)
|
||||
----------------------------------------------------------------------------
|
||||
CONSTANT STD_wired_and_rmap : VitalResultMapType := ('U','X','0','Z');
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
-- Table for computing a single signal from a differential receiver input
|
||||
-- pair.
|
||||
----------------------------------------------------------------------------
|
||||
CONSTANT diff_rec_tab : VitalStateTableType := (
|
||||
|
||||
------INPUTS--|-PREV-|-OUTPUT----
|
||||
-- A ANeg | Aint | Aint' --
|
||||
--------------|------|-----------
|
||||
( 'X', '-', '-', 'X'), -- A unknown
|
||||
( '-', 'X', '-', 'X'), -- A unknown
|
||||
( '1', '-', 'X', '1'), -- Recover from 'X'
|
||||
( '0', '-', 'X', '0'), -- Recover from 'X'
|
||||
( '/', '0', '0', '1'), -- valid diff. rising edge
|
||||
( '1', '\', '0', '1'), -- valid diff. rising edge
|
||||
( '\', '1', '1', '0'), -- valid diff. falling edge
|
||||
( '0', '/', '1', '0'), -- valid diff. falling edge
|
||||
( '-', '-', '-', 'S') -- default
|
||||
); -- end of VitalStateTableType definition
|
||||
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
-- Default Constants
|
||||
----------------------------------------------------------------------------
|
||||
CONSTANT UnitDelay : VitalDelayType := 1 ns;
|
||||
CONSTANT UnitDelay01 : VitalDelayType01 := (1 ns, 1 ns);
|
||||
CONSTANT UnitDelay01Z : VitalDelayType01Z := (others => 1 ns);
|
||||
CONSTANT UnitDelay01ZX : VitalDelayType01ZX := (others => 1 ns);
|
||||
|
||||
CONSTANT DefaultInstancePath : STRING := "*";
|
||||
CONSTANT DefaultTimingChecks : BOOLEAN := FALSE;
|
||||
CONSTANT DefaultTimingModel : STRING := "UNIT";
|
||||
CONSTANT DefaultXon : BOOLEAN := TRUE;
|
||||
CONSTANT DefaultMsgOn : BOOLEAN := TRUE;
|
||||
|
||||
-- Older VITAL generic being phased out
|
||||
CONSTANT DefaultXGeneration : BOOLEAN := TRUE;
|
||||
|
||||
-------------------------------------------------------------------
|
||||
-- Generate Parity for each 8-bit in 9th bit
|
||||
-------------------------------------------------------------------
|
||||
FUNCTION GenParity
|
||||
(Data : in std_logic_vector; -- Data
|
||||
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
|
||||
SIZE : in POSITIVE) -- Bit Size
|
||||
RETURN std_logic_vector;
|
||||
|
||||
-------------------------------------------------------------------
|
||||
-- Check Parity for each 8-bit in 9th bit
|
||||
-------------------------------------------------------------------
|
||||
FUNCTION CheckParity
|
||||
(Data : in std_logic_vector; -- Data
|
||||
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
|
||||
SIZE : in POSITIVE) -- Bit Size
|
||||
RETURN std_logic; -- '0' - Parity Error
|
||||
|
||||
END gen_utils;
|
||||
|
||||
PACKAGE BODY gen_utils IS
|
||||
|
||||
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
|
||||
-- pragma subpgm_id 403
|
||||
variable result: STD_LOGIC;
|
||||
begin
|
||||
result := '0';
|
||||
for i in ARG'range loop
|
||||
result := result xor ARG(i);
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
-------------------------------------------------------------------
|
||||
-- Generate Parity for each 8-bit in 9th bit
|
||||
-------------------------------------------------------------------
|
||||
FUNCTION GenParity
|
||||
(Data : in std_logic_vector; -- Data
|
||||
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
|
||||
SIZE : in POSITIVE) -- Bit Size
|
||||
RETURN std_logic_vector
|
||||
IS
|
||||
VARIABLE I: NATURAL;
|
||||
VARIABLE Result: std_logic_vector (Data'Length - 1 DOWNTO 0);
|
||||
BEGIN
|
||||
I := 0;
|
||||
WHILE (I < SIZE) LOOP
|
||||
Result(I+7 DOWNTO I) := Data(I+7 downto I);
|
||||
Result(I+8) := XOR_REDUCE( Data(I+7 downto I) ) XOR ODDEVEN;
|
||||
I := I + 9;
|
||||
END LOOP;
|
||||
RETURN Result;
|
||||
END GenParity;
|
||||
|
||||
-------------------------------------------------------------------
|
||||
-- Check Parity for each 8-bit in 9th bit
|
||||
-------------------------------------------------------------------
|
||||
FUNCTION CheckParity
|
||||
(Data : in std_logic_vector; -- Data
|
||||
ODDEVEN : in std_logic; -- ODD (1) / EVEN(0)
|
||||
SIZE : in POSITIVE) -- Bit Size
|
||||
RETURN std_logic -- '0' - Parity Error
|
||||
IS
|
||||
VARIABLE I: NATURAL;
|
||||
VARIABLE Result: std_logic;
|
||||
BEGIN
|
||||
I := 0; Result := '1';
|
||||
WHILE (I < SIZE) LOOP
|
||||
Result := Result AND
|
||||
NOT (XOR_REDUCE( Data(I+8 downto I) ) XOR ODDEVEN);
|
||||
I := I + 9;
|
||||
END LOOP;
|
||||
RETURN Result;
|
||||
END CheckParity;
|
||||
|
||||
END gen_utils;
|
||||
Reference in New Issue
Block a user