jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- use SPI flash as SPI slave

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1292 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-06-10 20:01:26 +00:00
parent b19c4c2883
commit 295095e2b0
3 changed files with 69 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/spi/src/tb_spi_master.vhd
+29 -13
View File
@@ -33,7 +33,7 @@ END tb_spi_master;
ARCHITECTURE behavior OF tb_spi_master IS
constant CLK_PERIOD : time := 10 ns;
constant CLK_PERIOD : time := 20 ns;
signal CLK : std_logic := '1';
signal RST : std_logic := '1';
@@ -54,6 +54,9 @@ ARCHITECTURE behavior OF tb_spi_master IS
signal ctrl : ctrl_t;
signal status : status_t;
signal mso : STD_LOGIC;
signal mso_n : STD_LOGIC;
signal HOLDNeg : STD_LOGIC := '1';
signal WPNeg : STD_LOGIC := '1';
signal mst_rx_data : unsigned(31 downto 0);
signal slv_rx_shiftreg : unsigned(31 downto 0) := (others => '0');
@@ -68,6 +71,9 @@ BEGIN
ctrl.cpha <= '0';
ctrl.msb_first <= '1';
ctrl.clk_div <= X"00";
mso_n <= not mso;
HOLDNeg <= '1';
WPNeg <= '1';
inst_spi_master : entity work.spi_master
GENERIC MAP
@@ -97,6 +103,16 @@ inst_spi_master : entity work.spi_master
);
inst_spi_slave: entity work.S25fl064k
PORT MAP (
SCK => mst_clk, -- serial clock input
SI => mosi, -- serial data input
CSNeg => mso_n, -- chip select input
HOLDNeg => HOLDNeg, -- hold input
WPNeg => WPNeg, -- write protect input
SO => miso -- SO
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
@@ -139,7 +155,7 @@ TX_SLAVE_SIM_SHIFT_REG: process(mst_clk)
end if;
end process;
miso <= slv_tx_shiftreg(slv_tx_shiftreg'left);
-- miso <= slv_tx_shiftreg(slv_tx_shiftreg'left);
RX_SLAVE_SIM_DATA_REG: process(clk)
variable data_vld : unsigned(1 downto 0);
@@ -176,13 +192,13 @@ STIMULUS: process
wait for 600*CLK_PERIOD;
wait until rising_edge(CLK);
mst_din <= X"C355AAC1";
mst_din <= X"9F55AAC1";
mst_din_vld <= '1';
wait until rising_edge(CLK) and mst_din_rdy = '1';
mst_din_vld <= '0';
wait until rising_edge(CLK);
mst_cmd <= to_cmd(32, 32);
mst_cmd <= to_cmd(32, 8);
mst_cmd_vld <= '1';
wait until rising_edge(CLK) and mst_cmd_rdy = '1';
mst_cmd_vld <= '0';
@@ -208,33 +224,33 @@ STIMULUS: process
mst_din_vld <= '0';
wait until rising_edge(CLK);
mst_cmd <= to_cmd(256, 8);
mst_cmd <= to_cmd(656, 8);
mst_cmd_vld <= '1';
wait until rising_edge(CLK) and mst_cmd_rdy = '1';
mst_cmd_vld <= '0';
--------------------------------------------------------
wait until rising_edge(CLK);
mst_din <= X"C3AA55C1";
mst_din <= X"030155C1";
mst_din_vld <= '1';
wait until rising_edge(CLK) and mst_din_rdy = '1';
mst_din_vld <= '0';
wait until rising_edge(CLK);
mst_cmd <= to_cmd(64, 64);
mst_cmd <= to_cmd(64, 32);
mst_cmd_vld <= '1';
wait until rising_edge(CLK) and mst_cmd_rdy = '1';
mst_cmd_vld <= '0';
wait for 200*CLK_PERIOD;
wait until rising_edge(CLK) and mst_din_rdy = '1';
mst_din <= X"83AAFF05";
mst_din <= X"0311FF05";
mst_din_vld <= '1';
wait until rising_edge(CLK) and mst_din_rdy = '1';
mst_din_vld <= '0';
--------------------------------------------------------
mst_din <= X"00000000";
mst_din <= X"03000000";
for i in 0 to 16 loop
wait until rising_edge(CLK);
@@ -255,7 +271,7 @@ STIMULUS: process
--------------------------------------------------------
wait until rising_edge(CLK);
mst_din <= X"C355AAC1";
mst_din <= X"0355AAC1";
mst_din_vld <= '1';
wait until rising_edge(CLK) and mst_din_rdy = '1';
mst_din_vld <= '0';
@@ -268,20 +284,20 @@ STIMULUS: process
--------------------------------------------------------
wait until rising_edge(CLK);
mst_din <= X"C355AA00";
mst_din <= X"0355AA00";
mst_din_vld <= '1';
wait until rising_edge(CLK) and mst_din_rdy = '1';
mst_din_vld <= '0';
wait until rising_edge(CLK);
mst_cmd <= to_cmd(32, 24);
mst_cmd <= to_cmd(32, 32);
mst_cmd_vld <= '1';
wait until rising_edge(CLK) and mst_cmd_rdy = '1';
mst_cmd_vld <= '0';
--------------------------------------------------------
wait until rising_edge(CLK);
mst_din <= X"C355AAC1";
mst_din <= X"0311AAC1";
mst_din_vld <= '1';
wait until rising_edge(CLK) and mst_din_rdy = '1';
mst_din_vld <= '0';