From 295095e2b0d710cc656fa6b53bca21c9b15b5d75 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 10 Jun 2015 20:01:26 +0000 Subject: [PATCH] - use SPI flash as SPI slave git-svn-id: http://moon:8086/svn/vhdl/trunk@1292 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/spi/sim/tb_spi_master.fdo | 5 +++++ lib/spi/sim/tb_spi_master.wdo | 38 ++++++++++++++++++++++++++++--- lib/spi/src/tb_spi_master.vhd | 42 ++++++++++++++++++++++++----------- 3 files changed, 69 insertions(+), 16 deletions(-) diff --git a/lib/spi/sim/tb_spi_master.fdo b/lib/spi/sim/tb_spi_master.fdo index 4705fc4..5f632f2 100644 --- a/lib/spi/sim/tb_spi_master.fdo +++ b/lib/spi/sim/tb_spi_master.fdo @@ -3,6 +3,10 @@ ## if {[file exists work]} {vdel -lib work -all} +vlib fmf +vcom -work fmf -93 "../../models/memory/flash/serial/S25fl064k/utilities/conversions.vhd" +vcom -work fmf -93 "../../models/memory/flash/serial/S25fl064k/utilities/gen_utils.vhd" + vlib work vcom -explicit -93 "../../misc/utils_pkg.vhd" vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" @@ -14,6 +18,7 @@ vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd" vcom -explicit -93 "../../FIFO/src/fifo_sync.vhd" vcom -explicit -93 "../src/spi_types.vhd" vcom -explicit -93 "../src/spi_master.vhd" +vcom -explicit -93 "../../models/memory/flash/serial/S25fl064k/model/S25fl064k.vhd" vcom -explicit -93 "../src/tb_spi_master.vhd" vsim -t 1ps -lib work tb_spi_master view wave diff --git a/lib/spi/sim/tb_spi_master.wdo b/lib/spi/sim/tb_spi_master.wdo index 2fb407c..2524ae8 100644 --- a/lib/spi/sim/tb_spi_master.wdo +++ b/lib/spi/sim/tb_spi_master.wdo @@ -60,7 +60,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_spi_master/inst_spi_ma add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/write_fifo_full add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/write_fifo_empty add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/slv_enable -add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/rx_enable add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/read_fifo_full add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/read_fifo_empty add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/read_fifo_we @@ -70,8 +69,41 @@ add wave -noupdate -format Literal /tb_spi_master/inst_spi_master/spi_rst_count add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/spi_rst add wave -noupdate -format Logic /tb_spi_master/inst_spi_master/spi_clk_div_en add wave -noupdate -format Literal /tb_spi_master/inst_spi_master/spi_clk_div_count +add wave -noupdate -divider Flash +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/sck +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/si +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/csneg +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/holdneg +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/wpneg +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/so +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/sck_ipd +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/si_ipd +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/so_ipd +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/csneg_ipd +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/holdneg_ipd +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/wpneg_ipd +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/holdneg_pullup +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/wpneg_pullup +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/pp_in +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/pp_out +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/pu_in +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/pu_out +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/se_in +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/se_out +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/be_in +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/be_out +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/ep_in +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/ep_out +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/wr_in +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/wr_out +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/dp_in +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/dp_out +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/pe_in +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/pe_out +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/res_in +add wave -noupdate -format Logic /tb_spi_master/inst_spi_slave/res_out TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {23780000 ps} 0} +WaveRestoreCursors {{Cursor 1} {34359846 ps} 0} configure wave -namecolwidth 197 configure wave -valuecolwidth 131 configure wave -justifyvalue left @@ -85,4 +117,4 @@ configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 0 update -WaveRestoreZoom {31046634 ps} {50997546 ps} +WaveRestoreZoom {31046634 ps} {50872181 ps} diff --git a/lib/spi/src/tb_spi_master.vhd b/lib/spi/src/tb_spi_master.vhd index 172504b..dc2b070 100644 --- a/lib/spi/src/tb_spi_master.vhd +++ b/lib/spi/src/tb_spi_master.vhd @@ -33,7 +33,7 @@ END tb_spi_master; ARCHITECTURE behavior OF tb_spi_master IS - constant CLK_PERIOD : time := 10 ns; + constant CLK_PERIOD : time := 20 ns; signal CLK : std_logic := '1'; signal RST : std_logic := '1'; @@ -54,6 +54,9 @@ ARCHITECTURE behavior OF tb_spi_master IS signal ctrl : ctrl_t; signal status : status_t; signal mso : STD_LOGIC; + signal mso_n : STD_LOGIC; + signal HOLDNeg : STD_LOGIC := '1'; + signal WPNeg : STD_LOGIC := '1'; signal mst_rx_data : unsigned(31 downto 0); signal slv_rx_shiftreg : unsigned(31 downto 0) := (others => '0'); @@ -68,6 +71,9 @@ BEGIN ctrl.cpha <= '0'; ctrl.msb_first <= '1'; ctrl.clk_div <= X"00"; + mso_n <= not mso; + HOLDNeg <= '1'; + WPNeg <= '1'; inst_spi_master : entity work.spi_master GENERIC MAP @@ -97,6 +103,16 @@ inst_spi_master : entity work.spi_master ); +inst_spi_slave: entity work.S25fl064k + PORT MAP ( + SCK => mst_clk, -- serial clock input + SI => mosi, -- serial data input + CSNeg => mso_n, -- chip select input + HOLDNeg => HOLDNeg, -- hold input + WPNeg => WPNeg, -- write protect input + SO => miso -- SO + ); + CLK_GEN: process begin wait for CLK_PERIOD/2; @@ -139,7 +155,7 @@ TX_SLAVE_SIM_SHIFT_REG: process(mst_clk) end if; end process; - miso <= slv_tx_shiftreg(slv_tx_shiftreg'left); +-- miso <= slv_tx_shiftreg(slv_tx_shiftreg'left); RX_SLAVE_SIM_DATA_REG: process(clk) variable data_vld : unsigned(1 downto 0); @@ -176,13 +192,13 @@ STIMULUS: process wait for 600*CLK_PERIOD; wait until rising_edge(CLK); - mst_din <= X"C355AAC1"; + mst_din <= X"9F55AAC1"; mst_din_vld <= '1'; wait until rising_edge(CLK) and mst_din_rdy = '1'; mst_din_vld <= '0'; wait until rising_edge(CLK); - mst_cmd <= to_cmd(32, 32); + mst_cmd <= to_cmd(32, 8); mst_cmd_vld <= '1'; wait until rising_edge(CLK) and mst_cmd_rdy = '1'; mst_cmd_vld <= '0'; @@ -208,33 +224,33 @@ STIMULUS: process mst_din_vld <= '0'; wait until rising_edge(CLK); - mst_cmd <= to_cmd(256, 8); + mst_cmd <= to_cmd(656, 8); mst_cmd_vld <= '1'; wait until rising_edge(CLK) and mst_cmd_rdy = '1'; mst_cmd_vld <= '0'; -------------------------------------------------------- wait until rising_edge(CLK); - mst_din <= X"C3AA55C1"; + mst_din <= X"030155C1"; mst_din_vld <= '1'; wait until rising_edge(CLK) and mst_din_rdy = '1'; mst_din_vld <= '0'; wait until rising_edge(CLK); - mst_cmd <= to_cmd(64, 64); + mst_cmd <= to_cmd(64, 32); mst_cmd_vld <= '1'; wait until rising_edge(CLK) and mst_cmd_rdy = '1'; mst_cmd_vld <= '0'; wait for 200*CLK_PERIOD; wait until rising_edge(CLK) and mst_din_rdy = '1'; - mst_din <= X"83AAFF05"; + mst_din <= X"0311FF05"; mst_din_vld <= '1'; wait until rising_edge(CLK) and mst_din_rdy = '1'; mst_din_vld <= '0'; -------------------------------------------------------- - mst_din <= X"00000000"; + mst_din <= X"03000000"; for i in 0 to 16 loop wait until rising_edge(CLK); @@ -255,7 +271,7 @@ STIMULUS: process -------------------------------------------------------- wait until rising_edge(CLK); - mst_din <= X"C355AAC1"; + mst_din <= X"0355AAC1"; mst_din_vld <= '1'; wait until rising_edge(CLK) and mst_din_rdy = '1'; mst_din_vld <= '0'; @@ -268,20 +284,20 @@ STIMULUS: process -------------------------------------------------------- wait until rising_edge(CLK); - mst_din <= X"C355AA00"; + mst_din <= X"0355AA00"; mst_din_vld <= '1'; wait until rising_edge(CLK) and mst_din_rdy = '1'; mst_din_vld <= '0'; wait until rising_edge(CLK); - mst_cmd <= to_cmd(32, 24); + mst_cmd <= to_cmd(32, 32); mst_cmd_vld <= '1'; wait until rising_edge(CLK) and mst_cmd_rdy = '1'; mst_cmd_vld <= '0'; -------------------------------------------------------- wait until rising_edge(CLK); - mst_din <= X"C355AAC1"; + mst_din <= X"0311AAC1"; mst_din_vld <= '1'; wait until rising_edge(CLK) and mst_din_rdy = '1'; mst_din_vld <= '0';