jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- interface change to rams

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1111 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-17 17:24:05 +00:00
parent 5e38a6ff43
commit 228e893904
19 changed files with 201 additions and 291 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/rams/dpram_2w2r2c_ra_sim.vhd
+6 -6
View File
@@ -38,8 +38,8 @@ entity dpram_2w2r2c_ra is
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
re_a : in STD_LOGIC;
re_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
@@ -66,9 +66,9 @@ begin
process (clk_a, clk_b)
begin
if clk_a'event and clk_a = '1' and en_a = '1' and we_a = '1' then
if clk_a'event and clk_a = '1' and we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
elsif clk_b'event and clk_b = '1' and en_b = '1' and we_b = '1' then
elsif clk_b'event and clk_b = '1' and we_b = '1' then
RAM(to_integer(addr_b)) <= din_b;
end if;
end process;
@@ -76,7 +76,7 @@ end process;
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
if re_a = '1' then
addr_a_r <= addr_a;
end if;
end if;
@@ -85,7 +85,7 @@ end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
if re_b = '1' then
addr_b_r <= addr_b;
end if;
end if;