From 228e8939045725c4e3180fdeddf90e6179b2ce0c Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 17 May 2015 17:24:05 +0000 Subject: [PATCH] - interface change to rams git-svn-id: http://moon:8086/svn/vhdl/trunk@1111 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_dcache.vhd | 12 +-- lib/CPUs/MIPS/src/core/mips_icache.vhd | 18 ++--- lib/FIFO/src/fifo_async.vhd | 11 ++- lib/FIFO/src/fifo_sync.vhd | 13 ++-- lib/misc/ram_wb.vhd | 56 +++++++------- ...r2c_ra_xil.vhd => dpram_1w1r1c_ra_alt.vhd} | 73 ++++++++----------- lib/rams/dpram_1w1r1c_ra_sim.vhd | 48 ++++++------ lib/rams/dpram_1w1r1wc_sim.vhd | 69 ------------------ lib/rams/dpram_1w1r2c_ra_alt.vhd | 13 ++-- lib/rams/dpram_1w1r2c_ra_sim.vhd | 11 +-- lib/rams/dpram_1w1r2c_ra_xil.vhd | 11 +-- lib/rams/dpram_1w1r2c_ro_alt.vhd | 28 ++++--- lib/rams/dpram_1w1r2c_ro_sim.vhd | 28 ++++--- lib/rams/dpram_1w1r2c_ro_xil.vhd | 11 +-- lib/rams/dpram_2w2r2c_ra_alt.vhd | 16 ++-- lib/rams/dpram_2w2r2c_ra_sim.vhd | 12 +-- lib/rams/dpram_2w2r2c_ra_xil.vhd | 20 ++--- lib/rams/dpram_2w2r2c_ro_sim.vhd | 20 ++--- lib/rams/dpram_2w2r2c_ro_xil.vhd | 22 +++--- 19 files changed, 201 insertions(+), 291 deletions(-) rename lib/rams/{dpram_x1w1r2c_ra_xil.vhd => dpram_1w1r1c_ra_alt.vhd} (54%) delete mode 100644 lib/rams/dpram_1w1r1wc_sim.vhd diff --git a/lib/CPUs/MIPS/src/core/mips_dcache.vhd b/lib/CPUs/MIPS/src/core/mips_dcache.vhd index 85d1639..f1cf792 100644 --- a/lib/CPUs/MIPS/src/core/mips_dcache.vhd +++ b/lib/CPUs/MIPS/src/core/mips_dcache.vhd @@ -69,8 +69,8 @@ COMPONENT dpram_2w2r2c_ra is ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; + re_a : in STD_LOGIC; + re_b : in STD_LOGIC; we_a : in STD_LOGIC; we_b : in STD_LOGIC; addr_a : in unsigned (addr_width-1 downto 0); @@ -268,8 +268,8 @@ inst_tag_ram : dpram_2w2r2c_ra ( clk_a => CLK_I, clk_b => CLK_I, - en_a => '1', - en_b => '1', + re_a => '1', + re_b => '1', we_a => tag_ram_we, we_b => '0', addr_a => tag_ram_addr_wr, @@ -294,8 +294,8 @@ gen_data_ram: ( clk_a => CLK_I, clk_b => CLK_I, - en_a => '1', - en_b => '1', + re_a => '1', + re_b => '1', we_a => cpu_data_ram_we(i), we_b => ctrl_data_ram_we(i), addr_a => ctrl_data_ram_addr, diff --git a/lib/CPUs/MIPS/src/core/mips_icache.vhd b/lib/CPUs/MIPS/src/core/mips_icache.vhd index 696a409..57c747d 100644 --- a/lib/CPUs/MIPS/src/core/mips_icache.vhd +++ b/lib/CPUs/MIPS/src/core/mips_icache.vhd @@ -64,9 +64,8 @@ COMPONENT dpram_1w1r2c_ra PORT ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; we_a : in STD_LOGIC; + re_b : in STD_LOGIC; addr_a : in unsigned (addr_width-1 downto 0); addr_b : in unsigned (addr_width-1 downto 0); din_a : in unsigned (data_width-1 downto 0); @@ -84,8 +83,8 @@ COMPONENT dpram_2w2r2c_ra is ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; + re_a : in STD_LOGIC; + re_b : in STD_LOGIC; we_a : in STD_LOGIC; we_b : in STD_LOGIC; addr_a : in unsigned (addr_width-1 downto 0); @@ -271,10 +270,10 @@ inst_tag_ram : dpram_2w2r2c_ra ( clk_a => CLK_I, clk_b => CLK_I, - en_a => '1', - en_b => tag_ram_re, - we_a => tag_ram_we, - we_b => '0', + re_a => '1', + we_a => tag_ram_we, + re_b => tag_ram_re, + we_b => '0', addr_a => tag_ram_addr_wr, addr_b => tag_ram_addr_rd, din_a => tag_ram_data_wr, @@ -293,8 +292,7 @@ inst_data_ram : dpram_1w1r2c_ra ( clk_a => CLK_I, clk_b => CLK_I, - en_a => data_ram_we, - en_b => data_ram_re, + re_b => data_ram_re, we_a => data_ram_we, addr_a => data_ram_addr_wr, addr_b => data_ram_addr_rd, diff --git a/lib/FIFO/src/fifo_async.vhd b/lib/FIFO/src/fifo_async.vhd index 4b64a62..28d08ab 100644 --- a/lib/FIFO/src/fifo_async.vhd +++ b/lib/FIFO/src/fifo_async.vhd @@ -110,13 +110,12 @@ inst_dpram_1w1r2c: entity work.dpram_1w1r2c_ra PORT MAP( clk_a => clk_w, clk_b => clk_r, - en_a => '1', - en_b => mem_rd_en, - we_a => mem_wr_en, - addr_a => ptr_w, - addr_b => ptr_r, + we_a => mem_wr_en, + re_b => mem_rd_en, + addr_a => ptr_w, + addr_b => ptr_r, din_a => data_w, - dout_b => data_r + dout_b => data_r ); end Behavioral; diff --git a/lib/FIFO/src/fifo_sync.vhd b/lib/FIFO/src/fifo_sync.vhd index 8ae9a99..aa84305 100644 --- a/lib/FIFO/src/fifo_sync.vhd +++ b/lib/FIFO/src/fifo_sync.vhd @@ -44,8 +44,8 @@ entity fifo_sync is ( rst : in STD_LOGIC; clk : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; + we : in STD_LOGIC; + re : in STD_LOGIC; fifo_full : out STD_LOGIC; fifo_empty : out STD_LOGIC; fifo_afull : out STD_LOGIC; @@ -109,13 +109,12 @@ inst_dpram_1w1r2c: entity work.dpram_1w1r2c_ra PORT MAP( clk_a => clk, clk_b => clk, - en_a => '1', - en_b => mem_rd_en, we_a => mem_wr_en, - addr_a => ptr_w, - addr_b => ptr_r, + re_b => mem_rd_en, + addr_a => ptr_w, + addr_b => ptr_r, din_a => data_w, - dout_b => data_r + dout_b => data_r ); end Behavioral; diff --git a/lib/misc/ram_wb.vhd b/lib/misc/ram_wb.vhd index e62bad6..d5fbd1f 100644 --- a/lib/misc/ram_wb.vhd +++ b/lib/misc/ram_wb.vhd @@ -30,15 +30,17 @@ END ram_wb; ARCHITECTURE behavior OF ram_wb IS constant addr_width : natural := NextExpBaseTwo(NUM_WORDS); - signal data_en : std_logic; + signal ram_en : std_logic; signal we : unsigned(3 downto 0); + signal re : std_logic; begin - we <= SEL_I and (3 downto 0 => WE_I); + SRDY_O <= CYC_I; - data_en <= CYC_I and STB_I and MRDY_I; - SRDY_O <= CYC_I; + ram_en <= CYC_I and STB_I and MRDY_I; + we <= SEL_I and (3 downto 0 => ram_en and WE_I); + re <= ram_en and not WE_I; data_valid_register: process(CLK_I) @@ -47,7 +49,7 @@ data_valid_register: if RST_I = '1' then ACK_O <= '0'; else - ACK_O <= data_en and not WE_I; + ACK_O <= re; end if; end if; end process; @@ -61,11 +63,12 @@ inst_ram_0 : entity work.dpram_1w1r1c_ra PORT MAP ( clk => CLK_I, - en => data_en, - we => we(0), - addr => ADDR_I(addr_width+1 downto 2), - din => DAT_I(7 downto 0), - dout => DAT_O(7 downto 0) + we_a => we(0), + re_b => '1', + addr_a => ADDR_I(addr_width+1 downto 2), + addr_b => ADDR_I(addr_width+1 downto 2), + din_a => DAT_I(7 downto 0), + dout_b => DAT_O(7 downto 0) ); inst_ram_1 : entity work.dpram_1w1r1c_ra @@ -77,11 +80,12 @@ inst_ram_1 : entity work.dpram_1w1r1c_ra PORT MAP ( clk => CLK_I, - en => data_en, - we => we(1), - addr => ADDR_I(addr_width+1 downto 2), - din => DAT_I(15 downto 8), - dout => DAT_O(15 downto 8) + we_a => we(1), + re_b => '1', + addr_a => ADDR_I(addr_width+1 downto 2), + addr_b => ADDR_I(addr_width+1 downto 2), + din_a => DAT_I(15 downto 8), + dout_b => DAT_O(15 downto 8) ); inst_ram_2 : entity work.dpram_1w1r1c_ra @@ -93,11 +97,12 @@ inst_ram_2 : entity work.dpram_1w1r1c_ra PORT MAP ( clk => CLK_I, - en => data_en, - we => we(2), - addr => ADDR_I(addr_width+1 downto 2), - din => DAT_I(23 downto 16), - dout => DAT_O(23 downto 16) + we_a => we(2), + re_b => '1', + addr_a => ADDR_I(addr_width+1 downto 2), + addr_b => ADDR_I(addr_width+1 downto 2), + din_a => DAT_I(23 downto 16), + dout_b => DAT_O(23 downto 16) ); inst_ram_3 : entity work.dpram_1w1r1c_ra @@ -109,11 +114,12 @@ inst_ram_3 : entity work.dpram_1w1r1c_ra PORT MAP ( clk => CLK_I, - en => data_en, - we => we(3), - addr => ADDR_I(addr_width+1 downto 2), - din => DAT_I(31 downto 24), - dout => DAT_O(31 downto 24) + we_a => we(3), + re_b => '1', + addr_a => ADDR_I(addr_width+1 downto 2), + addr_b => ADDR_I(addr_width+1 downto 2), + din_a => DAT_I(31 downto 24), + dout_b => DAT_O(31 downto 24) ); diff --git a/lib/rams/dpram_x1w1r2c_ra_xil.vhd b/lib/rams/dpram_1w1r1c_ra_alt.vhd similarity index 54% rename from lib/rams/dpram_x1w1r2c_ra_xil.vhd rename to lib/rams/dpram_1w1r1c_ra_alt.vhd index f6c8201..95a353e 100644 --- a/lib/rams/dpram_x1w1r2c_ra_xil.vhd +++ b/lib/rams/dpram_1w1r1c_ra_alt.vhd @@ -21,64 +21,51 @@ -- For questions and ideas, please contact the author at jens@jayfield.org ----------------------------------------------------------------------- --- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $ +-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $ ----------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; -entity dpram_x1w1r2c_ra is - Generic +entity dpram_1w1r1c_ra is + Generic ( - addr_width_a : integer := 10; - addr_width_b : integer := 10; - data_width_a : integer := 32; - data_width_b : integer := 32 + addr_width : integer := 3; + data_width : integer := 8 ); - Port + Port ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; + clk : in STD_LOGIC; we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width_a-1 downto 0); - addr_b : in unsigned (addr_width_b-1 downto 0); - din_a : in unsigned (data_width_a-1 downto 0); - dout_b : out unsigned (data_width_b-1 downto 0) + re_b : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) ); -end dpram_x1w1r2c_ra; +end dpram_1w1r1c_ra; -architecture Behavioral of dpram_x1w1r2c_ra is +architecture Behavioral of dpram_1w1r1c_ra is - constant NUM_RAM_INSTANCES : integer := data_width_a; - -begin -gen_rams: -for i in 0 to NUM_RAM_INSTANCES-1 generate +TYPE MEM IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0); +SIGNAL ram_block: MEM; -inst_dpram_1w1r2c_ra: entity work.dpram_1w1r2c_ra - GENERIC MAP - ( - addr_width => addr_width_a, - data_width => 1 - ) - PORT MAP - ( - clk_a => clk_a, - clk_b => clk_b, - en_a => '1', - en_b => en_b, - we_a => we_a, - addr_a => addr_a, - addr_b => addr_b, - din_a => din_a(i downto i), - dout_b => dout_b(i downto i) - ); - -end generate; +BEGIN + PROCESS (clk) + BEGIN + IF (clk'event AND clk = '1') THEN + IF (we_a = '1') THEN + ram_block(to_integer(addr_a)) <= din_a; + END IF; + IF (re_b = '1') THEN + dout_b <= ram_block(to_integer(addr_b)); + END IF; + -- VHDL semantics imply that q doesn't get data + -- in this clock cycle + END IF; + END PROCESS; end Behavioral; diff --git a/lib/rams/dpram_1w1r1c_ra_sim.vhd b/lib/rams/dpram_1w1r1c_ra_sim.vhd index 26c1f4a..95a353e 100644 --- a/lib/rams/dpram_1w1r1c_ra_sim.vhd +++ b/lib/rams/dpram_1w1r1c_ra_sim.vhd @@ -34,38 +34,38 @@ entity dpram_1w1r1c_ra is addr_width : integer := 3; data_width : integer := 8 ); - Port ( + Port + ( clk : in STD_LOGIC; - en : in STD_LOGIC; - we : in STD_LOGIC; - addr : in unsigned (addr_width-1 downto 0); - din : in unsigned (data_width-1 downto 0); - dout : out unsigned (data_width-1 downto 0) + we_a : in STD_LOGIC; + re_b : in STD_LOGIC; + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); + din_a : in unsigned (data_width-1 downto 0); + dout_b : out unsigned (data_width-1 downto 0) ); end dpram_1w1r1c_ra; architecture Behavioral of dpram_1w1r1c_ra is - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal RAM : RAMtype; - signal addr_reg : unsigned (addr_width-1 downto 0); - -begin - dout <= RAM(to_integer(addr_reg)); +TYPE MEM IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0); +SIGNAL ram_block: MEM; -process (clk) -begin -if clk'event and clk = '1' then - if en = '1' then - if we = '1' then - RAM(to_integer(addr)) <= din; - end if; - addr_reg <= addr; - end if; -end if; -end process; +BEGIN + PROCESS (clk) + BEGIN + IF (clk'event AND clk = '1') THEN + IF (we_a = '1') THEN + ram_block(to_integer(addr_a)) <= din_a; + END IF; + IF (re_b = '1') THEN + dout_b <= ram_block(to_integer(addr_b)); + END IF; + -- VHDL semantics imply that q doesn't get data + -- in this clock cycle + END IF; + END PROCESS; end Behavioral; diff --git a/lib/rams/dpram_1w1r1wc_sim.vhd b/lib/rams/dpram_1w1r1wc_sim.vhd deleted file mode 100644 index 1437c0f..0000000 --- a/lib/rams/dpram_1w1r1wc_sim.vhd +++ /dev/null @@ -1,69 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: On-Chip work registers --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity dpram_1w1r1wc is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clk_w : in STD_LOGIC; - we : in STD_LOGIC; - wptr : in unsigned (addr_width-1 downto 0); - rptr : in unsigned (addr_width-1 downto 0); - din : in unsigned (data_width-1 downto 0); - dout : out unsigned (data_width-1 downto 0) - ); -end dpram_1w1r1wc; - -architecture Behavioral of dpram_1w1r1wc is - - constant depth : integer := 2**addr_width; - type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0); - - signal mem : mem_t; - -begin - -reg_in: - process(clk_w) - begin - if rising_edge(clk_w) then - if we = '1' then - mem(to_integer(wptr)) <= din; - end if; - end if; - end process; - - dout <= mem(to_integer(rptr)); - -end Behavioral; - diff --git a/lib/rams/dpram_1w1r2c_ra_alt.vhd b/lib/rams/dpram_1w1r2c_ra_alt.vhd index 727bc16..7253652 100644 --- a/lib/rams/dpram_1w1r2c_ra_alt.vhd +++ b/lib/rams/dpram_1w1r2c_ra_alt.vhd @@ -36,13 +36,12 @@ entity dpram_1w1r2c_ra is Port ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; + re_b : in STD_LOGIC; we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); + addr_a : in unsigned (addr_width-1 downto 0); + addr_b : in unsigned (addr_width-1 downto 0); din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) + dout_b : out unsigned (data_width-1 downto 0) ); end dpram_1w1r2c_ra; @@ -61,7 +60,7 @@ begin process(clk_a) begin if(rising_edge(clk_a)) then - if(we_a = '1' and en_a = '1') then + if(we_a = '1') then ram(to_integer(addr_a)) <= din_a; end if; end if; @@ -70,7 +69,7 @@ begin process(clk_b) begin if(rising_edge(clk_b)) then - if(en_b = '1') then + if(re_b = '1') then dout_b <= ram(to_integer(addr_b)); end if; end if; diff --git a/lib/rams/dpram_1w1r2c_ra_sim.vhd b/lib/rams/dpram_1w1r2c_ra_sim.vhd index fa44e85..2e92c4f 100644 --- a/lib/rams/dpram_1w1r2c_ra_sim.vhd +++ b/lib/rams/dpram_1w1r2c_ra_sim.vhd @@ -36,9 +36,8 @@ entity dpram_1w1r2c_ra is Port ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; we_a : in STD_LOGIC; + re_b : in STD_LOGIC; addr_a : in unsigned (addr_width-1 downto 0); addr_b : in unsigned (addr_width-1 downto 0); din_a : in unsigned (data_width-1 downto 0); @@ -60,10 +59,8 @@ begin process (clk_a) begin if clk_a'event and clk_a = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; + if we_a = '1' then + RAM(to_integer(addr_a)) <= din_a; end if; end if; end process; @@ -71,7 +68,7 @@ end process; process (clk_b) begin if clk_b'event and clk_b = '1' then - if en_b = '1' then + if re_b = '1' then addr_b_r <= addr_b; end if; end if; diff --git a/lib/rams/dpram_1w1r2c_ra_xil.vhd b/lib/rams/dpram_1w1r2c_ra_xil.vhd index ff10f8c..e23615d 100644 --- a/lib/rams/dpram_1w1r2c_ra_xil.vhd +++ b/lib/rams/dpram_1w1r2c_ra_xil.vhd @@ -36,9 +36,8 @@ entity dpram_1w1r2c_ra is Port ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; we_a : in STD_LOGIC; + re_b : in STD_LOGIC; addr_a : in unsigned (addr_width-1 downto 0); addr_b : in unsigned (addr_width-1 downto 0); din_a : in unsigned (data_width-1 downto 0); @@ -60,10 +59,8 @@ begin process (clk_a) begin if clk_a'event and clk_a = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; + if we_a = '1' then + RAM(to_integer(addr_a)) <= din_a; end if; end if; end process; @@ -71,7 +68,7 @@ end process; process (clk_b) begin if clk_b'event and clk_b = '1' then - if en_b = '1' then + if re_b = '1' then addr_b_r <= addr_b; end if; end if; diff --git a/lib/rams/dpram_1w1r2c_ro_alt.vhd b/lib/rams/dpram_1w1r2c_ro_alt.vhd index 4e6fd30..f13300f 100644 --- a/lib/rams/dpram_1w1r2c_ro_alt.vhd +++ b/lib/rams/dpram_1w1r2c_ro_alt.vhd @@ -21,7 +21,7 @@ -- For questions and ideas, please contact the author at jens@jayfield.org ----------------------------------------------------------------------- --- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $ +-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $ ----------------------------------------------------------------------- LIBRARY IEEE; @@ -29,16 +29,17 @@ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; entity dpram_1w1r2c_ro is - Generic ( + Generic + ( addr_width : integer := 3; data_width : integer := 8 ); - Port ( + Port + ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; we_a : in STD_LOGIC; + re_b : in STD_LOGIC; addr_a : in unsigned (addr_width-1 downto 0); addr_b : in unsigned (addr_width-1 downto 0); din_a : in unsigned (data_width-1 downto 0); @@ -54,25 +55,22 @@ architecture Behavioral of dpram_1w1r2c_ro is begin - process (clk_a) -begin -if clk_a'event and clk_a = '1' then - if en_a = '1' then + begin + if clk_a'event and clk_a = '1' then if we_a = '1' then RAM(to_integer(addr_a)) <= din_a; end if; end if; -end if; end process; process (clk_b) -begin -if clk_b'event and clk_b = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); + begin + if clk_b'event and clk_b = '1' then + if re_b = '1' then + dout_b <= RAM(to_integer(addr_b)); + end if; end if; -end if; end process; diff --git a/lib/rams/dpram_1w1r2c_ro_sim.vhd b/lib/rams/dpram_1w1r2c_ro_sim.vhd index 4e6fd30..f13300f 100644 --- a/lib/rams/dpram_1w1r2c_ro_sim.vhd +++ b/lib/rams/dpram_1w1r2c_ro_sim.vhd @@ -21,7 +21,7 @@ -- For questions and ideas, please contact the author at jens@jayfield.org ----------------------------------------------------------------------- --- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $ +-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $ ----------------------------------------------------------------------- LIBRARY IEEE; @@ -29,16 +29,17 @@ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; entity dpram_1w1r2c_ro is - Generic ( + Generic + ( addr_width : integer := 3; data_width : integer := 8 ); - Port ( + Port + ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; we_a : in STD_LOGIC; + re_b : in STD_LOGIC; addr_a : in unsigned (addr_width-1 downto 0); addr_b : in unsigned (addr_width-1 downto 0); din_a : in unsigned (data_width-1 downto 0); @@ -54,25 +55,22 @@ architecture Behavioral of dpram_1w1r2c_ro is begin - process (clk_a) -begin -if clk_a'event and clk_a = '1' then - if en_a = '1' then + begin + if clk_a'event and clk_a = '1' then if we_a = '1' then RAM(to_integer(addr_a)) <= din_a; end if; end if; -end if; end process; process (clk_b) -begin -if clk_b'event and clk_b = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); + begin + if clk_b'event and clk_b = '1' then + if re_b = '1' then + dout_b <= RAM(to_integer(addr_b)); + end if; end if; -end if; end process; diff --git a/lib/rams/dpram_1w1r2c_ro_xil.vhd b/lib/rams/dpram_1w1r2c_ro_xil.vhd index 76533dc..f13300f 100644 --- a/lib/rams/dpram_1w1r2c_ro_xil.vhd +++ b/lib/rams/dpram_1w1r2c_ro_xil.vhd @@ -38,9 +38,8 @@ entity dpram_1w1r2c_ro is ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; we_a : in STD_LOGIC; + re_b : in STD_LOGIC; addr_a : in unsigned (addr_width-1 downto 0); addr_b : in unsigned (addr_width-1 downto 0); din_a : in unsigned (data_width-1 downto 0); @@ -59,10 +58,8 @@ begin process (clk_a) begin if clk_a'event and clk_a = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; + if we_a = '1' then + RAM(to_integer(addr_a)) <= din_a; end if; end if; end process; @@ -70,7 +67,7 @@ end process; process (clk_b) begin if clk_b'event and clk_b = '1' then - if en_b = '1' then + if re_b = '1' then dout_b <= RAM(to_integer(addr_b)); end if; end if; diff --git a/lib/rams/dpram_2w2r2c_ra_alt.vhd b/lib/rams/dpram_2w2r2c_ra_alt.vhd index 5bf5cac..87f61ea 100644 --- a/lib/rams/dpram_2w2r2c_ra_alt.vhd +++ b/lib/rams/dpram_2w2r2c_ra_alt.vhd @@ -38,8 +38,8 @@ entity dpram_2w2r2c_ra is ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; + re_a : in STD_LOGIC; + re_b : in STD_LOGIC; we_a : in STD_LOGIC; we_b : in STD_LOGIC; addr_a : in unsigned (addr_width-1 downto 0); @@ -63,10 +63,12 @@ begin process (clk_a) begin if rising_edge(clk_a) then - if en_a = '1' and we_a = '1' then + if we_a = '1' then RAM(to_integer(addr_a)) := din_a; end if; - dout_a <= RAM(to_integer(addr_a)); + if re_a = '1' then + dout_a <= RAM(to_integer(addr_a)); + end if; end if; end process; @@ -74,10 +76,12 @@ end process; process (clk_b) begin if rising_edge(clk_b) then - if en_b = '1' and we_b = '1' then + if we_b = '1' then RAM(to_integer(addr_b)) := din_b; end if; - dout_b <= RAM(to_integer(addr_b)); + if re_b = '1' then + dout_b <= RAM(to_integer(addr_b)); + end if; end if; end process; diff --git a/lib/rams/dpram_2w2r2c_ra_sim.vhd b/lib/rams/dpram_2w2r2c_ra_sim.vhd index c96138c..b272817 100644 --- a/lib/rams/dpram_2w2r2c_ra_sim.vhd +++ b/lib/rams/dpram_2w2r2c_ra_sim.vhd @@ -38,8 +38,8 @@ entity dpram_2w2r2c_ra is ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; + re_a : in STD_LOGIC; + re_b : in STD_LOGIC; we_a : in STD_LOGIC; we_b : in STD_LOGIC; addr_a : in unsigned (addr_width-1 downto 0); @@ -66,9 +66,9 @@ begin process (clk_a, clk_b) begin - if clk_a'event and clk_a = '1' and en_a = '1' and we_a = '1' then + if clk_a'event and clk_a = '1' and we_a = '1' then RAM(to_integer(addr_a)) <= din_a; - elsif clk_b'event and clk_b = '1' and en_b = '1' and we_b = '1' then + elsif clk_b'event and clk_b = '1' and we_b = '1' then RAM(to_integer(addr_b)) <= din_b; end if; end process; @@ -76,7 +76,7 @@ end process; process (clk_a) begin if clk_a'event and clk_a = '1' then - if en_a = '1' then + if re_a = '1' then addr_a_r <= addr_a; end if; end if; @@ -85,7 +85,7 @@ end process; process (clk_b) begin if clk_b'event and clk_b = '1' then - if en_b = '1' then + if re_b = '1' then addr_b_r <= addr_b; end if; end if; diff --git a/lib/rams/dpram_2w2r2c_ra_xil.vhd b/lib/rams/dpram_2w2r2c_ra_xil.vhd index 53b18fb..774c88e 100644 --- a/lib/rams/dpram_2w2r2c_ra_xil.vhd +++ b/lib/rams/dpram_2w2r2c_ra_xil.vhd @@ -38,8 +38,8 @@ entity dpram_2w2r2c_ra is ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; + re_a : in STD_LOGIC; + re_b : in STD_LOGIC; we_a : in STD_LOGIC; we_b : in STD_LOGIC; addr_a : in unsigned (addr_width-1 downto 0); @@ -67,10 +67,10 @@ begin process (clk_a) begin if clk_a'event and clk_a = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) := din_a; - end if; + if we_a = '1' then + RAM(to_integer(addr_a)) := din_a; + end if; + if re_a = '1' then addr_a_r <= addr_a; end if; end if; @@ -80,10 +80,10 @@ end process; process (clk_b) begin if clk_b'event and clk_b = '1' then - if en_b = '1' then - if we_b = '1' then - RAM(to_integer(addr_b)) := din_b; - end if; + if we_b = '1' then + RAM(to_integer(addr_b)) := din_b; + end if; + if re_b = '1' then addr_b_r <= addr_b; end if; end if; diff --git a/lib/rams/dpram_2w2r2c_ro_sim.vhd b/lib/rams/dpram_2w2r2c_ro_sim.vhd index 3c69b8b..1451831 100644 --- a/lib/rams/dpram_2w2r2c_ro_sim.vhd +++ b/lib/rams/dpram_2w2r2c_ro_sim.vhd @@ -38,8 +38,8 @@ entity dpram_2w2r2c_ro is ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; + re_a : in STD_LOGIC; + re_b : in STD_LOGIC; we_a : in STD_LOGIC; we_b : in STD_LOGIC; addr_a : in unsigned (addr_width-1 downto 0); @@ -62,10 +62,10 @@ begin process (clk_a) begin if clk_a'event and clk_a = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) := din_a; - end if; + if we_a = '1' then + RAM(to_integer(addr_a)) := din_a; + end if; + if re_a = '1' then dout_a <= RAM(to_integer(addr_a)); end if; end if; @@ -74,10 +74,10 @@ end process; process (clk_b) begin if clk_b'event and clk_b = '1' then - if en_b = '1' then - if we_b = '1' then - RAM(to_integer(addr_b)) := din_b; - end if; + if we_b = '1' then + RAM(to_integer(addr_b)) := din_b; + end if; + if re_b = '1' then dout_b <= RAM(to_integer(addr_b)); end if; end if; diff --git a/lib/rams/dpram_2w2r2c_ro_xil.vhd b/lib/rams/dpram_2w2r2c_ro_xil.vhd index d30fd2b..1451831 100644 --- a/lib/rams/dpram_2w2r2c_ro_xil.vhd +++ b/lib/rams/dpram_2w2r2c_ro_xil.vhd @@ -21,7 +21,7 @@ -- For questions and ideas, please contact the author at jens@jayfield.org ----------------------------------------------------------------------- --- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $ +-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $ ----------------------------------------------------------------------- library IEEE; @@ -38,8 +38,8 @@ entity dpram_2w2r2c_ro is ( clk_a : in STD_LOGIC; clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; + re_a : in STD_LOGIC; + re_b : in STD_LOGIC; we_a : in STD_LOGIC; we_b : in STD_LOGIC; addr_a : in unsigned (addr_width-1 downto 0); @@ -62,10 +62,10 @@ begin process (clk_a) begin if clk_a'event and clk_a = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) := din_a; - end if; + if we_a = '1' then + RAM(to_integer(addr_a)) := din_a; + end if; + if re_a = '1' then dout_a <= RAM(to_integer(addr_a)); end if; end if; @@ -74,10 +74,10 @@ end process; process (clk_b) begin if clk_b'event and clk_b = '1' then - if en_b = '1' then - if we_b = '1' then - RAM(to_integer(addr_b)) := din_b; - end if; + if we_b = '1' then + RAM(to_integer(addr_b)) := din_b; + end if; + if re_b = '1' then dout_b <= RAM(to_integer(addr_b)); end if; end if;