- interface change to rams

git-svn-id: http://moon:8086/svn/vhdl/trunk@1111 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
2015-05-17 17:24:05 +00:00
parent 5e38a6ff43
commit 228e893904
19 changed files with 201 additions and 291 deletions
+10 -6
View File
@@ -38,8 +38,8 @@ entity dpram_2w2r2c_ra is
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
re_a : in STD_LOGIC;
re_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
@@ -63,10 +63,12 @@ begin
process (clk_a)
begin
if rising_edge(clk_a) then
if en_a = '1' and we_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
end if;
dout_a <= RAM(to_integer(addr_a));
if re_a = '1' then
dout_a <= RAM(to_integer(addr_a));
end if;
end if;
end process;
@@ -74,10 +76,12 @@ end process;
process (clk_b)
begin
if rising_edge(clk_b) then
if en_b = '1' and we_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
end if;
dout_b <= RAM(to_integer(addr_b));
if re_b = '1' then
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;