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- interface change to rams

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1111 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-17 17:24:05 +00:00
parent 5e38a6ff43
commit 228e893904
19 changed files with 201 additions and 291 deletions
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lib/rams/dpram_1w1r2c_ro_sim.vhd
+13 -15
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@@ -21,7 +21,7 @@
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
@@ -29,16 +29,17 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r2c_ro is
Generic (
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port (
Port
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
re_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
@@ -54,25 +55,22 @@ architecture Behavioral of dpram_1w1r2c_ro is
begin
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
dout_b <= RAM(to_integer(addr_b));
begin
if clk_b'event and clk_b = '1' then
if re_b = '1' then
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end if;
end process;