- interface change to rams

git-svn-id: http://moon:8086/svn/vhdl/trunk@1111 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
2015-05-17 17:24:05 +00:00
parent 5e38a6ff43
commit 228e893904
19 changed files with 201 additions and 291 deletions
+6 -7
View File
@@ -36,13 +36,12 @@ entity dpram_1w1r2c_ra is
Port (
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
re_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r2c_ra;
@@ -61,7 +60,7 @@ begin
process(clk_a)
begin
if(rising_edge(clk_a)) then
if(we_a = '1' and en_a = '1') then
if(we_a = '1') then
ram(to_integer(addr_a)) <= din_a;
end if;
end if;
@@ -70,7 +69,7 @@ begin
process(clk_b)
begin
if(rising_edge(clk_b)) then
if(en_b = '1') then
if(re_b = '1') then
dout_b <= ram(to_integer(addr_b));
end if;
end if;