- interface change to rams

git-svn-id: http://moon:8086/svn/vhdl/trunk@1111 cc03376c-175c-47c8-b038-4cd826a8556b

lib/rams/dpram_1w1r1c_ra_sim.vhd

@@ -34,38 +34,38 @@ entity dpram_1w1r1c_ra is
 		addr_width : integer := 3;
 		data_width : integer := 8
 	);
-	Port (
+	Port 
+	(
 		clk		: in  STD_LOGIC;
-		en		: in  STD_LOGIC;
-		we		: in  STD_LOGIC;
-		addr		: in  unsigned (addr_width-1 downto 0);
-		din		: in  unsigned (data_width-1 downto 0);
-		dout		: out unsigned (data_width-1 downto 0)
+		we_a		: in  STD_LOGIC;
+		re_b		: in  STD_LOGIC;
+		addr_a	: in  unsigned (addr_width-1 downto 0);
+		addr_b	: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b	: out unsigned (data_width-1 downto 0)
 	);
 end dpram_1w1r1c_ra;
 
 architecture Behavioral of dpram_1w1r1c_ra is
 
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	signal addr_reg : unsigned (addr_width-1 downto 0);
-	
-begin
 
-	dout <= RAM(to_integer(addr_reg));
+TYPE MEM IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0);
+SIGNAL ram_block: MEM;
 
-process (clk)
-begin
-if clk'event and clk = '1' then
-	if en = '1' then
-		if we = '1' then
-			RAM(to_integer(addr)) <= din;
-		end if;
-		addr_reg	<= addr;
-	end if;
-end if;
-end process;
+BEGIN
+	PROCESS (clk)
+	BEGIN
+	IF (clk'event AND clk = '1') THEN
+		IF (we_a = '1') THEN
+			ram_block(to_integer(addr_a)) <= din_a;
+		END IF;
+		IF (re_b = '1') THEN
+			dout_b <= ram_block(to_integer(addr_b));
+		END IF;
+		-- VHDL semantics imply that q doesn't get data
+		-- in this clock cycle
+		END IF;
+	END PROCESS;
 
 end Behavioral;